WO2015043032A1 - 液晶显示装置及其显示控制方法 - Google Patents

液晶显示装置及其显示控制方法 Download PDF

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Publication number
WO2015043032A1
WO2015043032A1 PCT/CN2013/085770 CN2013085770W WO2015043032A1 WO 2015043032 A1 WO2015043032 A1 WO 2015043032A1 CN 2013085770 W CN2013085770 W CN 2013085770W WO 2015043032 A1 WO2015043032 A1 WO 2015043032A1
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Prior art keywords
transistor
control switches
drain
display area
group
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PCT/CN2013/085770
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English (en)
French (fr)
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陈政鸿
廖作敏
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深圳市华星光电技术有限公司
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Priority to RU2016114304A priority Critical patent/RU2633403C1/ru
Priority to KR1020167010794A priority patent/KR101789952B1/ko
Priority to GB1601013.4A priority patent/GB2531210B/en
Priority to JP2016539384A priority patent/JP6201055B2/ja
Priority to US14/233,385 priority patent/US9159279B2/en
Publication of WO2015043032A1 publication Critical patent/WO2015043032A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G09G2300/0447—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a liquid crystal display device and a display control method thereof.
  • each sub-pixel unit 100 shown in FIG. 1 includes three display areas 110, 120, and 130.
  • three transistors 111, 121, 131 corresponding to the three display areas 110, 120, 130 are connected in series to the same data line D to obtain a data voltage supplied from the data line D.
  • the voltage applied to each display region is controlled to be distributed, thereby controlling the degree of deflection of the liquid crystal molecules to adjust the light transmittance.
  • the width of the channel of the transistor 111 when the voltage distributed to the display region 110 shown in FIG. 1 is close to the data voltage supplied from the data line D, it is necessary to set the width of the channel of the transistor 111 to be small in advance, and the width thereof may not be infinitely small due to limitations of the TFT process. Therefore, it is necessary to set the width of the channel of the transistor 121 (or the transistor 131) to be large so that the voltage difference allocated to both becomes small.
  • the width of the transistor 131 is set in advance to be large.
  • the width of the channel of the transistor is set to be large, so that the area of the opaque transistor is increased, the aperture ratio of the pixel is lowered, and power consumption is also increased.
  • the technical problem to be solved by the present invention is to provide a liquid crystal display device and a display control method thereof, which can improve the pixel aperture ratio of a liquid crystal display device having a wide viewing angle and reduce power consumption.
  • the present invention adopts a technical solution to provide a liquid crystal display device, which is provided with a plurality of scan lines, a plurality of data lines, and a plurality of sub-pixel units, each of the sub-pixel units including a common electrode line and a plurality of a display area and a plurality of control switches, the control switch is configured to control the display area to receive a corresponding data voltage, wherein the plurality of control switches comprise a first group of control switches and a second group of control switches, and the first group of control switches and the second The group control switch is connected in parallel to the same data line to apply a corresponding data voltage to the plurality of display areas through the data line; wherein the plurality of display areas include the first display area, the second display area, and the third display area, first The group control switch includes a first transistor, and the second group of control switches includes a second transistor and a third transistor, wherein a gate of the first transistor is connected to one scan line, a source is connected to the data
  • the gate of the second transistor is connected to the scan line, the source is connected to the data line, and the drain is connected to the second display area;
  • the gate of the transistor is connected to the scan line, the source is connected to the drain of the second transistor, and the drain is connected to the third display region;
  • the first transistor is further connected in series with the fourth transistor, and the third transistor is also connected in series with the fifth transistor,
  • the source of the four transistor is connected to the drain of the first transistor, the drain is connected to the common electrode line, the gate is connected to the scan line, the source of the fifth transistor is connected to the drain of the third transistor, and the drain and the common electrode line are connected. Connection, the gate is connected to the scan line.
  • the first display area is an area in which the display area is the largest among the plurality of display areas of the sub-pixel unit.
  • a liquid crystal display device which is provided with a plurality of scan lines, a plurality of data lines, and a plurality of sub-pixel units, each of the sub-pixel units including a plurality of display areas.
  • the control switch is configured to control the display area to receive a corresponding data voltage
  • the plurality of control switches comprise a first group of control switches and a second group of control switches, and the first group of control switches and the second group of control switches Parallel connection to the same data line to apply a corresponding data voltage to the plurality of display areas through the data line.
  • the plurality of display areas include a first display area, a second display area, and a third display area
  • the first group of control switches includes a first transistor
  • the second group of control switches includes a second transistor and a third transistor, wherein the first transistor
  • the gate is connected to a scan line
  • the source is connected to the data line
  • the drain is connected to the first display area
  • the gate of the second transistor is connected to the scan line
  • the source is connected to the data line
  • the drain and the second display area are connected.
  • the gate of the third transistor is connected to the scan line
  • the source is connected to the drain of the second transistor
  • the drain is connected to the third display region.
  • the sub-pixel unit further includes a common electrode line, the first transistor further has a fourth transistor connected in series, the source of the fourth transistor is connected to the drain of the first transistor, the drain is connected to the common electrode line, and the gate is connected to the scan line. .
  • the sub-pixel unit further includes a common electrode line, the third transistor further has a fifth transistor connected in series, the source of the fifth transistor is connected to the drain of the third transistor, the drain is connected to the common electrode line, and the gate is connected to the scan line. .
  • the first display area is an area in which the display area is the largest among the plurality of display areas of the sub-pixel unit.
  • the liquid crystal display device is provided with a plurality of scan lines, a plurality of data lines, and a plurality of sub-pixel units, each of which The pixel unit includes a plurality of display areas and a plurality of control switches, wherein the control switch is configured to control the display area to receive the corresponding data voltage
  • the display control method includes: setting the plurality of control switches including the first group of control switches and the second group of control switches, and The first group of control switches and the second group of control switches are connected in parallel to the same data line; corresponding data voltages are applied to the plurality of display areas through the data lines.
  • the plurality of display areas include a first display area, a second display area, and a third display area
  • the first group of control switches includes a first transistor
  • the second group of control switches includes a second transistor and a third transistor
  • the gate of the transistor is connected to a scan line, the source is connected to the data line, the drain is connected to the first display area, the gate of the second transistor is connected to the scan line, the source is connected to the data line, and the drain and the second display are connected.
  • the area is connected; the gate of the third transistor is connected to the scan line, the source is connected to the drain of the second transistor, and the drain is connected to the third display area.
  • the sub-pixel unit further includes a common electrode line, the first transistor is connected in series with the fourth transistor, the source of the fourth transistor is connected to the drain of the first transistor, the drain is connected to the common electrode line, and the gate is connected to the scan line. .
  • the sub-pixel unit further includes a common electrode line, the third transistor is connected in series with the fifth transistor, the source of the fifth transistor is connected to the drain of the third transistor, the drain is connected to the common electrode line, and the gate is connected to the scan line. .
  • the first display area is set as the area with the largest display area among the plurality of display areas of the sub-pixel unit.
  • the liquid crystal display device of the present invention includes a plurality of display regions and a plurality of control switches by providing each of the sub-pixel units, wherein the plurality of control switches includes a first group of control switches and a second group of control switches, and The first group of control switches and the second group of control switches are connected in parallel to the same data line such that when a corresponding data voltage is applied to the plurality of display areas through the data lines, the voltages of the first group of control switches and the second group of control switches And equal, so that one of the control switches is compared with the prior art, the preset channel width is far reduced, and the sum of the areas occupied by the plurality of control switches is generally reduced, and the wide viewing angle can be improved.
  • the pixel aperture ratio of the liquid crystal display device and the power consumption are reduced.
  • FIG. 1 is a circuit equivalent diagram of a sub-pixel unit of a liquid crystal display device in the prior art
  • FIG. 2 is a circuit equivalent diagram of an embodiment of a liquid crystal display device of the present invention.
  • FIG. 3 is a circuit equivalent diagram of a first embodiment of a sub-pixel unit of the present invention.
  • FIG. 4 is a circuit equivalent diagram of a second embodiment of a sub-pixel unit of the present invention.
  • FIG. 5 is a circuit equivalent diagram of a third embodiment of a sub-pixel unit of the present invention.
  • FIG. 6 is a circuit equivalent diagram of a fourth embodiment of a sub-pixel unit of the present invention.
  • Fig. 7 is a flow chart showing an embodiment of a display control method of a liquid crystal display device of the present invention.
  • the liquid crystal display device 300 of the present embodiment includes a plurality of scan lines g1-gn and a plurality of data lines d1-dn, and the plurality of scan lines g1-gn and the plurality of data lines d1-dn are vertically insulated and intersected. And correspondingly arranged to define the sub-pixel unit 310 of the liquid crystal display device 300.
  • each sub-pixel unit 310 further includes a plurality of display areas and corresponding plurality of control switches, and preferably the control switch is a thin film transistor (Thin-film) Transistor, TFT).
  • the control switch is a thin film transistor (Thin-film) Transistor, TFT).
  • TFT thin film transistor
  • the sub-pixel unit 310 of the present embodiment includes a first display area 311, a second display area 312, a third display area 313, and a first transistor. 314, a second transistor 315, and a third transistor 316.
  • the first transistor 314, the second transistor 315, and the third transistor 316 are divided into two groups.
  • the first group of control switches T1 includes a first transistor 314, and the second group of control switches T2 includes a second transistor 315. And a third transistor 316.
  • the first group of control switches T1 of the present invention are not limited to including one thin film transistor.
  • the first group of control switches T1 may also include a plurality of thin film transistors, and only need to satisfy the first group of control switches T1 and The two sets of control switches T2 are connected in parallel to the same data line d1. Based on the plurality of control switches of the embodiment, specifically,
  • the gate G1 of the first transistor 314 is connected to the scanning line g1, the source S1 is connected to the data line d1, and the drain D1 is connected to the first display region 311.
  • the gate G2 of the second transistor 315 is connected to the scanning line g1, the source S2 is connected to the data line d1, and the drain D2 is connected to the second display region 312.
  • the gate G3 of the third transistor 316 is connected to the scanning line g1, the source S3 is connected to the drain D2 of the second transistor 315, and the drain D3 is connected to the third display region 313.
  • the present embodiment can be regarded as that the transistor 121 having the largest area due to the maximum channel width is connected in parallel with the transistor 111 and the transistor 131, that is, the first embodiment.
  • a display area 311 and a first transistor 314 are equivalent to the display area 120 and the transistor 121 shown in FIG. 1.
  • the second display area 312 and the second transistor 315 of the present embodiment correspond to the display area 110 and the transistor 111 shown in FIG. 1.
  • the third display area 313 and the third transistor 316 of the present embodiment are equivalent to the display area 130 and the transistor 131 shown in FIG. 1. Therefore, the first transistor 314 and the first display area 311 can be individually powered.
  • the width of the channel of the second transistor 315 is set in advance as compared with FIG.
  • the width of the illustrated transistor 131 is increased, but the voltage distributed by the first transistor 314 is equal to the sum of the voltages assigned to the second transistor 315 and the third transistor 314 due to the parallel connection, resulting in a pre-set channel of the first transistor 314.
  • the width is much smaller than the width of the transistor 121 shown in FIG.
  • the area occupied by the first transistor 314, the second transistor 315, and the third transistor 316 is much smaller than the area occupied by the three transistors 111, 121, and 131 shown in FIG. 1, so that each sub-pixel unit can be increased.
  • the light transmission area increases the pixel aperture ratio and reduces power consumption.
  • the display area of the first display area 311 is larger than the display area of any one of the second display area 312 and the third display area 313, so that power consumption can be better reduced.
  • the sub-pixel unit 510 of the present embodiment further includes a common electrode line c1, which is based on the embodiment shown in FIG. 3, and further includes a fourth transistor 517.
  • the source S4 of the fourth transistor 517 is connected to the drain D3 of the third transistor 516 (corresponding to the third transistor 316 shown in FIG. 3), the drain D4 is connected to the common electrode line c1, and the gate G4 and the scan line g1 are connected. connection.
  • the fourth transistor 517 is mainly used for voltage division, and can prevent the common when the data line d1 stops supplying power to the second transistor 515 and the third transistor 516.
  • the voltage of the electrode line c1 is reflowed, thereby preventing the display screen from flickering.
  • the first transistor 614 (corresponding to the first transistor 314 shown in FIG. 3) may be disposed in series with the fourth transistor 617 on the basis of the embodiment shown in FIG.
  • the source S4 of the fourth transistor 617 is connected to the drain D1 of the first transistor 614, the drain D4 is connected to the common electrode line c1, and the gate G4 is connected to the scanning line g1.
  • the fourth transistor 617 mainly functions to divide voltage and prevent backflow.
  • a first transistor 714 (corresponding to the first transistor 314 shown in FIG. 3) is further provided with a fourth transistor 717 connected in series, and the third transistor is provided on the basis of the embodiment shown in FIG. 716 (corresponding to the third transistor 316 shown in FIG. 3) is connected in series with a fifth transistor 718, such as the sub-pixel unit 710 shown in FIG. 6, wherein the sub-pixel unit 710 further includes a common electrode line c1.
  • the source S4 of the fourth transistor 717 is connected to the drain D1 of the first transistor 714, the drain D4 is connected to the common electrode line c1, and the gate G4 is connected to the scanning line g1.
  • the source S5 of the fifth transistor 718 is connected to the drain D3 of the third transistor 716, the drain D5 is connected to the common electrode line c1, and the gate G5 is connected to the scanning line g1.
  • the fourth transistor 717 and the fifth transistor 718 mainly function to divide and prevent backflow.
  • the present invention also provides a display control method for a liquid crystal display device.
  • the display control method of the present embodiment mainly includes:
  • Step S810 Setting a plurality of control switches includes a first group of control switches and a second group of control switches, and the first group of control switches and the second group of control switches are connected in parallel to the same data line.
  • Step S820 applying a corresponding data voltage to the plurality of display areas through the data lines.
  • the display control method of the present embodiment is based on the liquid crystal display device 200 of the above embodiment, and has any one of the sub-pixel units 510, 610, and 710 of the above embodiment, which has the same advantageous effects, and is specifically referred to herein. No longer.
  • the liquid crystal display device of the present invention includes a plurality of display areas and a plurality of control switches by providing each sub-pixel unit, wherein the plurality of control switches includes a first group of control switches and a second group of control switches, and the first The group control switch and the second group of control switches are connected in parallel to the same data line, such that when a corresponding data voltage is applied to the plurality of display areas through the data line, the voltages of the first group of control switches and the second group of control switches And equal, so that one of the control switches is compared with the prior art, the width of the preset channel is far reduced, and the sum of the areas occupied by the plurality of control switches is generally reduced, and the wide viewing angle can be improved.
  • the liquid crystal display device has a pixel aperture ratio and reduces power consumption.

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Abstract

一种液晶显示装置（300）及其显示控制方法。液晶显示装置（300）的每一子像素单元（310）包括多个显示区域（311，312，313）和多个控制开关（314，315，316），控制开关（314，315，316）用于控制显示区域（311，312，313）接收对应的数据电压，其中多个控制开关（314，315，316）包括第一组控制开关（T1）和第二组控制开关（T2），且第一组控制开关（T1）和第二组控制开关（T2）并联连接于同一条数据线（d1）。通过上述方式，能够提升具有广视角的液晶显示装置（300）的像素开口率，并降低功耗。

Description

液晶显示装置及其显示控制方法
【技术领域】
本发明涉及显示技术领域，特别是涉及一种液晶显示装置及其显示控制方法。
【背景技术】
液晶显示的市场迅速成长，应用领域的不断扩展，特别是大尺寸液晶显示装置的应用，要求其具有更广的视角范围，而广视角的液晶显示装置在显示时容易出现色偏问题。
为解决色偏问题，现有技术主要是将每一子像素单元设置为多个显示区域，例如图1所示的子像素单元100包括三个显示区域110、120、130。参阅图1，三个显示区域110、120、130对应的三个晶体管111、121、131相互串联连接于同一条数据线D，以获得数据线D提供的数据电压。在显示时，通过预先设置每一晶体管的沟道的宽长比值，从而控制分配施加于每一显示区域的电压，进而控制液晶分子的偏转程度，以调整光透过率。
然而，当对图1所示的显示区域110分配的电压接近数据线D提供的数据电压时，需要预先设置晶体管111的沟道的宽度很小，由于TFT制程的限制导致其宽度不可能无限小，因此需要设置晶体管121（或晶体管131）的沟道的宽度很大，以使得对二者分配的电压差异变小。
又或者，当对显示区域120、130分配的电压相等时，由于晶体管111、121的阻抗作用，因此需要设置晶体管131的宽度很小，因TFT制程的限制导致其宽度不可能无限小，则需要预先设置晶体管121的沟道的宽度很大。
上述两种情况，预先设置晶体管的沟道的宽度很大，使得不透光的晶体管的面积增大，降低了像素的开口率，同时也增加了功耗。
因此，有必要提供一种液晶显示装置及其显示控制方法，以解决上述问题。
【发明内容】
本发明主要解决的技术问题是提供一种液晶显示装置及其显示控制方法，能够提升具有广视角的液晶显示装置的像素开口率，并降低功耗。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种液晶显示装置，设置有多条扫描线、多条数据线以及多个子像素单元，每一子像素单元包括公共电极线、多个显示区域和多个控制开关，控制开关用于控制显示区域接收对应的数据电压，其中，多个控制开关包括第一组控制开关和第二组控制开关，且第一组控制开关和第二组控制开关并联连接于同一条数据线，以通过数据线对多个显示区域施加对应的数据电压；其中，多个显示区域包括第一显示区域、第二显示区域和第三显示区域，第一组控制开关包括第一晶体管，第二组控制开关包括第二晶体管和第三晶体管，其中第一晶体管的栅极与一条扫描线连接，源极与数据线连接，漏极与第一显示区域连接；第二晶体管的栅极与扫描线连接，源极与数据线连接，漏极与第二显示区域连接；第三晶体管的栅极与扫描线连接，源极与第二晶体管的漏极连接，漏极与第三显示区域连接；第一晶体管还串联有第四晶体管，第三晶体管还串联有第五晶体管，第四晶体管的源极与第一晶体管的漏极连接，漏极与公共电极线连接，栅极与扫描线连接，第五晶体管的源极与第三晶体管的漏极连接，漏极与公共电极线连接，栅极与扫描线连接。
其中，第一显示区域为子像素单元的多个显示区域中显示面积最大的区域。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示装置，设置有多条扫描线、多条数据线以及多个子像素单元，每一子像素单元包括多个显示区域和多个控制开关，控制开关用于控制显示区域接收对应的数据电压，其中，多个控制开关包括第一组控制开关和第二组控制开关，且第一组控制开关和第二组控制开关并联连接于同一条数据线，以通过数据线对多个显示区域施加对应的数据电压。
其中，多个显示区域包括第一显示区域、第二显示区域和第三显示区域，第一组控制开关包括第一晶体管，第二组控制开关包括第二晶体管和第三晶体管，其中第一晶体管的栅极与一条扫描线连接，源极与数据线连接，漏极与第一显示区域连接；第二晶体管的栅极与扫描线连接，源极与数据线连接，漏极与第二显示区域连接；第三晶体管的栅极与扫描线连接，源极与第二晶体管的漏极连接，漏极与第三显示区域连接。
其中，子像素单元还包括公共电极线，第一晶体管还串联有第四晶体管，第四晶体管的源极与第一晶体管的漏极连接，漏极与公共电极线连接，栅极与扫描线连接。
其中，子像素单元还包括公共电极线，第三晶体管还串联有第五晶体管，第五晶体管的源极与第三晶体管的漏极连接，漏极与公共电极线连接，栅极与扫描线连接。
其中，第一显示区域为子像素单元的多个显示区域中显示面积最大的区域。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示装置的显示控制方法，液晶显示装置设置有多条扫描线、多条数据线以及多个子像素单元，每一子像素单元包括多个显示区域和多个控制开关，控制开关用于控制显示区域接收对应的数据电压，显示控制方法包括：设置多个控制开关包括第一组控制开关和第二组控制开关，且第一组控制开关和第二组控制开关并联连接于同一条数据线；通过数据线对多个显示区域施加对应的数据电压。
其中，设置多个显示区域包括第一显示区域、第二显示区域和第三显示区域，第一组控制开关包括第一晶体管，第二组控制开关包括第二晶体管和第三晶体管；其中第一晶体管的栅极与一条扫描线连接，源极与数据线连接，漏极与第一显示区域连接；第二晶体管的栅极与扫描线连接，源极与数据线连接，漏极与第二显示区域连接；第三晶体管的栅极与扫描线连接，源极与第二晶体管的漏极连接，漏极与第三显示区域连接。
其中，设置子像素单元还包括公共电极线，第一晶体管与第四晶体管串联，第四晶体管的源极与第一晶体管的漏极连接，漏极与公共电极线连接，栅极与扫描线连接。
其中，设置子像素单元还包括公共电极线，第三晶体管与第五晶体管串联，第五晶体管的源极与第三晶体管的漏极连接，漏极与公共电极线连接，栅极与扫描线连接。
其中，设置第一显示区域为子像素单元的多个显示区域中显示面积最大的区域。
本发明的有益效果是：本发明的液晶显示装置通过设置每一子像素单元包括多个显示区域和多个控制开关，其中多个控制开关包括第一组控制开关和第二组控制开关，且第一组控制开关和第二组控制开关并联连接于同一条数据线，使得在通过数据线对多个显示区域施加对应的数据电压时，第一组控制开关和第二组控制开关的电压之和相等，从而使得其中一组控制开关相比较于现有技术，其预先设置的沟道宽度远远减小，总体上多个控制开关所占的面积之和减小，能够提升具有广视角的液晶显示装置的像素开口率，并降低功耗。
【附图说明】
图1是现有技术中液晶显示装置的子像素单元的电路等效示意图；
图2是本发明液晶显示装置一实施例的电路等效示意图；
图3是本发明一个子像素单元第一实施例的电路等效示意图；
图4是本发明一个子像素单元第二实施例的电路等效示意图；
图5是本发明一个子像素单元第三实施例的电路等效示意图；
图6是本发明一个子像素单元第四实施例的电路等效示意图；
图7是本发明液晶显示装置的显示控制方法一实施例的流程图。
【具体实施方式】
下面结合附图2~7和实施例对本发明进行详细说明。
图2是本发明液晶显示装置一实施例的结构示意图。如图2所示，本实施例的液晶显示装置300包括多条扫描线g1-gn、多条数据线d1-dn，多条扫描线g1-gn和多条数据线d1-dn垂直绝缘相交，并且对应围设以限定液晶显示装置300的子像素单元310。
在本发明中，每一子像素单元310还包括多个显示区域和对应的多个控制开关，并且优选控制开关为薄膜晶体管（Thin-film transistor，TFT）。具体而言，参阅图3所示的子像素单元310的电路等效示意图，本实施例的子像素单元310包括第一显示区域311、第二显示区域312、第三显示区域313、第一晶体管314、第二晶体管315以及第三晶体管316。
其中，第一晶体管314、第二晶体管315和第三晶体管316划分为两组，在本实施例中，第一组控制开关T1包括第一晶体管314，第二组控制开关T2包括第二晶体管315和第三晶体管316。应理解，本发明的第一组控制开关T1不仅限于包括一个薄膜晶体管，在其他实施例中，第一组控制开关T1也可包括多个薄膜晶体管，只需满足第一组控制开关T1和第二组控制开关T2并联连接于同一条数据线d1即可。基于本实施例的多个控制开关，具体而言，
第一晶体管314的栅极G1与扫描线g1连接，源极S1与数据线d1连接，漏极D1与第一显示区域311连接。
第二晶体管315的栅极G2与扫描线g1连接，源极S2与数据线d1连接，漏极D2与第二显示区域312连接。
第三晶体管316的栅极G3与扫描线g1连接，源极S3与第二晶体管315的漏极D2连接，漏极D3与第三显示区域313连接。
相比较于图1所示现有技术的子像素单元100，本实施可以看作是将因沟道宽度最大导致的面积最大的晶体管121与晶体管111和晶体管131并联，即，本实施例的第一显示区域311和第一晶体管314相当于图1所示的显示区域120和晶体管121，本实施例的第二显示区域312和第二晶体管315相当于图1所示的显示区域110和晶体管111，本实施例的第三显示区域313和第三晶体管316相当于图1所示的显示区域130和晶体管131，因此本实施例可以对第一晶体管314及第一显示区域311单独进行供电控制。
在数据线d1对第一显示区域311、第二显示区域312、第三显示区域313施加与图1相同的数据电压时，虽然预先设置第二晶体管315的沟道的宽度相比较于图1所示的晶体管131的宽度有所增加，但是，由于并联则第一晶体管314分配的电压等于分配给第二晶体管315和第三晶体管314的电压之和，导致第一晶体管314预先设置的沟道的宽度远远小于图1所示的晶体管121的宽度。因此，总体上第一晶体管314、第二晶体管315和第三晶体管316所占的面积远远小于图1所示三个晶体管111、121、131所占的面积，从而能够增加每一个子像素单元的透光面积，提升像素开口率，降低功耗。另外，本实施例优选第一显示区域311的显示面积大于第二显示区域312和第三显示区域313中任意一个的显示面积，可以更好的降低功耗。
图4是本发明一个子像素单元第二实施例的电路等效示意图。如图4所示，本实施例的子像素单元510还包括公共电极线c1，其是在图3所示实施例的基础上，进一步包括第四晶体管517。
其中，第四晶体管517的源极S4与第三晶体管516（对应于图3所示第三晶体管316）的漏极D3连接，漏极D4与公共电极线c1连接，栅极G4与扫描线g1连接。
在分配施加至第二显示区域512和第三显示区域513的电压时，第四晶体管517主要用于分压，并且能够在数据线d1对第二晶体管515和第三晶体管516停止供电时防止公共电极线c1的电压回流，从而避免显示画面产生闪烁现象。
应理解，在本发明的第三实施例中，还可以在图3所示实施例的基础上设置第一晶体管614（对应于图3所示第一晶体管314）串联有第四晶体管617，如图5所示的子像素单元610，其中子像素单元610还包括公共电极线c1。
其中，第四晶体管617的源极S4与第一晶体管614的漏极D1连接，漏极D4与公共电极线c1连接，栅极G4与扫描线g1连接。在本实施例中，第四晶体管617主要起到分压和防止回流的作用。
在本发明的第四实施例中，还可以在图3所示实施例的基础上设置第一晶体管714（对应于图3所示第一晶体管314）串联有第四晶体管717，同时第三晶体管716（对应于图3所示第三晶体管316）串联有第五晶体管718，如图6所示的子像素单元710，其中子像素单元710还包括公共电极线c1。
其中，第四晶体管717的源极S4与第一晶体管714的漏极D1连接，漏极D4与公共电极线c1连接，栅极G4与扫描线g1连接。第五晶体管718的源极S5与第三晶体管716的漏极D3连接，漏极D5与公共电极线c1连接，栅极G5与扫描线g1连接。在本实施例中，第四晶体管717和第五晶体管718主要起到分压和防止回流的作用。
此外，本发明还提供了一种液晶显示装置的显示控制方法，如图7所示，本实施例的显示控制方法主要包括：
步骤S810：设置多个控制开关包括第一组控制开关和第二组控制开关，且第一组控制开关和第二组控制开关之间并联连接于同一条数据线。
步骤S820：通过数据线对多个显示区域施加对应的数据电压。
本实施例的显示控制方法基于上述实施例的液晶显示装置200，并具有上述实施例的子像素单元510、610、710中的任意一种，与其具有相同的有益效果，具体参见上述，此处不再赘述。
综上所述，本发明的液晶显示装置通过设置每一子像素单元包括多个显示区域和多个控制开关，其中多个控制开关包括第一组控制开关和第二组控制开关，且第一组控制开关和第二组控制开关之间并联连接于同一条数据线，使得在通过数据线对多个显示区域施加对应的数据电压时，第一组控制开关和第二组控制开关的电压之和相等，从而使得其中一组控制开关相比较于现有技术，其预先设置的沟道的宽度远远减小，总体上多个控制开关所占的面积之和减小，能够提升具有广视角的液晶显示装置的像素开口率，并降低功耗。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (12)

  1. 一种液晶显示装置，设置有多条扫描线、多条数据线以及多个子像素单元，其中，
    每一所述子像素单元包括公共电极线、多个显示区域和多个控制开关，所述控制开关用于控制所述显示区域接收对应的数据电压，其中，
    多个所述控制开关包括第一组控制开关和第二组控制开关，且所述第一组控制开关和所述第二组控制开关并联连接于同一条数据线，以通过所述数据线对所述多个显示区域施加对应的所述数据电压；
    其中，所述多个显示区域包括第一显示区域、第二显示区域和第三显示区域，所述第一组控制开关包括第一晶体管，所述第二组控制开关包括第二晶体管和第三晶体管，所述第一晶体管的栅极与一条扫描线连接，源极与所述数据线连接，漏极与所述第一显示区域连接；所述第二晶体管的栅极与所述扫描线连接，源极与所述数据线连接，漏极与所述第二显示区域连接；所述第三晶体管的栅极与所述扫描线连接，源极与所述第二晶体管的漏极连接，漏极与所述第三显示区域连接；所述第一晶体管还串联有第四晶体管，所述第三晶体管还串联有第五晶体管，所述第四晶体管的源极与所述第一晶体管的漏极连接，漏极与所述公共电极线连接，栅极与所述扫描线连接，所述第五晶体管的源极与所述第三晶体管的漏极连接，漏极与所述公共电极线连接，栅极与所述扫描线连接。
  2. 根据权利要求1所述的液晶显示装置，其中，所述第一显示区域为所述子像素单元的多个所述显示区域中显示面积最大的区域。
  3. 一种液晶显示装置，设置有多条扫描线、多条数据线以及多个子像素单元，其中，
    每一所述子像素单元包括多个显示区域和多个控制开关，所述控制开关用于控制所述显示区域接收对应的数据电压，其中，
    多个所述控制开关包括第一组控制开关和第二组控制开关，且所述第一组控制开关和所述第二组控制开关并联连接于同一条数据线，以通过所述数据线对所述多个显示区域施加对应的所述数据电压。
  4. 根据权利要求3所述的液晶显示装置，其中，所述多个显示区域包括第一显示区域、第二显示区域和第三显示区域，所述第一组控制开关包括第一晶体管，所述第二组控制开关包括第二晶体管和第三晶体管，其中，
    所述第一晶体管的栅极与一条扫描线连接，源极与所述数据线连接，漏极与所述第一显示区域连接；
    所述第二晶体管的栅极与所述扫描线连接，源极与所述数据线连接，漏极与所述第二显示区域连接；
    所述第三晶体管的栅极与所述扫描线连接，源极与所述第二晶体管的漏极连接，漏极与所述第三显示区域连接。
  5. 根据权利要求4所述的液晶显示装置，其中，所述子像素单元还包括公共电极线，所述第一晶体管还串联有第四晶体管，其中，所述第四晶体管的源极与所述第一晶体管的漏极连接，漏极与所述公共电极线连接，栅极与所述扫描线连接。
  6. 根据权利要求4所述的液晶显示装置，其中，所述子像素单元还包括公共电极线，所述第三晶体管还串联有第五晶体管，其中，所述第五晶体管的源极与所述第三晶体管的漏极连接，漏极与所述公共电极线连接，栅极与所述扫描线连接。
  7. 根据权利要求4所述的液晶显示装置，其中，所述第一显示区域为所述子像素单元的多个所述显示区域中显示面积最大的区域。
  8. 一种液晶显示装置的显示控制方法，所述液晶显示装置设置有多条扫描线、多条数据线以及多个子像素单元，每一所述子像素单元包括多个显示区域和多个控制开关，所述控制开关用于控制所述显示区域接收对应的数据电压，其中，所述显示控制方法包括：
    设置多个所述控制开关包括第一组控制开关和第二组控制开关，且所述第一组控制开关和所述第二组控制开关并联连接于同一条数据线；
    通过所述数据线对所述多个显示区域施加对应的所述数据电压。
  9. 根据权利要求8所述的显示控制方法，其中，设置所述多个显示区域包括第一显示区域、第二显示区域和第三显示区域，所述第一组控制开关包括第一晶体管，所述第二组控制开关包括第二晶体管和第三晶体管；其中，
    所述第一晶体管的栅极与一条扫描线连接，源极与所述数据线连接，漏极与所述第一显示区域连接；
    所述第二晶体管的栅极与所述扫描线连接，源极与所述数据线连接，漏极与所述第二显示区域连接；
    所述第三晶体管的栅极与所述扫描线连接，源极与所述第二晶体管的漏极连接，漏极与所述第三显示区域连接。
  10. 根据权利要求9所述的显示控制方法，其中，设置所述子像素单元还包括公共电极线，所述第一晶体管与第四晶体管串联，其中，所述第四晶体管的源极与所述第一晶体管的漏极连接，漏极与所述公共电极线连接，栅极与所述扫描线连接。
  11. 根据权利要求9所述的显示控制方法，其中，设置所述子像素单元还包括公共电极线，所述第三晶体管与第五晶体管串联，其中，所述第五晶体管的源极与所述第三晶体管的漏极连接，漏极与所述公共电极线连接，栅极与所述扫描线连接。
  12. 根据权利要求9所述的显示控制方法，其中，设置所述第一显示区域为所述子像素单元的多个所述显示区域中显示面积最大的区域。
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