WO2017054264A1 - 一种goa电路及液晶显示器 - Google Patents

一种goa电路及液晶显示器 Download PDF

Info

Publication number
WO2017054264A1
WO2017054264A1 PCT/CN2015/092364 CN2015092364W WO2017054264A1 WO 2017054264 A1 WO2017054264 A1 WO 2017054264A1 CN 2015092364 W CN2015092364 W CN 2015092364W WO 2017054264 A1 WO2017054264 A1 WO 2017054264A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
terminal
goa
voltage limiting
circuit
Prior art date
Application number
PCT/CN2015/092364
Other languages
English (en)
French (fr)
Inventor
肖军城
赵莽
Original Assignee
深圳市华星光电技术有限公司
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司, 武汉华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/891,646 priority Critical patent/US9972273B2/en
Publication of WO2017054264A1 publication Critical patent/WO2017054264A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/22—Antistatic materials or arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a GOA circuit and a liquid crystal display.
  • Gate Driver On Array is a technology that uses the existing thin film transistor liquid crystal display Array process to make the Gate scan drive signal circuit on the Array substrate to realize the drive mode of Gate progressive scan.
  • the technical problem to be solved by the present invention is to provide a GOA circuit and a liquid crystal display, which can effectively avoid damage caused by large static electricity to the GOA circuit and improve the stability of the entire panel GOA circuit.
  • a technical solution adopted by the present invention is to provide a GOA circuit for a liquid crystal display, the GOA circuit including a potential pull-down processing circuit and a plurality of cascaded GOA sub-circuits, the potential pull-down processing
  • the circuit includes a first voltage limiting transistor (PTX), a second filter transistor PT), and a third transistor PTN.
  • the first voltage limiting transistor PTX is connected in series with the second filter transistor PTY and connected to an output of the initial scan signal STV signal.
  • the control terminal of the first voltage limiting transistor PTX and the first terminal of the third transistor PTN are respectively connected to the first power terminal, and the third transistor PTN is connected between the terminal and the control terminal of the third transistor PTN.
  • the second end is coupled to the GOA subcircuit.
  • the first end of the second filter transistor PTY is connected to the control end thereof and the output end of the STV signal, and the second end of the second filter transistor PTY and the first end of the first voltage limiting transistor PTX
  • the second terminal of the first voltage limiting transistor (PTX) is connected to the control terminal of the third transistor PTN.
  • the first voltage limiting transistor PTX, the second filtering transistor PTY, and the third transistor PTN are all PMOS transistors; the first end of the first voltage limiting transistor PTX is a source, and the second end thereof The first end of the second filter transistor PTY is a source, and the second end thereof is a drain; the first end of the third transistor PTN is a source, and the second end thereof is a drain.
  • the first voltage limiting transistor PTX, the third transistor PTN and the second filtering transistor PTY are both NTFT tubes, and the first end of the first voltage limiting transistor PTX is a drain and the second end thereof
  • the first end of the second filter transistor PTY is a drain, and the second end thereof is a source; the first end of the third transistor PTN is a drain, and the second end thereof is a source.
  • the potential pull-down processing circuit further includes a fourth transistor PTM, the first end of the fourth transistor PTM is connected to the second end of the third transistor PTN, and the control end of the fourth transistor PTM is A first end of the fourth transistor PTM is connected, and a second end of the fourth transistor PTM is connected to the GOA sub-circuit; wherein the fourth transistor (PTM) is of the same type as the third transistor PTN.
  • the potential pull-down processing circuit further includes a fourth transistor PTM, the first end of the fourth transistor PTM is connected to the first power terminal, and the control end is connected to the first end, and the second end thereof is The first terminal of the third transistor PTN is connected; wherein the fourth transistor PTM is of the same type as the third transistor PTN.
  • the first end of the first voltage limiting transistor PTX is connected to the output end of the STV signal, and the second end of the first voltage limiting transistor PTX is connected to the first end of the second filter transistor PTY.
  • the control end of the second filter transistor PTY is connected to the first end of the second filter transistor PTY, and the second end of the second filter transistor PTY is connected to the control end of the third transistor PTN.
  • the second end of the third transistor PTN of the potential pull-down processing circuit is respectively connected to each of the GOA sub-circuits of the third stage to the last stage of the COA circuit.
  • the GOA circuit includes a plurality of the potential pull-down processing circuits, and a second end of the third transistor PTN of each of the potential pull-down processing circuits and a GOA circuit of the third to last stage of the COA circuit A corresponding connection.
  • a liquid crystal display including an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate,
  • the array substrate includes the GOA circuit described in any of the above embodiments.
  • the array substrate includes the GOA circuit of any of the above.
  • the potential pull-down processing circuit of the present invention further includes a first voltage limiting transistor PTX and a second filtering transistor PTY in series with each other, and the first voltage limiting transistor PTX can effectively filter out negative static electricity in the STV signal and reduce negative The level of the static electricity, the second filter transistor PTY can filter out the positive static electricity in the STV signal, and the gate voltage of the third transistor PTN is reduced by the cooperation of the first voltage limiting transistor PTX and the second filter transistor PTY.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a plurality of GOA sub-circuit cascades of a GOA circuit of the present invention
  • FIG. 2 is a schematic diagram showing a specific circuit connection of a first embodiment of a GOA circuit of the present invention
  • 3 is a timing chart showing the operation of the first sub-circuit in the GOA circuit of the first embodiment of the present invention
  • FIG. 4 is a schematic waveform diagram of a first embodiment of a GOV circuit STV signal of the present invention.
  • FIG. 5 is a schematic diagram of a specific circuit connection of a second embodiment of the GOA circuit of the present invention.
  • Figure 6 is a waveform diagram showing a second embodiment of the STV signal of the GOA circuit of the present invention.
  • FIG. 7 is a schematic diagram showing a specific circuit connection of a third embodiment of the GOA circuit of the present invention.
  • FIG. 8 is a schematic structural diagram of a second embodiment of a plurality of GOA sub-circuits cascaded in a GOA circuit of the present invention.
  • FIG. 9 is a schematic diagram showing a specific circuit connection of a fourth embodiment of the GOA circuit of the present invention.
  • FIG. 10 is a schematic diagram showing a specific circuit connection of a fifth embodiment of the GOA circuit of the present invention.
  • FIG. 11 is a schematic diagram showing a specific circuit connection of a sixth embodiment of the GOA circuit of the present invention.
  • FIG. 12 is a schematic diagram showing a specific circuit connection of a seventh embodiment of the GOA circuit of the present invention.
  • Figure 13 is a schematic view showing the structure of an embodiment of the liquid crystal display of the present invention.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a plurality of GOA sub-circuit cascades of the GOA circuit of the present invention.
  • the GOA circuit of the present embodiment includes a potential pull-down processing circuit 101 and a plurality of cascaded GOA sub-circuits 102.
  • the potential pull-down processing circuit 101 is connected to each of the GOA sub-circuits of the third to last stages of the COA circuit.
  • FIG. 2 is a schematic diagram of a specific circuit connection of the first embodiment of the GOA circuit.
  • the GOA sub-circuit is any one of the third stage to the last stage of the GOA circuit, which is not limited herein.
  • the potential pull-down processing circuit 101 includes a transistor PTN
  • the GOA sub-circuit 202 includes a forward/reverse scan unit 100, an input control unit 200, a pull-up maintaining unit 300, an output control unit 400, a GAS signal action unit 500, and a bootstrap. Capacitor unit 600.
  • the forward and reverse scanning unit 100 is respectively connected to the pull-up maintaining unit 300 and the input control unit 200
  • the GAS signal applying unit 500 is connected to the pull-up maintaining unit 300, and the connection point is a common signal point P, to the GOA circuit.
  • the transistor PTN is a PMOS transistor
  • the drain of the transistor PTN is connected to the common signal point P
  • the gate control terminal of the transistor PTN is connected to the STV signal terminal
  • the source of the transistor PTN is connected to the The power control terminal, the transistor PTN control terminal GAS signal action unit 500, the bootstrap capacitor unit 600, and the output control unit 400 are commonly connected
  • the common connection terminal is the gate drive signal output terminal GATE terminal.
  • the forward and reverse scanning unit 100 is used to control the forward driving and the reverse driving of the GOA circuit.
  • the fifth transistor PT0, the sixth transistor PT1, the seventh transistor PT2, and the eighth transistor PT3 are included.
  • the gate of the fifth transistor PT0 receives the reverse scan control signal, and the source of the fifth transistor PT0 receives the next-stage GOA sub-circuit G_N.
  • the gate drive signal outputted by the GATE terminal of +1, the gate of the sixth transistor PT1 receives the forward scan control signal, and the source of the sixth transistor PT1 receives the gate of the GATE terminal output of the GOA sub-circuit G_N-1 of the previous stage.
  • the drains of the fifth transistor PT0 and the sixth transistor PT1 are connected to each other and connected to the input control unit 200, and the gate of the seventh transistor PT2 receives the reverse scan control signal, the source of the seventh transistor PT2 Receiving the first control clock CK_N+3, the gate of the eighth transistor PT3 receives the forward scan control signal, the source of the eighth transistor PT3 receives the second control clock CK_N+1, the seventh transistor PT2 and the eighth transistor PT3
  • the drains are connected to each other and connected to the pull-up maintaining unit 300.
  • the input control unit 200 is configured to control the input of the level transmission signal according to the level transfer clock control signal to complete charging of the gate signal point.
  • the ninth transistor PT4 is included, and the gate of the ninth transistor PT4 receives the first cascaded clock signal CK_N+2, and the source of the ninth transistor PT4 is connected to the drains of the fifth transistor PT0 and the sixth transistor PT1, respectively. The drain of the nine transistor PT4 is connected to the gate signal point.
  • the pull-up maintaining unit 300 is configured to control the gate signal point to maintain a predetermined level, that is, an inactive level, during the inactive period according to the common signal point P.
  • the tenth transistor PT5, the eleventh transistor PT6, the twelfth transistor PT8, the thirteenth transistor PT9, and the first capacitor C1 are included, and the gate of the tenth transistor PT5 is connected to the common signal point P, tenth
  • the source of the transistor PT5 is connected to the drain of the ninth transistor PT4, the drain of the tenth transistor PT5 is connected to the second power supply terminal VGH, the gate of the eleventh transistor PT6 and the drain of the ninth transistor PT4.
  • the source of the eleventh transistor PT6 is connected to the common signal point P
  • the drain of the eleventh transistor PT6 is connected to the second power terminal VGH
  • the gate of the twelfth transistor PT8 is connected to the first
  • the drains of the seven transistors PT2 and the eighth transistor PT3 are connected, the source of the twelfth transistor PT8 is connected to the first power supply terminal VGL, and the drain of the twelfth transistor PT8 is connected to the common signal point P
  • the thirteenth a gate of the transistor PT9 is connected to the common signal point P, a source of the thirteenth transistor PT9 is connected to the GATE terminal, and a drain of the thirteenth transistor PT9 is connected to a second power terminal VGH.
  • One end of the first capacitor C1 is connected to the second power terminal VGH
  • the other end of a capacitor C1 is connected to the common point P signal points.
  • the output control unit 400 is configured to control an output of a gate signal point corresponding to a gate signal point according to the level transmission clock signal.
  • a gate of the fourteenth transistor PT10 is connected to the gate signal point, and a drain of the fourteenth transistor PT10 is connected to a GATE terminal, the fourteenth transistor
  • the source of the PT 10 receives the second-stage clock CK_N, one end of the second capacitor C2 is connected to the gate signal point, and the other end of the second capacitor C2 is connected to the GATE terminal.
  • the GAS signal action unit 500 is for controlling the gate drive signal to be at an active level to effect charging of the horizontal scan line of the GOA sub-circuit.
  • the fifteenth transistor PT12 and the sixteenth transistor PT13 are included.
  • the gate of the fifteenth transistor PT12, the gate and the drain of the sixteenth transistor PT13 receive a GAS signal, and the drain of the fifteenth transistor PT12 is connected.
  • a second power supply terminal VGH a source of the fifteenth transistor PT12 is connected to the common signal point P, and a drain of the sixteenth transistor PT13 is connected to the GATE terminal;
  • the bootstrap capacitor unit 600 is used to lift the voltage of the gate signal point again.
  • the bootstrap capacitor Cloud includes one end of the bootstrap capacitor Cloud connected to the GATE end, and the other end of the bootstrap capacitor Cloud is grounded.
  • the GOA sub-circuit further includes a voltage stabilizing unit 700 for implementing voltage regulation of the gate signal point and leakage prevention of the gate signal point.
  • the voltage stabilizing unit 700 includes a seventeenth transistor PT7, and the seventeenth transistor PT7 is connected in series between the source and the gate signal point of the ninth transistor PT4, and the gate and negative voltage of the seventeenth transistor PT7 are constant.
  • the voltage source is connected, the drain of the seventeenth transistor PT7 is connected to the drain of the ninth transistor PT4, and the source of the seventeenth transistor PT7 is connected to the gate signal point.
  • the GOA sub-circuit further includes a pull-up auxiliary unit 800 for preventing leakage of the ninth transistor PT4 and the tenth transistor PT5 during charging of the gate signal point.
  • the pull-up auxiliary unit 800 includes an eighteenth transistor PT11, the gate of the eighteenth transistor PT11 is connected to the drains of the fifth transistor PT0 and the sixth transistor PT1, and the source of the eighteenth transistor PT11 is The common signal point is connected to point P, and the drain of the eighteenth transistor PT11 is connected to the positive voltage constant voltage source VGH.
  • the transistor PTN in the STV signal control potential pull-down processing circuit 101 is turned on, and the PTN transistor is turned on.
  • the low-level VGL signal is transmitted to the drain of the PTN transistor through the source of the PTN transistor.
  • the signal of the pole and the drain output is transmitted to the common signal point P of the circuit, and is used for the pull-down of the point P of the common signal point of the circuit and the reset of the Gate signal.
  • the potential pull-down of the point P of the common signal point is no longer existed due to the bootstrap. The problem of low potential maintenance caused by the presence of the capacitor unit 600.
  • FIG. 3 is a timing chart showing the operation of the GOA sub-circuit in the GOA circuit of the first embodiment of the present invention.
  • the third-level GOA sub-circuit is taken as an example.
  • the GOA circuit implements All The Gate On function outputs a low level signal to the gate drive signal G(2N+1) corresponding to each odd-level horizontal scanning line.
  • the GOA circuit completes All Gate After the On function, due to the presence of the bootstrap capacitor Cload, the gate drive signal corresponding to each odd-level horizontal scan line does not immediately become a high level, but will remain Cload Holding a low level signal.
  • the signal of the common signal point P of the third stage changes from the high level to the low level
  • the GATE (3) signal changes from the low level to the high level. level.
  • the GATE (3) signal is not in a state of maintaining a low potential. Since the GOA circuits of all subsequent stages add the same potential pull-down processing circuit, all Gate drive signals are at a high level before the clock signal comes, and will not affect the normal driving of the GOA circuit.
  • the first cascaded clock CK_N+1 and the second cascaded clock CK_N need not be compensated in advance, and can be directly controlled by the first cascaded clock CK_N+1.
  • the input of the first stage GOA sub-circuit controls the output of the first stage GOA through the second cascaded clock CK_N. There is no limit here.
  • the STV signal is generally designed to be the outermost part of the GOA during the design process of the layout, it is easily affected by the static electricity to cause deformation of the STV signal, as shown in FIG. 4, the upward positive static electricity and the direction of the STV signal.
  • the negative static electricity is large.
  • the STV signal only works once in one frame time, during the inactive period, the variation of the STV signal also affects the normal display of the panel.
  • the STV signal is applied to the entire GOA. The effect of the circuit,
  • the potential pull-down processing circuit 201 includes a first voltage limiting transistor (PTX) and a second filter transistor PTY in addition to the third transistor PTN.
  • PTX first voltage limiting transistor
  • PTY second filter transistor
  • the first voltage limiting transistor PTX and the second filter transistor PTY are connected in series and connected between the output end of the initial scan signal STV signal and the control end of the third transistor PTN, specifically, the first voltage limiting transistor PTX
  • the control terminal is connected to the first power terminal
  • the first end of the third transistor PTN is connected to the first power terminal
  • the second end of the third transistor PTN is connected to the GOA sub-circuit.
  • the first end of the second filter transistor PTY is respectively connected to its control terminal and the output end of the STV signal, and the second end of the second filter transistor (PTY) is connected to the first The first end of the voltage limiting transistor PTX is connected, and the second end of the first voltage limiting transistor (PTX) is connected to the control end of the third transistor PTN.
  • FIG. 5 is a schematic diagram of a specific circuit connection of the second embodiment of the GOA circuit of the present invention.
  • the first end of the first voltage limiting transistor PTX is connected to the output end of the STV signal, and the second end of the first end of the first voltage limiting transistor PTX is connected to the first end of the second filter transistor PTY
  • the control end of the second filter transistor PTY is connected to the first end of the second filter transistor PTY, and the second end of the second filter transistor PTY is connected to the control terminal of the third transistor PTN.
  • the first terminal of the first voltage limiting transistor PTX is a source, and the second end thereof is a drain;
  • the first end of the second filter transistor PTY is a source, and the second end thereof is a drain;
  • the first end of the third transistor PTN is a source, and the second end thereof is a drain.
  • the first power terminal is a low level signal VGL.
  • the STV signal inputs a low level signal to the second filter transistor PTY source and the control terminal gate, and is filtered by the second filter transistor PTY to turn the high voltage in the STV low level signal.
  • the electrostatic filter is filtered off, and the filtered signal is transmitted to the source of the first voltage limiting transistor PTX.
  • the first power terminal connected to the gate of the control terminal of the first voltage limiting transistor PTX is a low level VGL.
  • the first voltage-limiting transistor PTX is turned on, and the low-level signal input from the source is limited according to a predetermined voltage, thereby reducing the negative static electricity in the STV signal, so that the first voltage-limiting transistor PTX is passed.
  • the gate voltage of the drain terminal transmitted to the control terminal of the third transistor PTN is reduced to avoid damage of the third transistor PTN under the action of large static electricity.
  • FIG. 6 is a waveform diagram of a second embodiment of the STV signal of the GOA circuit of the present invention.
  • the positive static electricity of the STV signal input to the PTN is completely filtered out, and the negative static electricity is also controlled within an appropriate range.
  • the third transistor PTN is turned on, the source transmits the low-level signal of the first power supply terminal to its drain, and the drain transmits the signal to the common signal point P of the GOA sub-circuit.
  • the gate potential of the third transistor PTN is maintained at a low potential due to the presence of parasitic capacitance, and is continuously maintained at the point P of the common signal point.
  • the GATE stage transmits a signal to pull up the P point. At this time, the high resistance state of the gate of the third transistor PTN does not affect the normal operation of the GOA.
  • the GOA circuit can also be an NTFT circuit, that is, the transistors in the GOA circuit are all NTFT transistors.
  • FIG. 7 is a schematic diagram of a specific circuit connection of a third embodiment of the GOA circuit of the present invention.
  • the first voltage limiting transistor PTX, the third transistor PTN, and the second filtering transistor PTY are both NTFT tubes, the first end of the first voltage limiting transistor PTX is a drain, and the second end thereof is a source;
  • the first end of the filter transistor PTY is a drain, and the second end thereof is a source;
  • the first end of the third transistor PTN is a drain, and the second end thereof is a source.
  • the first power terminal is at a high level VGH, and the second power terminal is at a low level VGL.
  • FIG. 8 is a schematic structural diagram of a second embodiment of a plurality of GOA sub-circuit cascades of the GOA circuit of the present invention.
  • the GOA circuit includes a plurality of potential pull-down processing circuits 801, each of which is connected in one-to-one correspondence with the GOA sub-circuits from the third stage to the last stage.
  • the second end of the third transistor PTN of each of the potential pull-down processing circuits 801 is connected in one-to-one correspondence with the GOA circuits of the third to last stages of the COA circuit. There is no limit here.
  • FIG. 9 is a schematic diagram of a specific circuit connection of a fourth embodiment of the GOA circuit of the present invention.
  • the potential pull-down circuit of the present embodiment further includes a fourth transistor PTM, wherein the fourth transistor PTM and the third transistor PTN cooperate with each other to solve the GOA.
  • the potential of the circuit is maintained.
  • the GOA circuit Take the GOA circuit as a PMOS circuit as an example.
  • a gate and a source of the fourth transistor PTM are respectively connected to a drain of the third transistor PTN, and a drain of the fourth transistor (PTM) is connected to the GOA sub-circuit.
  • FIG. 10 is a schematic diagram of a specific circuit connection of a fifth embodiment of the GOA circuit of the present invention.
  • the GOA circuit of the present embodiment is still a PMOS circuit.
  • the source of the fourth transistor PTM is connected to the first power supply terminal VGL, the control terminal gate is connected to the source thereof, and the drain thereof is connected to the source of the third transistor PTN.
  • FIGS. 11 and 12 When the GOA circuit is an NTFT circuit, as shown in FIGS. 11 and 12.
  • Figure 11 is a block diagram showing the structure of a sixth embodiment of the GOA circuit of the present invention.
  • Figure 12 is a block diagram showing the structure of a seventh embodiment of the GOA circuit of the present invention.
  • FIG. 11 is a schematic diagram showing a specific circuit connection of a sixth embodiment of the GOA circuit of the present invention.
  • the drain of the fourth transistor PTM is connected to the source of the third transistor PTN
  • the gate is connected to the drain of the fourth transistor PTM
  • the source is connected to the common signal point P of the GOA sub-circuit.
  • FIG. 12 is a schematic diagram showing a specific circuit connection of a seventh embodiment of the GOA circuit of the present invention.
  • the drain of the fourth transistor PTM is connected to the first power supply terminal VGH, the gate is connected to the drain thereof, and the source is connected to the drain of the third transistor PTN.
  • the GOA circuit of the present invention includes a potential pull-down processing circuit connected to the STV signal, which can pull the potential of the common signal point P to a low level when the STV signal outputs a low level, effectively solving the work of the GOA circuit. Maintenance problems due to the bootstrap capacitor II.
  • the potential pull-down processing circuit of the present invention further includes a first voltage limiting transistor PTX and a second filtering transistor PTY in series with each other, and the first voltage limiting transistor PTX can effectively filter out negative static electricity in the STV signal and reduce the level of negative static electricity.
  • the second filter transistor PTY can filter out the positive static electricity in the STV signal, and the gate voltage of the third transistor PTN is reduced by the cooperation of the first voltage limiting transistor PTX and the second filter transistor PTY, effectively avoiding the STV signal.
  • the damage of the third transistor PTN by the large static electricity can also effectively avoid the damage caused by the large static electricity in the STV signal flowing into the GOA sub-circuit through the third transistor PTN into the GOA sub-circuit, thereby improving the stability of the GOA circuit.
  • the present invention also provides a liquid crystal display, as shown in FIG. 13, which is a schematic structural view of an embodiment of the liquid crystal display of the present invention.
  • the liquid crystal display device includes an array substrate 1301 and a color filter substrate 1302, and a liquid crystal layer 1303 disposed between the array substrate 1301 and the color filter substrate 1302.
  • the array substrate 1301 includes the GOA circuit of any of the above embodiments. I will not repeat them here.
  • the array substrate of the liquid crystal display device of the present invention includes a GOA circuit.
  • the GOA circuit includes a potential pull-down processing circuit connected to the STV signal, which can pull the potential of the common signal point P to a low level when the STV signal outputs a low level, effectively solving the maintenance problem caused by the bootstrap capacitor 2 when the GOA circuit operates.
  • the potential pull-down processing circuit of the present invention further includes a first voltage limiting transistor PTX and a second filtering transistor PTY in series with each other, and the first voltage limiting transistor PTX can effectively filter out negative static electricity in the STV signal and reduce the level of negative static electricity.
  • the second filter transistor PTY can filter out the positive static electricity in the STV signal, and the gate voltage of the third transistor PTN is reduced by the cooperation of the first voltage limiting transistor PTX and the second filter transistor PTY, effectively avoiding the STV signal.
  • the damage of the third transistor PTN by the large static electricity can also effectively avoid the damage caused by the large static electricity in the STV signal flowing into the GOA sub-circuit through the third transistor PTN into the GOA sub-circuit, thereby improving the stability of the GOA circuit.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种GOA电路及液晶显示器，该GOA电路包括电位下拉处理电路（101）和多个级联的GOA子电路（102），其中包括N级GOA子电路（102），所述电位下拉处理电路（101）包括第一限压晶体管（PTX）、第二滤波晶体管(PTY)以及第三晶体管（PTN），所述第一限压晶体管（PTX）与所述第二滤波晶体管(PTY)串联后连接在初始扫描信号STV信号的输出端与所述第三晶体管（PTN）的控制端之间，所述第一限压晶体管（PTX）的控制端与所述第三晶体管（PTN）的第一端分别与第一电源端（VGL）连接，所述第三晶体管（PTN）的第二端与所述GOA子电路（102）连接。通过上述方式，能够有效避免大静电对GOA电路带来的损伤，提高整个面板GOA电路的稳定性。

Description

一种GOA电路及液晶显示器
【技术领域】
本发明涉及液晶显示领域，特别是涉及一种GOA电路及液晶显示器。
【背景技术】
Gate Driver On Array，简称GOA，也就是利用现有薄膜晶体管液晶显示器Array制程将Gate行扫描驱动信号电路制作在Array基板上，实现对Gate逐行扫描的驱动方式的一项技术。
随着低温多晶硅（LTPS）半导体薄膜晶体管的发展，而且由于LTPS半导体本身超高载流子迁移率的特性，相应的面板周边集成电路也成为大家关注的焦点，并且很多人投入到System on Panel（SOP）的相关技术研究，并逐步成为现实。
液晶显示器在开启的时候，要进行一次AllGateOn的初始化操作，以将GOA电路中所有的扫描Gate信号的电压拉至一个低电平，以实现显示器的全黑或全白，保证显示画面的质量。在初始化之后，要完成正常扫描工作，Gate信号是需要在一定时期保持高电平。但是由于Gate信号的输出端自举电容单元的存在，会存在维持的问题。
【发明内容】
本发明主要解决的技术问题是提供一种GOA电路及液晶显示器，能够有效避免大静电对GOA电路带来的损伤，提高整个面板GOA电路的稳定性。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种GOA电路，用于液晶显示器，所述GOA电路包括电位下拉处理电路和多个级联的GOA子电路，所述电位下拉处理电路包括第一限压晶体管(PTX)、第二滤波晶体管PT）以及第三晶体管PTN，所述第一限压晶体管PTX与所述第二滤波晶体管PTY串联后连接在初始扫描信号STV信号的输出端与所述第三晶体管PTN的控制端之间，所述第一限压晶体管PTX的控制端与所述第三晶体管PTN的第一端分别与第一电源端连接，所述第三晶体管PTN的第二端与所述GOA子电路连接。
其中，所述第二滤波晶体管PTY的第一端分别与其控制端以及所述STV信号的输出端连接，所述第二滤波晶体管PTY的第二端与所述第一限压晶体管PTX的第一端连接，所述第一限压晶体管(PTX)的第二端与所述第三晶体管PTN的控制端连接。
其中，所述第一限压晶体管PTX、所述第二滤波晶体管PTY以及所述第三晶体管PTN均为PMOS晶体管；所述第一限压晶体管PTX的第一端为源极，其第二端为漏极；所述第二滤波晶体管PTY的第一端为源极，其第二端为漏极；所述第三晶体管PTN的第一端为源极，其第二端为漏极。
其中，所述第一限压晶体管PTX、所述第三晶体管PTN和所述第二滤波晶体管PTY均为NTFT管，所述第一限压晶体管PTX的第一端为漏极，其第二端为源极；所述第二滤波晶体管PTY的第一端为漏极，其第二端为源极；所述第三晶体管PTN的第一端为漏极，其第二端为源极。
其中，所述电位下拉处理电路还包括第四晶体管PTM，所述第四晶体管PTM的第一端与所述第三晶体管PTN的第二端连接，所述第四晶体管PTM的控制端与所述述第四晶体管PTM的第一端连接，所述第四晶体管PTM的第二端与所述GOA子电路连接；其中，所述第四晶体管（PTM）与所述第三晶体管PTN的类型相同。
其中，所述电位下拉处理电路还包括第四晶体管PTM，所述第四晶体管PTM的第一端与所述第一电源端连接，其控制端与所述第一端连接，其第二端与所述第三晶体管PTN的第一端连接；其中，所述第四晶体管PTM与所述第三晶体管PTN的类型相同。
其中，所述第一限压晶体管PTX的第一端与所述STV信号的输出端连接，所述第一限压晶体管PTX的第二端与所述第二滤波晶体管PTY的第一端连接，所述第二滤波晶体管PTY的控制端与所述第二滤波晶体管PTY的第一端连接，所述第二滤波晶体管PTY的第二端与所述第三晶体管PTN的控制端连接。
其中，所述电位下拉处理电路的所述第三晶体管PTN的第二端与所述COA电路的第三级至最后一级的每个所述GOA子电路分别连接。
其中，所述GOA电路包括多个所述电位下拉处理电路，每个所述电位下拉处理电路的第三晶体管PTN的第二端与所述COA电路的第三级至最后一级的GOA电路一一对应连接。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示器，包括阵列基板、彩膜基板以及设置在所述阵列基板以及所述彩膜基板之间的液晶层，所述阵列基板包括上述任意实施方式所述的GOA电路。所述阵列基板包括上述任一项所述的GOA电路。
区别于现有技术，本发明电位下拉处理电路还包括相互串联的第一限压晶体管PTX、第二滤波晶体管PTY，第一限压晶体管PTX能够有效d过滤掉STV信号中的负静电，降低负静电的电平，第二滤波晶体管PTY能够过滤掉STV信号中的正静电，在第一限压晶体管PTX和第二滤波晶体管PTY的配合下，使得进入第三晶体管PTN的栅极电压减小，有效避免STV信号中的大静电对第三晶体管PTN的损伤，也能够有效避免STV信号中的大静电通过第三晶体管PTN流入到GOA子电路中对GOA子电路带来的损伤，提高GOA电路的稳定性。
【附图说明】
图1是本发明GOA电路多个GOA子电路级联第一实施方式的结构示意图；
图2是本发明GOA电路第一实施方式的具体电路连接示意图；
图3是本发明第一实施方式的GOA电路中的第一子电路的工作时序图；
图4是本发明GOA电路STV信号的第一实施方式的波形示意图；
图5是本发明GOA电路第二实施方式的具体电路连接示意图；
图6是本发明GOA电路STV信号的第二实施方式波形示意图；
图7是本发明GOA电路第三实施方式的具体电路连接示意图；
图8是本发明GOA电路多个GOA子电路级联第二实施方式的结构示意图；
图9是本发明GOA电路第四实施方式的具体电路连接示意图；
图10是本发明GOA电路第五实施方式的具体电路连接示意图；
图11是本发明GOA电路第六实施方式的具体电路连接示意图；
图12是本发明GOA电路第七实施方式的具体电路连接示意图；
图13是本发明液晶显示器一实施方式的结构示意图。
【具体实施方式】
在说明书及权利要求书当中使用了某些词汇来指称特定的组件，所属领域中的技术人员应可理解，制造商可能会用不同的名词来称呼同样的组件。本说明书及权利要求书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的基准。下面结合附图和实施例对本发明进行详细说明。
为了解决GOA电路的维持问题，本发明提供了一种GOA电路，如图1所示，图1是本发明本发明GOA电路多个GOA子电路级联第一实施方式的结构示意图。本实施方式的GOA电路包括电位下拉处理电路101以及多个级联的GOA子电路102。其中，在本实施方式中，电位下拉处理电路101与所述COA电路的第三级至最后一级的每个所述GOA子电路分别连接。进一步的参阅图2，图2是GOA电路第一实施方式的具体电路连接示意图。所述GOA子电路为GOA电路的第三级至最后一级的中的任一级，在此不做限定。
如图2所示，电位下拉处理电路101包括晶体管PTN，GOA子电路202包括正反扫描单元100、输入控制单元200、上拉维持单元300、输出控制单元400、GAS信号作用单元500和自举电容单元600。正反扫描单元100分别与所述上拉维持单元300、输入控制单元200连接，所述GAS信号作用单元500与所述上拉维持单元300连接，连接点为公共信号点P点，以GOA电路为PMOS电路为例来说明，晶体管PTN为PMOS管，晶体管PTN的漏极连接于所述公共信号点P点，晶体管PTN的栅极控制端连接STV信号端，晶体管PTN的源极连接于所述电源控制端，晶体管PTN控制端GAS信号作用单元500、自举电容单元600、与输出控制单元400共同连接，共同连接端为栅极驱动信号输出端GATE端。
其中，正反扫描单元100用于控制GOA电路的正向驱动和反向驱动。包括第五晶体管PT0、第六晶体管PT1、第七晶体管PT2和第八晶体管PT3，第五晶体管PT0的栅极接收反向扫描控制信号，第五晶体管PT0的源极接收下一级GOA子电路G_N+1的GATE端输出的栅极驱动信号，第六晶体管PT1的栅极接收正向扫描控制信号，第六晶体管PT1的源极接收上一级GOA子电路G_N-1的GATE端输出的栅极驱动信号，第五晶体管PT0和第六晶体管PT1的漏极相互连接后与所述输入控制单元200连接，第七晶体管PT2的栅极接收所述反向扫描控制信号，第七晶体管PT2的源极接收第一控制时钟CK_N+3，第八晶体管PT3的栅极接收所述正向扫描控制信号，第八晶体管PT3的源极接收第二控制时钟CK_N+1，第七晶体管PT2和第八晶体管PT3的漏极相互连接后与上拉维持单元300连接。
输入控制单元200用于根据级传时钟控制信号控制级传信号的输入以完成对栅极信号点的充电。包括第九晶体管PT4，第九晶体管PT4的栅极接收第一级联时钟信号CK_N+2，所述第九晶体管PT4的源极分别与第五晶体管PT0、第六晶体管PT1的漏极连接，第九晶体管PT4的漏极与栅极信号点连接。
上拉维持单元300用于根据公共信号点P点控制栅极信号点在非作用期间保持预定电平也即无效电平。包括第十晶体管PT5、第十一晶体管PT6、第十二晶体管PT8、第十三晶体管PT9和第一电容C1，所述第十晶体管PT5的栅极与所述公共信号点P点连接，第十晶体管PT5的源极与所述第九晶体管PT4的漏极连接，第十晶体管PT5的漏极与第二电源端VGH连接，所述第十一晶体管PT6的栅极与第九晶体管PT4的漏极连接，第十一晶体管PT6的源极与所述公共信号点P点连接，所述第十一晶体管PT6的漏极与第二电源端VGH连接，第十二晶体管PT8的栅极与所述第七晶体管PT2、第八晶体管PT3的漏极连接，第十二晶体管PT8的源极与第一电源端VGL连接，第十二晶体管PT8的漏极与所述公共信号点P点连接，第十三晶体管PT9的栅极与所述公共信号点P点连接，所述第十三晶体管PT9的源极与所述GATE端连接，第十三晶体管PT9的漏极与第二电源端VGH连接，所述第一电容C1的一端与第二电源端VGH连接，所述第一电容C1的另一端与所述公共信号点P点连接。
所述输出控制单元400用于根据级传时钟信号控制与栅极信号点对应的栅极信号点的输出。包括第十四晶体管PT10和第二电容C2，第十四晶体管PT10的栅极与所述栅极信号点连接，所述第十四晶体管PT10的漏极与GATE端连接，所述第十四晶体管PT10的源极接收第二级传时钟CK_N，所述第二电容C2的一端与所述栅极信号点连接，所述第二电容C2的另一端与所述GATE端连接。
GAS信号作用单元500用于控制栅极驱动信号处于有效电平，以实现GOA子电路的水平扫描线的充电。包括第十五晶体管PT12和第十六晶体管PT13，所述第十五晶体管PT12的栅极、第十六晶体管PT13的栅极和漏极接收GAS信号，所述第十五晶体管PT12的漏极连接第二电源端VGH，所述第十五晶体管PT12的源极连接所述公共信号点P点，所述第十六晶体管PT13的漏极连接所述GATE端；
所述自举电容单元600用于对栅极信号点的电压进行再次抬升。包括自举电容Cloud，所述自举电容Cloud的一端与所述GATE端连接，所述自举电容Cloud的另一端与接地。
优选地，GOA子电路进一步还包括稳压单元700，稳压单元700用于实现栅极信号点的稳压以及栅极信号点的漏电防治。具体来说，稳压单元700包括第十七晶体管PT7，第十七晶体管PT7串接于第九晶体管PT4的源极与栅极信号点之间，第十七晶体管PT7的栅极与负压恒压源连接，第十七晶体管PT7的漏极与第九晶体管PT4的漏极连接，第十七晶体管PT7的源极与栅极信号点连接。
优选地，GOA子电路进一步包括上拉辅助单元800，上拉辅助单元800用于防止第九晶体管PT4和第十晶体管PT5在对栅极信号点进行充电的过程中出现漏电的问题。具体来说，上拉辅助单元800包括第十八晶体管PT11，第十八晶体管PT11的栅极与第五晶体管PT0、第六晶体管PT1的漏极连接，第十八晶体管PT11的源极与所述公共信号点P点连接，第十八晶体管PT11的漏极与正压恒压源VGH连接。
具体地，在GAS信号作用单元500工作之前，STV信号控制电位下拉处理电路101中的晶体管PTN导通，PTN晶体管打开，此时低电平VGL信号经过PTN晶体管的源极传输到PTN晶体管的漏极，漏极输出的信号传输到电路的公共信号点P点，用于电路公共信号点P点的下拉和Gate信号的Reset，在实现公共信号点P点的电位下拉，不再存在由于自举电容单元600的存在而导致的低电位维持的问题。
如图3所示，图3是本发明第一实施方式的GOA电路中的GOA子电路的工作时序图。结合图2和图3，以第三级GOA子电路为例来说。当GAS信号有效，即GAS信号为低电平信号时，GOA电路实现All Gate On功能，与各奇数级水平扫描线对应的栅极驱动信号G（2N+1）输出低电平信号。当GOA电路完成All Gate On功能后，由于自举电容Cload的存在，与各奇数级水平扫描线对应的栅极驱动信号不会马上变为高电平，而会保持Cload holding的低电平信号。当STV信号的低电平信号来临时，第三级的公共信号点P点P(3)的信号由高电平变成低电平状态，GATE(3)信号从低电平变成高电平。此时，GATE(3)信号不处于维持低电位的状态。由于后面所有级数的GOA电路都添加了相同的电位下拉处理电路，因此在时钟信号来临之前，所有的Gate驱动信号都处于高电平，不会影响GOA电路的正常驱动。
另外，由于STV信号对于公共信号点P点的Reset作用，也不需要对第一级联时钟CK_N+1和第二级联时钟CK_N提前进行补偿，可以直接通过第一级联时钟CK_N+1控制第一级GOA子电路的输入，通过第二级联时钟CK_N控制第一级GOA的输出。在此不做限定。
进一步地，由于在版图的设计过程中，STV信号一般设计在GOA的最外面，因此，很容易受到静电的影响造成STV信号的变形，如图4所示，STV信号的向上的正静电和向下的负静电都较大。虽然STV信号在一帧的时间内只工作一次，然而在非作用期间，STV信号的变异也会影响面板的正常显示。为了克服在利用公共信号点P点处理单元的电路设计解决电位维持的问题时，STV信号对整个GOA 电路造成的影响，
进一步参阅图2，电位下拉处理电路201除了包括第三晶体管PTN，还包括第一限压晶体管(PTX)、第二滤波晶体管PTY。
该第一限压晶体管PTX与所述第二滤波晶体管PTY串联后连接在初始扫描信号STV信号的输出端与所述第三晶体管PTN的控制端之间，具体地，第一限压晶体管PTX的控制端与第一电源端连接，第三晶体管PTN的第一端与第一电源端连接，第三晶体管PTN的第二端与所述GOA子电路连接。
具体地，如图2所示，第二滤波晶体管PTY的第一端分别与其控制端以及所述STV信号的输出端连接，所述第二滤波晶体管（PTY）的第二端与所述第一限压晶体管PTX的第一端连接，所述第一限压晶体管(PTX)的第二端与所述第三晶体管PTN的控制端连接。
在另一个方式中，如图5所示，图5是本发明GOA电路第二实施方式的具体电路连接示意图。第一限压晶体管PTX的第一端与STV信号的输出端连接，所述第一限压晶体管PTX的第一端的第二端与所述第二滤波晶体管PTY的第一端连接，所述第二滤波晶体管PTY的控制端与所述第二滤波晶体管PTY的第一端连接，所述第二滤波晶体管PTY的第二端与所述第三晶体管PTN的控制端连接。
在上述两个实施方式中，以GOA电路为PMOS电路为例，当所有的晶体管为PMOS晶体管时，第一限压晶体管PTX的第一端为源极，其第二端为漏极；所述第二滤波晶体管PTY的第一端为源极，其第二端为漏极；所述第三晶体管PTN的第一端为源极，其第二端为漏极。第一电源端为低电平信号VGL。
具体地，在STV信号打开后，STV信号输入一个低电平信号至第二滤波晶体管PTY源极和控制端栅极，经过第二滤波晶体管PTY的滤波，将STV低电平信号中的高电平即正静电过滤掉，过滤后的信号传输至经过第一限压晶体管PTX的源极，此时，第一限压晶体管PTX的控制端栅极连接的第一电源端为低电平VGL，在低电平信号VGL的驱动下，第一限压晶体管PTX打开，将源极输入的低电平信号按照预定电压限压后，降低STV信号中的负静电，使得经过第一限压晶体管PTX漏极传输至第三晶体管PTN的控制端栅极的栅极电压减小，避免第三晶体管PTN在大静电作用下的损伤。
如图6所示，图6是本发明GOA电路STV信号的第二实施方式波形示意图。由图6可以看出，输入PTN的STV信号的正静电被完全过滤掉，负静电也被控制在适当范围内。在低电平信号的驱动下，第三晶体管PTN打开，源极将第一电源端的低电平信号传输至其漏极，漏极再将信号传输至GOA子电路的公共信号点P点。在STV信号的低电平作用完毕后，第三晶体管PTN的栅极电位由于寄生电容的存在会维持在偏低的电位，用于公共信号点P点的持续维持。当GOA电路开始工作时，GATE级传信号进行P点的上拉，此时，第三晶体管PTN的栅极的高阻态不会影响GOA的正常工作。
在其他实施方式中，GOA电路也可以为NTFT电路，即GOA电路中的晶体管均为NTFT晶体管。如图7所示，图7为本发明GOA电路第三实施方式的具体电路连接示意图。当第一限压晶体管PTX、第三晶体管PTN和第二滤波晶体管PTY均为NTFT管时，所述第一限压晶体管PTX的第一端为漏极，其第二端为源极；第二滤波晶体管PTY的第一端为漏极，其第二端为源极；所述第三晶体管PTN的第一端为漏极，其第二端为源极。第一电源端为高电平VGH，第二电源端为低电平VGL。
在另一个实施方式中，如图8所示，图8是本发明GOA电路多个GOA子电路级联第二实施方式的结构示意图。GOA电路包括多个电位下拉处理电路801，每个所述电位下拉处理电路801与从第三级到最后一级的GOA子电路一一对应连接。具体地，每个所述电位下拉处理电路801的第三晶体管PTN的第二端与COA电路的第三级至最后一级的GOA电路一一对应连接。在此不做限定。
如图9所示，图9是本发明GOA电路第四实施方式的具体电路连接示意图。本实施方式的GOA电路与上述任一实施方式的GOA电路的区别在于，本实施方式的电位下拉电路还包括第四晶体管PTM，其中，第四晶体管PTM与第三晶体管PTN相互配合，共同解决GOA电路的电位维持问题。以GOA电路为PMOS电路为例。第四晶体管PTM的栅极和源极分别与第三晶体管PTN的漏极连接，所述第四晶体管（PTM）的漏极与所述GOA子电路连接。
在另一个实施方式中，如图10所示，图10为本发明GOA电路第五实施方式的具体电路连接示意图。本实施方式的GOA电路仍为PMOS电路。第四晶体管PTM的源极与所述第一电源端VGL连接，其控制端栅极与其源极相连接，其漏极与所述第三晶体管PTN的源极连接。
当GOA电路为NTFT电路时，如图11和图12所示。图11是本发明GOA电路第六实施方式的结构示意图。图12是本发明GOA电路第七实施方式的结构示意图。
如图11所示，图11是本发明GOA电路第六实施方式的具体电路连接示意图。本实施方式中第四晶体管PTM的漏极与第三晶体管PTN的源极连接，栅极与第四晶体管PTM的漏极连接，源极与GOA子电路的公共信号点P点连接。
如图12所示，图12是本发明GOA电路第七实施方式的具体电路连接示意图。本实施方式中第四晶体管PTM的漏极与第一电源端VGH连接，栅极与其漏极连接，源极与第三晶体管PTN的漏极连接。
区别于现有技术，本发明的GOA电路包括与STV信号连接的电位下拉处理电路，能够在STV信号输出低电平时将公共信号点P点的电位拉成低电平，有效解决GOA电路工作时由于自举电容二产生的维持问题。另外本发明电位下拉处理电路还包括相互串联的第一限压晶体管PTX、第二滤波晶体管PTY，第一限压晶体管PTX能够有效d过滤掉STV信号中的负静电，降低负静电的电平，第二滤波晶体管PTY能够过滤掉STV信号中的正静电，在第一限压晶体管PTX和第二滤波晶体管PTY的配合下，使得进入第三晶体管PTN的栅极电压减小，有效避免STV信号中的大静电对第三晶体管PTN的损伤，也能够有效避免STV信号中的大静电通过第三晶体管PTN流入到GOA子电路中对GOA子电路带来的损伤，提高GOA电路的稳定性。
本发明还提供一种液晶显示器，如图13所示，图13是本发明液晶显示器一实施方式的结构示意图。液晶显示装置包括相对设置的阵列基板1301以及彩膜基板1302，还包括设置在阵列基板1301和彩膜基板1302之间的液晶层1303，其中，阵列基板1301上包括上述任意实施方式的GOA电路，在此不再赘述。
区别于现有技术，本发明液晶显示装置的阵列基板包括GOA电路， GOA电路包括与STV信号连接的电位下拉处理电路，能够在STV信号输出低电平时将公共信号点P点的电位拉成低电平，有效解决GOA电路工作时由于自举电容二产生的维持问题。另外本发明电位下拉处理电路还包括相互串联的第一限压晶体管PTX、第二滤波晶体管PTY，第一限压晶体管PTX能够有效d过滤掉STV信号中的负静电，降低负静电的电平，第二滤波晶体管PTY能够过滤掉STV信号中的正静电，在第一限压晶体管PTX和第二滤波晶体管PTY的配合下，使得进入第三晶体管PTN的栅极电压减小，有效避免STV信号中的大静电对第三晶体管PTN的损伤，也能够有效避免STV信号中的大静电通过第三晶体管PTN流入到GOA子电路中对GOA子电路带来的损伤，提高GOA电路的稳定性。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种GOA电路，用于液晶显示器，其中，所述GOA电路包括电位下拉处理电路和多个级联的GOA子电路，
    所述电位下拉处理电路包括第一限压晶体管、第二滤波晶体管以及第三晶体管，所述第一限压晶体管与所述第二滤波晶体管串联后连接在初始扫描信号STV信号的输出端与所述第三晶体管的控制端之间，所述第一限压晶体管的控制端与所述第三晶体管的第一端分别与第一电源端连接，所述第三晶体管的第二端与所述GOA子电路连接。
  2. 根据权利要求1所述的GOA电路，其中，所述第二滤波晶体管的第一端分别与其控制端以及所述STV信号的输出端连接，所述第二滤波晶体管的第二端与所述第一限压晶体管的第一端连接，所述第一限压晶体管的第二端与所述第三晶体管的控制端连接。
  3. 根据权利要求2所述的GOA电路，其中，所述第一限压晶体管、所述第二滤波晶体管以及所述第三晶体管均为PMOS晶体管；所述第一限压晶体管的第一端为源极，其第二端为漏极；所述第二滤波晶体管的第一端为源极，其第二端为漏极；所述第三晶体管的第一端为源极，其第二端为漏极。
  4. 根据权利要求2所述的GOA电路，其中，所述第一限压晶体管、所述第三晶体管和所述第二滤波晶体管均为NTFT管，所述第一限压晶体管的第一端为漏极，其第二端为源极；所述第二滤波晶体管的第一端为漏极，其第二端为源极；所述第三晶体管的第一端为漏极，其第二端为源极。
  5. 根据权利要求3所述的GOA电路，其中，所述电位下拉处理电路还包括第四晶体管，所述第四晶体管的第一端与所述第三晶体管的第二端连接，所述第四晶体管的控制端与所述述第四晶体管的第一端连接，所述第四晶体管的第二端与所述GOA子电路连接；其中，所述第四晶体管与所述第三晶体管的类型相同。
  6. 根据权利要求4所述的GOA电路，其中，所述电位下拉处理电路还包括第四晶体管，所述第四晶体管的第一端与所述第三晶体管的第二端连接，所述第四晶体管的控制端与所述述第四晶体管的第一端连接，所述第四晶体管的第二端与所述GOA子电路连接；其中，所述第四晶体管与所述第三晶体管的类型相同。
  7. 根据权利要求3所述的GOA电路，其中，所述电位下拉处理电路还包括第四晶体管，所述第四晶体管的第一端与所述第一电源端连接，其控制端与所述第一端连接，其第二端与所述第三晶体管的第一端连接；其中，所述第四晶体管与所述第三晶体管的类型相同。
  8. 根据权利要求4所述的GOA电路，其中，所述电位下拉处理电路还包括第四晶体管，所述第四晶体管的第一端与所述第一电源端连接，其控制端与所述第一端连接，其第二端与所述第三晶体管的第一端连接；其中，所述第四晶体管与所述第三晶体管的类型相同。
  9. 根据权利要求1所述的GOA电路，其中，所述第一限压晶体管的第一端与所述STV信号的输出端连接，所述第一限压晶体管的第二端与所述第二滤波晶体管的第一端连接，所述第二滤波晶体管的控制端与所述第二滤波晶体管的第一端连接，所述第二滤波晶体管的第二端与所述第三晶体管的控制端连接。
  10. 根据权利要求1所述的GOA电路，其中，所述电位下拉处理电路的所述第三晶体管的第二端与所述COA电路的第三级至最后一级的每个所述GOA子电路分别连接。
  11. 根据权利要求1所述的GOA电路，其中，所述GOA电路包括多个所述电位下拉处理电路，每个所述电位下拉处理电路的第三晶体管的第二端与所述COA电路的第三级至最后一级的GOA电路一一对应连接。
  12. 一种液晶显示器，包括阵列基板、彩膜基板以及设置在所述阵列基板以及所述彩膜基板之间的液晶层，其中，所述阵列基板包括GOA电路；所述GOA电路包括电位下拉处理电路和多个级联的GOA子电路，
    所述电位下拉处理电路包括第一限压晶体管、第二滤波晶体管以及第三晶体管，所述第一限压晶体管与所述第二滤波晶体管串联后连接在初始扫描信号STV信号的输出端与所述第三晶体管的控制端之间，所述第一限压晶体管的控制端与所述第三晶体管的第一端分别与第一电源端连接，所述第三晶体管的第二端与所述GOA子电路连接。
  13. 根据权利要求12所述的液晶显示器，其中，所述第二滤波晶体管的第一端分别与其控制端以及所述STV信号的输出端连接，所述第二滤波晶体管的第二端与所述第一限压晶体管的第一端连接，所述第一限压晶体管的第二端与所述第三晶体管的控制端连接。
  14. 根据权利要求13所述的液晶显示器，其中，所述第一限压晶体管、所述第二滤波晶体管以及所述第三晶体管均为PMOS晶体管；所述第一限压晶体管的第一端为源极，其第二端为漏极；所述第二滤波晶体管的第一端为源极，其第二端为漏极；所述第三晶体管的第一端为源极，其第二端为漏极。
  15. 根据权利要求13所述的液晶显示器，，其中，所述第一限压晶体管、所述第三晶体管和所述第二滤波晶体管均为NTFT管，所述第一限压晶体管的第一端为漏极，其第二端为源极；所述第二滤波晶体管的第一端为漏极，其第二端为源极；所述第三晶体管的第一端为漏极，其第二端为源极。
  16. 根据权利要求14所述的液晶显示器，其中，所述电位下拉处理电路还包括第四晶体管，所述第四晶体管的第一端与所述第三晶体管的第二端连接，所述第四晶体管的控制端与所述述第四晶体管的第一端连接，所述第四晶体管的第二端与所述GOA子电路连接；其中，所述第四晶体管与所述第三晶体管的类型相同。
  17. 根据权利要求15所述的液晶显示器，其中，所述电位下拉处理电路还包括第四晶体管，所述第四晶体管的第一端与所述第三晶体管的第二端连接，所述第四晶体管的控制端与所述述第四晶体管的第一端连接，所述第四晶体管的第二端与所述GOA子电路连接；其中，所述第四晶体管与所述第三晶体管的类型相同。
  18. 根据权利要求14所述的液晶显示器，其中，所述电位下拉处理电路还包括第四晶体管，所述第四晶体管的第一端与所述第一电源端连接，其控制端与所述第一端连接，其第二端与所述第三晶体管的第一端连接；其中，所述第四晶体管与所述第三晶体管的类型相同。
  19. 根据权利要求15所述的液晶显示器，其中，所述电位下拉处理电路还包括第四晶体管，所述第四晶体管的第一端与所述第一电源端连接，其控制端与所述第一端连接，其第二端与所述第三晶体管的第一端连接；其中，所述第四晶体管与所述第三晶体管的类型相同。
  20. 根据权利要求12所述的液晶显示器，其中，所述第一限压晶体管的第一端与所述STV信号的输出端连接，所述第一限压晶体管的第二端与所述第二滤波晶体管的第一端连接，所述第二滤波晶体管的控制端与所述第二滤波晶体管的第一端连接，所述第二滤波晶体管的第二端与所述第三晶体管的控制端连接。
PCT/CN2015/092364 2015-09-29 2015-10-21 一种goa电路及液晶显示器 WO2017054264A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/891,646 US9972273B2 (en) 2015-09-29 2015-10-21 GOA circuit and a liquid crystal display

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510632682.2 2015-09-29
CN201510632682.2A CN105139820B (zh) 2015-09-29 2015-09-29 一种goa电路及液晶显示器

Publications (1)

Publication Number Publication Date
WO2017054264A1 true WO2017054264A1 (zh) 2017-04-06

Family

ID=54725142

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/092364 WO2017054264A1 (zh) 2015-09-29 2015-10-21 一种goa电路及液晶显示器

Country Status (3)

Country Link
US (1) US9972273B2 (zh)
CN (1) CN105139820B (zh)
WO (1) WO2017054264A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114758634A (zh) * 2022-04-25 2022-07-15 合肥京东方卓印科技有限公司 驱动模组、驱动方法和显示装置

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105139796B (zh) * 2015-09-23 2018-03-09 深圳市华星光电技术有限公司 一种goa电路、显示装置和goa电路的驱动方法
CN105575349B (zh) * 2015-12-23 2018-03-06 武汉华星光电技术有限公司 Goa电路及液晶显示装置
CN105513550B (zh) * 2016-01-04 2019-02-01 武汉华星光电技术有限公司 Goa驱动电路
CN105869588B (zh) * 2016-05-27 2018-06-22 武汉华星光电技术有限公司 基于ltps半导体薄膜晶体管的goa电路
US10403382B2 (en) * 2016-08-05 2019-09-03 Hannstar Display Corporation Gate driving circuit and display apparatus
CN108962168A (zh) * 2018-07-24 2018-12-07 武汉华星光电技术有限公司 单型goa电路
CN111179871B (zh) * 2020-02-12 2021-01-15 武汉华星光电技术有限公司 一种goa电路及其显示面板
CN113035109B (zh) * 2021-02-25 2024-05-17 福建华佳彩有限公司 一种内嵌式显示屏的gip驱动电路及其控制方法
CN114999397A (zh) * 2022-04-27 2022-09-02 湖北长江新型显示产业创新中心有限公司 一种发光控制电路、显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201023156A (en) * 2008-12-12 2010-06-16 Au Optronics Corp Shift register with pre-pull-down circuit
US20100164915A1 (en) * 2008-12-29 2010-07-01 Hak-Gyu Kim Gate driving circuit and display device having the gate driving circuit
US20100260312A1 (en) * 2009-04-08 2010-10-14 Tsung-Ting Tsai Shift register of lcd devices
CN102650751A (zh) * 2011-09-22 2012-08-29 京东方科技集团股份有限公司 一种goa电路、阵列基板及液晶显示器件
CN103943081A (zh) * 2014-03-14 2014-07-23 京东方科技集团股份有限公司 移位寄存器、其制作方法、栅线集成驱动电路及相关装置
CN104778928A (zh) * 2015-03-26 2015-07-15 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路、显示面板及显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103390392B (zh) * 2013-07-18 2016-02-24 合肥京东方光电科技有限公司 Goa电路、阵列基板、显示装置及驱动方法
US9437324B2 (en) * 2013-08-09 2016-09-06 Boe Technology Group Co., Ltd. Shift register unit, driving method thereof, shift register and display device
CN103489484B (zh) * 2013-09-22 2015-03-25 京东方科技集团股份有限公司 一种移位寄存器单元及栅极驱动电路
CN103730093B (zh) * 2013-12-26 2017-02-01 深圳市华星光电技术有限公司 一种阵列基板驱动电路、阵列基板及相应的液晶显示器
CN103744206B (zh) * 2013-12-27 2016-08-17 深圳市华星光电技术有限公司 一种阵列基板驱动电路、阵列基板及相应的液晶显示器
CN104299591B (zh) * 2014-10-31 2017-01-18 深圳市华星光电技术有限公司 阵列基板行驱动电路及液晶显示装置
CN104464667B (zh) * 2014-12-08 2017-04-19 深圳市华星光电技术有限公司 Goa型显示面板及其驱动电路结构和驱动方法
CN104537994B (zh) * 2014-12-30 2017-04-12 深圳市华星光电技术有限公司 一种应用于平板显示器的goa驱动电路及平板显示器

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201023156A (en) * 2008-12-12 2010-06-16 Au Optronics Corp Shift register with pre-pull-down circuit
US20100164915A1 (en) * 2008-12-29 2010-07-01 Hak-Gyu Kim Gate driving circuit and display device having the gate driving circuit
US20100260312A1 (en) * 2009-04-08 2010-10-14 Tsung-Ting Tsai Shift register of lcd devices
CN102650751A (zh) * 2011-09-22 2012-08-29 京东方科技集团股份有限公司 一种goa电路、阵列基板及液晶显示器件
CN103943081A (zh) * 2014-03-14 2014-07-23 京东方科技集团股份有限公司 移位寄存器、其制作方法、栅线集成驱动电路及相关装置
CN104778928A (zh) * 2015-03-26 2015-07-15 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路、显示面板及显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114758634A (zh) * 2022-04-25 2022-07-15 合肥京东方卓印科技有限公司 驱动模组、驱动方法和显示装置
CN114758634B (zh) * 2022-04-25 2023-09-29 合肥京东方卓印科技有限公司 驱动模组、驱动方法和显示装置

Also Published As

Publication number Publication date
CN105139820B (zh) 2017-11-10
CN105139820A (zh) 2015-12-09
US20170193956A1 (en) 2017-07-06
US9972273B2 (en) 2018-05-15

Similar Documents

Publication Publication Date Title
WO2017054264A1 (zh) 一种goa电路及液晶显示器
WO2016074283A1 (zh) 用于液晶显示的goa电路及液晶显示装置
WO2017049688A1 (zh) 一种goa电路及其驱动方法、液晶显示器
WO2016106803A1 (zh) 用于液晶显示装置的goa电路
WO2018072304A1 (zh) Goa驱动电路及液晶显示装置
WO2015021660A1 (zh) 阵列基板及液晶显示装置
WO2016161679A1 (zh) 一种goa电路及液晶显示器
WO2016106802A1 (zh) 用于液晶显示装置的goa电路
WO2016165162A1 (zh) 一种goa电路及液晶显示器
WO2017054260A1 (zh) 一种显示装置、tft基板及goa驱动电路
WO2017215040A1 (zh) 栅极驱动电路及液晶显示装置
WO2018094807A1 (zh) Goa驱动电路及液晶显示装置
WO2017049658A1 (zh) 栅极驱动电路
WO2018218718A1 (zh) 双向移位寄存器单元、双向移位寄存器及显示面板
WO2017045220A1 (zh) 一种goa电路及液晶显示器
CN101377595B (zh) 液晶显示器栅极驱动装置
WO2017028350A1 (zh) 液晶显示装置及其goa扫描电路
WO2017028332A1 (zh) 扫描驱动电路及具有该电路的液晶显示装置
WO2018035995A1 (zh) 扫描驱动电路
WO2017049687A1 (zh) 一种goa电路、显示装置和goa电路的驱动方法
WO2018120286A1 (zh) 一种驱动电路及显示面板
WO2017045215A1 (zh) 一种液晶显示装置及其栅极驱动电路
WO2018018724A1 (zh) 扫描驱动电路及具有该电路的平面显示装置
WO2018023859A1 (zh) 扫描驱动电路及具有该电路的平面显示装置
WO2018223519A1 (zh) Goa驱动电路及液晶显示器

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14891646

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15905176

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15905176

Country of ref document: EP

Kind code of ref document: A1