WO2017049658A1 - 栅极驱动电路 - Google Patents

栅极驱动电路 Download PDF

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Publication number
WO2017049658A1
WO2017049658A1 PCT/CN2015/091047 CN2015091047W WO2017049658A1 WO 2017049658 A1 WO2017049658 A1 WO 2017049658A1 CN 2015091047 W CN2015091047 W CN 2015091047W WO 2017049658 A1 WO2017049658 A1 WO 2017049658A1
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WO
WIPO (PCT)
Prior art keywords
gate
switch
switch tube
source
drain
Prior art date
Application number
PCT/CN2015/091047
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English (en)
French (fr)
Inventor
戴超
Original Assignee
深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/891,422 priority Critical patent/US9898987B2/en
Publication of WO2017049658A1 publication Critical patent/WO2017049658A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a gate driving circuit.
  • GOA Gate Driver On Array
  • Array liquid crystal display array
  • the GOA circuit includes a pull-up portion, a pull-up control circuit, a downlink portion, a pull-down circuit portion, a bootstrap capacitor, and a pull-down sustaining module.
  • the pull-up portion is mainly responsible for outputting an input clock signal (Clock) to the gate of the thin film transistor as a driving signal of the liquid crystal display.
  • the pull-up control circuit is responsible for controlling the start of the GOA, which is generally a signal transmitted by the superior GOA circuit.
  • the downstream part is responsible for outputting the level signal when outputting the scanning signal; the pull-down circuit part is responsible for the signal of the scanning signal and the pull-up circuit (commonly referred to as Q point). Stay in the off state (ie set negative potential).
  • the pull-down maintenance module is responsible for the secondary rise of the Q point potential, thus ensuring the normal output of the G(N) of the pull-up circuit.
  • each stage of the GOA circuit has the same module, so that each stage of the GOA circuit has a large number of thin film transistors (Thin Film).
  • Transistor, TFT Transistor
  • Low Temperature low temperature polysilicon
  • LTPS Poly-silicon
  • the embodiment of the invention provides a gate driving circuit, which can reduce the number of components of the GOA circuit and facilitate the design of the ultra-narrow bezel.
  • the present invention provides a gate driving circuit including a plurality of cascaded gate driving units, each gate driving unit for driving two scanning lines that are continuously disposed, including: a pull-up control module, according to the upper level The level-transmitting signal generates a scan level signal; the first pull-up module is configured to pull up a gate driving signal of the first one of the two scan lines according to the scan level signal and the first clock signal; and the second pull-up a module, configured to pull up a gate driving signal of a second one of the two scan lines according to the scan level signal and the second clock signal; and the first downlink module is configured to generate the first level according to the scan level signal Transmitting a signal; a second downlink module for generating a second-level transmission signal according to the scan level signal; and a pull-down module for driving the gate drive signal of the first scan line and the second scan line; the first bootstrap capacitor a low level for generating a gate driving signal of the first scan line; a second bootstrap capacitor for generating a low level
  • the pull-up control module includes a first switch tube, the gate of the first switch tube inputs a signal transmitted from the upper stage, the source is connected to the first reference level, and the drain is respectively connected to the first pull-up module and the second pull-up module.
  • the first downlink module, the second downlink module, the first bootstrap capacitor, the second bootstrap capacitor, and the pull-down maintenance module are connected.
  • the first pull-up module includes a second switch, the gate of the second switch is connected to the drain of the first switch, the drain inputs a first clock signal, and the source outputs a gate drive signal of the first scan line.
  • the first downstream module includes a third switching transistor, the gate of the third switching transistor is connected to the drain of the first switching transistor, the drain inputs a first clock signal, and the source outputs a first level transmission signal.
  • the second pull-up module includes a fourth switch tube, the gate of the fourth switch tube is connected to the drain of the first switch tube, the drain inputs a second clock signal, and the source outputs a gate drive signal of the second scan line. .
  • the second downlink module includes a fifth switch tube, the gate of the fifth switch tube is connected to the drain of the first switch tube, the drain input is a second clock signal, and the source outputs a second level signal.
  • the pull-down module includes a sixth switch tube and a seventh switch tube.
  • the gate of the sixth switch tube inputs a lower-level signal or a lower-level gate drive signal, and the drain is connected to the drain of the first switch tube, and the source is connected.
  • the drain of the seventh switch tube; the gate of the seventh switch tube inputs a third clock signal, and the source is connected to the gate drive signal of the first scan line.
  • the pull-down maintenance module includes an inverter, an eighth switch tube, a ninth switch tube, a tenth switch tube, an eleventh switch tube, and a twelfth switch tube: an input end of the inverter and the first switch tube
  • the drain is connected, and the output end of the inverter is connected to the gate of the eighth switch tube, the gate of the ninth switch tube, the gate of the tenth switch tube, and the gate of the eleventh switch tube, and the drain of the eighth switch tube
  • the pole is connected to the drain of the first switch tube, the source is connected to the source of the eleventh switch tube, the drain of the ninth switch tube is input to the second reference level, and the source is connected to the gate drive signal of the first scan line
  • the drain of the tenth switch tube is input to the second reference level, the source is connected to the gate drive signal of the second scan line, the drain of the eleventh switch tube is input to the third reference level, and the source is connected to the twelfth
  • the drain of the switch tube is
  • the inverter comprises a main inverting module and an auxiliary inverting module
  • the main inverting module comprises: a thirteenth switch tube, a fourteenth switch tube, a fifteenth switch tube and a sixteenth switch tube, and an auxiliary inversion module Including a seventeenth switch tube and an eighteenth switch tube, the gate of the thirteenth switch tube is connected to the drain of the first switch tube, the drain is input to the second reference level, and the source is connected to the drain of the fourteenth switch tube a pole, a gate and a source of the fourteenth switch tube are input with a first reference level; a gate of the fifteenth switch tube is connected to a drain of the first switch tube, and a drain is connected to a source of the seventeenth switch tube;
  • the source is the output of the inverter, connected to the drain of the sixteenth switch; the gate of the sixteenth switch is connected to the source of the thirteenth switch, the source is input to the first reference level; the seventeenth switch
  • the gate of the tube is connected to
  • the inverter comprises three main inverting modules and one auxiliary inverting module
  • the first main inverting module comprises: a nineteenth switch tube, a twentieth switch tube, a twenty-first switch tube, and a twentieth
  • the second switching tube includes a twenty-third switching tube, a twenty-fourth switching tube, a twenty-fifth switching tube, and a twenty-six switching tube
  • the second main inverting module includes: twenty-seventh The switch tube, the twenty-eighth switch tube, the twenty-ninth switch tube, the thirty-th switch tube
  • the third main reverse phase module comprises: a thirty-first switch tube and a thirty-second switch tube, thirty-third a switch tube and a thirty-fourth switch tube
  • a gate of the nineteenth switch tube is connected to an output end of the pull-up control module in the first-stage gate drive unit, a drain input second reference level, and a source connection
  • the drain of the twenty-two switch tube, the gate and the source of the twentieth switch tube are input to the
  • the present invention also provides a gate driving circuit including a plurality of cascaded gate driving units, each gate driving unit for driving two scan lines that are continuously disposed, including: a pull-up control module, for The upper level transmitting signal generates a scan level signal; the first pull-up module is configured to pull up the gate driving signal of the first scan line of the two scan lines according to the scan level signal and the first clock signal; a pull module, configured to pull up a gate driving signal of a second one of the two scan lines according to the scan level signal and the second clock signal; and a first downlink module configured to generate a first image according to the scan level signal a second transmission module, configured to generate a second-level transmission signal according to the scan level signal; and a pull-down module, configured to pull down the gate drive signal of the first scan line and the second scan line; a capacitor for generating a low level of a gate driving signal of the first scan line; a second bootstrap capacitor for generating a low level of a gate driving signal of the second scan line; and
  • the pull-up control module includes a first switch tube, the gate of the first switch tube inputs a signal transmitted from the upper stage, the source is connected to the first reference level, and the drain is respectively connected to the first pull-up module and the second pull-up module.
  • the first downlink module, the second downlink module, the first bootstrap capacitor, the second bootstrap capacitor, and the pull-down maintenance module are connected.
  • the first pull-up module includes a second switch, the gate of the second switch is connected to the drain of the first switch, the drain inputs a first clock signal, and the source outputs a gate drive signal of the first scan line.
  • the first downstream module includes a third switching transistor, the gate of the third switching transistor is connected to the drain of the first switching transistor, the drain inputs a first clock signal, and the source outputs a first level transmission signal.
  • the second pull-up module includes a fourth switch tube, the gate of the fourth switch tube is connected to the drain of the first switch tube, the drain inputs a second clock signal, and the source outputs a gate drive signal of the second scan line. .
  • the second downlink module includes a fifth switch tube, the gate of the fifth switch tube is connected to the drain of the first switch tube, the drain input is a second clock signal, and the source outputs a second level signal.
  • the pull-down module includes a sixth switch tube and a seventh switch tube.
  • the gate of the sixth switch tube inputs a lower-level signal or a lower-level gate drive signal, and the drain is connected to the drain of the first switch tube, and the source is connected.
  • the drain of the seventh switch tube; the gate of the seventh switch tube inputs a third clock signal, and the source is connected to the gate drive signal of the first scan line.
  • the pull-down maintenance module includes an inverter, an eighth switch tube, a ninth switch tube, a tenth switch tube, an eleventh switch tube, and a twelfth switch tube: an input end of the inverter and the first switch tube
  • the drain is connected, and the output end of the inverter is connected to the gate of the eighth switch tube, the gate of the ninth switch tube, the gate of the tenth switch tube, and the gate of the eleventh switch tube, and the drain of the eighth switch tube
  • the pole is connected to the drain of the first switch tube, the source is connected to the source of the eleventh switch tube, the drain of the ninth switch tube is input to the second reference level, and the source is connected to the gate drive signal of the first scan line
  • the drain of the tenth switch tube is input to the second reference level, the source is connected to the gate drive signal of the second scan line, the drain of the eleventh switch tube is input to the third reference level, and the source is connected to the twelfth
  • the drain of the switch tube is
  • the inverter comprises a main inverting module and an auxiliary inverting module
  • the main inverting module comprises: a thirteenth switch tube, a fourteenth switch tube, a fifteenth switch tube and a sixteenth switch tube, and an auxiliary inversion module Including a seventeenth switch tube and an eighteenth switch tube, the gate of the thirteenth switch tube is connected to the drain of the first switch tube, the drain is input to the second reference level, and the source is connected to the drain of the fourteenth switch tube a pole, a gate and a source of the fourteenth switch tube are input with a first reference level; a gate of the fifteenth switch tube is connected to a drain of the first switch tube, and a drain is connected to a source of the seventeenth switch tube;
  • the source is the output of the inverter, connected to the drain of the sixteenth switch; the gate of the sixteenth switch is connected to the source of the thirteenth switch, the source is input to the first reference level; the seventeenth switch
  • the gate of the tube is connected to
  • the inverter comprises three main inverting modules and one auxiliary inverting module
  • the first main inverting module comprises: a nineteenth switch tube, a twentieth switch tube, a twenty-first switch tube, and a twentieth
  • the second switching tube includes a twenty-third switching tube, a twenty-fourth switching tube, a twenty-fifth switching tube, and a twenty-six switching tube
  • the second main inverting module includes: twenty-seventh The switch tube, the twenty-eighth switch tube, the twenty-ninth switch tube, the thirty-th switch tube
  • the third main reverse phase module comprises: a thirty-first switch tube and a thirty-second switch tube, thirty-third a switch tube and a thirty-fourth switch tube
  • a gate of the nineteenth switch tube is connected to an output end of the pull-up control module in the first-stage gate drive unit, a drain input second reference level, and a source connection
  • the drain of the twenty-two switch tube, the gate and the source of the twentieth switch tube are input to the
  • the present invention has an advantageous effect that the present invention includes a pull-up control module for generating a scan level signal according to a signal transmitted from the upper stage in each stage of the gate driving unit, for using a scan level signal and a a clock signal, a first pull-up module that pulls up a gate drive signal of the first scan line of the two scan lines, for pulling up the second of the two scan lines according to the scan level signal and the second clock signal a second pull-up module of the gate driving signal of the two scan lines, a first downlink module for generating a first-level signal according to the scan level signal, and a second signal for generating a second-level signal according to the scan level signal a second downlink module, a pull-down module for pulling down a gate driving signal of the first scan line and the second scan line, a first bootstrap capacitor, a second bootstrap capacitor, and a second scan line and a second
  • the low-level pull-down maintaining module of the gate driving signal of the scan line enables each gate driving unit to
  • FIG. 1 is a circuit diagram of a gate driving unit according to a first embodiment of the present invention
  • FIG. 2 is a circuit diagram showing the application of the gate driving unit of FIG. 1 to the first stage
  • FIG. 3 is a circuit diagram showing the application of the gate driving unit of FIG. 1 to the second stage;
  • FIG. 4 is a schematic waveform diagram of a gate driving unit of FIG. 1;
  • FIG. 5 is a circuit diagram showing the application of the gate driving unit of FIG. 1 to the final stage;
  • FIG. 6 is a circuit diagram of a gate driving unit according to a second embodiment of the present invention.
  • FIG. 7 is a circuit diagram showing the application of the gate driving unit of FIG. 6 to the final stage;
  • Figure 8 is a circuit diagram of an inverter of a first embodiment of the present invention.
  • Figure 9 is a circuit diagram of an inverter of a second embodiment of the present invention.
  • FIG. 10 is a waveform diagram of a gate driving unit including the inverter of FIG.
  • FIG. 1 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention.
  • the gate driving circuit includes a plurality of cascaded gate driving units 1 , and each gate driving unit 1 is configured to respectively drive two scan lines that are continuously disposed, including: a pull-up control module 10 , A pull-up module 11, a second pull-up module 12, a first downlink module 13, a second downlink module 14, a pull-down module 15, a first bootstrap capacitor 16, a second bootstrap capacitor 17, and a pull-down maintenance module 18.
  • the pull-up control module 10 is configured to generate a scan level signal Q(2N-1) according to the upper stage pass signal ST(2N-2).
  • the first pull-up module 11 is configured to pull up the gate driving signal G of the first one of the two scan lines according to the scan level signal Q(2N-1) and the first clock signal CK(n) (2N- 1).
  • the second pull-up module 12 is configured to pull up the gate driving signal G of the second one of the two scan lines according to the scan level signal Q(2N-1) and the second clock signal CK(n+1) ( 2N).
  • the first downlink module 13 is configured to generate a first-level transmission signal ST(2N-1) according to the scan level signal Q(2N-1).
  • the second downlink module 14 is configured to generate a second-level transmission signal ST(2N) according to the scan level signal Q(2N-1).
  • the pull-down module 15 is for pulling down the gate drive signals G(2N-1) and G(2N) of the first scan line and the second scan line.
  • the first bootstrap capacitor 16 is used to generate a low level of the gate drive signal G(2N-1) of the first scan line.
  • the second bootstrap capacitor 17 is used to generate a low level of the gate drive signal G(2N) of the second scan line.
  • the pull-down maintaining module 18 is for maintaining a low level of the gate driving signals G(2N-1) and G(2N) of the first scan line and the second scan line.
  • Each of the gate driving units 1 of the embodiment of the present invention includes two pull-up modules 11, 12 and two downlink modules 13, 14 that can output two gate driving signals G(2N-1) and G(2N).
  • the two scan lines are continuously driven, and the other parts can be shared. This can reduce the number of components of the GOA circuit and facilitate the design of the ultra-narrow bezel.
  • the pull up control module 10 includes a first switch tube T1.
  • the gate of the first switch T1 is input to the upper stage signal ST(2N-2), the source is connected to the first reference level VSS1, and the drain is respectively connected to the first pull-up module 11, the second pull-up module 12, and the first
  • the downlink module 13, the second downlink module 14, the first bootstrap capacitor 16, the second bootstrap capacitor 17, and the pull-down maintaining module 18 are connected, and the common connection point is referred to as a first control node Q (2N-1).
  • the first reference level VSS1 is a constant voltage negative potential.
  • the first pull-up module 11 includes a second switch tube T2.
  • the gate of the second switching transistor T2 is connected to the drain of the first switching transistor T1, the drain receives the first clock signal CK(n), and the source outputs the gate driving signal G(2N-1) of the first scanning line.
  • the first downlink module 13 includes a third switch T3, the gate of the third switch T3 is connected to the drain of the first switch T1, the drain inputs the first clock signal CK(n), and the source outputs the first stage.
  • the second pull-up module 12 includes a fourth switch tube T4.
  • the gate of the fourth switching transistor T4 is connected to the drain of the first switching transistor T1, the drain receives the second clock signal CK(n+1), and the source outputs the gate driving signal G(2N) of the second scanning line.
  • the second downlink module 14 includes a fifth switch T5, the gate of the fifth switch T5 is connected to the drain of the first switch T1, the drain is input with the second clock signal CK(n+1), and the source output is The secondary signal ST (2N).
  • the first pull-up module 11 and the second pull-up module 12 and the first downlink module 13 and the second downlink module 14 share the first control node Q(2N-1), and can output two consecutive gate drive signals G ( 2N-1) and G(2N) respectively drive two scan lines that are continuously arranged, and other portions can be shared, so that two consecutive scan lines that are originally required to be driven by the two-stage gate drive unit are used in the embodiment of the present invention.
  • the first-level gate drive unit can be realized, which can greatly reduce the number of components of the GOA circuit, and at least 12 TFT elements are reduced every two stages as a whole, thereby facilitating the design of the ultra-narrow bezel.
  • the first clock signal CK(n) is translated by 1/4 clock cycle to obtain the second clock signal CK(n+1).
  • the second clock signal CK(n+1) may also be a direct input instead of being translated by the first clock signal CK(n), which is not limited herein.
  • the pull-down module 15 includes a sixth switch tube T6 and a seventh switch tube T7.
  • the gate of the sixth switching transistor T6 is input to the lower stage transmission signal ST(2N+2) or the lower stage gate driving signal G(2N+2), the drain is connected to the drain of the first switching transistor T1, and the source is connected to the seventh.
  • the drain of the switch T7 The gate of the seventh switching transistor T7 inputs a third clock signal CK(n+3), and the source is connected to the gate driving signal G(2N-1) of the first scanning line.
  • the third clock signal CK(n+3) may be obtained by shifting the first clock signal CK(n) by 3/4 clock cycles.
  • the pull-down maintenance module 18 includes an inverter U1, an eighth switch tube T8, a ninth switch tube T9, a tenth switch tube T10, an eleventh switch tube T11, and a twelfth switch tube T12.
  • the input end of the inverter U1 is connected to the drain of the first switch tube T1, and the output end of the inverter U1 is connected to the gate of the eighth switch tube T8, the gate of the ninth switch tube T9, and the tenth switch tube T10.
  • the gate and the gate of the eleventh switching transistor T11 The drain of the eighth switching transistor T8 is connected to the drain of the first switching transistor T1, and the source is connected to the source of the eleventh switching transistor T11.
  • the drain of the ninth switch T9 is input to the second reference level VDD1, the source is connected to the gate drive signal G(2N-1) of the first scan line, and the drain of the tenth switch T10 is input to the second reference level.
  • VDD1 the source is connected to the gate drive signal G(2N) of the second scan line
  • the drain of the eleventh switch T11 is input to the third reference level VDD2
  • the source is connected to the drain of the twelfth switch T12.
  • the gate of the twelfth switch T12 is connected to the drain of the first switch T1, and the source is input to the first reference level VSS1.
  • the second reference level VDD1 and the third reference level VDD2 are constant voltage positive potentials, and the potential of the third reference level VDD2 is higher than the potential of the second reference level VDD1.
  • Each of the above switching tubes is a P-type thin film transistor.
  • N and n are both positive integers.
  • FIG. 2 is a circuit diagram showing the application of the gate driving unit 1 of FIG. 1 to the first stage.
  • the gate of the first switch T1 inputs the enable signal STV
  • the first clock signal input by the first pull-up module 11 is the clock signal CK1
  • the second pull-up module inputs the second clock signal to the clock signal CK2.
  • the clock signal CK2 can be obtained by shifting the clock signal CK1 by 1/4 cycle.
  • the driving signal G1 of the first scanning line is output through the second switching transistor T2, the driving signal G2 of the second scanning line is outputted through the fourth switching transistor T4, and the first-level transmission signal ST1 is output through the third switching tube T3, and is passed through the fifth
  • the switch tube T3 outputs a second stage transmission signal ST2.
  • FIG. 3 is a circuit diagram showing the application of the gate driving unit 1 of FIG. 1 to the second stage.
  • the gate of the first switching transistor T1 is input to the second-stage transmission signal ST2 outputted by the first-stage gate driving unit.
  • the first clock signal input by the first pull-up module 11 is the clock signal CK3, and the second pull-up module 12 inputs the second clock signal as the clock signal CK4.
  • the clock signal CK3 can be obtained by shifting the clock signal CK2 by 1/4 cycle
  • the clock signal CK4 can be obtained by shifting the clock signal CK3 by 1/4 cycle.
  • the gate drive signal G3 of the third scan line and the gate drive signal G4 of the fourth scan line are output through the second switch transistor T2 and the fourth switch transistor T4, respectively.
  • the third stage transmission signal ST3 and the fourth stage transmission signal ST4 are output through the third switching tube T3 and the fifth switching tube T5, respectively.
  • the operation of the gate driving unit 1 in FIG. 1 is as follows:
  • the first switching tube T1 When the upper stage transmission signal ST(2N-2) is at a low potential, the first switching tube T1 is turned on, and the first bootstrap capacitor 16 is turned on. The second bootstrap capacitor 17 is charged to cause the first node Q(N) to obtain a negative potential to activate the gate driving unit 1. Then the superior level transmits the signal ST(2N-2) The transition to a high potential, and the first control node Q(2N-1) at the drain of the first switching transistor T1 maintains a negative potential through the first bootstrap capacitor Cb1 and the second bootstrap capacitor Cb2.
  • the second switch tube T2, the third switch tube T3, the fourth switch tube T4, and the fifth switch tube T5 are turned on by the control of the first control node Q(2N-1), and the first clock signal CK(n)
  • the first bootstrap capacitor Cb1 continues to be charged through the second switch transistor T2 and the third switch transistor T3, so that the first control node Q(2N-1) reaches a lower negative potential.
  • the source of the second switching transistor T2 outputs a low level of the first stage transmission signal ST(2N-1), and the source of the third switching tube T3 outputs a gate driving signal G of the first scanning line (2N).
  • -1) Low level. for In the PMOS gate drive circuit a time slot in which the scan drive signal is low is generally referred to as an active period.
  • the second control node P(2N-1) is obtained to be high after being inverted by the inverter U1, and is pulled down in the maintenance module 18.
  • the twelfth switch tube T12 is turned on, and the eleventh switch tube T11, the eighth switch tube T8, the ninth switch tube T9, and the tenth switch tube T10 are all turned off.
  • the potential of the source of the eighth switching transistor T12 is pulled down to the first reference level VSS1, so that leakage of the first control node Q(2N-1) through the eighth switching transistor T8 can be reduced.
  • the first control node Q(2N-1) is approximately maintained at the first reference level VSS1, and the first reference level VSS1 is used to perform signal transmission of the first switch T1.
  • the leakage of the first control node Q (2N-1) can be reduced.
  • the first clock signal CK(n) becomes a high potential, correspondingly the gate drive signal G(2N-1) of the first scan line outputted by the source of the second switch transistor T2 and the source of the third switch transistor T3
  • the first-stage transmission signal ST(2N-1) of the pole output also transitions to a high potential.
  • the fourth switch tube T4 and the fifth switch tube T5 are continuously turned on by the control of the first control node Q (2N-1). At this time, the low level of the second clock signal CK(n+1) comes through the fourth switch.
  • the tube T4 and the fifth switching transistor T5 charge the second bootstrap capacitor Cb2 such that the first control node Q(2N-1) continues to maintain a negative potential.
  • the source of the fourth switching transistor T4 outputs the low level of the second stage transmission signal ST(2N), and the source of the fifth switching transistor T5 outputs the gate driving signal G(2N) of the second scanning line. Low level.
  • the second clock signal CK(n+1) becomes a high potential, correspondingly the gate drive signal G(2N) of the second scan line outputted by the source of the fourth switch transistor T4 and the source of the fifth switch transistor T5
  • the second-stage transmission signal ST(2N) of the pole output also transitions to a high potential, and the circuit enters a non-operation period.
  • the sixth switch tube T6 and the seventh switch The tube T7 is both turned on, the potential of the first control node Q(2N-1) is pulled to the high potential of the gate driving signal G(2N-1) of the first scanning line, and the second switching tube T2 and the third switching tube T3, the fourth switching transistor T4, and the fifth switching transistor T5 are all turned off.
  • the second control node P(2N-1) is inverted to be low after being inverted by the inverter U1.
  • the twelfth switch tube T12 in the pull-down maintenance module 18 is turned off, and the eighth switch tube T8, the ninth switch tube T9, the tenth switch tube T10, and the eleventh switch tube T11 are all turned on, and the first control node Q (2N)
  • the potential of -1) is raised by the eighth switching transistor T8 and the eleventh switching transistor T11 and maintained at the third reference level VDD2.
  • the gate drive signal of the first scan line The potentials of the gate drive signals G(2N) of G(2N-1) and the second scan line are held at the second reference level VDD1 by the ninth switch T9 and the tenth switch T10, respectively.
  • the gate driving unit of the first stage shown in FIG. 2 is cascaded with the gate driving unit of the second stage shown in FIG. 3, and the waveform thereof is as follows.
  • Figure 4 shows.
  • the start pulse STV is low
  • the gate driving unit of the first stage is started.
  • the first control node Q(1) is low level
  • the corresponding second control node P1 is at a high level
  • the gate of the first stage is The low potentials of the first clock signal CK1 and the second clock signal CK2 of the pole drive unit sequentially arrive, corresponding to the gate drive signal G1 of the first scan line and the gate drive signal G2 of the second scan line, respectively.
  • the gate driving unit of the second stage is activated by the low level of the second stage transmission signal ST2 outputted simultaneously with the gate driving signal G2 of the second scanning line. And during the period when the first control node Q(3) is low level, the corresponding second control node P3 is at a high level, and the first clock signal CK3 and the second clock signal CK4 of the gate driving unit of the second stage are The low potentials sequentially come in correspondence with the gate drive signal G3 of the third scan line and the gate drive signal G4 of the fourth scan line, respectively.
  • FIG. 5 is a circuit diagram showing the application of the gate driving unit 1 of FIG. 1 to the final stage.
  • the gate of the first switching transistor T1 inputs the second-level signal ST(last-2) output by the previous gate driving unit, and is input by the first pull-up module 11 and the first downlink module 12.
  • the first clock signal is CK3, and the gate drive signal G(last-1) of the penultimate scan line and the second last down signal ST(last-1) are respectively output.
  • the second clock signal input by the second pull-up module 13 and the second downlink module 14 is CK4, and outputs the gate drive signal G(last) of the last scan line and the downlink signal ST(last) of the last stage, respectively.
  • the gate of the sixth switching transistor is connected to the start pulse STV while the seventh switching transistor T7 is removed.
  • FIG. 6 is a circuit diagram of a gate driving unit of a second embodiment of the present invention.
  • the difference from the gate driving unit in FIG. 1 is that the sixth switching transistor T6 is connected by a diode, that is, the drain and the gate of the sixth switching transistor T6 are both connected to the first control node. That is, the drain of the first switching transistor T1.
  • the circuit of the corresponding last stage gate driving unit is as shown in FIG. 7, retaining the seventh switching transistor T7, and the gate of the seventh switching transistor is connected to the second clock signal CK2.
  • the inverter U1 in the pull-down maintaining module 18 includes a main inverting module 101 and an auxiliary inverting module 102.
  • the main inverting module 101 includes a thirteenth switch tube T13, a fourteenth switch tube T14, a fifteenth switch tube T15, and a sixteenth switch tube T16.
  • the auxiliary inverting module 102 includes a seventeenth switch tube T17 and an eighteenth switch tube T18.
  • the gate of the thirteenth switch T13 is connected to the drain of the first switch T1, the drain is input to the second reference level VDD1, and the source is connected to the drain of the fourteenth switch T14.
  • the gate and source of the fourteenth switching transistor T14 are input to the first reference level VSS1.
  • the gate of the fifteenth switch tube T15 is connected to the drain of the first switch tube T1, the drain is connected to the source of the seventeenth switch tube T17, the source is the output end of the inverter U1, and the sixteenth switch tube T16 is connected.
  • the gate of the sixteenth switch transistor T16 is connected to the source of the thirteenth switch transistor T13, and the source is input to the first reference level VSS1.
  • the gate of the seventeenth switch transistor T17 is connected to the drain of the first switch transistor T1, and the drain is input to the third reference level VDD2.
  • the gate of the eighteenth switch transistor T18 is connected to the gate of the sixteenth switch transistor T16, the source is input to the first reference level VSS1, and the drain is connected to the source of the seventeenth switch transistor T17.
  • inverter U1 The working process of inverter U1 is as follows:
  • First control node Q (2N-1) When the potential is low, the thirteenth switch tube T13 and the fifteenth switch tube T15 in the main inverter 101 are both turned on, and the fourteenth switch tube T14 and the sixteenth switch tube T16 are both turned off. The seventeenth switch tube T17 in the auxiliary inverter 102 is turned on, and the eighteenth switch tube T18 is turned off.
  • the potential of the second control node P(2N-1) is raised to a potential higher than the third reference level VDD2 of the second reference level VDD1.
  • First control node Q (2N-1) When it is high, the thirteenth switch tube T13 and the fifteenth switch tube T15 in the main inverter 101 are both turned off, and the fourteenth switch tube T14 and the sixteenth switch tube T16 are both turned on. The seventeenth switch tube T17 in the auxiliary inverter 102 is turned off, and the eighteenth switch tube T18 is turned on.
  • the potential of the second control node P(2N-1) is limited to the potential of the first reference level VSS1.
  • the second control node P(2N-1) is the output end of the inverter U1.
  • the gate driving units of three consecutive stages may share one inverter.
  • the inverter U2 includes three main inverting modules 201, 203, 204 and an auxiliary inverting module 202.
  • the first main inverting module 201 includes: a nineteenth switch tube T19, a twentieth switch tube T20, a twenty-first switch tube T21, and a twenty-second switch tube T22.
  • the auxiliary inverting module 202 includes a twenty-third switch tube T23, a twenty-fourth switch tube T24, a twenty-fifth switch tube T25, and a twenty-six switch tube T26.
  • the second main inverting module 203 includes: a twenty-seventh switch tube T27, a twenty-eighth switch tube T28, a twenty-ninth switch tube T29, and a thirty-th switch tube T30.
  • the third main inverting module 204 includes: a thirty-first switch tube T31 and a thirty-second switch tube T32, a thirty-third switch tube T33, and a thirty-fourth switch tube T34.
  • the gate of the nineteenth switch transistor T19 is connected to the output terminal of the pull-up control module in the first-stage gate drive unit, the drain input is the second reference level VDD1, and the source is connected to the drain of the twentieth switch transistor T20.
  • the gate and source of the twentieth switch transistor T20 are input to the first reference level VSS1.
  • the gate of the twenty-first switch tube T21 is connected to the output end of the pull-up control module in the first-stage gate drive unit, and the drain is connected to the source of the twenty-fifth switch tube T25, and the source is extremely inverter U2
  • the first output terminal P(N) is connected to the gate of the eighth switching transistor of the first-stage gate driving unit.
  • the gate of the twenty-second switch transistor T22 is connected to the source of the nineteenth switch transistor T19, the source is input to the first reference level VSS1, and the drain is connected to the source of the twenty-first switch transistor T21.
  • the gate of the twenty-third switch transistor T23 is connected to the output terminal of the pull-up control module in the first-stage gate driving unit, the drain is input to the third reference level VDD2, and the source is connected to the second fifteen-switch transistor T25. Source.
  • the gate of the twenty-fourth switch tube T24 is connected to the gate of the twenty-second switch tube T22, the drain is connected to the source of the twenty-fifth switch tube T25, and the source is connected to the drain of the twenty-six switch tube T26.
  • the gate of the twenty-fifth switch transistor T25 is connected to the output terminal of the pull-up control module in the third-stage gate drive unit, and the drain is input to the third reference level VDD2.
  • the gate of the twenty-sixth switch transistor T26 is connected to the gate of the thirty-fourth switch transistor T34, and the source is input to the first reference level VSS1.
  • the gate of the twenty-seventh switch transistor T27 is connected to the output terminal of the pull-up control module in the second-stage gate drive unit, the drain input is the second reference level VDD1, and the source is connected to the drain of the twenty-eighth switch transistor T28. pole.
  • the gate and source of the twenty-eighth switch transistor T28 are input to the first reference level VSS1.
  • the gate of the twenty-ninth switch tube T29 is connected to the output end of the pull-up control module in the second-stage gate drive unit, and the drain is connected to the source of the twenty-fifth switch tube T25.
  • the second output terminal P(N+1) is connected to the gate of the eighth switching transistor in the second-stage gate driving unit.
  • the gate of the thirtieth switch transistor T30 is connected to the source of the twenty-seventh switch transistor T27, the source is input to the first reference level VSS1, and the drain is connected to the source of the twenty-ninth switch transistor T29.
  • the gate of the thirty-first switch transistor T31 is connected to the output terminal of the pull-up control module in the third-stage gate drive unit, the drain input is the second reference level VDD1, and the source is connected to the drain of the thirty-second switch transistor T32. pole.
  • the gate and source of the thirty-second switch transistor T32 are input to the first reference level VSS1.
  • the gate of the thirty-third switch tube T33 is connected to the gate of the eleventh switch tube T31, the drain is connected to the source of the twenty-fifth switch tube T25, and the source is the third output end of the inverter U2.
  • the gate of the eighth switching transistor in the tertiary gate drive unit is connected to the source of the thirty-first switch transistor T31, the source is input to the first reference level VSS1, and the drain is connected to the source of the thirty-third switch transistor T33.
  • FIG. 10 is a waveform diagram of a gate driving unit including the inverter of FIG.
  • K1 is a shared node of the inverter U2 and is located at the source of the twenty-fifth switch tube 25.
  • the potential of the first output terminal P1 of the inverter U2 is opposite to the potential of the first control node Q1 in the first-stage gate driving unit, and the first main inverting module 201 is in operation at this time.
  • the potential of the second output terminal P2 of the inverter U2 is opposite to the potential of the first control node Q2 of the second-stage gate driving unit, at which time the second main inverting module 203 is in operation.
  • the potential of the third output terminal P3 of the inverter U2 is opposite to the potential of the first control node Q3 in the third-stage gate driving unit, at which time the third main inverting module 204 is in operation.
  • the shared node K1 is high when any of the main inverting modules are operating.
  • the present invention includes a pull-up control module for generating a scan level signal according to a signal transmitted by the upper stage in each stage of the gate driving unit, for pulling up two according to the scan level signal and the first clock signal.
  • a first pull-up module of a gate driving signal of a first scan line of the scan lines, and a gate driving for pulling up a second one of the two scan lines according to the scan level signal and the second clock signal a second pull-up module of the signal
  • a first downlink module for generating a first-level transmission signal according to the scan level signal
  • a second downlink module for generating a second-level transmission signal according to the scan level signal
  • a pull-down module that pulls down gate drive signals of the first scan line and the second scan line, a first bootstrap capacitor, a second bootstrap capacitor, and a gate drive signal for maintaining the first scan line and the second scan line
  • the low-level pull-down sustaining module enables each gate driving unit to drive two consecutively arranged scanning lines, which can reduce

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Abstract

一种栅极驱动电路，包括级联的多个栅极驱动单元（1），每个所述栅极驱动单元（1）用于分别驱动连续设置的两条扫描线，通过第一上拉模块（11）和第一下传模块（13）分别输出第一扫描线的栅极驱动信号（G(2N-1)）和第一级传信号（ST(2N-1)），通过第二上拉模块（12）和第二下传模块（14）分别输出第二扫描线的栅极驱动信号（G(2N)）和第二级传信号（ST(2N)）。通过以上方式，能够减少GOA电路的元件数量，便于实现超窄边框设计。

Description

栅极驱动电路
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种栅极驱动电路。
【背景技术】
GOA（Gate Driver On Array）是利用现有薄膜晶体管液晶显示器阵列（Array）基板制程将栅极（Gate）行扫描驱动信号电路制作在Array基板上，实现对Gate逐行扫描的驱动方式。其具有降低生产成本和窄边框设计的优点，为多种显示器所使用。
GOA电路包括上拉部分、上拉控制电路、下传部分、下拉电路部分、自举电容以及下拉维持模块。具体地，上拉部分主要负责将输入的时钟讯号（Clock）输出至薄膜晶体管的栅极，作为液晶显示器的驱动信号。上拉控制电路负责控制GOA启动，一般是由上级GOA电路传递来的信号作用。下传部分负责在输出扫描信号时，输出级传信号；下拉电路部分则负责将扫描信号和上拉电路的信号（通常称为Q点） 保持在关闭状态（即设定的负电位）。下拉维持模块则负责Q点电位的二次抬升，这样确保上拉电路的G(N)正常输出。
现有技术中的GOA电路，每一级GOA电路都具有相同的模块，这样每一级GOA电路都具有数量较多的薄膜晶体管（Thin Film Transistor，TFT）元件，这样会增加GOA电路的布局（Layout）空间，尤其是低温多晶硅（Low Temperature Poly-silicon，LTPS）制程具有高电子迁移率和技术成熟的优点，目前被中小尺寸显示器广泛使用，显示器的边框追求越窄越好，超窄边框的设计能够有效地增加手机的屏占比。
【发明内容】
本发明实施例提供了一种栅极驱动电路，能够减少GOA电路的元件数量，便于实现超窄边框设计。
本发明提供一种栅极驱动电路，包括级联的多个栅极驱动单元，每个栅极驱动单元用于分别驱动连续设置的两条扫描线，包括：上拉控制模块，用于根据上级级传信号生成扫描电平信号；第一上拉模块，用于根据扫描电平信号和第一时钟信号，拉升两条扫描线中的第一扫描线的栅极驱动信号；第二上拉模块，用于根据扫描电平信号和第二时钟信号，拉升两条扫描线中的第二扫描线的栅极驱动信号；第一下传模块，用于根据扫描电平信号生成第一级传信号；第二下传模块，用于根据扫描电平信号生成第二级传信号；下拉模块，用于拉低第一扫描线和第二扫描线的栅极驱动信号；第一自举电容，用于生成第一扫描线的栅极驱动信号的低电平；第二自举电容，用于生成第二扫描线的栅极驱动信号的低电平；下拉维持模块，用于维持第一扫描线和第二扫描线的栅极驱动信号的低电平。
其中，上拉控制模块包括第一开关管，第一开关管的栅极输入上级级传信号，源极接第一参考电平，漏极分别与第一上拉模块、第二上拉模块、第一下传模块、第二下传模块、第一自举电容、第二自举电容以及下拉维持模块连接。
其中，第一上拉模块包括第二开关管，第二开关管的栅极与第一开关管的漏极连接，漏极输入第一时钟信号，源极输出第一扫描线的栅极驱动信号；第一下传模块包括第三开关管，第三开关管的栅极与第一开关管的漏极连接，漏极输入第一时钟信号，源极输出第一级传信号。
其中，第二上拉模块包括第四开关管，第四开关管的栅极与第一开关管的漏极连接，漏极输入第二时钟信号，源极输出第二扫描线的栅极驱动信号。
其中，第二下传模块包括第五开关管，第五开关管的栅极与第一开关管的漏极连接，漏极输入第二时钟信号，源极输出第二级传信号。
其中，下拉模块包括第六开关管和第七开关管，第六开关管的栅极输入下级级传信号或下级栅极驱动信号，漏极与第一开关管的漏极连接，源极连接第七开关管的漏极；第七开关管的栅极输入第三时钟信号，源极连接于第一扫描线的栅极驱动信号。
其中，下拉维持模块包括包括反相器、第八开关管、第九开关管、第十开关管、第十一开关管以及第十二开关管：反相器的输入端与第一开关管的漏极连接，反相器的输出端连接第八开关管的栅极、第九开关管的栅极、第十开关管的栅极以及第十一开关管的栅极，第八开关管的漏极与第一开关管的漏极连接，源极连接第十一开关管的源极，第九开关管的漏极输入第二参考电平，源极连接于第一扫描线的栅极驱动信号，第十开关管的漏极输入第二参考电平，源极连接于第二扫描线的栅极驱动信号，第十一开关管的漏极输入第三参考电平，源极连接第十二开关管的漏极，第十二开关管的栅极与第一开关管的漏极连接，源极输入第一参考电平。
其中，反相器包括主反相模块和辅助反相模块，主反相模块包括：第十三开关管、第十四开关管、第十五开关管以及第十六开关管，辅助反相模块包括第十七开关管以及第十八开关管，第十三开关管的栅极与第一开关管的漏极连接，漏极输入第二参考电平，源极连接第十四开关管的漏极，第十四开关管的栅极和源极输入第一参考电平；第十五开关管的栅极与第一开关管的漏极连接，漏极连接第十七开关管的源极，源极为反相器的输出端，连接第十六开关管的漏极；第十六开关管的栅极连接第十三开关管的源极，源极输入第一参考电平；第十七开关管的栅极与第一开关管的漏极连接，漏极输入第三参考电平；第十八开关管的栅极连接第十六开关管的栅极，源极输入第一参考电平，漏极连接第十七开关管的源极。
其中，连续三级的栅极驱动单元共享反相器。
其中，反相器包括三个主反相模块和一辅助反相模块，第一个主反相模块包括：第十九开关管、第二十开关管、第二十一开关管、第二十二开关管；辅助反相模块包括第二十三开关管、第二十四开关管、第二十五开关管、第二十六开关管；第二个主反相模块包括：第二十七开关管、第二十八开关管、第二十九开关管、第三十开关管；第三个主反相模块包括：第三十一开关管以及第三十二开关管、第三十三开关管以及第三十四开关管；第十九开关管的栅极与第一级栅极驱动单元中的上拉控制模块的输出端连接，漏极输入第二参考电平，源极连接第二十开关管的漏极，第二十开关管的栅极和源极输入第一参考电平；第二十一开关管的栅极与上拉控制模块的输出端连接，漏极连接第二十五开关管的源极，源极为反相器的第一输出端，连接第一级栅极驱动单元中的第八开关管的栅极，第二十二开关管的栅极连接第十九开关管的源极，源极输入第一参考电平，漏极连接第二十一开关管的源极；第二十三开关管的栅极与上拉控制模块的输出端连接，漏极输入第三参考电平，源极连接第二十五开关管的源极；第二十四开关管的栅极连接第二十二开关管的栅极，漏极连接第二十五开关管的源极，源极连接第二十六开关管的漏极；第二十五开关管的栅极连接第三级栅极驱动单元中的上拉控制模块的输出端，漏极输入第三参考电平；第二十六开关管的栅极连接第三十四开关管的栅极，源极输入第一参考电平；第二十七开关管的栅极连接第二级栅极驱动单元中的上拉控制模块的输出端，漏极输入第二参考电平，源极连接第二十八开关管的漏极；第二十八开关管的栅极和源极输入第一参考电平；第二十九开关管的栅极连接第二级栅极驱动单元中的上拉控制模块的输出端，漏极连接第二十五开关管的源极，源极为反相器的第二输出端，连接第二级栅极驱动单元中的第八开关管的栅极；第三十开关管的栅极连接第二十七开关管的源极，源极输入第一参考电平，漏极连接第二十九开关管的源极；第三十一开关管的栅极连接第三级栅极驱动单元中的上拉控制模块的输出端，漏极输入第二参考电平，源极连接第三十二开关管的漏极；第三十二开关管的栅极和源极输入第一参考电平；第三十三开关管的栅极连接第三十一开关管的栅极，漏极连接第二十五开关管的源极，源极为反相器的第三输出端，连接第三级栅极驱动单元中的第八开关管的栅极；第三十四开关管的栅极连接第三十一开关管的源极，源极输入第一参考电平，漏极连接第三十三开关管的源极。
本发明还提供一种栅极驱动电路，包括级联的多个栅极驱动单元，每个栅极驱动单元用于分别驱动连续设置的两条扫描线，包括：上拉控制模块，用于根据上级级传信号生成扫描电平信号；第一上拉模块，用于根据扫描电平信号和第一时钟信号，拉升两条扫描线中的第一扫描线的栅极驱动信号；第二上拉模块，用于根据扫描电平信号和第二时钟信号，拉升两条扫描线中的第二扫描线的栅极驱动信号；第一下传模块，用于根据扫描电平信号生成第一级传信号；第二下传模块，用于根据扫描电平信号生成第二级传信号；下拉模块，用于拉低第一扫描线和第二扫描线的栅极驱动信号；第一自举电容，用于生成第一扫描线的栅极驱动信号的低电平；第二自举电容，用于生成第二扫描线的栅极驱动信号的低电平；下拉维持模块，用于维持第一扫描线和第二扫描线的栅极驱动信号的低电平；其中，第一时钟信号平移1/4个时钟周期即可得到第二时钟信号。
其中，上拉控制模块包括第一开关管，第一开关管的栅极输入上级级传信号，源极接第一参考电平，漏极分别与第一上拉模块、第二上拉模块、第一下传模块、第二下传模块、第一自举电容、第二自举电容以及下拉维持模块连接。
其中，第一上拉模块包括第二开关管，第二开关管的栅极与第一开关管的漏极连接，漏极输入第一时钟信号，源极输出第一扫描线的栅极驱动信号；第一下传模块包括第三开关管，第三开关管的栅极与第一开关管的漏极连接，漏极输入第一时钟信号，源极输出第一级传信号。
其中，第二上拉模块包括第四开关管，第四开关管的栅极与第一开关管的漏极连接，漏极输入第二时钟信号，源极输出第二扫描线的栅极驱动信号。
其中，第二下传模块包括第五开关管，第五开关管的栅极与第一开关管的漏极连接，漏极输入第二时钟信号，源极输出第二级传信号。
其中，下拉模块包括第六开关管和第七开关管，第六开关管的栅极输入下级级传信号或下级栅极驱动信号，漏极与第一开关管的漏极连接，源极连接第七开关管的漏极；第七开关管的栅极输入第三时钟信号，源极连接于第一扫描线的栅极驱动信号。
其中，下拉维持模块包括包括反相器、第八开关管、第九开关管、第十开关管、第十一开关管以及第十二开关管：反相器的输入端与第一开关管的漏极连接，反相器的输出端连接第八开关管的栅极、第九开关管的栅极、第十开关管的栅极以及第十一开关管的栅极，第八开关管的漏极与第一开关管的漏极连接，源极连接第十一开关管的源极，第九开关管的漏极输入第二参考电平，源极连接于第一扫描线的栅极驱动信号，第十开关管的漏极输入第二参考电平，源极连接于第二扫描线的栅极驱动信号，第十一开关管的漏极输入第三参考电平，源极连接第十二开关管的漏极，第十二开关管的栅极与第一开关管的漏极连接，源极输入第一参考电平。
其中，反相器包括主反相模块和辅助反相模块，主反相模块包括：第十三开关管、第十四开关管、第十五开关管以及第十六开关管，辅助反相模块包括第十七开关管以及第十八开关管，第十三开关管的栅极与第一开关管的漏极连接，漏极输入第二参考电平，源极连接第十四开关管的漏极，第十四开关管的栅极和源极输入第一参考电平；第十五开关管的栅极与第一开关管的漏极连接，漏极连接第十七开关管的源极，源极为反相器的输出端，连接第十六开关管的漏极；第十六开关管的栅极连接第十三开关管的源极，源极输入第一参考电平；第十七开关管的栅极与第一开关管的漏极连接，漏极输入第三参考电平；第十八开关管的栅极连接第十六开关管的栅极，源极输入第一参考电平，漏极连接第十七开关管的源极。
其中，连续三级的栅极驱动单元共享反相器。
其中，反相器包括三个主反相模块和一辅助反相模块，第一个主反相模块包括：第十九开关管、第二十开关管、第二十一开关管、第二十二开关管；辅助反相模块包括第二十三开关管、第二十四开关管、第二十五开关管、第二十六开关管；第二个主反相模块包括：第二十七开关管、第二十八开关管、第二十九开关管、第三十开关管；第三个主反相模块包括：第三十一开关管以及第三十二开关管、第三十三开关管以及第三十四开关管；第十九开关管的栅极与第一级栅极驱动单元中的上拉控制模块的输出端连接，漏极输入第二参考电平，源极连接第二十开关管的漏极，第二十开关管的栅极和源极输入第一参考电平；第二十一开关管的栅极与上拉控制模块的输出端连接，漏极连接第二十五开关管的源极，源极为反相器的第一输出端，连接第一级栅极驱动单元中的第八开关管的栅极，第二十二开关管的栅极连接第十九开关管的源极，源极输入第一参考电平，漏极连接第二十一开关管的源极；第二十三开关管的栅极与上拉控制模块的输出端连接，漏极输入第三参考电平，源极连接第二十五开关管的源极；第二十四开关管的栅极连接第二十二开关管的栅极，漏极连接第二十五开关管的源极，源极连接第二十六开关管的漏极；第二十五开关管的栅极连接第三级栅极驱动单元中的上拉控制模块的输出端，漏极输入第三参考电平；第二十六开关管的栅极连接第三十四开关管的栅极，源极输入第一参考电平；第二十七开关管的栅极连接第二级栅极驱动单元中的上拉控制模块的输出端，漏极输入第二参考电平，源极连接第二十八开关管的漏极；第二十八开关管的栅极和源极输入第一参考电平；第二十九开关管的栅极连接第二级栅极驱动单元中的上拉控制模块的输出端，漏极连接第二十五开关管的源极，源极为反相器的第二输出端，连接第二级栅极驱动单元中的第八开关管的栅极；第三十开关管的栅极连接第二十七开关管的源极，源极输入第一参考电平，漏极连接第二十九开关管的源极；第三十一开关管的栅极连接第三级栅极驱动单元中的上拉控制模块的输出端，漏极输入第二参考电平，源极连接第三十二开关管的漏极；第三十二开关管的栅极和源极输入第一参考电平；第三十三开关管的栅极连接第三十一开关管的栅极，漏极连接第二十五开关管的源极，源极为反相器的第三输出端，连接第三级栅极驱动单元中的第八开关管的栅极；第三十四开关管的栅极连接第三十一开关管的源极，源极输入第一参考电平，漏极连接第三十三开关管的源极。
通过上述方案，本发明的有益效果是：本发明通过在每级栅极驱动单元中包括用于根据上级级传信号生成扫描电平信号的上拉控制模块、用于根据扫描电平信号和第一时钟信号，拉升两条扫描线中的第一扫描线的栅极驱动信号的第一上拉模块、用于根据扫描电平信号和第二时钟信号，拉升两条扫描线中的第二扫描线的栅极驱动信号的第二上拉模块、用于根据扫描电平信号生成第一级传信号的第一下传模块、用于根据扫描电平信号生成第二级传信号的第二下传模块、用于拉低第一扫描线和第二扫描线的栅极驱动信号的下拉模块、第一自举电容、第二自举电容、以及用于维持第一扫描线和第二扫描线的栅极驱动信号的低电平的下拉维持模块，使每个栅极驱动单元分别驱动连续设置的两条扫描线，能够减少GOA电路的元件数量，便于实现超窄边框设计。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本发明第一实施例的栅极驱动单元的电路示意图；
图2是图1中的栅极驱动单元应用于第一级的电路示意图；
图3是图1中的栅极驱动单元应用于第二级的电路示意图；
图4是图1中的栅极驱动单元的波形示意图；
图5是图1中的栅极驱动单元应用于最后一级的电路示意图；
图6是本发明第二实施例的栅极驱动单元的电路示意图；
图7是图6中的栅极驱动单元应用于最后一级的电路示意图；
图8是本发明第一实施例的反相器的电路示意图；
图9是本发明第二实施例的反相器的电路示意图；
图10是包括图9中的反相器的栅极驱动单元的波形示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1所示，图1是本发明实施例的栅极驱动电路的结构示意图。如图1所示，栅极驱动电路包括级联的多个栅极驱动单元1，每个栅极驱动单元1用于分别驱动连续设置的两条扫描线，包括：上拉控制模块10、第一上拉模块11、第二上拉模块12、第一下传模块13、第二下传模块14、下拉模块15、第一自举电容16、第二自举电容17以及下拉维持模块18。
上拉控制模块10用于根据上级级传信号ST(2N-2)生成扫描电平信号Q(2N-1)。第一上拉模块11用于根据扫描电平信号Q(2N-1)和第一时钟信号CK(n)，拉升两条扫描线中的第一扫描线的栅极驱动信号G(2N-1)。第二上拉模块12用于根据扫描电平信号Q(2N-1)和第二时钟信号CK(n+1)，拉升两条扫描线中的第二扫描线的栅极驱动信号G(2N)。第一下传模块13用于根据扫描电平信号Q(2N-1)生成第一级传信号ST(2N-1)。第二下传模块14用于根据扫描电平信号Q(2N-1)生成第二级传信号ST(2N)。下拉模块15用于拉低第一扫描线和第二扫描线的栅极驱动信号G(2N-1)和G(2N)。第一自举电容16用于生成第一扫描线的栅极驱动信号G(2N-1)的低电平。第二自举电容17用于生成第二扫描线的栅极驱动信号G(2N)的低电平。下拉维持模块18用于维持第一扫描线和第二扫描线的栅极驱动信号G(2N-1)和G(2N)的低电平。本发明实施例的每个栅极驱动单元1包括两个上拉模块11、12以及两个下传模块13、14，可以输出两个栅极驱动信号G(2N-1)和G(2N)，分别驱动连续设置的两条扫描线，其他部分可以共用，如此能够减少GOA电路的元件数量，便于实现超窄边框设计。
在更具体的实施例中，上拉控制模块10包括第一开关管T1。第一开关管T1的栅极输入上级级传信号ST(2N-2)，源极接第一参考电平VSS1，漏极分别与第一上拉模块11、第二上拉模块12、第一下传模块13、第二下传模块14、第一自举电容16、第二自举电容17以及下拉维持模块18连接，共同的连接点称为第一控制节点Q(2N-1)。其中，第一参考电平VSS1为恒压负电位。
第一上拉模块11包括第二开关管T2。第二开关管T2的栅极与第一开关管T1的漏极连接，漏极输入第一时钟信号CK(n)，源极输出第一扫描线的栅极驱动信号G(2N-1)。第一下传模块13包括第三开关管T3，第三开关管T3的栅极与第一开关管T1的漏极连接，漏极输入第一时钟信号CK(n)，源极输出第一级传信号ST(2N-1)。第二上拉模块12包括第四开关管T4。第四开关管T4的栅极与第一开关管T1的漏极连接，漏极输入第二时钟信号CK(n+1)，源极输出第二扫描线的栅极驱动信号G(2N)。第二下传模块14包括第五开关管T5，第五开关管T5的栅极与第一开关管T1的漏极连接，漏极输入第二时钟信号CK(n+1)，源极输出第二级传信号ST(2N)。第一上拉模块11和第二上拉模块12以及第一下传模块13和第二下传模块14共享第一控制节点Q(2N-1)，能够输出连续两个栅极驱动信号G(2N-1)和G(2N)，分别驱动连续设置的两条扫描线，而其他部分可以共用，使原来需要使用两级栅极驱动单元来驱动的连续两条扫描线，本发明实施例使用一级栅极驱动单元就能实现，如此能够大大减少GOA电路的元件数量，整体上每两级至少减少了12个TFT元件，便于实现超窄边框设计。其中第一时钟信号CK(n)平移1/4个时钟周期即可得到第二时钟信号CK(n+1)。当然第二时钟信号CK(n+1)也可以是直接输入，而不是通过第一时钟信号CK(n)平移获取，在此不作限制。
下拉模块15包括第六开关管T6和第七开关管T7。第六开关管T6的栅极输入下级级传信号ST(2N+2)或下级栅极驱动信号G(2N+2)，漏极与第一开关管T1的漏极连接，源极连接第七开关管T7的漏极。第七开关管T7的栅极输入第三时钟信号CK(n+3)，源极连接于第一扫描线的栅极驱动信号G(2N-1)。其中第三时钟信号CK(n+3)可以是通过第一时钟信号CK(n)平移3/4个时钟周期获得。
下拉维持模块18包括反相器U1、第八开关管T8、第九开关管T9、第十开关管T10、第十一开关管T11以及第十二开关管T12。反相器U1的输入端与第一开关管T1的漏极连接，反相器U1的输出端连接第八开关管T8的栅极、第九开关管T9的栅极、第十开关管T10的栅极以及第十一开关管T11的栅极。第八开关管T8的漏极与第一开关管T1的漏极连接，源极连接第十一开关管T11的源极。第九开关管T9的漏极输入第二参考电平VDD1，源极连接于第一扫描线的栅极驱动信号G(2N-1)，第十开关管T10的漏极输入第二参考电平VDD1，源极连接于第二扫描线的栅极驱动信号G(2N)，第十一开关管T11的漏极输入第三参考电平VDD2，源极连接第十二开关管T12的漏极，第十二开关管T12的栅极与第一开关管T1的漏极连接，源极输入第一参考电平VSS1。其中，第二参考电平VDD1和第三参考电平VDD2为恒压正电位，第三参考电平VDD2的电位高于第二参考电平VDD1的电位。
以上各开关管皆为P型薄膜晶体管。N和n皆为正整数。
图2是图1中的栅极驱动单元1应用于第一级的电路示意图。如图2所示，第一开关管T1的栅极输入启动信号STV，第一上拉模块11输入的第一时钟信号为时钟信号CK1，第二上拉模块输入第二时钟信号为时钟信号CK2。其中时钟信号CK2可以通过时钟信号CK1平移1/4个周期得到。通过第二开关管T2输出第一扫描线的驱动信号G1，通过第四开关管T4输出第二扫描线的驱动信号G2，并通过第三开关管T3输出第一级传信号ST1，通过第五开关管T3输出第二级传信号ST2。图3是图1中的栅极驱动单元1应用于第二级的电路示意图。如图3所示，第一开关管T1的栅极输入第一级栅极驱动单元输出的第二级传信号ST2。第一上拉模块11输入的第一时钟信号为时钟信号CK3，第二上拉模块12输入第二时钟信号为时钟信号CK4。其中时钟信号CK3可以通过时钟信号CK2平移1/4个周期得到，时钟信号CK4可以通过时钟信号CK3平移1/4个周期得到。分别通过第二开关管T2和第四开关管T4输出第三扫描线的栅极驱动信号G3和第四扫描线的栅极驱动信号G4。同时分别通过第三开关管T3和第五开关管T5输出第三级传信号ST3和第四级传信号ST4。
图1中的栅极驱动单元1的工作过程如下：
上级级传信号ST(2N-2)为低电位时，第一开关管T1导通，对第一自举电容16 和第二自举电容17充电，使第一节点 Q(N) 得到一负电位，启动该栅极驱动单元1。随后上级级传信号ST(2N-2) 转变为高电位，而位于第一开关管T1漏极的第一控制节点Q(2N-1)通过第一自举电容Cb1和第二自举电容Cb2维持负电位。然后，第二开关管T2、第三开关管T3、第四开关管T4以及第五开关管T5受第一控制节点Q(2N-1)的控制导通，此时第一时钟信号CK(n)的低电平到来，通过第二开关管T2和第三开关管T3继续向第一自举电容Cb1充电，使得第一控制节点Q(2N-1)达到更低的负电位。与此同时，第二开关管T2的源极输出第一级传信号ST(2N-1)的低电平，第三开关管T3的源极输出第一扫描线的栅极驱动信号G(2N-1)的低电平。对于 PMOS 栅极驱动电路，一般将扫描驱动信号为低电位的时隙称为作用期间。
此时在作用期间，由于第一控制节点Q(2N-1)为低电位，经反相器U1反相后得到第二控制节点P(2N-1)为高电位，下拉维持模块18中的第十二开关管T12导通，而第十一开关管T11、第八开关管T8、第九开关管T9以及第十开关管T10均关闭。第八开关管T12的源极的电位被拉低至第一参考电平VSS1，如此能够减少第一控制节点Q(2N-1)经过第八开关管T8的漏电。另外由于第十二开关管导通，使第一控制节点Q(2N-1)近似维持第一参考电平VSS1，而采用第一参考电平VSS1来进行第一开关管T1的信号传递，也而可以减少第一控制节点Q(2N-1)的漏电。
接着，第一时钟信号CK(n)变为高电位，相应地由第二开关管T2源极输出的第一扫描线的栅极驱动信号G(2N-1)以及由第三开关管T3源极输出的第一级传信号ST(2N-1)也转变为高电位。第四开关管T4和第五开关管T5受第一控制节点Q(2N-1)的控制继续导通，此时第二时钟信号CK(n+1)的低电平到来，通过第四开关管T4和第五开关管T5向第二自举电容Cb2充电，使得第一控制节点Q(2N-1)继续维持负电位。与此同时，第四开关管T4的源极输出第二级传信号ST(2N)的低电平，第五开关管T5的源极输出第二扫描线的栅极驱动信号G(2N)的低电平。
之后，第二时钟信号CK(n+1)变为高电位，相应地由第四开关管T4源极输出的第二扫描线的栅极驱动信号G(2N)以及由第五开关管T5源极输出的第二级传信号ST(2N)也转变为高电位，电路进入非工作期间。当第三时钟信号CK(n+3)、以及下级级传信号ST(2N+2)或下级栅极驱动信号G(2N+2)的低电位到来时，第六开关管T6和第七开关管T7均导通，第一控制节点Q(2N-1)的电位被拉到第一扫描线的栅极驱动信号G(2N-1)的高电位，第二开关管T2、第三开关管T3、第四开关管T4以及第五开关管T5均关闭。
此时在非作用期间，由于第一控制节点Q(2N-1)为高电位，经反相器U1反相后得到第二控制节点P(2N-1)为低电位。下拉维持模块18中的第十二开关管T12关闭，而第八开关管T8、第九开关管T9、第十开关管T10以及第十一开关管T11均导通，第一控制节点Q(2N-1)的电位被第八开关管T8和第十一开关管T11抬升并保持在第三参考电平VDD2。而第一扫描线的栅极驱动信号 G(2N-1)和第二扫描线的栅极驱动信号G(2N)的电位分别被第九开关管T9和第十开关管T10保持在第二参考电平VDD1。
以图2和图3中的栅极驱动单元1为例，将图2所示的第一级的栅极驱动单元与图3所示的第二级的栅极驱动单元级联，其波形如图4所示。启动脉冲STV为低电平时启动第一级的栅极驱动单元，在其第一控制节点Q(1)为低电平期间，对应的第二控制节点P1为高电平，第一级的栅极驱动单元的第一时钟信号CK1和第二时钟信号CK2的低电位依次到来，对应分别输出第一扫描线的栅极驱动信号G1和第二扫描线的栅极驱动信号G2。通过与第二扫描线的栅极驱动信号G2同时输出的第二级传信号ST2的低电平启动第二级的栅极驱动单元。并在其第一控制节点Q(3)为低电平期间，对应的第二控制节点P3为高电平，第二级的栅极驱动单元的第一时钟信号CK3和第二时钟信号CK4的低电位依次到来，对应分别输出第三扫描线的栅极驱动信号G3和第四扫描线的栅极驱动信号G4。
图5是图1中的栅极驱动单元1应用于最后一级的电路示意图。如图5所示，第一开关管T1的栅极输入前一个栅极驱动单元输出的第二级传信号ST(last-2)，第一上拉模块11和第一下传模块12输入的第一时钟信号为CK3，分别输出倒数第二条扫描线的栅极驱动信号G(last-1)和倒数第二个下传信号ST(last-1)。第二上拉模块13和第二下传模块14输入的第二时钟信号为CK4，分别输出最后一条扫描线的栅极驱动信号G(last)和最后一级的下传信号ST(last)。第六开关管的栅极连接到启动脉冲STV，同时去掉第七开关管T7。
图6是本发明第二实施例的栅极驱动单元的电路示意图。如图6所示，与图1中的栅极驱动单元的区别在于：第六开关管T6采用二极体接法，即第六开关管T6的漏极和栅极皆连接至第一控制节点，即第一开关管T1的漏极。对应的最后一级的栅极驱动单元的电路如图7所示，保留第七开关管T7，并且第七开关管的栅极连接至第二时钟信号CK2。
进一步地，如图8所示，下拉维持模块18中的反相器U1包括主反相模块101和辅助反相模块102。主反相模块101包括：第十三开关管T13、第十四开关管T14、第十五开关管T15以及第十六开关管T16。辅助反相模块102包括第十七开关管T17以及第十八开关管T18。第十三开关管T13的栅极与第一开关管T1的漏极连接，漏极输入第二参考电平VDD1，源极连接第十四开关管T14的漏极。第十四开关管T14的栅极和源极输入第一参考电平VSS1。第十五开关管T15的栅极与第一开关管T1的漏极连接，漏极连接第十七开关管T17的源极，源极为反相器U1的输出端，连接第十六开关管T16的漏极。第十六开关管T16的栅极连接第十三开关管T13的源极，源极输入第一参考电平VSS1。第十七开关管T17的栅极与第一开关管T1的漏极连接，漏极输入第三参考电平VDD2。第十八开关管T18的栅极连接第十六开关管T16的栅极，源极输入第一参考电平VSS1，漏极连接第十七开关管T17的源极。
反相器U1的工作过程如下：
第一控制节点Q(2N-1) 为低电位时，主反相器101中的第十三开关管T13和第十五开关管T15均导通，第十四开关管T14和第十六开关管T16均关闭。辅助反相器102中的第十七开关管T17导通，第十八开关管T18关闭。第二控制节点P(2N-1)的电位被抬升至电位高于第二参考电平VDD1的第三参考电平VDD2的电位。第一控制节点Q(2N-1) 为高电位时，主反相器101中的第十三开关管T13和第十五开关管T15均关闭，第十四开关管T14和第十六开关管T16均导通。辅助反相器102中的第十七开关管T17关闭，第十八开关管T18导通。第二控制节点P(2N-1)的电位被限制为第一参考电平VSS1的电位。其中，第二控制节点P(2N-1)即为反相器U1的输出端。
在本发明实施例中，连续三级的栅极驱动单元可以共享一个反相器。如图9所示，反相器U2包括三个主反相模块201、203、204和一辅助反相模块202。第一个主反相模块201包括：第十九开关管T19、第二十开关管T20、第二十一开关管T21、第二十二开关管T22。辅助反相模块202包括第二十三开关管T23、第二十四开关管T24、第二十五开关管T25、第二十六开关管T26。第二个主反相模块203包括：第二十七开关管T27、第二十八开关管T28、第二十九开关管T29、第三十开关管T30。第三个主反相模块204包括：第三十一开关管T31以及第三十二开关管T32、第三十三开关管T33以及第三十四开关管T34。第十九开关管T19的栅极与第一级栅极驱动单元中的上拉控制模块的输出端连接，漏极输入第二参考电平VDD1，源极连接第二十开关管T20的漏极，第二十开关管T20的栅极和源极输入第一参考电平VSS1。第二十一开关管T21的栅极与第一级栅极驱动单元中的上拉控制模块的输出端连接，漏极连接第二十五开关管T25的源极，源极为反相器U2的第一输出端P(N)，连接第一级栅极驱动单元中的第八开关管的栅极。第二十二开关管T22的栅极连接第十九开关管T19的源极，源极输入第一参考电平VSS1，漏极连接第二十一开关管T21的源极。第二十三开关管T23的栅极与第一级栅极驱动单元中的上拉控制模块的输出端连接，漏极输入第三参考电平VDD2，源极连接第二十五开关管T25的源极。第二十四开关管T24的栅极连接第二十二开关管T22的栅极，漏极连接第二十五开关管T25的源极，源极连接第二十六开关管T26的漏极。第二十五开关管T25的栅极连接第三级栅极驱动单元中的上拉控制模块的输出端，漏极输入第三参考电平VDD2。第二十六开关管T26的栅极连接第三十四开关管T34的栅极，源极输入第一参考电平VSS1。第二十七开关管T27的栅极连接第二级栅极驱动单元中的上拉控制模块的输出端，漏极输入第二参考电平VDD1，源极连接第二十八开关管T28的漏极。第二十八开关管T28的栅极和源极输入第一参考电平VSS1。第二十九开关管T29的栅极连接第二级栅极驱动单元中的上拉控制模块的输出端，漏极连接第二十五开关管T25的源极，源极为反相器U2的第二输出端P(N+1)，连接第二级栅极驱动单元中的第八开关管的栅极。第三十开关管T30的栅极连接第二十七开关管T27的源极，源极输入第一参考电平VSS1，漏极连接第二十九开关管T29的源极。第三十一开关管T31的栅极连接第三级栅极驱动单元中的上拉控制模块的输出端，漏极输入第二参考电平VDD1，源极连接第三十二开关管T32的漏极。第三十二开关管T32的栅极和源极输入第一参考电平VSS1。第三十三开关管T33的栅极连接第三十一开关管T31的栅极，漏极连接第二十五开关管T25的源极，源极为反相器U2的第三输出端，连接第三级栅极驱动单元中的第八开关管的栅极。第三十四开关管T34的栅极连接第三十一开关管T31的源极，源极输入第一参考电平VSS1，漏极连接第三十三开关管T33的源极。
反相器U2的具体的工作过程与反相器U1类似，在此不再赘述。
图10是包括图9中的反相器的栅极驱动单元的波形示意图。如图10所示，取N=1，M=1，对应地，P1为反相器U2的第一输出端，连接至第一级栅极驱动单元中的第八开关管的栅极，P2为第二输出端，连接至第二级栅极驱动单元中的第八开关管的栅极，P3为第三输出端，连接至第三给栅极驱动单元中的第八开关管的栅极。K1为反相器U2的共享节点，位于第二十五开关管25的源极。从图中可以看出，反相器U2的第一输出端P1的电位与第一级栅极驱动单元中的第一控制节点Q1的电位相反，此时第一主反相模块201处于工作期间。反相器U2的第二输出端P2的电位与第二级栅极驱动单元中的第一控制节点Q2的电位相反，此时第二主反相模块203处于工作期间。反相器U2的第三输出端P3的电位与第三级栅极驱动单元中的第一控制节点Q3的电位相反，此时第三主反相模块204处于工作期间。而共享节点K1在任一一个主反相模块工作时皆为高电位。
综上所述，本发明在每级栅极驱动单元中包括用于根据上级级传信号生成扫描电平信号的上拉控制模块、用于根据扫描电平信号和第一时钟信号，拉升两条扫描线中的第一扫描线的栅极驱动信号的第一上拉模块、用于根据扫描电平信号和第二时钟信号，拉升两条扫描线中的第二扫描线的栅极驱动信号的第二上拉模块、用于根据扫描电平信号生成第一级传信号的第一下传模块、用于根据扫描电平信号生成第二级传信号的第二下传模块、用于拉低第一扫描线和第二扫描线的栅极驱动信号的下拉模块、第一自举电容、第二自举电容、以及用于维持第一扫描线和第二扫描线的栅极驱动信号的低电平的下拉维持模块，使每个栅极驱动单元分别驱动连续设置的两条扫描线，能够减少GOA电路的元件数量，便于实现超窄边框设计。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种栅极驱动电路，其中，所述栅极驱动电路包括级联的多个栅极驱动单元，每个所述栅极驱动单元用于分别驱动连续设置的两条扫描线，包括：
    上拉控制模块，用于根据上级级传信号生成扫描电平信号；
    第一上拉模块，用于根据所述扫描电平信号和第一时钟信号，拉升所述两条扫描线中的第一扫描线的栅极驱动信号；
    第二上拉模块，用于根据所述扫描电平信号和第二时钟信号，拉升所述两条扫描线中的第二扫描线的栅极驱动信号；
    第一下传模块，用于根据所述扫描电平信号生成第一级传信号；
    第二下传模块，用于根据所述扫描电平信号生成第二级传信号；
    下拉模块，用于拉低所述第一扫描线和所述第二扫描线的栅极驱动信号；
    第一自举电容，用于生成所述第一扫描线的栅极驱动信号的低电平；
    第二自举电容，用于生成所述第二扫描线的栅极驱动信号的低电平；
    下拉维持模块，用于维持所述第一扫描线和所述第二扫描线的栅极驱动信号的低电平。
  2. 根据权利要求1所述的电路，其中，所述上拉控制模块包括第一开关管，所述第一开关管的栅极输入所述上级级传信号，源极接第一参考电平，漏极分别与所述第一上拉模块、所述第二上拉模块、第一下传模块、所述第二下传模块、所述第一自举电容、所述第二自举电容以及所述下拉维持模块连接。
  3. 根据权利要求2所述的电路，其中，
    所述第一上拉模块包括第二开关管，所述第二开关管的栅极与所述第一开关管的漏极连接，漏极输入所述第一时钟信号，源极输出所述第一扫描线的栅极驱动信号；
    所述第一下传模块包括第三开关管，所述第三开关管的栅极与所述第一开关管的漏极连接，漏极输入所述第一时钟信号，源极输出所述第一级传信号。
  4. 根据权利要求2所述的电路，其中，
    所述第二上拉模块包括第四开关管，所述第四开关管的栅极与所述第一开关管的漏极连接，漏极输入所述第二时钟信号，源极输出所述第二扫描线的栅极驱动信号。
  5. 根据权利要求2所述的电路，其中，所述第二下传模块包括第五开关管，所述第五开关管的栅极与所述第一开关管的漏极连接，漏极输入所述第二时钟信号，源极输出所述第二级传信号。
  6. 根据权利要求2所述的电路，其中，所述下拉模块包括第六开关管和第七开关管，所述第六开关管的栅极输入下级级传信号或下级栅极驱动信号，漏极与所述第一开关管的漏极连接，源极连接所述第七开关管的漏极；所述第七开关管的栅极输入第三时钟信号，源极连接于所述第一扫描线的栅极驱动信号。
  7. 根据权利要求2所述的电路，其中，所述下拉维持模块包括包括反相器、第八开关管、第九开关管、第十开关管、第十一开关管以及第十二开关管：
    所述反相器的输入端与所述第一开关管的漏极连接，所述反相器的输出端连接所述第八开关管的栅极、第九开关管的栅极、第十开关管的栅极以及第十一开关管的栅极，所述第八开关管的漏极与所述第一开关管的漏极连接，源极连接所述第十一开关管的源极，所述第九开关管的漏极输入第二参考电平，源极连接于所述第一扫描线的栅极驱动信号，所述第十开关管的漏极输入所述第二参考电平，源极连接于所述第二扫描线的栅极驱动信号，所述第十一开关管的漏极输入第三参考电平，源极连接第十二开关管的漏极，所述第十二开关管的栅极与所述第一开关管的漏极连接，源极输入第一参考电平。
  8. 根据权利要求7所述的电路，其中，所述反相器包括主反相模块和辅助反相模块，所述主反相模块包括：第十三开关管、第十四开关管、第十五开关管以及第十六开关管，所述辅助反相模块包括第十七开关管以及第十八开关管，所述第十三开关管的栅极与所述第一开关管的漏极连接，漏极输入所述第二参考电平，源极连接所述第十四开关管的漏极，所述第十四开关管的栅极和源极输入所述第一参考电平；所述第十五开关管的栅极与所述第一开关管的漏极连接，漏极连接所述第十七开关管的源极，源极为所述反相器的输出端，连接所述第十六开关管的漏极；所述第十六开关管的栅极连接所述第十三开关管的源极，源极输入所述第一参考电平；所述第十七开关管的栅极与所述第一开关管的漏极连接，漏极输入所述第三参考电平；所述第十八开关管的栅极连接所述第十六开关管的栅极，源极输入所述第一参考电平，漏极连接所述第十七开关管的源极。
  9. 根据权利要求7所述的电路，其中，连续三级的所述栅极驱动单元共享所述反相器。
  10. 根据权利要求9所述的电路，其中，所述反相器包括三个主反相模块和一辅助反相模块，第一个所述主反相模块包括：第十九开关管、第二十开关管、第二十一开关管、第二十二开关管；所述辅助反相模块包括第二十三开关管、第二十四开关管、第二十五开关管、第二十六开关管；第二个所述主反相模块包括：第二十七开关管、第二十八开关管、第二十九开关管、第三十开关管；第三个所述主反相模块包括：第三十一开关管以及第三十二开关管、第三十三开关管以及第三十四开关管；
    所述第十九开关管的栅极与第一级栅极驱动单元中的所述上拉控制模块的输出端连接，漏极输入所述第二参考电平，源极连接所述第二十开关管的漏极，所述第二十开关管的栅极和源极输入所述第一参考电平；所述第二十一开关管的栅极与所述上拉控制模块的输出端连接，漏极连接所述第二十五开关管的源极，源极为所述反相器的第一输出端，连接所述第一级栅极驱动单元中的所述第八开关管的栅极，所述第二十二开关管的栅极连接第十九开关管的源极，源极输入所述第一参考电平，漏极连接所述第二十一开关管的源极；
    所述第二十三开关管的栅极与所述上拉控制模块的输出端连接，漏极输入所述第三参考电平，源极连接所述第二十五开关管的源极；所述第二十四开关管的栅极连接所述第二十二开关管的栅极，漏极连接所述第二十五开关管的源极，源极连接所述第二十六开关管的漏极；所述第二十五开关管的栅极连接第三级栅极驱动单元中的上拉控制模块的输出端，漏极输入所述第三参考电平；所述第二十六开关管的栅极连接所述第三十四开关管的栅极，源极输入所述第一参考电平；
    所述第二十七开关管的栅极连接第二级栅极驱动单元中的上拉控制模块的输出端，漏极输入所述第二参考电平，源极连接所述第二十八开关管的漏极；所述第二十八开关管的栅极和源极输入所述第一参考电平；所述第二十九开关管的栅极连接所述第二级栅极驱动单元中的上拉控制模块的输出端，漏极连接所述第二十五开关管的源极，源极为所述反相器的第二输出端，连接所述第二级栅极驱动单元中的第八开关管的栅极；第三十开关管的栅极连接所述第二十七开关管的源极，源极输入所述第一参考电平，漏极连接所述第二十九开关管的源极；
    所述第三十一开关管的栅极连接所述第三级栅极驱动单元中的上拉控制模块的输出端，漏极输入所述第二参考电平，源极连接所述第三十二开关管的漏极；所述第三十二开关管的栅极和源极输入所述第一参考电平；所述第三十三开关管的栅极连接所述第三十一开关管的栅极，漏极连接所述第二十五开关管的源极，源极为所述反相器的第三输出端，连接所述第三级栅极驱动单元中的第八开关管的栅极；所述第三十四开关管的栅极连接所述第三十一开关管的源极，源极输入所述第一参考电平，漏极连接所述第三十三开关管的源极。
  11. 一种栅极驱动电路，其中，所述栅极驱动电路包括级联的多个栅极驱动单元，每个所述栅极驱动单元用于分别驱动连续设置的两条扫描线，包括：
    上拉控制模块，用于根据上级级传信号生成扫描电平信号；
    第一上拉模块，用于根据所述扫描电平信号和第一时钟信号，拉升所述两条扫描线中的第一扫描线的栅极驱动信号；
    第二上拉模块，用于根据所述扫描电平信号和第二时钟信号，拉升所述两条扫描线中的第二扫描线的栅极驱动信号；
    第一下传模块，用于根据所述扫描电平信号生成第一级传信号；
    第二下传模块，用于根据所述扫描电平信号生成第二级传信号；
    下拉模块，用于拉低所述第一扫描线和所述第二扫描线的栅极驱动信号；
    第一自举电容，用于生成所述第一扫描线的栅极驱动信号的低电平；
    第二自举电容，用于生成所述第二扫描线的栅极驱动信号的低电平；
    下拉维持模块，用于维持所述第一扫描线和所述第二扫描线的栅极驱动信号的低电平；
    其中，所述第一时钟信号平移1/4个时钟周期即可得到所述第二时钟信号。
  12. 根据权利要求11所述的电路，其中，所述上拉控制模块包括第一开关管，所述第一开关管的栅极输入所述上级级传信号，源极接第一参考电平，漏极分别与所述第一上拉模块、所述第二上拉模块、第一下传模块、所述第二下传模块、所述第一自举电容、所述第二自举电容以及所述下拉维持模块连接。
  13. 根据权利要求12所述的电路，其中，
    所述第一上拉模块包括第二开关管，所述第二开关管的栅极与所述第一开关管的漏极连接，漏极输入所述第一时钟信号，源极输出所述第一扫描线的栅极驱动信号；
    所述第一下传模块包括第三开关管，所述第三开关管的栅极与所述第一开关管的漏极连接，漏极输入所述第一时钟信号，源极输出所述第一级传信号。
  14. 根据权利要求12所述的电路，其中，
    所述第二上拉模块包括第四开关管，所述第四开关管的栅极与所述第一开关管的漏极连接，漏极输入所述第二时钟信号，源极输出所述第二扫描线的栅极驱动信号。
  15. 根据权利要求12所述的电路，其中，所述第二下传模块包括第五开关管，所述第五开关管的栅极与所述第一开关管的漏极连接，漏极输入所述第二时钟信号，源极输出所述第二级传信号。
  16. 根据权利要求12所述的电路，其中，所述下拉模块包括第六开关管和第七开关管，所述第六开关管的栅极输入下级级传信号或下级栅极驱动信号，漏极与所述第一开关管的漏极连接，源极连接所述第七开关管的漏极；所述第七开关管的栅极输入第三时钟信号，源极连接于所述第一扫描线的栅极驱动信号。
  17. 根据权利要求12所述的电路，其中，所述下拉维持模块包括包括反相器、第八开关管、第九开关管、第十开关管、第十一开关管以及第十二开关管：
    所述反相器的输入端与所述第一开关管的漏极连接，所述反相器的输出端连接所述第八开关管的栅极、第九开关管的栅极、第十开关管的栅极以及第十一开关管的栅极，所述第八开关管的漏极与所述第一开关管的漏极连接，源极连接所述第十一开关管的源极，所述第九开关管的漏极输入第二参考电平，源极连接于所述第一扫描线的栅极驱动信号，所述第十开关管的漏极输入所述第二参考电平，源极连接于所述第二扫描线的栅极驱动信号，所述第十一开关管的漏极输入第三参考电平，源极连接第十二开关管的漏极，所述第十二开关管的栅极与所述第一开关管的漏极连接，源极输入第一参考电平。
  18. 根据权利要求17所述的电路，其中，所述反相器包括主反相模块和辅助反相模块，所述主反相模块包括：第十三开关管、第十四开关管、第十五开关管以及第十六开关管，所述辅助反相模块包括第十七开关管以及第十八开关管，所述第十三开关管的栅极与所述第一开关管的漏极连接，漏极输入所述第二参考电平，源极连接所述第十四开关管的漏极，所述第十四开关管的栅极和源极输入所述第一参考电平；所述第十五开关管的栅极与所述第一开关管的漏极连接，漏极连接所述第十七开关管的源极，源极为所述反相器的输出端，连接所述第十六开关管的漏极；所述第十六开关管的栅极连接所述第十三开关管的源极，源极输入所述第一参考电平；所述第十七开关管的栅极与所述第一开关管的漏极连接，漏极输入所述第三参考电平；所述第十八开关管的栅极连接所述第十六开关管的栅极，源极输入所述第一参考电平，漏极连接所述第十七开关管的源极。
  19. 根据权利要求17所述的电路，其中，连续三级的所述栅极驱动单元共享所述反相器。
  20. 根据权利要求19所述的电路，其中，所述反相器包括三个主反相模块和一辅助反相模块，第一个所述主反相模块包括：第十九开关管、第二十开关管、第二十一开关管、第二十二开关管；所述辅助反相模块包括第二十三开关管、第二十四开关管、第二十五开关管、第二十六开关管；第二个所述主反相模块包括：第二十七开关管、第二十八开关管、第二十九开关管、第三十开关管；第三个所述主反相模块包括：第三十一开关管以及第三十二开关管、第三十三开关管以及第三十四开关管；
    所述第十九开关管的栅极与第一级栅极驱动单元中的所述上拉控制模块的输出端连接，漏极输入所述第二参考电平，源极连接所述第二十开关管的漏极，所述第二十开关管的栅极和源极输入所述第一参考电平；所述第二十一开关管的栅极与所述上拉控制模块的输出端连接，漏极连接所述第二十五开关管的源极，源极为所述反相器的第一输出端，连接所述第一级栅极驱动单元中的所述第八开关管的栅极，所述第二十二开关管的栅极连接第十九开关管的源极，源极输入所述第一参考电平，漏极连接所述第二十一开关管的源极；
    所述第二十三开关管的栅极与所述上拉控制模块的输出端连接，漏极输入所述第三参考电平，源极连接所述第二十五开关管的源极；所述第二十四开关管的栅极连接所述第二十二开关管的栅极，漏极连接所述第二十五开关管的源极，源极连接所述第二十六开关管的漏极；所述第二十五开关管的栅极连接第三级栅极驱动单元中的上拉控制模块的输出端，漏极输入所述第三参考电平；所述第二十六开关管的栅极连接所述第三十四开关管的栅极，源极输入所述第一参考电平；
    所述第二十七开关管的栅极连接第二级栅极驱动单元中的上拉控制模块的输出端，漏极输入所述第二参考电平，源极连接所述第二十八开关管的漏极；所述第二十八开关管的栅极和源极输入所述第一参考电平；所述第二十九开关管的栅极连接所述第二级栅极驱动单元中的上拉控制模块的输出端，漏极连接所述第二十五开关管的源极，源极为所述反相器的第二输出端，连接所述第二级栅极驱动单元中的第八开关管的栅极；第三十开关管的栅极连接所述第二十七开关管的源极，源极输入所述第一参考电平，漏极连接所述第二十九开关管的源极；
    所述第三十一开关管的栅极连接所述第三级栅极驱动单元中的上拉控制模块的输出端，漏极输入所述第二参考电平，源极连接所述第三十二开关管的漏极；所述第三十二开关管的栅极和源极输入所述第一参考电平；所述第三十三开关管的栅极连接所述第三十一开关管的栅极，漏极连接所述第二十五开关管的源极，源极为所述反相器的第三输出端，连接所述第三级栅极驱动单元中的第八开关管的栅极；所述第三十四开关管的栅极连接所述第三十一开关管的源极，源极输入所述第一参考电平，漏极连接所述第三十三开关管的源极。
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