WO2016095267A1 - 移位寄存器、级传栅极驱动电路及显示面板 - Google Patents

移位寄存器、级传栅极驱动电路及显示面板 Download PDF

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Publication number
WO2016095267A1
WO2016095267A1 PCT/CN2014/095388 CN2014095388W WO2016095267A1 WO 2016095267 A1 WO2016095267 A1 WO 2016095267A1 CN 2014095388 W CN2014095388 W CN 2014095388W WO 2016095267 A1 WO2016095267 A1 WO 2016095267A1
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WIPO (PCT)
Prior art keywords
transistor
signal input
stage
signal
input end
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PCT/CN2014/095388
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English (en)
French (fr)
Inventor
曹尚操
Original Assignee
深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to RU2017116636A priority Critical patent/RU2658887C1/ru
Priority to GB1708872.5A priority patent/GB2548047B/en
Priority to KR1020177019411A priority patent/KR101989718B1/ko
Priority to US14/426,354 priority patent/US9564097B2/en
Priority to DE112014007252.4T priority patent/DE112014007252B4/de
Priority to JP2017531506A priority patent/JP6593891B2/ja
Publication of WO2016095267A1 publication Critical patent/WO2016095267A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a shift register, a level transfer gate driving circuit and a display panel.
  • the horizontal scanning drive of the current liquid crystal display panel is mainly completed by an external integrated circuit, and the external integrated circuit realizes scanning by controlling the stepwise charging and discharging of the horizontal scanning lines of each level.
  • GOA Gate Driver on Array
  • the output time of the scan signal output terminal is too long, so that the volume of the TFT at the output end of the scan signal is increased, and the pull-down module discharges only the output end of the scan signal, resulting in deterioration of part of the TFT and output capability of the scan signal output terminal. Decline.
  • the technical problem to be solved by the present invention is to provide a shift register, a level transfer gate driving circuit and a display panel, which can reduce the size of the transistor, prevent the deterioration of the transistor, and increase the output capability of the circuit.
  • a technical solution adopted by the present invention is to provide a shift register, which includes: a downlink module, an output module, a first pull-down maintaining module, a second pull-down maintaining module, and a first a pull-down module, a second pull-down module; a downlink module, an output module, a first pull-down maintaining module, and a second pull-down maintaining module are connected to the first common point, and the first pull-down module is connected to the first pull-down maintaining module and the second Pulling down the maintenance module, the second pull-down module is connected between the first pull-down module and the output module; the first common point becomes high when the downlink module receives the high-level signal of the upper shift register; The sustaining module and the second pull-down maintaining module alternately receive the high-potential signal input by the lower-level shift register to cause the first pull-down module to conduct the pull-down with the first common point and maintain the first common point to a low potential, and the second pull-down module Pulling down and maintaining
  • the downlink module includes a first stage signal input end and a second stage signal input end, and is connected to the first stage signal output end of the upper stage shift register and the second stage signal output end;
  • the output module includes a signal input end, a second signal input end, a first stage signal output end, a second stage signal output end and a scan signal output end; wherein, the first stage signal output end and the second stage signal of the output module The output end is respectively connected to the first stage signal input end of the upper stage and/or the lower stage shift register and the second stage signal input end to provide a level transmission signal, and the first signal input end and the second signal input end receive the AC signal;
  • a pull-down maintenance module includes a third-level signal input end and a third signal input end, the third-level signal input end is connected to the first-stage signal output end of the lower-stage shift register, and the third signal input end receives the AC signal;
  • a second pull-down maintenance module includes a fourth-level signal input terminal and a fourth signal input terminal, and the
  • the output terminal transmits the potential of the first common point to a high potential through the first-level signal input terminal and the second-stage signal input terminal when receiving the high-level signal of the upper-stage shift register, and the output module first
  • the signal input end and the second signal input end receive the low potential clock signal to output the low potential scan signal through the scan signal output end; after the downlink module is turned off, the first common point is still high, and the first signal input end of the output module and The second signal input end receives the high potential clock signal to output the high potential scan signal through the scan signal output end; after the scan signal output end outputs, the third stage signal input end, the fourth signal level transmission input end and the sixth signal input end Inputting a high-level signal of the first-stage signal output end of the lower-stage shift register, and alternating the third signal input end and the fourth signal input end
  • the high potential signal turns on the first pull-down module to be electrically connected to the first common point to alternately pull down the first common point and the scan signal output end to a low potential, and the second
  • the downstream module includes a first transistor; the drain of the first transistor is connected to the second-stage signal input terminal, the source is connected to the first common point, and the gate is connected to the first-stage signal input terminal.
  • the drain of the first transistor is connected to a DC source.
  • the output module includes a second transistor, a third transistor and a fourth transistor; a drain of the second transistor is connected to the first signal input end, a source is connected to the scan signal output end; and a drain of the third transistor is connected to the second signal input end The source is connected to the first stage signal output end; the drain of the fourth transistor is connected to the second signal input end, the source is connected to the second stage signal output end; the gates of the second transistor, the third transistor and the fourth transistor are Each of the first common points is connected; a capacitor is connected between the gate and the source of the third transistor.
  • the first pull-down module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor
  • the first pull-down maintaining module includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a a thirteenth transistor and a fourteenth transistor
  • the second pull-down sustaining module includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor
  • a fifth transistor, a sixth transistor, and a seventh The gates of the transistors are connected to the first common point, the sources of the sixth transistor and the seventh transistor are connected to the fifth signal input end; the gates of the eighth transistor and the ninth transistor are connected to the first stage signal input end, and the source is connected The fifth signal input terminal.
  • the drains of the tenth transistor, the eleventh and twelfth transistors, and the gate of the twelfth transistor are all connected to the third signal input end, and the gate of the tenth transistor is connected to the third stage signal input end, and the source is connected
  • the source of the eleventh transistor is at a second common point; the gate of the eleventh transistor is connected to the source of the twelfth transistor; the source of the twelfth transistor is connected to the drain of the eighth transistor; and the drain of the thirteenth transistor
  • the pole is connected to the first common point, the gate is connected to the second common point, the source is connected to the fifth signal input end; the drain of the fourteenth transistor is connected to the scan signal output end, the gate is connected to the second common point, and the source is connected to the fifth terminal Signal input.
  • the drains of the fifteenth transistor, the sixteenth and seventeenth transistors, and the gate of the seventeenth transistor are all connected to the fourth signal input end, and the gate of the fifteenth transistor is connected to the fourth stage signal input end, the source
  • the terminal of the sixteenth transistor is connected to the third common point; the gate of the sixteenth transistor is connected to the source of the seventeenth transistor; the source of the seventeenth transistor is connected to the drain of the ninth transistor; the eighteenth transistor
  • the drain is connected to the first common point, the gate is connected to the third common point, and the source is connected to the fifth signal input end; the drain of the nineteenth transistor is connected to the scan signal output end, the gate is connected to the third common point, and the source is connected The fifth signal input terminal.
  • the gate of the tenth transistor is connected to the fourth signal input end, and the gate of the fifteenth transistor is connected to the third signal input end.
  • the second pull-down module includes a twentieth transistor, a twenty-first transistor, and a twenty-second transistor; the gates of the twentieth transistor, the twenty-first transistor, and the twenty-second transistor are all connected to the fifth-level signal.
  • the input end and the source are connected to the fifth signal input end; the drain of the twentieth transistor is connected to the scan signal output end, the drain of the twenty-first transistor is connected to the first stage signal output end, and the second twenty-second transistor is drained
  • the pole is connected to the first common point.
  • another technical solution adopted by the present invention is to provide a level transfer gate driving circuit, and the level transfer gate driving circuit includes a plurality of shift registers as above; wherein, each shift register The first-level signal output end and the second-level signal output end are connected to the upper-level shift register and the sub-level shift register of each stage of the signal input end and provide a level-transmitted signal.
  • the first stage signal input end of the first stage shift register of the level gate drive circuit and the second stage signal input end are connected to the STV signal;
  • the third stage signal input end of the last stage shift register is fourth
  • the STV signal is connected to the level signal input terminal and the fifth level signal input terminal.
  • the downlink module includes a first stage signal input end and a second stage signal input end, and is connected to the first stage signal output end of the upper stage shift register and the second stage signal output end;
  • the output module includes a signal input end, a second signal input end, a first stage signal output end, a second stage signal output end and a scan signal output end; wherein, the first stage signal output end and the second stage signal of the output module The output end is respectively connected to the first stage signal input end of the upper stage and/or the lower stage shift register and the second stage signal input end to provide a level transmission signal, and the first signal input end and the second signal input end receive the AC signal;
  • a pull-down maintenance module includes a third-level signal input end and a third signal input end, the third-level signal input end is connected to the first-stage signal output end of the lower-stage shift register, and the third signal input end receives the AC signal;
  • a second pull-down maintenance module includes a fourth-level signal input terminal and a fourth signal input terminal, and the
  • the output terminal transmits the potential of the first common point to a high potential through the first-level signal input terminal and the second-stage signal input terminal when receiving the high-level signal of the upper-stage shift register, and the output module first
  • the signal input end and the second signal input end receive the low potential clock signal to output the low potential scan signal through the scan signal output end; after the downlink module is turned off, the first common point is still high, and the first signal input end of the output module and The second signal input end receives the high potential clock signal to output the high potential scan signal through the scan signal output end; after the scan signal output end outputs, the third stage signal input end, the fourth signal level transmission input end and the sixth signal input end Inputting a high-level signal of the first-stage signal output end of the lower-stage shift register, and alternating the third signal input end and the fourth signal input end
  • the high potential signal turns on the first pull-down module to be electrically connected to the first common point to alternately pull down the first common point and the scan signal output end to a low potential, and the second
  • the downstream module includes a first transistor; the drain of the first transistor is connected to the second-stage signal input terminal, the source is connected to the first common point, and the gate is connected to the first-stage signal input terminal.
  • the drain of the first transistor is connected to a DC source.
  • the output module includes a second transistor, a third transistor and a fourth transistor; a drain of the second transistor is connected to the first signal input end, a source is connected to the scan signal output end; and a drain of the third transistor is connected to the second signal input end The source is connected to the first stage signal output end; the drain of the fourth transistor is connected to the second signal input end, the source is connected to the second stage signal output end; the gates of the second transistor, the third transistor and the fourth transistor are Each of the first common points is connected; a capacitor is connected between the gate and the source of the third transistor.
  • the first pull-down module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor
  • the first pull-down maintaining module includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a a thirteenth transistor and a fourteenth transistor
  • the second pull-down sustaining module includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor
  • a fifth transistor, a sixth transistor, and a seventh The gates of the transistors are connected to the first common point, the sources of the sixth transistor and the seventh transistor are connected to the fifth signal input end; the gates of the eighth transistor and the ninth transistor are connected to the first stage signal input end, and the source is connected The fifth signal input terminal.
  • the drains of the tenth transistor, the eleventh and twelfth transistors, and the gate of the twelfth transistor are all connected to the third signal input end, and the gate of the tenth transistor is connected to the third stage signal input end, and the source is connected
  • the source of the eleventh transistor is at a second common point; the gate of the eleventh transistor is connected to the source of the twelfth transistor; the source of the twelfth transistor is connected to the drain of the eighth transistor; and the drain of the thirteenth transistor
  • the pole is connected to the first common point, the gate is connected to the second common point, the source is connected to the fifth signal input end; the drain of the fourteenth transistor is connected to the scan signal output end, the gate is connected to the second common point, and the source is connected to the fifth terminal Signal input.
  • the drains of the fifteenth transistor, the sixteenth and seventeenth transistors, and the gate of the seventeenth transistor are all connected to the fourth signal input end, and the gate of the fifteenth transistor is connected to the fourth stage signal input end, the source
  • the terminal of the sixteenth transistor is connected to the third common point; the gate of the sixteenth transistor is connected to the source of the seventeenth transistor; the source of the seventeenth transistor is connected to the drain of the ninth transistor; the eighteenth transistor
  • the drain is connected to the first common point, the gate is connected to the third common point, and the source is connected to the fifth signal input end; the drain of the nineteenth transistor is connected to the scan signal output end, the gate is connected to the third common point, and the source is connected The fifth signal input terminal.
  • the gate of the tenth transistor is connected to the fourth signal input end, and the gate of the fifteenth transistor is connected to the third signal input end.
  • the second pull-down module includes a twentieth transistor, a twenty-first transistor, and a twenty-second transistor; the gates of the twentieth transistor, the twenty-first transistor, and the twenty-second transistor are all connected to the fifth-level signal.
  • the input end and the source are connected to the fifth signal input end; the drain of the twentieth transistor is connected to the scan signal output end, the drain of the twenty-first transistor is connected to the first stage signal output end, and the second twenty-second transistor is drained
  • the pole is connected to the first common point.
  • another technical solution adopted by the present invention is to provide a display panel including the above-described level gate driving circuit.
  • the first stage signal input end of the first stage shift register of the level gate drive circuit and the second stage signal input end are connected to the STV signal;
  • the third stage signal input end of the last stage shift register is fourth
  • the STV signal is connected to the level signal input terminal and the fifth level signal input terminal.
  • the invention has the beneficial effects that the invention is different from the prior art, and the invention controls the output of the scan signal of the lower shift register by the level transfer signal of the upper shift register, and alternately pulls down the scan by the two pull-down maintenance modules after the scan signal is output.
  • the potential of the signal output terminal is low, and the potential of the output terminal of the scan signal is pulled down to the low potential through the second pull-down module, thereby preventing leakage of some transistors in the circuit, ensuring stable output of the low-potential signal at the output end of the scan signal, and preventing the transistor from being Deteriorate and reduce the volume.
  • FIG. 1 is a schematic structural view of a first embodiment of a shift register of the present invention
  • Figure 2 is a circuit diagram of a second embodiment of the shift register of the present invention.
  • Figure 3 is a timing diagram of a second embodiment of the shift register of the present invention.
  • Figure 4 is a circuit diagram of a third embodiment of the shift register of the present invention.
  • Figure 5 is a circuit diagram of a fourth embodiment of the shift register of the present invention.
  • FIG. 6 is a schematic diagram showing the circuit structure of the first embodiment of the level gate driving circuit of the present invention.
  • the present invention assumes a schematic structural diagram of a first embodiment of a register, the shift register comprising:
  • the downlink module 110 includes a first level signal input terminal 111 and a second level signal input terminal 112, and is connected to the first stage signal output end and the second level signal output end of the upper stage shift register; and the output module 120, The first signal input terminal 121, the second signal input terminal 122, the first level signal output terminal 124, the second level signal output terminal 125 and the scan signal output terminal 123; wherein, the first stage signal output terminal 124 and The second stage signal output end 125 is respectively connected to the first stage signal input end and the second stage signal input end of the upper stage and/or the lower stage shift register to provide a level transmission signal, the first signal input end 121 and the second signal.
  • the input terminal 122 is connected to the AC signal;
  • the first pull-down maintaining module 130 includes a third-level signal input terminal 131 and a third signal input terminal 132, respectively connected to the first-stage signal output end of the lower-stage shift register and the AC signal;
  • the second pull-down maintaining module 140 includes a fourth-level signal input terminal 141 and a fourth signal input terminal 142, respectively connected to the first-stage signal output terminal of the lower-stage shift register and the AC signal;
  • the first pull-down module 150 the package
  • the fifth signal input terminal 151 is connected to the low level signal;
  • the second pull-down module 160 includes a fifth level signal input terminal 161, and is connected to the first stage signal output end of the lower stage shift register;
  • the downlink module 110, the output module 120, the first pull-down maintaining module 130, and the second pull-down maintaining module 140 are connected to the first common point 170, and the first pull-down module 150 is connected to the first pull-down maintaining module 130 and the second.
  • the pull-down maintenance module 140 is connected to the first pull-down module 150 and the output module 120.
  • the downlink module 110 increases the potential of the first common point 170 to a high potential when receiving the high-level signal of the upper shift register through the first-stage signal input terminal 111 and the second-stage signal input terminal 112, and the output module 120 is The first signal input terminal 121 and the second signal input terminal 122 receive the low potential clock signal to output the low potential scan signal through the scan signal output terminal 123; after the downlink module 110 is turned off, the first common point 170 is still high, the output module The first signal input terminal 121 and the second signal input terminal 122 of the 120 receive the high potential clock signal to output the high potential scan signal through the scan signal output terminal 123; after the scan signal output terminal 123 outputs, the third stage signal input terminal 131, The fourth signal level transmission input terminal 141 and the sixth signal input terminal 161 input the high potential level transmission signal of the first stage signal output end of the lower stage shift register, and the third signal input terminal 132 and the fourth signal input terminal 142 alternately input the high potential.
  • the signal causes the first pull-down module 150 to be turned on with the first common point 170 to alternately pull down the first common point 170 and the scan signal output end 123 to a low potential, while the second Pull-down module 160 first common point 170 and the scanning signal output terminal 123 to the low potential.
  • the present embodiment controls the output of the scan signal of the lower shift register by the level transfer signal of the upper shift register, and alternately pulls down the potential of the scan signal output terminal to the low potential through the two pull-down sustain modules after the scan signal is output.
  • the second pull-down module 140 cooperates with the potential of the common pull-down scan signal output terminal to a low potential, thereby preventing leakage of some transistors in the circuit, ensuring that the scan signal output terminal stably outputs a low potential signal, and preventing deterioration of the transistor and reducing the volume.
  • a circuit diagram of a second embodiment of a shift register of the present invention the circuit includes a plurality of TFT thin film transistors and a plurality of signal input/output terminals;
  • the downlink module 210 includes a first transistor T1; the drain of the first transistor T1 is coupled to the second stage signal input terminal 212, the source is coupled to the first common point Q 270, and the gate is coupled to the first stage signal input terminal. 211.
  • the output module 220 includes a second transistor T2, a third transistor T3, and a fourth transistor T4.
  • the drain of the second transistor T2 is connected to the first signal input terminal 221, the source is connected to the scan signal output terminal 223, and the third transistor T3 is connected.
  • the drain is connected to the second signal input terminal 222, the source is connected to the first stage signal output terminal 224;
  • the drain of the fourth transistor T4 is connected to the second signal input terminal 222, and the source is connected to the second stage signal output terminal 225;
  • the gates of the two transistors T2, the third transistor T3 and the fourth transistor T4 are all connected to the first common point Q point 270; a capacitor C is connected between the gate and the source of the third transistor T3.
  • the first pull-down module 250 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9.
  • the first pull-down maintaining module 230 includes a tenth transistor T10 and an eleventh.
  • the transistor T11, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14, the second pull-down maintaining module 240 includes a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, and an eighteenth transistor T18 and the nineteenth transistor T19; the gates of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all connected to the first common point Q point 270, and the sources of the sixth transistor T6 and the seventh transistor T7 are connected to the fifth The signal input terminal 251; the gates of the eighth transistor T8 and the ninth transistor T9 are connected to the first stage signal input terminal 211, and the source is connected to the fifth signal input terminal 251.
  • the drains of the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12, and the gate of the twelfth transistor T12 are all connected to the third signal input terminal 232, and the gate of the tenth transistor T10 is connected to the third-level signal.
  • the input terminal 231 has a source connected to the source of the eleventh transistor T11 at a second common point P 280; a gate of the eleventh transistor T11 is connected to a source of the twelfth transistor T12; and a source of the twelfth transistor T12 Connecting the drain of the eighth transistor T8; the drain of the thirteenth transistor T13 is connected to the first common point Q 270, the gate is connected to the second common point P 280, and the source is connected to the fifth signal input 251;
  • the drain of the transistor T14 is connected to the scan signal output terminal 223, the gate is connected to the second common point P point 280, and the source is connected to the fifth signal input terminal 251.
  • the drains of the fifteenth transistor T15, the sixteenth transistor T16 and the seventeenth transistor T17, and the gate of the seventeenth transistor T17 are both connected to the fourth signal input terminal 242, and the gate of the fifteenth transistor T15 is connected to the fourth stage.
  • the signal input terminal 241 the source is connected to the source of the sixteenth transistor T16 at the third common point K point 290; the gate of the sixteenth transistor T16 is connected to the source of the seventeenth transistor T17; the seventeenth transistor T17
  • the source is connected to the drain of the ninth transistor T19; the drain of the eighteenth transistor T18 is connected to the first common point Q point 270, the gate is connected to the third common point K point 290, and the source is connected to the fifth signal input end 251;
  • the drain of the nineteen transistor T19 is connected to the scan signal output terminal 223, the gate is connected to the third common point K point 290, and the source is connected to the fifth signal input terminal 251.
  • the second pull-down module 260 includes a twentieth transistor T20, a twenty-first transistor T21, and a twenty-second transistor T22; and a gate of the twentieth transistor T20, the twenty-first transistor T21, and the twenty-second transistor T22.
  • the second stage signal input terminal 261 is connected to the fifth stage, and the source is connected to the fifth signal input end 251; the drain of the twentieth transistor T20 is connected to the scan signal output end 223, and the drain of the twenty first transistor T21 is connected to the first stage.
  • the signal output terminal 224 transmits the drain of the twenty-second transistor T22 to the first common point Q 270.
  • the first stage signal input terminal 211 and the second stage signal input terminal 212 are respectively connected to the first stage signal output end and the second stage signal output end of the upper stage shift register to respectively input the signal ST(n-1).
  • CST(n-1), the third stage signal input terminal 231, the fourth stage signal input terminal 241 and the fifth stage signal input terminal 261 are connected to the first stage signal output end of the lower stage shift register for input.
  • the signal ST(n+1), the first signal input terminal 221 inputs the AC signal CK(n), the first signal input terminal inputs the AC signal SCK(n), and the third signal input terminal 232 and the fourth signal input terminal alternately input high.
  • the fifth signal input terminal 251 inputs a low potential signal Vss
  • the first stage signal output terminal 224 and the second stage signal output terminal 225 are connected to the upper stage or lower stage shift register to provide a level transmission signal ST.
  • the scan signal output terminal 223 is for outputting the scan signal G(n).
  • FIG. 3 a timing diagram of a second embodiment of the shift register of the present invention, the circuit operates as follows:
  • Timing 301 ST(n-1) and CST(n-1) are simultaneously high, T1 is turned on, Q point 270 is charged to high potential, and T5, T6, T7, T8, and T9 are simultaneously turned on, since Vss is low, Pulling down P point 280 and K point 290 is low, T13, T14, T18, T19 are turned off at the same time, but T2, T3, T4 are open, CK(n) and SCK(n) are both low, so , ST (n), CST (n) and G (n) output low potential.
  • Timing 302 ST(n-1) and CST(n-1) are low at the same time, T1 is off, Q point 270 remains high, T2, T3, T4 are still open, but CK(n) and SCK are at this time. (n) both become high, ST(n), CST(n), and G(n) both output high potential.
  • Q point 270 rises to a higher level, at this time T5, T6, T7 , T8, T9 are still open, because Vss is low, pull P point 280 and K point 290 potential is low, T13, T14, T18, T19 are still off, ST (n), CST (n) and G ( n) smooth output;
  • CK(n) will be low, SCK(n) will still be high, ST(n) and CST(n) will output high potential, and G(n) will output low potential.
  • Timing 303 CK (n) and SCK (n) input low potential, while ST (n + 1) input high potential, at this time T10, T17, T20, T21, T22 open, pull P point 280 low while raising K Point 290 (if LC1 is high at this time, LC2 is low, then pull K point 290 low and raise P point 280), T18, T19 open, pull Q point 270 and G(n) potential through Vss respectively Then T5, T6, T7, T8, T9 are closed.
  • Timing 304 LC1 and LC2 alternately operate at a high voltage, alternately charging P or K, and T13, T14 or T18, T19 alternately open, maintaining the potential of Q point 270 and G(n) at a low potential.
  • CK(n) is an AC signal. If T2 is large, there will be a large parasitic capacitance. The change of CK(n) signal (from low to high) will couple high potential at Q point 270, causing T2 leakage, thus making G ( n) The low potential cannot be stably outputted, so the potential of Q point and G(n) is pulled down after G(n) output;
  • the amorphous silicon TFT is used to form a circuit, and the TFT deterioration problem is considered. Therefore, the first pull-down module 230 and the second pull-down module 240 alternately function to prevent the gates of T13, T14, T18, and T19 from being The frame will have a positive potential bias for most of the time, resulting in deterioration of T13, T14, T18, and T19.
  • a circuit diagram of a third embodiment of the shift register of the present invention is different from the circuit of the second embodiment of the present invention in that the gate of T10 is connected to the LC2 signal, and the gate of T15 is connected to the LC1 signal to respectively control T10. And the opening and closing of the T15.
  • a circuit diagram of a fourth embodiment of the shift register of the present invention is different from the circuit of the third embodiment of the present invention in that the drain of T1 is connected to a DC source to charge the Q point.
  • the gate driving circuit includes a plurality of shift registers as described above; wherein, the first stage of each shift register The signal output end and the second stage signal output end are connected to the respective stage signal input terminals of the upper shift register and the lower shift register and provide a level transmission signal.
  • the first stage signal input end of the first stage shift register of the level gate drive circuit and the second stage signal input end are connected to the STV signal;
  • the third stage signal input end of the last stage shift register is fourth
  • the STV signal is connected to the level signal input terminal and the fifth level signal input terminal.
  • the present invention also provides a display panel including the level pass gate drive circuit as described above.
  • the space of the circuit and the frame of the display panel can be reduced, and the potential of the TFT output can be reduced by alternately pulling down the potential of the output of the scan signal by the two pull-down sustaining modules. Deterioration, ensuring output quality and reducing costs.

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Abstract

一种移位寄存器、级传栅极驱动电路及显示面板，能够减小晶体管的大小，防止晶体管的恶化，增加电路输出能力。移位寄存器包括下传模块（110）、输出模块（120）、第一下拉维持模块（130）、第二下拉维持模块（140）、第一下拉模块（150）及第二下拉模块（160）；下传模块（110）用于接收上级移位寄存器的级传信号（ST(n-1)，CST(n-1)），输出模块（120）用于输出级传信号（ST(n)，CST(n)）及扫描信号（G(n)），第一下拉维持模块（130）、第二下拉维持模块（140）、第一下拉模块（150）及第二下拉模块（160）用于在输出模块（120）输出扫描信号（G(n)）后保持输出信号为低电位。

Description

移位寄存器、级传栅极驱动电路及显示面板
【技术领域】
本发明涉及液晶显示领域，特别是涉及一种移位寄存器、级传栅极驱动电路及显示面板。
【背景技术】
目前的液晶显示面板的水平扫描驱动主要是通过外接的集成电路来完成的，外接的集成电路通过控制各级水平扫描线的逐级充电和放电实现扫描。
而GOA（Gate Driver on Array）技术，是利用原有的液晶显示面板制程，将水平扫描驱动电路制作在显示区周围的基板上，代替原有的外接集成电路完成水平扫描线的驱动，可以使液晶显示面板的边框更窄。
但是现有的GOA电路中，扫描信号输出端输出时间过长，从而使扫描信号输出端的TFT体积增大，下拉模块仅对扫描信号输出端放电，导致部分TFT的恶化和扫描信号输出端输出能力的下降。
【发明内容】
本发明主要解决的技术问题是提供一种移位寄存器、级传栅极驱动电路及显示面板，能够够减小晶体管的大小，防止晶体管的恶化，增加电路输出能力。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种移位寄存器，该移位寄存器包括：下传模块、输出模块、第一下拉维持模块、第二下拉维持模块、第一下拉模块、第二下拉模块；下传模块、输出模块、第一下拉维持模块及第二下拉维持模块连接于第一公共点，第一下拉模块连接第一下拉维持模块及第二下拉维持模块，第二下拉模块连接于第一下拉模块及输出模块之间；第一公共点在下传模块接收一上级移位寄存器的高电位级传信号时变为高电位；第一下拉维持模块和第二下拉维持模块交替接收一下级移位寄存器输入的高电位信号使第一下拉模块与第一公共点导通以下拉并保持第一公共点至低电位，同时第二下拉模块根据第一下拉模块与第一公共点导通的状态下拉并保持输出模块输出的扫描信号至低电位。
其中，下传模块，包括第一级传信号输入端及第二级传信号输入端，连接上级移位寄存器的第一级传信号输出端和第二级传信号输出端；输出模块，包括第一信号输入端、第二信号输入端、第一级传信号输出端、第二级传信号输出端及扫描信号输出端；其中，输出模块的第一级传信号输出端及第二级传信号输出端分别连接上级和/或下级移位寄存器的第一级传信号输入端及第二级传信号输入端以提供级传信号，第一信号输入端及第二信号输入端接收交流信号；第一下拉维持模块，包括第三级传信号输入端及第三信号输入端，第三级传信号输入端连接下级移位寄存器第一级传信号输出端，第三信号输入端接收交流信号；第二下拉维持模块，包括第四级传信号输入端及第四信号输入端，第四级传信号输入端连接下级移位寄存器第一级传信号输出端，第四信号输入端接收交流信号；第一下拉模块，包括第五信号输入端，接收低电平信号；第二下拉模块，包括第五级传信号输入端，连接下级移位寄存器第一级传信号输出端；下传模块通过第一级传信号输入端及第二级传信号输入端接收上级移位寄存器的高电位级传信号时使第一公共点的电位上升至高电位，输出模块的第一信号输入端及第二信号输入端接收低电位时钟信号以通过扫描信号输出端输出低电位扫描信号；下传模块关闭后，第一公共点仍为高电位，输出模块的第一信号输入端及第二信号输入端接收高电位时钟信号以通过扫描信号输出端输出高电位扫描信号；扫描信号输出端输出后，第三级传信号输入端、第四信号级传输入端及第六信号输入端输入下级移位寄存器第一级传信号输出端的高电位级传信号，第三信号输入端及第四信号输入端交替输入高电位信号使第一下拉模块与第一公共点导通从而交替下拉第一公共点及扫描信号输出端至低电位，同时第二下拉模块下拉第一公共点及扫描信号输出端至低电位。
其中，下传模块包括第一晶体管；第一晶体管的漏极连接第二级传信号输入端，源极连接第一公共点，栅极连接第一级传信号输入端。
其中，第一晶体管的漏极连接直流源。
其中，输出模块包括第二晶体管、第三晶体管及第四晶体管；第二晶体管的漏极连接第一信号输入端，源极连接扫描信号输出端；第三晶体管的漏极连接第二信号输入端，源极连接第一级传信号输出端；第四晶体管的漏极连接第二信号输入端，源极连接第二级传信号输出端；第二晶体管、第三晶体管及第四晶体管的栅极均连接第一公共点；第三晶体管的栅极和源极之间连接一电容。
其中，第一下拉模块包括第五晶体管、第六晶体管、第七晶体管、第八晶体管及第九晶体管，第一下拉维持模块包括第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管及第十四晶体管，第二下拉维持模块包括第十五晶体管、第十六晶体管、第十七晶体管、第十八晶体管及第十九晶体管；第五晶体管、第六晶体管、第七晶体管的栅极均连接第一公共点，第六晶体管及第七晶体管的源极连接第五信号输入端；第八晶体管及第九晶体管的栅极连接第一级传信号输入端，源极连接第五信号输入端。第十晶体管、第十一晶体管及第十二晶体管的漏极和第十二晶体管的栅极均连接第三信号输入端，第十晶体管的栅极连接第三级传信号输入端，源极连接第十一晶体管的源极于第二公共点；第十一晶体管的栅极连接第十二晶体管的源极；第十二晶体管的源极连接第八晶体管的漏极；第十三晶体管的漏极连接第一公共点，栅极连接第二公共点，源极连接第五信号输入端；第十四晶体管的漏极连接扫描信号输出端，栅极连接第二公共点，源极连接第五信号输入端。第十五晶体管、第十六晶体管及第十七晶体管的漏极和第十七晶体管的栅极均连接第四信号输入端，第十五晶体管的栅极连接第四级传信号输入端，源极连接第十六晶体管的源极于第三公共点；第十六晶体管的栅极连接第十七晶体管的源极；第十七晶体管的源极连接第九晶体管的漏极；第十八晶体管的漏极连接第一公共点，栅极连接第三公共点，源极连接第五信号输入端；第十九晶体管的漏极连接扫描信号输出端，栅极连接第三公共点，源极连接第五信号输入端。
其中，第十晶体管的栅极连接第四信号输入端，第十五晶体管的栅极连接第三信号输入端。
其中，第二下拉模块包括第二十晶体管、第二十一晶体管及第二十二晶体管；第二十晶体管、第二十一晶体管及第二十二晶体管的栅极均连接第五级传信号输入端，源极均连接第五信号输入端；第二十晶体管的漏极连接扫描信号输出端，第二十一晶体管的漏极连接第一级传信号输出端，第二十二晶体管的漏极连接第一公共点。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种级传栅极驱动电路，级传栅极驱动电路包括多个如上的移位寄存器；其中，每个移位寄存器的第一级传信号输出端及第二级传信号输出端连接上级移位寄存器及下级移位寄存器的各个级传信号输入端并提供级传信号。
其中，级传栅极驱动电路的首级移位寄存器的第一级传信号输入端及第二级传信号输入端连接STV信号；末级移位寄存器的第三级传信号输入端、第四级传信号输入端及第五级传信号输入端连接STV信号。
其中，下传模块，包括第一级传信号输入端及第二级传信号输入端，连接上级移位寄存器的第一级传信号输出端和第二级传信号输出端；输出模块，包括第一信号输入端、第二信号输入端、第一级传信号输出端、第二级传信号输出端及扫描信号输出端；其中，输出模块的第一级传信号输出端及第二级传信号输出端分别连接上级和/或下级移位寄存器的第一级传信号输入端及第二级传信号输入端以提供级传信号，第一信号输入端及第二信号输入端接收交流信号；第一下拉维持模块，包括第三级传信号输入端及第三信号输入端，第三级传信号输入端连接下级移位寄存器第一级传信号输出端，第三信号输入端接收交流信号；第二下拉维持模块，包括第四级传信号输入端及第四信号输入端，第四级传信号输入端连接下级移位寄存器第一级传信号输出端，第四信号输入端接收交流信号；第一下拉模块，包括第五信号输入端，接收低电平信号；第二下拉模块，包括第五级传信号输入端，连接下级移位寄存器第一级传信号输出端；下传模块通过第一级传信号输入端及第二级传信号输入端接收上级移位寄存器的高电位级传信号时使第一公共点的电位上升至高电位，输出模块的第一信号输入端及第二信号输入端接收低电位时钟信号以通过扫描信号输出端输出低电位扫描信号；下传模块关闭后，第一公共点仍为高电位，输出模块的第一信号输入端及第二信号输入端接收高电位时钟信号以通过扫描信号输出端输出高电位扫描信号；扫描信号输出端输出后，第三级传信号输入端、第四信号级传输入端及第六信号输入端输入下级移位寄存器第一级传信号输出端的高电位级传信号，第三信号输入端及第四信号输入端交替输入高电位信号使第一下拉模块与第一公共点导通从而交替下拉第一公共点及扫描信号输出端至低电位，同时第二下拉模块下拉第一公共点及扫描信号输出端至低电位。
其中，下传模块包括第一晶体管；第一晶体管的漏极连接第二级传信号输入端，源极连接第一公共点，栅极连接第一级传信号输入端。
其中，第一晶体管的漏极连接直流源。
其中，输出模块包括第二晶体管、第三晶体管及第四晶体管；第二晶体管的漏极连接第一信号输入端，源极连接扫描信号输出端；第三晶体管的漏极连接第二信号输入端，源极连接第一级传信号输出端；第四晶体管的漏极连接第二信号输入端，源极连接第二级传信号输出端；第二晶体管、第三晶体管及第四晶体管的栅极均连接第一公共点；第三晶体管的栅极和源极之间连接一电容。
其中，第一下拉模块包括第五晶体管、第六晶体管、第七晶体管、第八晶体管及第九晶体管，第一下拉维持模块包括第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管及第十四晶体管，第二下拉维持模块包括第十五晶体管、第十六晶体管、第十七晶体管、第十八晶体管及第十九晶体管；第五晶体管、第六晶体管、第七晶体管的栅极均连接第一公共点，第六晶体管及第七晶体管的源极连接第五信号输入端；第八晶体管及第九晶体管的栅极连接第一级传信号输入端，源极连接第五信号输入端。第十晶体管、第十一晶体管及第十二晶体管的漏极和第十二晶体管的栅极均连接第三信号输入端，第十晶体管的栅极连接第三级传信号输入端，源极连接第十一晶体管的源极于第二公共点；第十一晶体管的栅极连接第十二晶体管的源极；第十二晶体管的源极连接第八晶体管的漏极；第十三晶体管的漏极连接第一公共点，栅极连接第二公共点，源极连接第五信号输入端；第十四晶体管的漏极连接扫描信号输出端，栅极连接第二公共点，源极连接第五信号输入端。第十五晶体管、第十六晶体管及第十七晶体管的漏极和第十七晶体管的栅极均连接第四信号输入端，第十五晶体管的栅极连接第四级传信号输入端，源极连接第十六晶体管的源极于第三公共点；第十六晶体管的栅极连接第十七晶体管的源极；第十七晶体管的源极连接第九晶体管的漏极；第十八晶体管的漏极连接第一公共点，栅极连接第三公共点，源极连接第五信号输入端；第十九晶体管的漏极连接扫描信号输出端，栅极连接第三公共点，源极连接第五信号输入端。
其中，第十晶体管的栅极连接第四信号输入端，第十五晶体管的栅极连接第三信号输入端。
其中，第二下拉模块包括第二十晶体管、第二十一晶体管及第二十二晶体管；第二十晶体管、第二十一晶体管及第二十二晶体管的栅极均连接第五级传信号输入端，源极均连接第五信号输入端；第二十晶体管的漏极连接扫描信号输出端，第二十一晶体管的漏极连接第一级传信号输出端，第二十二晶体管的漏极连接第一公共点。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种显示面板，显示面板包括如上的级传栅极驱动电路。
其中，级传栅极驱动电路的首级移位寄存器的第一级传信号输入端及第二级传信号输入端连接STV信号；末级移位寄存器的第三级传信号输入端、第四级传信号输入端及第五级传信号输入端连接STV信号。
本发明的有益效果是：区别于现有技术的情况，本发明通过上级移位寄存器的级传信号控制下级移位寄存器扫描信号的输出，在扫描信号输出后通过两个下拉维持模块交替下拉扫描信号输出端的电位至低电位，并通过第二下拉模块配合共同下拉扫描信号输出端的电位至低电位，这样防止电路中部分晶体管漏电，保证扫描信号输出端稳定输出低电位信号，并且防止了晶体管的恶化，减小体积。
【附图说明】
图1是本发明移位寄存器的第一实施方式的结构示意图；
图2是本发明移位寄存器的第二实施方式的电路图；
图3是本发明移位寄存器的第二实施方式的时序图；
图4是本发明移位寄存器的第三实施方式的电路图；
图5是本发明移位寄存器的第四实施方式的电路图；
图6是本发明级传栅极驱动电路的第一实施方式的电路结构示意图。
【具体实施方式】
参阅图1，本发明以为寄存器的第一实施方式的结构示意图，该移位寄存器包括：
下传模块110，包括第一级传信号输入端111及第二级传信号输入端112，连接上级移位寄存器的第一级传信号输出端和第二级传信号输出端；输出模块120，包括第一信号输入端121、第二信号输入端122、第一级传信号输出端124、第二级传信号输出端125及扫描信号输出端123；其中，第一级传信号输出端124及第二级传信号输出端125分别连接上级和/或下级移位寄存器的第一级传信号输入端及第二级传信号输入端以提供级传信号，第一信号输入端121及第二信号输入端122连接交流信号；第一下拉维持模块130，包括第三级传信号输入端131及第三信号输入端132，分别连接下级移位寄存器第一级传信号输出端及交流信号；第二下拉维持模块140，包括第四级传信号输入端141及第四信号输入端142，分别连接下级移位寄存器第一级传信号输出端及交流信号；第一下拉模块150，包括第五信号输入端151，连接低电平信号；第二下拉模块160，包括第五级传信号输入端161，连接下级移位寄存器第一级传信号输出端；
其中，下传模块110、输出模块120、第一下拉维持模块130及第二下拉维持模块140连接与第一公共点170，第一下拉模块150连接第一下拉维持模块130及第二下拉维持模块140，第二下拉模块160连接第一下拉模块150及输出模块120。
下传模块110通过第一级传信号输入端111及第二级传信号输入端112接收上级移位寄存器的高电位级传信号时使第一公共点170的电位上升至高电位，输出模块120的第一信号输入端121及第二信号输入端122接收低电位时钟信号以通过扫描信号输出端123输出低电位扫描信号；下传模块110关闭后，第一公共点170仍为高电位，输出模块120的第一信号输入端121及第二信号输入端122接收高电位时钟信号以通过扫描信号输出端123输出高电位扫描信号；扫描信号输出端123输出后，第三级传信号输入端131、第四信号级传输入端141及第六信号输入端161输入下级移位寄存器第一级传信号输出端的高电位级传信号，第三信号输入端132及第四信号输入端142交替输入高电位信号使第一下拉模块150与第一公共点170导通从而交替下拉第一公共点170及扫描信号输出端123至低电位，同时第二下拉模块160下拉第一公共点170及扫描信号输出端123至低电位。
区别于现有技术，本实施方式通过上级移位寄存器的级传信号控制下级移位寄存器扫描信号的输出，在扫描信号输出后通过两个下拉维持模块交替下拉扫描信号输出端的电位至低电位，并通过第二下拉模块140配合共同下拉扫描信号输出端的电位至低电位，这样防止电路中部分晶体管漏电，保证扫描信号输出端稳定输出低电位信号，并且防止了晶体管的恶化，减小体积。
参阅图2，本发明移位寄存器第二实施方式的电路图，该电路包括多个TFT薄膜晶体管和多个信号输入/输出端；
其中，下传模块210包括第一晶体管T1；第一晶体管T1的漏极连接第二级传信号输入端212，源极连接第一公共点Q点270，栅极连接第一级传信号输入端211。
其中，输出模块220包括第二晶体管T2、第三晶体管T3及第四晶体管T4；第二晶体管T2的漏极连接第一信号输入端221，源极连接扫描信号输出端223；第三晶体管T3的漏极连接第二信号输入端222，源极连接第一级传信号输出端224；第四晶体管T4的漏极连接第二信号输入端222，源极连接第二级传信号输出端225；第二晶体管T2、第三晶体管T3及第四晶体管T4的栅极均连接第一公共点Q点270；第三晶体管T3的栅极和源极之间连接一电容C。
其中，第一下拉模块250包括第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8及第九晶体管T9，第一下拉维持模块230包括第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13及第十四晶体管T14，第二下拉维持模块240包括第十五晶体管T15、第十六晶体管T16、第十七晶体管T17、第十八晶体管T18及第十九晶体管T19；第五晶体管T5、第六晶体管T6、第七晶体管T7的栅极均连接第一公共点Q点270，第六晶体管T6及第七晶体管T7的源极连接第五信号输入端251；第八晶体管T8及第九晶体管T9的栅极连接第一级传信号输入端211，源极连接第五信号输入端251。第十晶体管T10、第十一晶体管T11及第十二晶体管T12的漏极和第十二晶体管T12的栅极均连接第三信号输入端232，第十晶体管T10的栅极连接第三级传信号输入端231，源极连接第十一晶体管T11的源极于第二公共点P点280；第十一晶体管T11的栅极连接第十二晶体管T12的源极；第十二晶体管T12的源极连接第八晶体管T8的漏极；第十三晶体管T13的漏极连接第一公共点Q点270，栅极连接第二公共点P点280，源极连接第五信号输入端251；第十四晶体管T14的漏极连接扫描信号输出端223，栅极连接第二公共点P点280，源极连接第五信号输入端251。第十五晶体管T15、第十六晶体管T16及第十七晶体管T17的漏极和第十七晶体管T17的栅极均连接第四信号输入端242，第十五晶体管T15的栅极连接第四级传信号输入端241，源极连接第十六晶体管T16的源极于第三公共点K点290；第十六晶体管T16的栅极连接第十七晶体管T17的源极；第十七晶体管T17的源极连接第九晶体管T19的漏极；第十八晶体管T18的漏极连接第一公共点Q点270，栅极连接第三公共点K点290，源极连接第五信号输入端251；第十九晶体管T19的漏极连接扫描信号输出端223，栅极连接第三公共点K点290，源极连接第五信号输入端251。
其中，第二下拉模块260包括第二十晶体管T20、第二十一晶体管T21及第二十二晶体管T22；第二十晶体管T20、第二十一晶体管T21及第二十二晶体管T22的栅极均连接第五级传信号输入端261，源极均连接第五信号输入端251；第二十晶体管T20的漏极连接扫描信号输出端223，第二十一晶体管T21的漏极连接第一级传信号输出端224，第二十二晶体管T22的漏极连接第一公共点Q点270。
其中，第一级传信号输入端211及第二级传信号输入端212分别连接上级移位寄存器的第一级传信号输出端及第二级传信号输出端以分别输入信号ST(n-1)及CST(n-1)，第三级传信号输入端231、第四级传信号输入端241及第五级传信号输入端261连接下级移位寄存器的第一级传信号输出端以输入信号ST(n+1)，第一信号输入端221输入交流信号CK(n)，第一信号输入端输入交流信号SCK(n)，第三信号输入端232及第四信号输入端交替输入高/低电位信号LC1及LC2，第五信号输入端251输入低电位信号Vss，第一级传信号输出端224及第二级传信号输出端225连接上级或下级移位寄存器以提供级传信号ST(n) 及CST(n)，扫描信号输出端223用于输出扫描信号G(n)。
同时参阅图3，本发明移位寄存器的第二实施方式的时序图，电路运作过程如下：
时序301：ST(n-1)及CST(n-1)同时为高电位，T1打开，Q点270充电为高电位，T5、T6、T7、T8、T9同时打开，由于Vss为低电位，拉低P点280及K点290的电位为低电位，T13、T14、T18、T19同时关闭，但T2、T3、T4打开，此时CK(n)和SCK(n)均为低电位，因此，ST(n)、CST(n)及G(n)均输出低电位。
时序302：ST(n-1)及CST(n-1)同时为低电位，T1关闭，Q点270仍保持为高电位，T2、T3、T4仍打开，但此时CK(n)和SCK(n)均变为高电位，ST(n)、CST(n)及G(n)均输出高电位，在电容C的耦合下，Q点270抬升到更高，此时T5、T6、T7、T8、T9仍打开，由于Vss为低电位，拉低P点280及K点290的电位为低电位，T13、T14、T18、T19仍关闭，ST(n)、CST(n)及G(n)顺利输出；
在时序302的后期，CK(n)将为低电位，SCK(n)仍为高电位，ST(n)及CST(n)顺利输出高电位，G(n)顺利输出低电位。
时序303：CK(n)和SCK(n)输入低电位，同时ST(n+1)输入高电位，此时T10、T17、T20、T21、T22打开，拉低P点280的同时抬高K点290（如果此时LC1为高电位，LC2为低电位则拉低K点290的同时抬高P点280），T18、T19打开，分别通过Vss拉低Q点270及G(n)的电位，随即T5、T6、T7、T8、T9关闭。
时序304：LC1及LC2交替为高电压，交替对P点或K点充电，T13、T14或T18、T19交替打开，维持Q点270及G(n)的电位为低电位。
CK(n)为交流信号，T2较大，会存在较大的寄生电容，CK(n)信号（从低到高）的变化会在Q点270耦合高电位，导致T2漏电，从而使G(n)无法稳定输出低电位，因此在G(n)输出后一直下拉Q点和G(n)的电位；
另外，本实施方式是采用非晶硅TFT组成电路，要考虑TFT恶化问题，所以第一下拉模块230和第二下拉模块240交替作用，目的是防止T13、T14、T18、T19栅极在一帧大部分的时间会有个正电位的偏压，导致T13、T14、T18、T19的恶化。
参阅图4，本发明移位寄存器第三实施方式的电路图，该电路与本发明第二实施方式的电路区别在于，T10的栅极连接LC2信号，T15的栅极连接LC1信号，以分别控制T10及T15的打开和关闭。
参阅图5，本发明移位寄存器第四实施方式的电路图，该电路与本发明第三实施方式的电路区别在于，T1的漏极连接直流源以对Q点充电。
参阅图6，本发明级传栅极驱动电路的第一实施方式的电路结构示意图，该栅极驱动电路包括多个如上所述的移位寄存器；其中，每个移位寄存器的第一级传信号输出端及第二级传信号输出端连接上级移位寄存器及下级移位寄存器的各个级传信号输入端并提供级传信号。
其中，级传栅极驱动电路的首级移位寄存器的第一级传信号输入端及第二级传信号输入端连接STV信号；末级移位寄存器的第三级传信号输入端、第四级传信号输入端及第五级传信号输入端连接STV信号。
本发明还提供一种显示面板，该显示面板包括如上所述的级传栅极驱动电路。
通过在显示面板中加入如上所述的级传栅极驱动电路，能够减小电路的空间及显示面板的边框，并且通过两个下拉维持模块交替下拉扫描信号输出端的电位，能够减小TFT晶体管的恶化，保证输出质量，减小成本。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (17)

  1. 一种移位寄存器，其中，包括：下传模块、输出模块、第一下拉维持模块、第二下拉维持模块、第一下拉模块、第二下拉模块；所述下传模块、输出模块、第一下拉维持模块及第二下拉维持模块连接于第一公共点，所述第一下拉模块连接所述第一下拉维持模块及第二下拉维持模块，所述第二下拉模块连接于所述第一下拉模块及所述输出模块之间；
    所述第一公共点在所述下传模块接收一上级移位寄存器的高电位级传信号时变为高电位；所述第一下拉维持模块和第二下拉维持模块交替接收一下级移位寄存器输入的高电位信号使所述第一下拉模块与所述第一公共点导通以下拉并保持所述第一公共点至低电位，同时所述第二下拉模块根据所述第一下拉模块与所述第一公共点导通的状态下拉并保持所述输出模块输出的扫描信号至低电位。
  2. 根据权利要求1所述的移位寄存器，其中，
    所述下传模块，包括第一级传信号输入端及第二级传信号输入端，连接上级移位寄存器的第一级传信号输出端和第二级传信号输出端；
    所述输出模块，包括第一信号输入端、第二信号输入端、第一级传信号输出端、第二级传信号输出端及扫描信号输出端；
    其中，所述输出模块的第一级传信号输出端及第二级传信号输出端分别连接上级和/或下级移位寄存器的第一级传信号输入端及第二级传信号输入端以提供级传信号，所述第一信号输入端及第二信号输入端接收交流信号；
    所述第一下拉维持模块，包括第三级传信号输入端及第三信号输入端，所述第三级传信号输入端连接下级移位寄存器第一级传信号输出端，所述第三信号输入端接收交流信号；
    所述第二下拉维持模块，包括第四级传信号输入端及第四信号输入端，所述第四级传信号输入端连接下级移位寄存器第一级传信号输出端，所述第四信号输入端接收交流信号；
    所述第一下拉模块，包括第五信号输入端，接收低电平信号；
    所述第二下拉模块，包括第五级传信号输入端，连接所述下级移位寄存器第一级传信号输出端；
    所述下传模块通过所述第一级传信号输入端及所述第二级传信号输入端接收所述上级移位寄存器的高电位级传信号时使所述第一公共点的电位上升至高电位，所述输出模块的第一信号输入端及第二信号输入端接收低电位时钟信号以通过所述扫描信号输出端输出低电位扫描信号；
    所述下传模块关闭后，所述第一公共点仍为高电位，所述输出模块的第一信号输入端及第二信号输入端接收高电位时钟信号以通过所述扫描信号输出端输出高电位扫描信号；
    所述扫描信号输出端输出后，所述第三级传信号输入端、第四信号级传输入端及第六信号输入端输入下级移位寄存器第一级传信号输出端的高电位级传信号，所述第三信号输入端及第四信号输入端交替输入高电位信号使所述第一下拉模块与所述第一公共点导通从而交替下拉所述第一公共点及扫描信号输出端至低电位，同时所述第二下拉模块下拉所述第一公共点及扫描信号输出端至低电位。
  3. 根据权利要求2所述的移位寄存器，其中，所述下传模块包括第一晶体管；
    所述第一晶体管的漏极连接所述第二级传信号输入端或直流源，源极连接所述第一公共点，栅极连接所述第一级传信号输入端。
  4. 根据权利要求2所述的移位寄存器，其中，所述输出模块包括第二晶体管、第三晶体管及第四晶体管；
    所述第二晶体管的漏极连接所述第一信号输入端，源极连接所述扫描信号输出端；
    所述第三晶体管的漏极连接所述第二信号输入端，源极连接所述第一级传信号输出端；
    所述第四晶体管的漏极连接所述第二信号输入端，源极连接所述第二级传信号输出端；
    所述第二晶体管、第三晶体管及第四晶体管的栅极均连接所述第一公共点；
    所述第三晶体管的栅极和源极之间连接一电容。
  5. 根据权利要求2所述的移位寄存器，其中，所述第一下拉模块包括第五晶体管、第六晶体管、第七晶体管、第八晶体管及第九晶体管，所述第一下拉维持模块包括第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管及第十四晶体管，所述第二下拉维持模块包括第十五晶体管、第十六晶体管、第十七晶体管、第十八晶体管及第十九晶体管；
    所述第五晶体管、第六晶体管、第七晶体管的栅极均连接所述第一公共点，所述第六晶体管及第七晶体管的源极连接所述第五信号输入端；
    所述第八晶体管及第九晶体管的栅极连接所述第一级传信号输入端，源极连接所述第五信号输入端。
    所述第十晶体管、第十一晶体管及第十二晶体管的漏极和第十二晶体管的栅极均连接第三信号输入端，所述第十晶体管的栅极连接所述第三级传信号输入端，源极连接所述第十一晶体管的源极于第二公共点；
    所述第十一晶体管的栅极连接所述第十二晶体管的源极；
    所述第十二晶体管的源极连接所述第八晶体管的漏极；
    所述第十三晶体管的漏极连接所述第一公共点，栅极连接所述第二公共点，源极连接所述第五信号输入端；
    所述第十四晶体管的漏极连接所述扫描信号输出端，栅极连接所述第二公共点，源极连接所述第五信号输入端。
    所述第十五晶体管、第十六晶体管及第十七晶体管的漏极和第十七晶体管的栅极均连接第四信号输入端，所述第十五晶体管的栅极连接所述第四级传信号输入端，源极连接所述第十六晶体管的源极于第三公共点；
    所述第十六晶体管的栅极连接所述第十七晶体管的源极；
    所述第十七晶体管的源极连接所述第九晶体管的漏极；
    所述第十八晶体管的漏极连接所述第一公共点，栅极连接所述第三公共点，源极连接所述第五信号输入端；
    所述第十九晶体管的漏极连接所述扫描信号输出端，栅极连接所述第三公共点，源极连接所述第五信号输入端。
  6. 根据权利要求5所述的移位寄存器，其中，所述第十晶体管的栅极连接所述第四信号输入端，所述第十五晶体管的栅极连接所述第三信号输入端。
  7. 根据权利要求2所述的移位寄存器，其中，所述第二下拉模块包括第二十晶体管、第二十一晶体管及第二十二晶体管；
    所述第二十晶体管、第二十一晶体管及第二十二晶体管的栅极均连接第五级传信号输入端，源极均连接所述第五信号输入端；
    所述第二十晶体管的漏极连接所述扫描信号输出端，所述第二十一晶体管的漏极连接所述第一级传信号输出端，所述第二十二晶体管的漏极连接所述第一公共点。
  8. 一种级传栅极驱动电路，其中，所述级传栅极驱动电路包括多个如权利要求1所述的移位寄存器；
    其中，所述每个移位寄存器的第一级传信号输出端及第二级传信号输出端连接上级移位寄存器及下级移位寄存器的各个级传信号输入端并提供级传信号。
  9. 根据权利要求8所述的级传栅极驱动电路，其中，所述级传栅极驱动电路的首级移位寄存器的第一级传信号输入端及第二级传信号输入端连接STV信号；
    末级移位寄存器的第三级传信号输入端、第四级传信号输入端及第五级传信号输入端连接所述STV信号。
  10. 根据权利要求8所述的栅极驱动电路，其中，
    所述下传模块，包括第一级传信号输入端及第二级传信号输入端，连接上级移位寄存器的第一级传信号输出端和第二级传信号输出端；
    所述输出模块，包括第一信号输入端、第二信号输入端、第一级传信号输出端、第二级传信号输出端及扫描信号输出端；
    其中，所述输出模块的第一级传信号输出端及第二级传信号输出端分别连接上级和/或下级移位寄存器的第一级传信号输入端及第二级传信号输入端以提供级传信号，所述第一信号输入端及第二信号输入端接收交流信号；
    所述第一下拉维持模块，包括第三级传信号输入端及第三信号输入端，所述第三级传信号输入端连接下级移位寄存器第一级传信号输出端，所述第三信号输入端接收交流信号；
    所述第二下拉维持模块，包括第四级传信号输入端及第四信号输入端，所述第四级传信号输入端连接下级移位寄存器第一级传信号输出端，所述第四信号输入端接收交流信号；
    所述第一下拉模块，包括第五信号输入端，接收低电平信号；
    所述第二下拉模块，包括第五级传信号输入端，连接所述下级移位寄存器第一级传信号输出端；
    所述下传模块通过所述第一级传信号输入端及所述第二级传信号输入端接收所述上级移位寄存器的高电位级传信号时使所述第一公共点的电位上升至高电位，所述输出模块的第一信号输入端及第二信号输入端接收低电位时钟信号以通过所述扫描信号输出端输出低电位扫描信号；
    所述下传模块关闭后，所述第一公共点仍为高电位，所述输出模块的第一信号输入端及第二信号输入端接收高电位时钟信号以通过所述扫描信号输出端输出高电位扫描信号；
    所述扫描信号输出端输出后，所述第三级传信号输入端、第四信号级传输入端及第六信号输入端输入下级移位寄存器第一级传信号输出端的高电位级传信号，所述第三信号输入端及第四信号输入端交替输入高电位信号使所述第一下拉模块与所述第一公共点导通从而交替下拉所述第一公共点及扫描信号输出端至低电位，同时所述第二下拉模块下拉所述第一公共点及扫描信号输出端至低电位。
  11. 根据权利要求10所述的栅极驱动电路，其中，所述下传模块包括第一晶体管；
    所述第一晶体管的漏极连接所述第二级传信号输入端或直流源，源极连接所述第一公共点，栅极连接所述第一级传信号输入端。
  12. 根据权利要求10所述的栅极驱动电路，其中，所述输出模块包括第二晶体管、第三晶体管及第四晶体管；
    所述第二晶体管的漏极连接所述第一信号输入端，源极连接所述扫描信号输出端；
    所述第三晶体管的漏极连接所述第二信号输入端，源极连接所述第一级传信号输出端；
    所述第四晶体管的漏极连接所述第二信号输入端，源极连接所述第二级传信号输出端；
    所述第二晶体管、第三晶体管及第四晶体管的栅极均连接所述第一公共点；
    所述第三晶体管的栅极和源极之间连接一电容。
  13. 根据权利要求10所述的栅极驱动电路，其中，所述第一下拉模块包括第五晶体管、第六晶体管、第七晶体管、第八晶体管及第九晶体管，所述第一下拉维持模块包括第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管及第十四晶体管，所述第二下拉维持模块包括第十五晶体管、第十六晶体管、第十七晶体管、第十八晶体管及第十九晶体管；
    所述第五晶体管、第六晶体管、第七晶体管的栅极均连接所述第一公共点，所述第六晶体管及第七晶体管的源极连接所述第五信号输入端；
    所述第八晶体管及第九晶体管的栅极连接所述第一级传信号输入端，源极连接所述第五信号输入端。
    所述第十晶体管、第十一晶体管及第十二晶体管的漏极和第十二晶体管的栅极均连接第三信号输入端，所述第十晶体管的栅极连接所述第三级传信号输入端，源极连接所述第十一晶体管的源极于第二公共点；
    所述第十一晶体管的栅极连接所述第十二晶体管的源极；
    所述第十二晶体管的源极连接所述第八晶体管的漏极；
    所述第十三晶体管的漏极连接所述第一公共点，栅极连接所述第二公共点，源极连接所述第五信号输入端；
    所述第十四晶体管的漏极连接所述扫描信号输出端，栅极连接所述第二公共点，源极连接所述第五信号输入端。
    所述第十五晶体管、第十六晶体管及第十七晶体管的漏极和第十七晶体管的栅极均连接第四信号输入端，所述第十五晶体管的栅极连接所述第四级传信号输入端，源极连接所述第十六晶体管的源极于第三公共点；
    所述第十六晶体管的栅极连接所述第十七晶体管的源极；
    所述第十七晶体管的源极连接所述第九晶体管的漏极；
    所述第十八晶体管的漏极连接所述第一公共点，栅极连接所述第三公共点，源极连接所述第五信号输入端；
    所述第十九晶体管的漏极连接所述扫描信号输出端，栅极连接所述第三公共点，源极连接所述第五信号输入端。
  14. 根据权利要求13所述的栅极驱动电路，其中，所述第十晶体管的栅极连接所述第四信号输入端，所述第十五晶体管的栅极连接所述第三信号输入端。
  15. 根据权利要求10所述的栅极驱动电路，其中，所述第二下拉模块包括第二十晶体管、第二十一晶体管及第二十二晶体管；
    所述第二十晶体管、第二十一晶体管及第二十二晶体管的栅极均连接第五级传信号输入端，源极均连接所述第五信号输入端；
    所述第二十晶体管的漏极连接所述扫描信号输出端，所述第二十一晶体管的漏极连接所述第一级传信号输出端，所述第二十二晶体管的漏极连接所述第一公共点。
  16. 一种显示面板，其中，所述显示面板包括如权利要求8所述的级传栅极驱动电路。
  17. 根据权利要求16所述的显示面板，其中，所述级传栅极驱动电路的首级移位寄存器的第一级传信号输入端及第二级传信号输入端连接STV信号；
    末级移位寄存器的第三级传信号输入端、第四级传信号输入端及第五级传信号输入端连接所述STV信号。
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