WO2017107255A1 - 液晶显示设备及goa电路 - Google Patents

液晶显示设备及goa电路 Download PDF

Info

Publication number
WO2017107255A1
WO2017107255A1 PCT/CN2016/070600 CN2016070600W WO2017107255A1 WO 2017107255 A1 WO2017107255 A1 WO 2017107255A1 CN 2016070600 W CN2016070600 W CN 2016070600W WO 2017107255 A1 WO2017107255 A1 WO 2017107255A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
circuit
goa
pull
liquid crystal
Prior art date
Application number
PCT/CN2016/070600
Other languages
English (en)
French (fr)
Inventor
王笑笑
杜鹏
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/907,825 priority Critical patent/US9972261B2/en
Publication of WO2017107255A1 publication Critical patent/WO2017107255A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to an array substrate row driver for a liquid crystal display device (Gate Driver On Array, GOA) circuit.
  • GOA Gate Driver On Array
  • Tri-gate It is a commonly used method to reduce costs. Its structure is to rotate all pixels by 90 degrees, the number of gate lines is increased by three times, and the data line (data) The number of lines is reduced to 1/3 of the original. Due to the high cost of the data chip, the use of the data chip is reduced by the above method, thereby achieving the purpose of reducing the cost.
  • Chip-on film on the side of the data chip (COF, chip on The number of film) is reduced, the fanout area of the corresponding data chip is longer, the RC delay of the fan-out area becomes severe, and the data signals on both sides of the panel are due to RC.
  • the delay is the largest and the waveform distortion is the most serious, and the two sides are not fully charged, causing color shift problems on both sides of the panel.
  • FIG. 1 is a schematic view showing the structure of a display area of a liquid crystal display device 10 of the prior art.
  • Fig. 2a is a first schematic view showing the actual display of the display area according to Fig. 1.
  • Fig. 2b is a second schematic view showing the actual display of the display area according to Fig. 1.
  • the display area includes a plurality of rows of pixels arranged in the order of red, green, and blue. For example, when a solid color is displayed and the gray level is 255 (hereinafter, L255 is used as an abbreviation), in FIG. 2a, both the red pixel row and the green pixel row need to be turned on to the brightness of L255, and then the red pixel is turned on first.
  • L255 is used as an abbreviation
  • the present invention provides a GOA circuit for a liquid crystal display device, the liquid crystal display device comprising a plurality of scan lines, characterized in that the GOA circuit comprises a plurality of GOA units.
  • the plurality of GOA units are mutually cascaded into a multi-level GOA unit, and the n-th stage GOA unit includes a clock circuit, a pull-down circuit, a bootstrap capacitor circuit, a pull-up circuit, and a pull-down sustain circuit.
  • the clock circuit is configured to receive an mth-level clock signal of the multi-level clock signal, an n-th scan line for connecting the nth-stage enable signal line and the plurality of scan lines.
  • the pull-down circuit is configured to connect a gate signal point, an nth-th scan line for connecting the n-th scan line, the plurality of scan lines, an n+2th start signal line, and a fixed voltage source.
  • the bootstrap capacitor circuit And for connecting the gate signal point and the fixed voltage source.
  • the pull-up circuit is configured to connect the gate signal point and the n-2th scan line and the n-2th start signal line connecting the plurality of scan lines.
  • the pull-down maintaining circuit is configured to connect the gate signal point, the fixed voltage source, and the nth-th scan line.
  • the m and the n are positive integers.
  • the clock circuit includes a first transistor and a second transistor.
  • the control terminal of the first transistor is connected to the gate signal point, the input end of the first transistor receives the mth-level clock signal, and the output end of the first transistor is connected to the n-th scan line.
  • a control terminal of the second transistor is connected to the gate signal point, an input end of the second transistor is connected to the input end of the first transistor, and an output end of the second transistor is connected to the nth stage Start the signal line.
  • the duty ratio of each of the m clock signals is the same.
  • the pull down circuit includes a third transistor and a fourth transistor.
  • a control terminal of the third transistor is connected to the n+2th scan line and the n+2th enable signal line, and an input end of the third transistor is connected to the fixed voltage source, the third transistor The output is connected to the nth scan line.
  • a control terminal of the fourth transistor is connected to the n+2th scan line and the n+2th enable signal line, and an input end of the fourth transistor receives the fixed voltage source, the fourth transistor The output terminal is connected to the gate signal point
  • the bootstrap capacitor circuit includes a first capacitor. Both ends of the first capacitor are connected to the gate signal point and the nth level data line.
  • the pull up circuit comprises a fifth transistor.
  • a control end of the fifth transistor is connected to the n-2th scan line and the n-2th enable signal line, and an input end of the fifth transistor is connected to the control end of the fifth transistor, An output of the fifth transistor is coupled to the gate signal point.
  • the pull-down sustain circuit includes a first pull-down sustain circuit and a second pull-down sustain circuit.
  • the first pull-down sustain circuit includes a sixth transistor, a seventh transistor, and an eighth transistor.
  • the input end of the sixth transistor is connected to the fixed voltage, and the output end of the sixth transistor is connected to the gate signal point.
  • the control terminal of the seventh transistor receives the first low frequency signal, and the output terminal of the seventh transistor is coupled to the control terminal of the seventh transistor.
  • the control terminal of the eighth transistor is coupled to the gate signal point, and the input of the eighth transistor is coupled to the fixed voltage source.
  • the second pull-down maintaining circuit includes a ninth transistor, a tenth transistor, and an eleventh transistor.
  • An input end of the ninth transistor is connected to the fixed voltage, and an output end of the ninth transistor is connected to the gate signal point.
  • the control terminal of the tenth transistor receives the second low frequency signal, and the output end of the tenth transistor is coupled to the control terminal of the tenth transistor.
  • the control terminal of the eleventh transistor is connected to the gate signal point, and the input of the eleventh transistor is connected to the fixed voltage source.
  • the first low frequency signal and the second low frequency signal are inverted.
  • the first low frequency signal and the second low frequency signal are switched once every 100 frames.
  • a liquid crystal display device such as the GOA circuit is included.
  • the invention replaces the conventional gate chip with the GOA circuit, improves the Tri-gate color shift problem by designing the driving mode of the GOA circuit, and simultaneously replaces the gate chip with the GOA circuit, thereby further reducing the production cost.
  • FIG. 1 is a schematic view showing the structure of a display area of a liquid crystal display device of the prior art
  • Figure 2a is a first schematic view showing the actual display of the display area according to Figure 1;
  • Figure 2b is a second schematic view showing the actual display of the display area according to Figure 1;
  • FIG. 3 is a schematic view showing the structure of a display area of a liquid crystal display device of the present invention.
  • FIG. 4 is a schematic view showing a GOA unit of a liquid crystal display device of the present invention.
  • FIG. 5 is a schematic diagram showing the actual display of the GOA circuit of FIG. 4 in the display area of FIG.
  • FIG. 3 is a schematic view showing the structure of a display area of the liquid crystal display device 20 of the present invention.
  • the liquid crystal display device 20 includes a plurality of data lines (D1-D6), a plurality of scanning lines (G1-G6), and a GOA circuit 30.
  • the display area includes a plurality of rows of pixels arranged in the order of red, green, and blue.
  • the liquid crystal display device provides a scan signal to the plurality of scan lines (G1-G6) by the GOA circuit 30.
  • the GOA circuit 30 includes a plurality of GOA units 40 that are cascaded with each other.
  • the nth stage GOA unit 40 includes a clock circuit 100, a pull-down circuit 200, a bootstrap capacitor circuit 300, a pull-up circuit 400, and a pull-down sustain circuit 500.
  • the clock circuit 100 is configured to receive the mth-level clock signal CKm of the multi-level clock signal and to connect the nth-stage enable signal line ST(n) and the n-th scan line G(n).
  • the pull-down circuit 200 is configured to connect the gate signal point Q(n), the nth scan line G(n), the n+2th scan line G(n+2), and the n+2 stage start Signal line ST(n+2) and fixed voltage source Vss.
  • the bootstrap capacitor circuit 300 is configured to connect the gate signal point Q(n) and the fixed voltage source Vss.
  • the pull-up circuit 400 is configured to connect the gate signal point Q(n) and the n-2th scan line G(n-2) and the n-2th stage enable signal connecting the plurality of scan lines Line ST (n-2).
  • the pull-down maintaining circuit 500 is configured to connect the gate signal point Q(n), the fixed voltage source Vss, and the nth-th scan line G(n).
  • the m and the n are positive integers. In general, m is less than or equal to n.
  • the clock circuit 100 includes a first transistor T1 and a second transistor T2.
  • the control terminal of the first transistor T1 is connected to the gate signal point Q(n), the input terminal of the first transistor T1 receives the m-th clock signal CKm, and the output of the first transistor T1 is connected.
  • the control terminal of the second transistor T2 is connected to the gate signal point Q(n), the input terminal of the second transistor T2 is connected to the input end of the first transistor T1, and the second transistor T2 is The output terminal is connected to the nth stage start signal line ST(n).
  • the pull-down circuit 200 includes a third transistor T3 and a fourth transistor T4.
  • a control terminal of the third transistor T3 is connected to the n+2th scanning line G(n+2) and the n+2th startup signal line ST(n+2), and the third transistor T3
  • the input terminal is connected to the fixed voltage source Vss, and the output terminal of the third transistor T3 is connected to the nth-th scan line G(n).
  • the control terminal of the fourth transistor T4 is connected to the n+2th scanning line G(n+2) and the n+2th starting signal line ST(n+2), and the fourth transistor T4
  • the input terminal receives the fixed voltage source Vss, and the output of the fourth transistor T4 is connected to the gate signal point Q(n).
  • the bootstrap capacitor circuit 300 includes a first capacitor C1. Both ends of the first capacitor C1 are connected to the gate signal point Q(n) and the nth-th scan line G(n).
  • the pull-up circuit 400 includes a fifth transistor T5.
  • a control terminal of the fifth transistor T5 is connected to the n-2th scanning line G(n-2) and the n-2th starting signal line ST(n-2), the fifth transistor T5
  • the input terminal is connected to the control terminal of the fifth transistor T5, and the output terminal of the fifth transistor T5 is connected to the gate signal point Q(n).
  • the pull-down maintaining circuit 500 includes a first pull-down maintaining circuit 510 and a second pull-down maintaining circuit 520.
  • the first pull-down maintaining circuit 510 includes a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.
  • the input terminal of the sixth transistor T6 is connected to the fixed voltage Vss, and the output terminal of the sixth transistor T6 is connected to the gate signal point Q(n).
  • the control terminal of the seventh transistor T7 receives the first low frequency signal LC1, and the output terminal of the seventh transistor T7 is connected to the control terminal of the seventh transistor T7.
  • the control terminal of the eighth transistor T8 is connected to the gate signal point Q(n), and the input terminal of the eighth transistor T8 is connected to the fixed voltage source Vss.
  • the second pull-down maintaining circuit 520 includes a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11.
  • An input end of the ninth transistor T9 is connected to the fixed voltage Vss, and an output end of the ninth transistor T9 is connected to the gate signal point Q(n).
  • the control terminal of the tenth transistor T10 receives the second low frequency signal LC2, and the output terminal of the tenth transistor T10 is connected to the control terminal of the tenth transistor T10.
  • the control terminal of the eleventh transistor T11 is connected to the gate signal point Q(n), and the input terminal of the eleventh transistor T11 is connected to the fixed voltage source Vss.
  • the first low frequency signal LC1 and the second low frequency signal LC2 are two inverted low frequency DC signals, which alternately operate to ensure the gate signal point Q(n) point and the nth stage scan line.
  • the low potential of G(n) is stable.
  • the output of the scan line G(n-2) of the n-2th stage is connected to the n-2th stage enable signal ST(n-2) signal for pulling up the potential of the gate signal point Q(n).
  • the (n+2)th scanning line G(n+2) is used to assist in pulling down the nth scanning line G(n) and the gate signal point Q(n) ).
  • FIG. 5 is a schematic diagram showing the actual display of the GOA unit 40 of FIG. 4 in the display area of FIG.
  • the duty portions of the plurality of clock signals are equal and do not overlap.
  • m is 4, that is, there are a total of four clock signals (CK1-CK4), and the duty of the four clock signals (CK1-CK4) does not overlap in each cycle.
  • n is 12, that is, there are a total of 12 pixel rows.
  • the duty ratio of the clock signals CK1-CK4 is set to 25%.
  • the n-2th GOA unit When scanning the n-2th pixel row, the n-2th GOA unit passes the (n-2)th stage start signal line ST(n-2).
  • the output, output n-2th enable signal line ST(n-2) is connected to the nth stage GOA unit for pulling up the gate signal point Q(n) of the nth stage GOA unit, waiting for the mth stage clock
  • the nth stage GOA unit starts outputting the gate waveform
  • the (n+2)th GOA unit starts outputting, and the (n+2)th stage scan line G (n+2) of the (n+2)th stage GOA unit
  • the (n+2)th stage start signal line ST(n+2) pulls down the potential of the gate signal point Q(n) and the output (n)th scan line G(n).
  • the actual operation method is as follows:
  • the first stage GOA unit is turned on, and the potential of the gate signal point of the third stage GOA unit is pulled high.
  • the output of the first stage GOA unit is pulled to a low level, that is, the first The first scanning line G(1) is turned off, and the third-level scanning line G(3) is turned on, and the gate signal point of the fifth-level scanning line G(5) is pulled up, to be the fifth The level scan line G(5) is turned on, and the output of the third stage scan line G(3) is pulled to the low level by the fifth level scan line G(5), and the circuit is sequentially transmitted downward, that is,
  • the first, fifth, and ninth GOA units 40 are paired with the first-stage clock signal CK1; the second, sixth, and tenth-level GOA units 40 are paired with the second-level clock signal CK2; and the third, seventh, and eleventh stages
  • the GOA unit 40 is associated with the third stage clock signal CK3; the fourth, eighth, and 12th stage GOA units 40 are
  • the first low frequency signal LC1 and the second low frequency signal LC2 are switched once every 100 frames.
  • the pixel row G1 is one pixel
  • the third pixel row G3 is simultaneously scanned
  • the fifth pixel row G5 is scanned
  • the third pixel row is simultaneously turned off.
  • the L255 yellow picture is taken as an example, and the vertical direction pixel arrangement is RGB repeated arrangement. It can be seen from the output signal of the data line that the number of green pixels G that are insufficiently charged in the vertical direction is reduced to half of the prior art (refer to FIG. 2b), and the color shift can be effectively improved.

Abstract

一种用于液晶显示设备（20）的数组基板行扫描驱动(Gate Driver On Array；GOA)电路（30），所述液晶显示设备（20）包括多条扫描线（G(1)-G(6)），所述GOA电路（30）包含多个GOA单元（40）。所述多个GOA单元（40）相互级联为多级GOA单元（40），所述第n级GOA单元（40）包括时钟电路（100）、下拉电路（200）、自举电容电路（300）、上拉电路（400）及下拉维持电路（500）。用以改善Tri-gate的色偏问题并降低生产成本。

Description

液晶显示设备及GOA电路 技术领域
本发明涉及液晶显示技术领域，特别是涉及一种用于液晶显示设备的数组基板行驱动（Gate Driver On Array，GOA）电路。
 背景技术
现代液晶面板生产中，降低成本，提高质量是提高液晶面板核心竞争力的重点。Tri-gate 是一种常用的降低成本的办法，其结构是把所有的像素旋转90度，扫描线(gate line)数目增加为三倍，数据线(data line)数目减少为原本的1/3，因数据芯片的成本较高，通过上述方法减少数据芯片的使用量，从而达到降低成本的目的。
数据芯片所在侧的覆晶薄膜(COF，chip on film)数量减少，对应的数据芯片所在侧扇出(fanout)区域走线变长，扇出区域的RC delay变严重，面板两侧数据信号因RC delay最大而波形失真最严重，两侧充电不足，使得面板两侧出现色偏问题。
参考图1、图2a以及图2b。图1，绘示现有技术的液晶显示设备10的显示区域结构示意图。图2a，绘示根据图1的显示区域的实际显示的第一示意图。图2b，绘示根据图1的显示区域的实际显示的第二示意图。所述显示区域包括多行像素，按照红、绿以及蓝的顺序排列。举例而言，当显示纯色且灰阶为255（后文用L255作为简称）的黄色画面，在图2a中，红色像素行与绿色像素行都需开启到L255的亮度，先打开红色像素，后打开绿色像素，驱动红色像素行(G(1)、G(4))的数据信号因波形失真，导致红色充电不足，无法达到L255要求的亮度，得到的黄色画面两侧会偏绿；在图2b中，如果先打开绿色像素，后打开红色像素，驱动绿色像素行(G(2)、G(5))的数据信号会波形失真而充电不足，从而导致显的黄色画面两侧偏红。
因此，需要提出一种液晶显示设备及GOA电路，以克服上述问题。
 技术问题
本发明的目的在于提供一种用于液晶显示设备GOA电路。
 技术解决方案
为实现上述目的，本发明提供一种用于液晶显示设备的GOA电路，所述液晶显示设备包括多条扫描线，其特征在于，所述GOA电路包含多个GOA单元。所述多个GOA单元相互级联为多级GOA单元，所述第n级GOA单元包括时钟电路、下拉电路、自举电容电路、上拉电路及下拉维持电路。
所述时钟电路，用于接收多级时钟信号的第m级时钟信号、用于连接第n级启动信号线以及所述多条扫描线的第n级扫描线。所述下拉电路，用于连接栅级信号点、用于连接所述第n级扫描线、所述多条扫描线的第n+2级扫描线、第n+2级启动信号线以及固定电压源。所述自举电容电路, 用于连接所述栅极信号点以及所述固定电压源。所述上拉电路，用于连接所述栅极信号点以及连接所述多条扫描线的第n-2级扫描线以及第n-2级启动信号线。所述下拉维持电路，用于连接所述栅级信号点、所述固定电压源以及所述第n级扫描线。所述m以及所述n为正整数。
在一优选实施例中，所述时钟电路包括第一晶体管以及第二晶体管。
所述第一晶体管的控制端连接所述栅极信号点，所述第一晶体管的输入端接收所述第m级时钟信号，所述第一晶体管的输出端连接所述第n级扫描线。
所述第二晶体管的控制端连接所述栅极信号点，所述第二晶体管的输入端连接所述第一晶体管的所述输入端，所述第二晶体管的输出端连接所述第n级启动信号线。
在一优选实施例中，每一所述m个时钟信号的占空比的大小相同。
在一优选实施例中，所述下拉电路包括第三晶体管以及第四晶体管。
所述第三晶体管的控制端连接所述第n+2级扫描线以及所述第n+2级启动信号线，所述第三晶体管的输入端连接所述固定电压源，所述第三晶体管的输出端连接所述第n级扫描线。
所述第四晶体管的控制端连接所述第n+2级扫描线以及所述第n+2级启动信号线，所述第四晶体管的输入端接收所述固定电压源，所述第四晶体管的输出端连接所述栅极信号点
在一优选实施例中，所述自举电容电路包括第一电容。所述第一电容的两端连接所述栅极信号点以及所述第n级数据线。
在一优选实施例中，所述上拉电路包括第五晶体管。所述第五晶体管的控制端连接所述第n-2级扫描线以及所述第n-2级启动信号线，所述第五晶体管的输入端连接所述第五晶体管的所述控制端，所述第五晶体管的输出端连接所述栅级信号点。
在一优选实施例中，所述下拉维持电路包括第一下拉维持电路以及第二下拉维持电路。
所述第一下拉维持电路包括第六晶体管、第七晶体管以及第八晶体管。
所述第六晶体管的输入端连接所述固定电压，所述第六晶体管的输出端连接所述栅级信号点。所述第七晶体管的控制端接收第一低频信号，所述第七晶体管的输出端连接所述第七晶体管的所述控制端。所述第八晶体管的控制端连接栅级信号点，所述第八晶体管的输入端连接所述固定电压源。
所述第二下拉维持电路包括第九晶体管、第十晶体管以及第十一晶体管。
所述第九晶体管的输入端连接所述固定电压，所述第九晶体管的输出端连接所述栅级信号点。所述第十晶体管的控制端接收第二低频信号，所述第十晶体管的输出端连接所述第十晶体管的所述控制端。所述第十一晶体管的控制端连接栅级信号点，所述第十一晶体管的输入端连接所述固定电压源。
在一优选实施例中，所述第一低频信号以及所述第二低频信号为反相的。
在一优选实施例中，所述第一低频信号和所述第二低频信号每100帧切换一次方向。
在一优选实施例中，包括如所述GOA电路的一种液晶显示设备。
 有益效果
本发明用GOA电路代替传统的栅极芯片，通过设计GOA电路的驱动方式，改善Tri-gate色偏问题，同时使用GOA电路代替栅极芯片,可进一步降低生产成本。
附图说明
图1，绘示现有技术的液晶显示设备的显示区域结构示意图；
图2a，绘示根据图1的显示区域的实际显示的第一示意图；
图2b，绘示根据图1的显示区域的实际显示的第二示意图；
图3，绘示本发明的液晶显示设备的显示区域结构示意图；
图4，绘示本发明的液晶显示设备的GOA单元的示意图；
图5，绘示根据图4的GOA电路在图3的显示区域的实际显示的示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
图3，绘示本发明的液晶显示设备20的显示区域结构示意图。所述液晶显示设备20包括多条数据线(D1-D6)、多条扫描线(G1-G6)、GOA电路30。所述显示区域包括多行像素，按照红、绿以及蓝的顺序排列。所述液晶显示设备利用所述GOA电路30对所述多条扫描线(G1-G6)提供扫描信号。所述GOA电路30包括多个相互级联的GOA单元40。
图4，绘示本发明的液晶显示设备20的GOA单元40的示意图。本图是以第n级GOA单元40为例。所述第n级GOA单元40包括时钟电路100、下拉电路200、自举电容电路300、上拉电路400及下拉维持电路500。
所述时钟电路100，用于接收多级时钟信号的第m级时钟信号CKm和用于连接第n级启动信号线ST(n)以及第n级扫描线G(n)。所述下拉电路200，用于连接栅级信号点Q(n)、所述第n级扫描线G(n)、第n+2级扫描线G(n+2)、第n+2级启动信号线ST(n+2)以及固定电压源Vss。所述自举电容电路300,用于连接所述栅极信号点Q(n)以及所述固定电压源Vss。所述上拉电路400,用于连接所述栅极信号点Q(n)以及连接所述多条扫描线的第n-2级扫描线G(n-2)以及第n-2级启动信号线ST (n-2)。所述下拉维持电路500，用于连接所述栅级信号点Q(n)、所述固定电压源Vss以及所述第n级扫描线G(n)。所述m以及所述n为正整数。一般而言，m小于或等于n。
所述时钟电路100包括第一晶体管T1以及第二晶体管T2。所述第一晶体管T1的控制端连接所述栅极信号点Q(n)，所述第一晶体管T1的输入端接收所述第m级时钟信号CKm，所述第一晶体管T1的输出端连接所述第n级扫描线G(n)。
所述第二晶体管T2的控制端连接所述栅极信号点Q(n)，所述第二晶体管T2的输入端连接所述第一晶体管T1的所述输入端，所述第二晶体管T2的输出端连接所述第n级启动信号线ST(n)。
所述下拉电路200包括第三晶体管T3以及第四晶体管T4。
所述第三晶体管T3的控制端连接所述第n+2级扫描线G(n+2)以及所述第n+2级启动信号线ST(n+2)，所述第三晶体管T3的输入端连接所述固定电压源Vss，所述第三晶体管T3的输出端连接所述第n级扫描线G(n)。
所述第四晶体管T4的控制端连接所述第n+2级扫描线G(n+2)以及所述第n+2级启动信号线ST(n+2)，所述第四晶体管T4的输入端接收所述固定电压源Vss，所述第四晶体管T4的输出端连接所述栅极信号点Q(n)。
所述自举电容电路300包括第一电容C1。所述第一电容C1的两端连接所述栅极信号点Q(n)以及所述第n级扫描线G(n)。
所述上拉电路400包括第五晶体管T5。所述第五晶体管T5的控制端连接所述第n-2级扫描线G(n-2)以及所述第n-2级启动信号线ST(n-2)，所述第五晶体管T5的输入端连接所述第五晶体管T5的所述控制端，所述第五晶体管T5的输出端连接所述栅级信号点Q(n)。
所述下拉维持电路500包括第一下拉维持电路510以及第二下拉维持电路520。
所述第一下拉维持电路510包括第六晶体管T6、第七晶体管T7以及第八晶体管T8。
所述第六晶体管T6的输入端连接所述固定电压Vss，所述第六晶体管T6的输出端连接所述栅级信号点Q(n)。所述第七晶体管T7的控制端接收第一低频信号LC1，所述第七晶体管T7的输出端连接所述第七晶体管T7的所述控制端。所述第八晶体管T8的控制端连接栅级信号点Q(n)，所述第八晶体管T8的输入端连接所述固定电压源Vss。
所述第二下拉维持电路520包括第九晶体管T9、第十晶体管T10以及第十一晶体管T11。
所述第九晶体管T9的输入端连接所述固定电压Vss，所述第九晶体管T9的输出端连接所述栅级信号点Q(n)。所述第十晶体管T10的控制端接收第二低频信号LC2，所述第十晶体管T10的输出端连接所述第十晶体管T10的所述控制端。所述第十一晶体管T11的控制端连接栅级信号点Q(n)，所述第十一晶体管T11的输入端连接所述固定电压源Vss。
较佳地，所述第一低频信号LC1和所述第二低频信号LC2为两个反相的低频直流讯号，交替工作，用以保证栅极信号点Q(n)点以及第n级扫描线G(n)的低电位稳定。第n-2级的扫描线G(n-2)的输出跟第n-2级启动信号ST(n-2)信号连接，用于拉高栅极信号点Q(n)的电位。在进行预充电的情况下，用所述第(n+2)级扫描线G（n+2）来辅助下拉所述第n级扫描线G(n)以及所述栅极信号点Q(n)。
图5，绘示根据图4的GOA单元40在图3的显示区域的实际显示的示意图。通过设计不同的的时钟讯号，来改善tri-gate色偏问题，同时也可以达到降低成本的效益。较佳地，所述多个时钟信号的占空部分均相等且不重叠。在本优选实施例中，假设m为4，即总共有4个时钟信号(CK1-CK4)，在每个周期中，所述4个时钟信号(CK1-CK4)的占空部份不重迭；假设n为12，即总共有12个像素行。时钟信号CK1-CK4的占空比设置为25%，当在扫描第n-2像素行时，第n-2级GOA单元会通过第（n-2）级启动信号线ST(n-2)输出，输出的第n-2级启动信号线ST(n-2)与第n级GOA单元连接，用于拉高第n级GOA单元的栅极信号点Q（n），待第m级时钟讯号开启，第n级GOA单元开始输出gate波形，待第（n+2）GOA单元开始输出，第（n+2）级GOA单元的第（n+2）级扫瞄线G(n+2)以及第（n+2）级启动信号线ST(n+2)会把栅极信号点Q（n）和输出第（n）级扫瞄线G(n)的电位拉低。实际操作方式如：
第一级GOA单元打开，第三级GOA单元的栅极信号点的电位被拉高，待所述第三级GOA单元打开，所述第一级GOA单元输出会被拉到低电位，即第一级扫瞄线G(1)关闭，第三级扫瞄线G(3)打开的同时，会将第五级扫瞄线G(5)的栅极信号点点拉高，待所述第五级扫瞄线G(5)打开，所述第三级扫瞄线G(3)输出会被所述第五级扫瞄线G(5)拉到低电位，电路依次往下传亦即，在本优选实施例中，第1、5、9级GOA单元40搭配第1级时钟信号CK1；第2、6、10级GOA单元40搭配第2级时钟信号CK2；第3、7、11级GOA单元40搭配第3级时钟信号CK3；第4、8、12级GOA单元40搭配第4级时钟信号CK4。且，较佳地，所述第一低频信号LC1和所述第二低频信号LC2每100帧切换一次方向。在扫描第n-2行像素时，同时开始扫描第n像素行，当在扫描第n+2像素行时，同时开始关闭第n像素行，举例而言，本优选实施例中，在扫描第1像素行G1时，同时开始扫描第3像素行G3，当在扫描第5像素行G5时，同时开始关闭第3像素行。这里也以L255黄色画面为例，垂直方向pixel的排列方式为RGB重复排列。从数据线的输出讯号可以看到，垂直方向充电不足的绿色像素G数量降低为现有技术的一半(请参考图2b)，能够有效的改善色偏。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (19)

  1. 一种用于液晶显示设备的数组基板行扫描驱动(Gate Driver On Array; GOA)电路，所述液晶显示设备包括多条扫描线，其特征在于，所述GOA电路包含：
    多个GOA单元，相互级联为多级GOA单元，所述第n级GOA单元包括：
    时钟电路，用于接收多级时钟信号的第m级时钟信号及用于连接第n级启动信号线以及所述多条扫描线的第n级扫描线;
    下拉电路，用于连接栅级信号点、所述第n级扫描线、所述多条扫描线的第n+2级扫描线、第n+2级启动信号线以及固定电压源；
    自举电容电路, 用于连接所述栅极信号点以及所述固定电压源;
    上拉电路，用于连接所述栅极信号点以及连接所述多条扫描线的第n-2级扫描线以及第n-2级启动信号线;
    下拉维持电路，用于连接所述栅级信号点、所述固定电压源以及所述第n级扫描线；
    其中所述m以及所述n为正整数，所述时钟电路包括第一晶体管，所述第一晶体管的控制端连接所述栅极信号点，所述第一晶体管的输入端接收所述第m级时钟信号，所述第一晶体管的输出端连接所述第n级扫描线，所述下拉电路包括第三晶体管，所述第三晶体管的控制端连接所述第n+2级扫描线以及所述第n+2级启动信号线，所述第三晶体管的输入端连接所述固定电压源，所述第三晶体管的输出端连接所述第n级扫描线。
  2. 如权利要求1所述的用于液晶显示设备的GOA 电路，其特征在于，所述时钟电路包括：
    第二晶体管，所述第二晶体管的控制端连接所述栅极信号点，所述第二晶体管的输入端连接所述第一晶体管的所述输入端，所述第二晶体管的输出端连接所述第n级启动信号线。
  3. 如权利要求1所述的用于液晶显示设备的GOA 电路，其特征在于，每一所述m个时钟信号的占空比的大小相同。
  4. 如权利要求1所述的用于液晶显示设备的GOA 电路，其特征在于，所述下拉电路包括：
    第四晶体管，所述第四晶体管的控制端连接所述第n+2级扫描线以及所述第n+2级启动信号线，所述第四晶体管的输入端接收所述固定电压源，所述第四晶体管的输出端连接所述栅极信号点；
  5. 如权利要求1所述的用于液晶显示设备的GOA 电路，其特征在于，所述自举电容电路包括：
    第一电容，其两端连接所述栅极信号点以及所述第n级扫描线。
  6. 如权利要求1所述的用于液晶显示设备的GOA 电路，其特征在于，所述上拉电路包括：
    第五晶体管，所述第五晶体管的控制端连接所述第n-2级扫描线以及所述第n-2级启动信号线，所述第五晶体管的输入端连接所述第五晶体管的所述控制端，所述第五晶体管的输出端连接所述栅级信号点。
  7. 如权利要求1所述的用于液晶显示设备的GOA 电路，其特征在于，所述下拉维持电路包括第一下拉维持电路以及第二下拉维持电路；
    所述第一下拉维持电路包括：
    第六晶体管，所述第六晶体管的输入端连接所述固定电压，所述第六晶体管的输出端连接所述栅级信号点；
    第七晶体管，所述第七晶体管的控制端接收第一低频信号，所述第七晶体管的输出端连接所述第七晶体管的所述控制端；以及
    第八晶体管，所述第八晶体管的控制端连接栅级信号点，所述第八晶体管的输入端连接所述固定电压源；
    所述第二下拉维持电路包括：
    第九晶体管，所述第九晶体管的输入端连接所述固定电压，所述第九晶体管的输出端连接所述栅级信号点；
    第十晶体管，所述第十晶体管的控制端接收第二低频信号，所述第十晶体管的输出端连接所述第十晶体管的所述控制端；以及
    第十一晶体管，所述第十一晶体管的控制端连接栅级信号点，所述第十一晶体管的输入端连接所述固定电压源。
  8. 如权利要求7所述的用于液晶显示设备的GOA 电路，其特征在于，所述第一低频信号以及所述第二低频信号为反相的。
  9. 如权利要求7所述的用于液晶显示设备的GOA 电路，其特征在于，所述第一低频信号和所述第二低频信号每100帧切换一次方向。
  10. 一种用于液晶显示设备的数组基板行扫描驱动(Gate Driver On Array; GOA)电路，所述液晶显示设备包括多条扫描线，其特征在于，所述GOA电路包含：
    多个GOA单元，相互级联为多级GOA单元，所述第n级GOA单元包括：
    时钟电路，用于接收多级时钟信号的第m级时钟信号及用于连接第n级启动信号线以及所述多条扫描线的第n级扫描线;
    下拉电路，用于连接栅级信号点、所述第n级扫描线、所述多条扫描线的第n+2级扫描线、第n+2级启动信号线以及固定电压源；
    自举电容电路, 用于连接所述栅极信号点以及所述固定电压源;
    上拉电路，用于连接所述栅极信号点以及连接所述多条扫描线的第n-2级扫描线以及第n-2级启动信号线;以及
    下拉维持电路，用于连接所述栅级信号点、所述固定电压源以及所述第n级扫描线；
    其中所述m以及所述n为正整数。
  11. 如权利要求10所述的用于液晶显示设备的GOA 电路，其特征在于，所述时钟电路包括：
    第一晶体管，所述第一晶体管的控制端连接所述栅极信号点，所述第一晶体管的输入端接收所述第m级时钟信号，所述第一晶体管的输出端连接所述第n级扫描线；以及
    第二晶体管，所述第二晶体管的控制端连接所述栅极信号点，所述第二晶体管的输入端连接所述第一晶体管的所述输入端，所述第二晶体管的输出端连接所述第n级启动信号线。
  12. 如权利要求10所述的用于液晶显示设备的GOA 电路，其特征在于，每一所述m个时钟信号的占空比的大小相同。
  13. 如权利要求10所述的用于液晶显示设备的GOA 电路，其特征在于，所述下拉电路包括：
    第三晶体管，所述第三晶体管的控制端连接所述第n+2级扫描线以及所述第n+2级启动信号线，所述第三晶体管的输入端连接所述固定电压源，所述第三晶体管的输出端连接所述第n级扫描线；以及
    第四晶体管，所述第四晶体管的控制端连接所述第n+2级扫描线以及所述第n+2级启动信号线，所述第四晶体管的输入端接收所述固定电压源，所述第四晶体管的输出端连接所述栅极信号点；
  14. 如权利要求10所述的用于液晶显示设备的GOA 电路，其特征在于，所述自举电容电路包括：
    第一电容，其两端连接所述栅极信号点以及所述第n级扫描线。
  15. 如权利要求10所述的用于液晶显示设备的GOA 电路，其特征在于，所述上拉电路包括：
    第五晶体管，所述第五晶体管的控制端连接所述第n-2级扫描线以及所述第n-2级启动信号线，所述第五晶体管的输入端连接所述第五晶体管的所述控制端，所述第五晶体管的输出端连接所述栅级信号点。
  16. 如权利要求10所述的用于液晶显示设备的GOA 电路，其特征在于，所述下拉维持电路包括第一下拉维持电路以及第二下拉维持电路；
    所述第一下拉维持电路包括：
    第六晶体管，所述第六晶体管的输入端连接所述固定电压，所述第六晶体管的输出端连接所述栅级信号点；
    第七晶体管，所述第七晶体管的控制端接收第一低频信号，所述第七晶体管的输出端连接所述第七晶体管的所述控制端；以及
    第八晶体管，所述第八晶体管的控制端连接栅级信号点，所述第八晶体管的输入端连接所述固定电压源；
    所述第二下拉维持电路包括：
    第九晶体管，所述第九晶体管的输入端连接所述固定电压，所述第九晶体管的输出端连接所述栅级信号点；
    第十晶体管，所述第十晶体管的控制端接收第二低频信号，所述第十晶体管的输出端连接所述第十晶体管的所述控制端；以及
    第十一晶体管，所述第十一晶体管的控制端连接栅级信号点，所述第十一晶体管的输入端连接所述固定电压源。
  17. 如权利要求16所述的用于液晶显示设备的GOA 电路，其特征在于，所述第一低频信号以及所述第二低频信号为反相的。
  18. 如权利要求16所述的用于液晶显示设备的GOA 电路，其特征在于，所述第一低频信号和所述第二低频信号每100帧切换一次方向。
  19. 一种液晶显示设备，其包括如权利要求10的所述GOA电路。
PCT/CN2016/070600 2015-12-24 2016-01-11 液晶显示设备及goa电路 WO2017107255A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/907,825 US9972261B2 (en) 2015-12-24 2016-01-11 Liquid crystal display device and GOA circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510990552.6A CN105390115B (zh) 2015-12-24 2015-12-24 液晶显示设备及goa电路
CN201510990552.6 2015-12-24

Publications (1)

Publication Number Publication Date
WO2017107255A1 true WO2017107255A1 (zh) 2017-06-29

Family

ID=55422335

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/070600 WO2017107255A1 (zh) 2015-12-24 2016-01-11 液晶显示设备及goa电路

Country Status (2)

Country Link
CN (1) CN105390115B (zh)
WO (1) WO2017107255A1 (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106057152B (zh) * 2016-07-19 2018-11-09 深圳市华星光电技术有限公司 一种goa电路及液晶显示面板
CN106297698A (zh) * 2016-08-30 2017-01-04 深圳市华星光电技术有限公司 一种栅极驱动电路及液晶显示面板
CN106128401A (zh) * 2016-08-31 2016-11-16 深圳市华星光电技术有限公司 一种双边阵列基板行驱动电路、液晶显示面板、驱动方法
CN106128397B (zh) * 2016-08-31 2019-03-15 深圳市华星光电技术有限公司 一种goa驱动单元及驱动电路
CN106571123B (zh) * 2016-10-18 2018-05-29 深圳市华星光电技术有限公司 Goa驱动电路及液晶显示装置
CN106328084A (zh) * 2016-10-18 2017-01-11 深圳市华星光电技术有限公司 Goa驱动电路及液晶显示装置
CN106571125B (zh) * 2016-11-07 2019-12-03 深圳市华星光电技术有限公司 Goa驱动电路及其驱动方法、液晶显示器
CN106409262A (zh) 2016-11-28 2017-02-15 深圳市华星光电技术有限公司 Goa驱动电路及液晶显示装置
CN106997753B (zh) * 2017-04-07 2019-07-12 深圳市华星光电技术有限公司 一种goa驱动电路
CN107221299B (zh) * 2017-07-12 2019-06-07 深圳市华星光电半导体显示技术有限公司 一种goa电路及液晶显示器
CN107358931B (zh) * 2017-09-04 2019-12-24 深圳市华星光电半导体显示技术有限公司 Goa电路
CN107731188B (zh) * 2017-11-07 2019-07-12 深圳市华星光电半导体显示技术有限公司 扫描驱动电路及显示面板
CN107863077B (zh) * 2017-11-16 2020-07-31 深圳市华星光电半导体显示技术有限公司 一种改善goa电路开机大电流的方法
CN108962166A (zh) * 2018-07-23 2018-12-07 深圳市华星光电技术有限公司 Goa电路及具有该goa电路的液晶显示装置
CN108962175A (zh) * 2018-08-06 2018-12-07 深圳市华星光电技术有限公司 Goa电路
CN109192160A (zh) * 2018-09-30 2019-01-11 惠科股份有限公司 一种显示面板的驱动方法、系统及显示装置
CN109448657A (zh) * 2018-12-26 2019-03-08 惠科股份有限公司 移位暂存器和栅极驱动电路

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070217563A1 (en) * 2006-03-14 2007-09-20 Au Optronics Corp. Shift register circuit
CN101976580A (zh) * 2010-10-12 2011-02-16 友达光电股份有限公司 可增加驱动能力的第n级移位寄存器及其方法
CN103310755A (zh) * 2013-07-03 2013-09-18 深圳市华星光电技术有限公司 阵列基板行驱动电路
CN203325416U (zh) * 2013-07-03 2013-12-04 深圳市华星光电技术有限公司 阵列基板行驱动电路
CN103956146A (zh) * 2014-04-17 2014-07-30 深圳市华星光电技术有限公司 一种液晶面板驱动电路、液晶显示装置及一种驱动方法
CN104036751A (zh) * 2014-05-05 2014-09-10 友达光电股份有限公司 移位寄存器

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100242244B1 (ko) * 1997-08-09 2000-02-01 구본준 스캐닝 회로
CN103680451B (zh) * 2013-12-18 2015-12-30 深圳市华星光电技术有限公司 用于液晶显示的goa电路及显示装置
CN103928007B (zh) * 2014-04-21 2016-01-20 深圳市华星光电技术有限公司 一种用于液晶显示的goa电路及液晶显示装置
CN104299591B (zh) * 2014-10-31 2017-01-18 深圳市华星光电技术有限公司 阵列基板行驱动电路及液晶显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070217563A1 (en) * 2006-03-14 2007-09-20 Au Optronics Corp. Shift register circuit
CN101976580A (zh) * 2010-10-12 2011-02-16 友达光电股份有限公司 可增加驱动能力的第n级移位寄存器及其方法
CN103310755A (zh) * 2013-07-03 2013-09-18 深圳市华星光电技术有限公司 阵列基板行驱动电路
CN203325416U (zh) * 2013-07-03 2013-12-04 深圳市华星光电技术有限公司 阵列基板行驱动电路
CN103956146A (zh) * 2014-04-17 2014-07-30 深圳市华星光电技术有限公司 一种液晶面板驱动电路、液晶显示装置及一种驱动方法
CN104036751A (zh) * 2014-05-05 2014-09-10 友达光电股份有限公司 移位寄存器

Also Published As

Publication number Publication date
CN105390115A (zh) 2016-03-09
CN105390115B (zh) 2018-10-16

Similar Documents

Publication Publication Date Title
WO2017107255A1 (zh) 液晶显示设备及goa电路
WO2018218718A1 (zh) 双向移位寄存器单元、双向移位寄存器及显示面板
WO2016095267A1 (zh) 移位寄存器、级传栅极驱动电路及显示面板
WO2018094807A1 (zh) Goa驱动电路及液晶显示装置
WO2018072304A1 (zh) Goa驱动电路及液晶显示装置
WO2016161679A1 (zh) 一种goa电路及液晶显示器
WO2018120286A1 (zh) 一种驱动电路及显示面板
WO2017088265A1 (zh) 一种栅极驱动电路及其显示器
WO2017080082A1 (zh) 液晶显示设备及goa电路
WO2015165124A1 (zh) 用于窄边框液晶显示器的栅极驱动器
WO2018072303A1 (zh) Goa驱动电路及液晶显示装置
WO2020113767A1 (zh) Goa电路及显示面板
WO2017049688A1 (zh) 一种goa电路及其驱动方法、液晶显示器
WO2018035995A1 (zh) 扫描驱动电路
WO2018223519A1 (zh) Goa驱动电路及液晶显示器
WO2017143646A1 (zh) 栅极驱动电路
WO2018018724A1 (zh) 扫描驱动电路及具有该电路的平面显示装置
WO2017177491A1 (zh) 液晶显示电路及液晶显示驱动方法
WO2019010816A1 (zh) 一种goa电路及液晶显示器
WO2022007147A1 (zh) Goa电路以及显示面板
WO2017201810A1 (zh) 基于ltps半导体薄膜晶体管的goa电路
WO2018023859A1 (zh) 扫描驱动电路及具有该电路的平面显示装置
WO2017084146A1 (zh) 液晶显示设备及goa电路
WO2017197684A1 (zh) 基于ltps半导体薄膜晶体管的goa电路
WO2016101293A1 (zh) 驱动电路

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14907825

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16877069

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16877069

Country of ref document: EP

Kind code of ref document: A1