WO2018120286A1 - 一种驱动电路及显示面板 - Google Patents

一种驱动电路及显示面板 Download PDF

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Publication number
WO2018120286A1
WO2018120286A1 PCT/CN2017/070466 CN2017070466W WO2018120286A1 WO 2018120286 A1 WO2018120286 A1 WO 2018120286A1 CN 2017070466 W CN2017070466 W CN 2017070466W WO 2018120286 A1 WO2018120286 A1 WO 2018120286A1
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WIPO (PCT)
Prior art keywords
goa unit
scan line
group
sub
nth
Prior art date
Application number
PCT/CN2017/070466
Other languages
English (en)
French (fr)
Inventor
杜鹏
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to JP2019528097A priority Critical patent/JP6861279B2/ja
Priority to KR1020197021284A priority patent/KR102216434B1/ko
Priority to US15/327,564 priority patent/US10223992B2/en
Priority to EP17885661.3A priority patent/EP3564942A4/en
Publication of WO2018120286A1 publication Critical patent/WO2018120286A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a driving circuit and a display panel.
  • GOA Gate-driver On Array
  • Figure 1 shows the existing The equivalent circuit diagram of the GOA unit.
  • the T11 of the nth stage GOA unit is connected to the ST(n-2) signal, which turns on the GOA circuit of the present stage, that is, pulls the potential of the Q point high.
  • the input terminals of T21 and T22 are connected to the clock signal CK, and T21 outputs the scanning signal G(n) of the present stage.
  • T22 outputs an ST(n) signal for turning on the next stage GOA circuit.
  • the input terminals of T31 and T41 are connected to the low level signal VSS, which is responsible for pulling the potential of the Q point and G(n) signal low.
  • the panel of the GOA architecture generally adopts a dual-drive architecture, but the STV signals in the conventional GOA circuit are only unilaterally transmitted. If the STV signal outputted by a certain level of the GOA unit is abnormal, the GOA unit of the stage is caused. Subsequent GOA units that are cascaded will fail.
  • the present invention provides a driving circuit for inputting a scan signal to a display panel, the display panel includes n rows of pixels; each row of pixels is correspondingly provided with a scan line group, the scan line The group includes a main scan line and a sub scan line;
  • the driving circuit includes: an n-th GOA unit group, a first clock signal group, and a second clock signal group, wherein the first clock signal group and the second clock signal group are oppositely disposed, wherein the nth-level GOA unit group corresponds to The nth main scanning line and the nkth sub scanning line; the GOA unit group includes two GOA units located on opposite sides of the corresponding scanning line group;
  • the nth-level GOA units located on the same side of the scan line group are respectively cascaded with the n+k-th GOA unit located on the same side of the scan line group;
  • An output end of the nth stage GOA unit located on the first side of the scan line group is connected to the nkth row sub-scan line, and an output end of the nth stage GOA unit located on the second side of the scan line group is also Nk rows are scanned by a scan line, where n is greater than or equal to 1, and k is greater than or equal to 1.
  • the present invention provides a driving circuit, wherein the driving circuit is configured to input a scanning signal to a display panel, the display panel includes n rows of pixels; each row of pixels is correspondingly disposed with a scanning line group, and the scanning line group includes a main scanning line. And sub-scan lines;
  • the driving circuit includes: an n-th GOA unit group, wherein the n-th GOA unit group corresponds to the n-th main scanning line and the nk-th sub-scanning line; and the GOA unit group includes two sides on opposite sides of the corresponding scanning line group.
  • the nth-level GOA units located on the same side of the scan line group are respectively cascaded with the n+k-th GOA unit located on the same side of the scan line group;
  • the nth stage GOA unit located on the first side of the scan line group is electrically connected to the nth stage GOA unit located on the second side of the scan line group, wherein n is greater than or equal to 1, and k is greater than or equal to 1.
  • the invention also provides a display panel comprising:
  • the pixel includes a main pixel area and a sub-pixel area, the main pixel area is provided with a first charging module and a pull-up module; and the first charging module is configured to: when charging the sub-pixel area, the main pixel The area is charged; the pull-up module is configured to pull up a potential of the main pixel area when the main pixel area and the sub-pixel area are charged;
  • the sub-pixel area is provided with a second charging module and a pull-down module; the second charging module is configured to charge the sub-pixel area when charging the main pixel area; the pull-down module is used in the When the main pixel region and the sub-pixel region are charged, the potential of the sub-pixel region is pulled down.
  • the driving circuit and the display panel of the present invention connect the output end of the left GOA unit in the same stage to the GOA unit on the right side, so that when the STV signal of one of the GOA units is abnormal, the normal side GOA unit can be output.
  • the STV signal is transmitted to the GOA unit on the abnormal side to avoid failure of the GOA unit in the subsequent stage.
  • Figure 1 is an equivalent circuit diagram of a conventional GOA unit.
  • FIG. 2 is a schematic structural view of a conventional driving circuit.
  • FIG. 3 is another schematic structural view of a conventional driving circuit.
  • FIG. 4 is another schematic structural view of a conventional driving circuit.
  • FIG. 5 is a schematic structural view of a driving circuit of the present invention.
  • FIG. 6 is another schematic structural view of a driving circuit of the present invention.
  • FIG. 7 is a schematic structural view of a pixel of the present invention.
  • FIG. 2 is a schematic structural diagram of a conventional driving circuit.
  • the driving circuit of this embodiment is a COA circuit, and each side has seven levels of COA units, which are respectively 101-114; in the forward scanning, the left level first stage GOA unit 101 is to the third level.
  • the GOA unit 103 inputs the concatenation signal ST1, the second stage GOA unit 102 on the left side inputs the concatenation signal ST2 to the fourth stage GOA unit 104, and the third stage GOA unit 103 on the left side inputs the concatenation to the fifth stage GOA unit 105.
  • Signal ST3 The fourth stage GOA unit 104 on the left side inputs the concatenation signal ST4 to the sixth stage GOA unit 106.
  • the fifth-stage GOA unit 105 on the left side inputs the concatenation signal ST5 to the seventh-stage GOA unit 107.
  • Each level of the GOA unit outputs two signals G(n) and ST(n), where G(n) is G(1) to G(7), where ST(n) is ST1 to ST8.
  • the G(n) signal is used to control the corresponding gate line
  • the ST(n) signal is used to turn on the NO+2 GOA unit
  • the ST(n) signal is also connected to the n-2th GOA unit.
  • the control section such as the third stage GOA unit 103, inputs ST3 to the first stage GOA unit 101 to pull down the potential of the output of the first stage GOA unit, and the remaining stages of the GOA unit are similar.
  • the ST signals of the first-stage GOA unit and the second-stage GOA unit on the left and right sides are directly provided by the drive IC.
  • the scan signals of the outputs of the GOA units of the same stage on both sides in Fig. 2 are connected to the same gate line, and the output STV signals are transmitted on one side.
  • the ST(n) signal and the G(n) waveform output by each level of the GOA unit are completely identical and are a square wave signal.
  • the scan signals output by each stage of the GOA unit respectively control two gate lines, which are the n-2th sub-gate line 11-17 and the nth main gate line 21-27, respectively.
  • the nth stage GOA unit corresponds to the nth main gate line for charging the nth row of pixels.
  • the nth-level GOA unit further corresponds to the n-2th sub-gate line for performing charge sharing on the n-2th row of pixels.
  • the nth stage GOA unit also outputs an ST(n) signal, which on the one hand pulls up the Q point potential of the n+2th GOA unit, and also connects the pulldown circuit of the n-2th stage GOA unit to The Q-point and G(n-2) signals of the n-2 stage circuit are pulled down to the Vss voltage.
  • the ST signal output by the bilaterally driven GOA circuit of Figure 3 is also unilaterally transmitted.
  • a chain reaction occurs when the ST signal output of a certain level of GOA circuit fails.
  • the ST1 signal output of the first-stage GOA unit on the right side fails (for example, an abnormality occurs in T22)
  • the GOA units of the 3rd, 5th, and 7th levels below it cannot be opened, as shown by the dotted line in the figure. As shown, the circuit does not work properly.
  • FIG. 5 is a schematic structural diagram of a driving circuit of the present invention.
  • the driving circuit of the embodiment is a GOA circuit for inputting a scan signal to a display panel.
  • the display panel includes n rows of pixels, and each row of pixels is correspondingly provided with a scan line group, and the scan line group is disposed. Includes main scan lines and sub scan lines.
  • the driving circuit includes: a 7-level GOA unit group including two GOA units located on two sides of a corresponding scan line group; for example, 1 to 7 GOA units 301 to 307 on the left side; 1 on the right side Up to level 7 GOA units 308 to 314.
  • Each of the GOA units corresponds to one row of pixels;
  • the nth GOA unit group corresponds to the nth main scanning line and the n-2th sub scanning line; wherein n is greater than or equal to 2, and k is greater than or equal to 1.
  • the level 3 GOA unit 303 corresponds to the main scanning line 43 of the third row of pixels and the sub-scanning line 33 of the first row of pixels; the remaining stages of the GOA unit are similar. It is to be understood that 31-37 in the figure denote sub-scan lines, and 41 to 47 denote main scanning lines.
  • An nth-level GOA unit located to the left of the scan line group is cascaded with an n+2th GOA unit located to the left of the scan line group, and an nth-level GOA unit located at the right side of the scan line group
  • the n+2th GOA unit on the right side of the scan line group is cascaded.
  • the first level GOA unit 301 is cascaded with the third level GOA unit 303
  • the third level GOA unit 303 is cascaded with the fifth level GOA unit 305
  • Unit 307 is cascaded and the GOA unit on the right is similar.
  • each level of the GOA unit on the left side is electrically connected to the GOA unit of the same level on the right side.
  • the first level GOA unit 301 on the left side is electrically connected to the first level GOA unit 308 on the right side, and the connection manners of the remaining level GOA units are similar.
  • the output of the left-stage third-level GOA unit 303 is connected to the sub-scanning line 33 of the first row of pixels (ie, the first row of sub-scanning lines); the third-level GOA unit 310 of the right side
  • the output is also coupled to the sub-scan line 33 of the first row of pixels; the output can include a scan signal output and a cascaded signal output.
  • the GOA units on the opposite sides are electrically connected through the sub-scanning lines, the signal at the output of the left GOA unit can be transmitted to the output of the GOA unit on the right side. Therefore, when an abnormality occurs in a certain level of the GOA unit on the right side, the GOA unit subsequent to the GOA unit of the level can still be operated normally. For example, when the ST signal output of the first stage GOA unit on the right side is abnormal, the T22 thin film transistor of the first stage GOA unit of the right side is cut, and the signals output by the GOA unit of the stage are all provided by the GOA unit on the left side. Therefore, the GOA units of the 3rd, 5th, and 7th levels on the right side can work normally. It can be understood that the remaining levels of the GOA units are connected in the same manner as the level 3 GOA units.
  • Each GOA unit includes a first cascade signal input terminal, a second cascade signal input terminal, a scan signal output terminal, and a cascade signal output terminal.
  • the cascaded signal output terminal 51 of the third stage GOA unit 303 on the left side is cascaded with the first cascade signal input end 52 of the fifth stage GOA unit on the left side;
  • the cascaded signal output terminal 51 of the stage GOA unit is also connected to the first row sub-scanning line 33, and the scanning signal output terminal 53 of the third-stage GOA unit 303 is connected to the third-row main scanning line 43;
  • the third-level GOA unit The first cascade signal input terminal 55 of the 303 is connected to the cascade signal output terminal 54 of the first stage GOA unit 301; the cascade signal of the second cascade signal input terminal of the third stage GOA unit 303 and the fifth stage GOA unit
  • the output is connected to pull the signal at the output of the level 3 GOA unit 303 low.
  • the right side is the same.
  • the scan signal output end of the nth stage GOA unit is connected to the n-2th row sub scan line.
  • the scan signal output end of the third stage GOA unit 303 on the left side is connected to the first line sub-scan line; the scan signal output end of the third stage GOA unit 310 on the right side is also connected to the first line. Sub-scan line connection.
  • the GOA unit includes a clock signal input for inputting a clock signal.
  • the driving circuit includes a first clock signal group and a second clock signal group, the first clock signal group and the second clock signal group are oppositely disposed, the first clock signal group and the second clock signal group Both include a first clock signal CK1, a second clock signal CK2, a third clock signal CK3, and a fourth clock signal CK4.
  • the GOA circuit can include GOA units of level 7 or higher.
  • the driving circuit includes a 4-level GOA unit group including two GOA units located on both sides of a corresponding scan line group; for example, 1 to 4 stage GOA units 401 to 404 on the left side; 1 to the right side Level 4 GOA units 405 to 408.
  • the nth stage GOA unit group corresponds to the nth main scanning line and the n-1th sub scanning line; wherein n is greater than or equal to 1, and k is greater than or equal to 1.
  • the third level GOA unit 403 corresponds to the main scanning line 63 of the third row of pixels and the sub-scanning line 53 of the second row of pixels; the remaining GOA units are similar. It is to be understood that 51-54 in the figure denote sub-scan lines, and 61 to 64 denote main scanning lines.
  • the nth-level GOA unit in the GOA circuit of this embodiment may also be cascaded with the n+k-th GOA unit, where k is greater than 2, and the nth is
  • the level GOA unit group corresponds to the nth row main scanning line and the nkth row sub scanning line; the nth level GOA unit located on the same side of the scanning line group and the n+kth level GOA on the same side of the scanning line group, respectively
  • the unit cascades; the nth stage GOA unit located on the first side of the scan line group is electrically connected to the nth stage GOA unit located on the second side of the scan line group.
  • the output of the nth stage GOA unit located on the first side of the scan line group is connected to the nkth row sub-scan line, and the output of the nth stage GOA unit located on the second side of the scan line group
  • the terminal is also connected to the nk row sub-scanning line.
  • the GOA unit includes a first cascade signal input terminal, a second cascade signal input terminal, a scan signal output terminal, and a cascade signal output terminal;
  • a cascaded signal output end of the nth stage GOA unit located on the same side of the scan line group is connected to a first cascade signal input end of the n+kth stage GOA unit located on the same side of the scan line group;
  • the cascaded signal output of the n-stage GOA unit is connected to the nk-th row sub-scan line.
  • the scan signal output end of the nth stage GOA unit is connected to the nth row main scan line; the cascade signal of the first cascade signal input end of the nth stage GOA unit and the nkth stage GOA unit The output terminal is connected; the second cascade signal input end of the nth stage GOA unit is connected to the cascade signal output end of the n+2th GOA unit.
  • the scan signal output end of the nth stage GOA unit is connected to the n-2th row sub scan line.
  • the driving circuit of the present invention connects the output end of the left GOA unit in the same stage to the GOA unit on the right side, so that when the STV signal of one of the GOA units is abnormal, the STV signal outputted by the normal side GOA unit can be output. Passed to the GOA unit on the abnormal side to avoid failure of the GOA unit at the later stage.
  • the present invention also provides a display panel including the above-described driving circuit.
  • FIG. 7 is a schematic structural diagram of a pixel of the present invention.
  • the display panel of this embodiment includes a plurality of scan line groups and a plurality of data lines and a plurality of pixels defined by the scan line groups and the data lines;
  • the scan line group includes a main scan line 74 and a sub-scan line 75, the pixel includes a main pixel area 71 and a sub-pixel area 72, the main pixel area 71 is provided with a first charging module 711 and a pull-up module 712;
  • a charging module is configured to charge the main pixel region 71 when the sub-pixel region 72 is charged.
  • the pull-up module 712 is configured to pull up the potential of the main pixel region 71 when the main pixel region 71 and the sub-pixel region 72 are fully charged.
  • the first charging module 711 includes a first thin film transistor T1; a gate of the first thin film transistor T1 is connected to the main scanning line 74, and a source of the first thin film transistor T1 is The data lines 73 are connected.
  • the first charging module 711 further includes a first liquid crystal capacitor C1. One end of the first liquid crystal capacitor C1 is connected to the drain of the first thin film transistor T1, and the other end of the first liquid crystal capacitor C1 is grounded.
  • the pull-up module 712 includes a first shared capacitor C2, one end of the first shared capacitor C2 is connected to the drain of the first thin film transistor T1, and the first shared capacitor C2 is One end is connected to the drain of the third thin film transistor T3.
  • the pull up module 712 can be other energy storage components.
  • the sub-pixel area 72 is provided with a second charging module 721 and a pull-down module 722;
  • the second charging module 721 is configured to charge the sub-pixel region 72 when the main pixel region 71 is charged.
  • the pull-down module 722 is configured to pull down the potential of the sub-pixel region 72 when the main pixel region 71 and the sub-pixel region 72 are fully charged.
  • the second charging module 721 includes a second thin film transistor T2; a gate of the second thin film transistor T2 is connected to the main scanning line 74, and a source of the second thin film transistor T2 is connected to the data line 73. ,
  • the second charging module 721 further includes a second liquid crystal capacitor C3. One end of the second liquid crystal capacitor C3 is connected to the drain of the second thin film transistor T2, and the other end of the second liquid crystal capacitor C2 is grounded.
  • the pull-down module 722 includes a third thin film transistor T3 and a second partial capacitor C4.
  • the gate of the third thin film transistor T3 is connected to the sub-scanning line 75, and the source of the third thin film transistor T3 is The drain of the second thin film transistor T2 is connected to the other end of the first shared capacitor C2 and one end of the second shared capacitor C4, the second shared capacitor The other end of C4 is grounded.
  • the third thin film transistor T3 Since the third thin film transistor T3 is turned on when the sub-scanning line 75 is at a high level, the second shared capacitor C4 is charged. Since the first sharing capacitor C2 is also connected to the drain of the third thin film transistor T3; thus, the voltage of the first sharing capacitor C2 and the voltage of the second sharing capacitor C4 are the same, that is, the voltage of the first liquid crystal capacitor C1 is increased, thereby increasing the voltage of the first liquid crystal capacitor C1, thereby The brightness of the main pixel area is increased.
  • the main scan line of the nth row of pixels is used to connect the scan signal output end of the nth stage GOA unit, and the sub scan line of the nth row of pixels is used to connect the n+2th GOA unit. Cascaded signal output.
  • the pull-up module is disposed in the main pixel region, not only can the potential of the sub-pixel region be pulled low, but also the potential of the main pixel region is pulled high, thereby further increasing the voltage difference between the main pixel region and the sub-pixel region, thereby Better reduce color cast.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Abstract

一种驱动电路及显示面板，驱动电路包括n级GOA单元组，其中第n级GOA单元组对应第n行主扫描线(31…37, 51…54,74)和第n-k行子扫描线(41…47,61…64,75)；GOA单元组包括位于对应的扫描线组两侧的两个GOA单元(301…307,401…404,308…314,405…408)；位于扫描线组第一侧的第n级GOA单元(301…307,401…404)与位于扫描线组第二侧的第n级GOA单元(308…314,405…408)电性连接。

Description

一种驱动电路及显示面板 技术领域
本发明涉及液晶显示器技术领域，特别是涉及一种驱动电路及显示面板。
 背景技术
GOA（Gate-driver On Array）技术由于可以降低成本以及减小面板边框的尺寸，因此被广泛地应用。
如图1所示，图1给出现有 GOA单元的等效电路图。第n级GOA单元的T11连接ST（n-2）信号，该信号将本级GOA电路打开，即把Q点的电位拉高。T21和T22的输入端连接时钟信号CK，其中T21输出本级的扫描信号G（n）。T22输出ST（n）信号，该信号用于将下一级GOA电路打开。T31和T41的输入端连接低电平信号VSS，负责将Q点和G（n）信号的电位拉低。
由于线路存在负载，因此GOA架构的面板一般都采用双驱架构，但传统的GOA电路中的STV信号都只是单边传递，如果某一级GOA单元输出的STV信号异常，则导致该级GOA单元之后的与其级联的GOA单元都会失效。
因此，有必要提供一种驱动电路及显示面板，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种驱动电路及显示面板，能够减小GOA区域的宽度。
 技术解决方案
为解决上述技术问题，本发明提供一种驱动电路，所述驱动电路用于向显示面板输入扫描信号，所述显示面板包括n行像素；每行像素对应设置一扫描线组，所述扫描线组包括主扫描线和子扫描线；
所述驱动电路包括：n级GOA单元组、第一时钟信号组以及第二时钟信号组，所述第一时钟信号组和所述第二时钟信号组相对设置，其中第n级GOA单元组对应第n行主扫描线和第n-k行子扫描线；所述GOA单元组包括位于对应的扫描线组两侧的两个GOA单元；
位于所述扫描线组同一侧的第n级GOA单元分别与位于所述扫描线组同一侧的第n+k级GOA单元级联；
位于所述扫描线组第一侧的第n级GOA单元的输出端与第n-k行子扫描线连接，位于所述扫描线组第二侧的第n级GOA单元的输出端也与所述第n-k行子扫描线连接，其中n大于等于1，k为大于等于1。
本发明提供一种驱动电路，其中所述驱动电路用于向显示面板输入扫描信号，所述显示面板包括n行像素；每行像素对应设置一扫描线组，所述扫描线组包括主扫描线和子扫描线；
所述驱动电路包括：n级GOA单元组，其中第n级GOA单元组对应第n行主扫描线和第n-k行子扫描线；所述GOA单元组包括位于对应的扫描线组两侧的两个GOA单元；
位于所述扫描线组同一侧的第n级GOA单元分别与位于所述扫描线组同一侧的第n+k级GOA单元级联；
位于所述扫描线组第一侧的第n级GOA单元与位于所述扫描线组第二侧的第n级GOA单元电性连接，其中n大于等于1，k为大于等于1。
本发明还提供一种显示面板，其包括：
多条扫描线组和多条数据线以及由所述扫描线组和所述数据线限定的多个像素；
所述像素包括主像素区和子像素区，所述主像素区设置有第一充电模块和上拉模块；所述第一充电模块用于在对所述子像素区充电时，对所述主像素区进行充电；所述上拉模块用于在所述主像素区和所述子像素区充电完毕时，上拉所述主像素区的电位；
所述子像素区设置有第二充电模块和下拉模块；所述第二充电模块用于在对所述主像素区充电时，对所述子像素区进行充电；所述下拉模块用于在所述主像素区和所述子像素区充电完毕时，下拉所述子像素区的电位。
 有益效果
本发明的驱动电路及显示面板，将同一级中左侧的GOA单元的输出端与右侧的GOA单元连接，从而当其中一侧的GOA单元的STV信号异常时，可以将正常侧GOA单元输出的STV信号传递至异常侧的GOA单元中，避免后面级的GOA单元失效。
 附图说明
图1为现有GOA单元的等效电路图。
图2为现有驱动电路的一结构示意图。
图3为现有驱动电路的另一结构示意图。
图4为现有驱动电路的又一结构示意图。
图5为本发明驱动电路的一结构示意图。
图6为本发明驱动电路的另一结构示意图。
图7为本发明像素的一结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参照图2至4，图2为现有驱动电路的一结构示意图。
如图2所示，本实施例的驱动电路为COA电路，其每侧都设置七级COA单元，分别为101-114；正向扫描时，左侧的第一级GOA单元101向第三级GOA单元103输入级联信号ST1、左侧的第二级GOA单元102向第四级GOA单元104输入级联信号ST2、左侧的第三级GOA单元103向第五级GOA单元105输入级联信号ST3。左侧的第四级GOA单元104向第六级GOA单元106输入级联信号ST4。左侧的第五级GOA单元105向第七级GOA单元107输入级联信号ST5。
每一级GOA单元会输出两个信号G（n）和ST（n），其中G（n）为G（1）至G（7），其中ST（n）为ST1至ST8。G（n）信号用于控制对应的栅极线，ST（n）信号用于将第n+2级的GOA单元打开，同时ST（n）信号也会连接第n-2级GOA单元的下拉控制部分，比如第三级GOA单元103向第一级GOA单元101输入ST3，以拉低第一级GOA单元输出端的电位，其余级的GOA单元与此类似。左右两侧第一级GOA单元和第二级GOA单元的ST信号是由驱动IC直接提供。
图2中两侧中同一级的GOA单元的输出的扫描信号连接到同一条栅极线，而输出的STV信号则是单侧传递。每一级GOA单元输出的ST（n）信号和G（n）的波形是完全一致的，都是一个方波信号。
在图3中，每一级GOA单元输出的扫描信号分别控制两条栅极线，分别为第n-2条子栅极线11-17和第n条主栅极线21-27。其中，第n级GOA单元对应第n条主栅极线，用于第n行像素的充电。第n级GOA单元还对应第n-2条子栅极线，用于对第n-2行像素进行电荷分享。同时第n级GOA单元还会输出ST（n）信号，它一方面将第n+2级GOA单元的Q点电位拉高，另外也连接第n-2级GOA单元的下拉电路，以将第n-2级电路的Q点和G（n-2）信号拉低至Vss电压。与图2中的架构相同，图3中双边驱动的GOA电路输出的ST信号也是单边传递。
因此，当某一级GOA电路的ST信号输出失效时就会出现连锁反应。具体如图4所示，比如右侧的第1级GOA单元的ST1信号输出失效时（比如T22出现异常），它下方的第3、5、7级GOA单元都无法被打开，如图中虚线所示，从而导致电路不能正常工作。
请参照图5，图5为本发明驱动电路的一结构示意图。
如图5所示，本实施例的驱动电路为GOA电路，其用于向显示面板输入扫描信号，所述显示面板包括n行像素，每行像素对应设置一扫描线组，所述扫描线组包括主扫描线和子扫描线。
所述驱动电路包括：7级GOA单元组，所述GOA单元组包括位于对应的扫描线组两侧的两个GOA单元；比如左侧的1至7级GOA单元301至307；右侧的1至7级GOA单元308至314。其中每一级GOA单元对应一行像素；第n级GOA单元组对应第n行主扫描线和第n-2行子扫描线；其中n大于等于2，k为大于等于1。比如，第3级GOA单元303对应第3行像素的主扫描线43以及第1行像素的子扫描线33；其余级的GOA单元与此类似。可以理解的，图中31-37表示子扫描线，41至47表示主扫描线。
位于所述扫描线组左侧的第n级GOA单元与位于所述扫描线组左侧的第n+2级GOA单元级联，位于所述扫描线组右侧的第n级GOA单元与位于所述扫描线组右侧的第n+2级GOA单元级联。比如以左侧为例，第1级GOA单元301与第3级GOA单元303级联，第3级GOA单元303与第5级GOA单元305级联，第5级GOA单元305与第7级GOA单元307级联，右侧的GOA单元与此类似。
同时左侧的每一级GOA单元与右侧的同一级的GOA单元电性连接。比如左侧的第1级GOA单元301与右侧的第1级GOA单元308电性连接，其余级的GOA单元的连接方式与此类似。
在一实施方式中，左侧的第3级GOA单元303的输出端与第1行像素的子扫描线33连接（也即第1行子扫描线）；右侧的第3级GOA单元310的输出端也与第1行像素的子扫描线33连接；该输出端可以包括扫描信号输出端和级联信号输出端。
由于通过子扫描线将对应两侧的GOA单元进行电性连接，从而可以将左侧GOA单元输出端的信号传递至右侧的GOA单元输出端。因此当右侧的某一级GOA单元出现异常时，仍然可以使该级GOA单元之后的GOA单元正常工作。比如，当右侧的第一级GOA单元的ST信号输出异常时，将右侧第一级GOA单元的T22薄膜晶体管切断，该级GOA单元输出的信号全部由左侧的GOA单元提供。因此右侧第3、5、7级的GOA单元就可以正常工作。可以理解的，其余级的GOA单元的连接方式与第3级GOA单元的连接方式相同。
每个GOA单元包括第一级联信号输入端、第二级联信号输入端、扫描信号输出端、级联信号输出端。在一实施方式中，位于所述扫描线组同一侧的第n级GOA单元的级联信号输出端与位于所述扫描线组同一侧的第n+2级GOA单元的第一级联信号输入端连接；所述第n级GOA单元的级联信号输出端与第n-2行子扫描线连接。
比如以第3级为例，左侧的第3级GOA单元303的级联信号输出端51与左侧的第5级GOA单元的第一级联信号输入端52级联；左侧的第3级GOA单元的级联信号输出端51还与第1行子扫描线33连接，所述第3级GOA单元303的扫描信号输出端53与第3行主扫描线43连接；第3级GOA单元303的第一级联信号输入端55与第1级GOA单元301的级联信号输出端54连接；第3级GOA单元303的第二级联信号输入端与第5级GOA单元的级联信号输出端连接，用于将第3级GOA单元303的输出端的信号拉低。右侧与此相同。
在一实施方式中，所述第n级GOA单元的扫描信号输出端与第n-2行子扫描线连接。比如以第3级为例，左侧的第3级GOA单元303的扫描信号输出端与第1行子扫描线连接；右侧的第3级GOA单元310的扫描信号输出端也与第1行子扫描线连接。
所述GOA单元包括时钟信号输入端，所述时钟信号输入端用于输入一时钟信号。所述驱动电路包括第一时钟信号组和第二时钟信号组，所述第一时钟信号组和所述第二时钟信号组相对设置，所述第一时钟信号组和所述第二时钟信号组都包括第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3、第四时钟信号CK4。
可以理解的，该GOA电路可以包括7级以上的GOA单元。
可以理解的，本实施例中的GOA单元的级联方式并不能对本发明构成限定。其他的级联方式同样适用于本发明。
如图6所示，位于扫描线同一侧的第1级GOA单元还可以与同一侧的第2级GOA单元级联。所述驱动电路包括4级GOA单元组，所述GOA单元组包括位于对应的扫描线组两侧的两个GOA单元；比如左侧的1至4级GOA单元401至404；右侧的1至4级GOA单元405至408。其中第n级GOA单元组对应第n行主扫描线和第n-1行子扫描线；其中n大于等于1，k为大于等于1。比如，第3级GOA单元403对应第3行像素的主扫描线63以及第2行像素的子扫描线53；其余级GOA单元与此类似。可以理解的，图中51-54表示子扫描线，61至64表示主扫描线。
当然，可以理解的，除了图5和图6的级联方式，本实施例的GOA电路中第n级GOA单元也可以与第n+k级GOA单元级联，k大于2，此时第n级GOA单元组对应第n行主扫描线和第n-k行子扫描线；位于所述扫描线组同一侧的第n级GOA单元分别与位于所述扫描线组同一侧的第n+k级GOA单元级联；位于所述扫描线组第一侧的第n级GOA单元与位于所述扫描线组第二侧的第n级GOA单元电性连接。
在一实施方式中，位于所述扫描线组第一侧的第n级GOA单元的输出端与第n-k行子扫描线连接，位于所述扫描线组第二侧的第n级GOA单元的输出端也与第n-k行子扫描线连接。
在一实施方式中，所述GOA单元包括第一级联信号输入端、第二级联信号输入端、扫描信号输出端、级联信号输出端；
位于所述扫描线组同一侧的第n级GOA单元的级联信号输出端与位于所述扫描线组同一侧的第n+k级GOA单元的第一级联信号输入端连接；所述第n级GOA单元的级联信号输出端与第n-k行子扫描线连接。
在一实施方式中，所述第n级GOA单元的扫描信号输出端与第n行主扫描线连接；第n级GOA单元的第一级联信号输入端与第n-k级GOA单元的级联信号输出端连接；第n级GOA单元的第二级联信号输入端与第n+2级GOA单元的级联信号输出端连接。
在一实施方式中，所述第n级GOA单元的扫描信号输出端与第n-2行子扫描线连接。
本发明的驱动电路，将同一级中左侧的GOA单元的输出端与右侧的GOA单元连接，从而当其中一侧的GOA单元的STV信号异常时，可以将正常侧GOA单元输出的STV信号传递至异常侧的GOA单元中，避免后面级的GOA单元失效。
本发明还提供一种显示面板，其包括上述的驱动电路。
请参照图7，图7为本发明像素的一结构示意图。
如图7所示，本实施例的显示面板包括多条扫描线组和多条数据线以及由所述扫描线组和所述数据线限定的多个像素；
所述扫描线组包括主扫描线74和子扫描线75，所述像素包括主像素区71和子像素区72，所述主像素区71设置有第一充电模块711和上拉模块712；所述第一充电模块用于在对所述子像素区72充电时，对所述主像素区71进行充电。所述上拉模块712用于在所述主像素区71和所述子像素区72充电完毕时，上拉所述主像素区71的电位。
在一实施方式中，所述第一充电模块711包括第一薄膜晶体管T1；所述第一薄膜晶体管T1的栅极与所述主扫描线74连接，所述第一薄膜晶体管T1的源极与所述数据线73连接。所述第一充电模块711还包括第一液晶电容C1，该第一液晶电容C1的一端与第一薄膜晶体管T1的漏极连接，该第一液晶电容C1的另一端接地。
在一实施方式中，所述上拉模块712包括第一分享电容C2，所述第一分享电容C2的一端与所述第一薄膜晶体管T1的漏极连接，所述第一分享电容C2的另一端与所述第三薄膜晶体管T3的漏极连接。在一实施方式中，所述上拉模块712可以为其他储能元件。
所述子像素区72设置有第二充电模块721和下拉模块722；
所述第二充电模块721用于对所述主像素区71充电时，对所述子像素区72进行充电。所述下拉模块722用于在所述主像素区71和所述子像素区72充电完毕时，下拉所述子像素区72的电位。
所述第二充电模块721包括第二薄膜晶体管T2；所述第二薄膜晶体管T2的栅极与所述主扫描线74连接，所述第二薄膜晶体管T2的源极与所述数据线73连接，
所述第二充电模块721还包括第二液晶电容C3，该第二液晶电容C3的一端与第二薄膜晶体管T2的漏极连接，该第二液晶电容C2的另一端接地。
所述下拉模块722包括第三薄膜晶体管T3和第二分电容C4，所述第三薄膜晶体管T3的栅极与所述子扫描线75连接，所述第三薄膜晶体管T3的源极与所述第二薄膜晶体管T2的漏极连接；所述第三薄膜晶体管T3的漏极分别与所述第一分享电容C2的另一端以及所述第二分享电容C4的一端连接，所述第二分享电容C4的另一端接地。
由于当子扫描线75为高电平时，第三薄膜晶体管T3开启，从而对第二分享电容C4充电。由于第一分享电容C2也连接第三薄膜晶体管T3的漏极；从而使得第一分享电容C2的电压和第二分享电容C4的电压相同，也即增大了第一液晶电容C1的电压，从而增大了主像素区的亮度。
可以理解的，在一实施方式中，第n行像素的主扫描线用于连接第n级GOA单元的扫描信号输出端，第n行像素的子扫描线用于连接第n+2级GOA单元的级联信号输出端。
本发明的显示面板，在主像素区设置上拉模块，不仅可以将子像素区的电位拉低，还将主像素区的电位拉高，进一步增大主像素区和子像素区的电压差，从而更好地降低色偏。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种驱动电路，其中所述驱动电路用于向显示面板输入扫描信号，所述显示面板包括n行像素；每行像素对应设置一扫描线组，所述扫描线组包括主扫描线和子扫描线；
    所述驱动电路包括：n级GOA单元组、第一时钟信号组以及第二时钟信号组，所述第一时钟信号组和所述第二时钟信号组相对设置，其中第n级GOA单元组对应第n行主扫描线和第n-k行子扫描线；所述GOA单元组包括位于对应的扫描线组两侧的两个GOA单元；
    位于所述扫描线组同一侧的第n级GOA单元分别与位于所述扫描线组同一侧的第n+k级GOA单元级联；
    位于所述扫描线组第一侧的第n级GOA单元的输出端与第n-k行子扫描线连接，位于所述扫描线组第二侧的第n级GOA单元的输出端也与所述第n-k行子扫描线连接，其中n大于等于1，k为大于等于1。
  2. 根据权利要求1所述的驱动电路，其中
    所述GOA单元包括第一级联信号输入端、级联信号输出端；
    位于所述扫描线组同一侧的第n级GOA单元的级联信号输出端与位于所述扫描线组同一侧的第n+k级GOA单元的第一级联信号输入端连接；所述第n级GOA单元的级联信号输出端与所述第n-k行子扫描线连接。
  3. 根据权利要求2所述的驱动电路，其中所述GOA单元还包括第二级联信号输入端、扫描信号输出端；
    所述第n级GOA单元的扫描信号输出端与第n行主扫描线连接；
    第n级GOA单元的第一级联信号输入端与第n-2级GOA单元的级联信号输出端连接；
    第n级GOA单元的第二级联信号输入端与第n+2级GOA单元的级联信号输出端连接。
  4. 根据权利要求1所述的驱动电路，其中所述GOA单元包括扫描信号输出端，所述第n级GOA单元的扫描信号输出端与第n-2行子扫描线连接。
  5. 根据权利要求1所述的驱动电路，其中所述GOA单元包括时钟信号输入端，所述时钟信号输入端用于输入一时钟信号。
  6. 一种驱动电路，其中所述驱动电路用于向显示面板输入扫描信号，所述显示面板包括n行像素；每行像素对应设置一扫描线组，所述扫描线组包括主扫描线和子扫描线；
    所述驱动电路包括：n级GOA单元组，其中第n级GOA单元组对应第n行主扫描线和第n-k行子扫描线；所述GOA单元组包括位于对应的扫描线组两侧的两个GOA单元；
    位于所述扫描线组同一侧的第n级GOA单元分别与位于所述扫描线组同一侧的第n+k级GOA单元级联；
    位于所述扫描线组第一侧的第n级GOA单元与位于所述扫描线组第二侧的第n级GOA单元电性连接，其中n大于等于1，k为大于等于1。
  7. 根据权利要求6所述的驱动电路，其中
    位于所述扫描线组第一侧的第n级GOA单元的输出端与第n-k行子扫描线连接，位于所述扫描线组第二侧的第n级GOA单元的输出端也与所述第n-k行子扫描线连接。
  8. 根据权利要求7所述的驱动电路，其中
    所述GOA单元包括第一级联信号输入端、级联信号输出端；
    位于所述扫描线组同一侧的第n级GOA单元的级联信号输出端与位于所述扫描线组同一侧的第n+k级GOA单元的第一级联信号输入端连接；所述第n级GOA单元的级联信号输出端与所述第n-k行子扫描线连接。
  9. 根据权利要求8所述的驱动电路，其中所述GOA单元还包括第二级联信号输入端、扫描信号输出端；
    所述第n级GOA单元的扫描信号输出端与第n行主扫描线连接；
    第n级GOA单元的第一级联信号输入端与第n-2级GOA单元的级联信号输出端连接；
    第n级GOA单元的第二级联信号输入端与第n+2级GOA单元的级联信号输出端连接。
  10. 根据权利要求6所述的驱动电路，其中所述GOA单元包括扫描信号输出端；
    所述第n级GOA单元的扫描信号输出端与第n-2行子扫描线连接。
  11. 根据权利要求6所述的驱动电路，其中所述驱动电路还包括第一时钟信号组和第二时钟信号组，所述第一时钟信号组和所述第二时钟信号组相对设置。
  12. 一种显示面板，其中多条扫描线组和多条数据线以及由所述扫描线组和所述数据线限定的多个像素；
    所述像素包括主像素区和子像素区，所述主像素区设置有第一充电模块和上拉模块；所述第一充电模块用于在对所述子像素区充电时，对所述主像素区进行充电；所述上拉模块用于在所述主像素区和所述子像素区充电完毕时，上拉所述主像素区的电位；
    所述子像素区设置有第二充电模块和下拉模块；所述第二充电模块用于在对所述主像素区充电时，对所述子像素区进行充电；所述下拉模块用于在所述主像素区和所述子像素区充电完毕时，下拉所述子像素区的电位。
  13. 根据权利要求12所述的显示面板，其中
    所述扫描线组包括主扫描线和子扫描线，所述第一充电模块包括第一薄膜晶体管和第一液晶电容；
    所述第一薄膜晶体管的栅极与所述主扫描线连接，所述第一薄膜晶体管的源极与所述数据线连接，所述第一薄膜晶体管的漏极连接所述第一液晶电容。
  14. 根据权利要求13所述的显示面板，其中
    所述上拉模块包括第一分享电容，所述第一分享电容的一端与所述第一薄膜晶体管的漏极连接。
  15. 根据权利要求14所述的显示面板，其中
    所述第二充电模块包括第二薄膜晶体管；所述第二薄膜晶体管的栅极与所述主扫描线连接，所述第二薄膜晶体管的源极与所述数据线连接。
  16. 根据权利要求15所述的显示面板，其中
    所述下拉模块包括第三薄膜晶体管和第二分电容，所述第三薄膜晶体管的栅极与所述子扫描线连接，所述第三薄膜晶体管的源极与所述第二薄膜晶体管的漏极连接；所述第三薄膜晶体管的漏极分别与所述第一分享电容的另一端以及所述第二分享电容的一端连接，所述第二分享电容的另一端接地。
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