WO2017101158A1 - 一种移位寄存器 - Google Patents

一种移位寄存器 Download PDF

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Publication number
WO2017101158A1
WO2017101158A1 PCT/CN2015/099677 CN2015099677W WO2017101158A1 WO 2017101158 A1 WO2017101158 A1 WO 2017101158A1 CN 2015099677 W CN2015099677 W CN 2015099677W WO 2017101158 A1 WO2017101158 A1 WO 2017101158A1
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WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
shift register
signal
clock signal
Prior art date
Application number
PCT/CN2015/099677
Other languages
English (en)
French (fr)
Inventor
张盛东
胡治晋
廖聪维
曹世杰
李长晔
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US15/023,407 priority Critical patent/US10115355B2/en
Publication of WO2017101158A1 publication Critical patent/WO2017101158A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/02—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
    • G11C19/08—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
    • G11C19/0808—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure using magnetic domain propagation
    • G11C19/0841—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure using magnetic domain propagation using electric current
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a shift register.
  • the integrated display driving circuit refers to a peripheral circuit such as a gate driving circuit and a data driving circuit of a flat panel display as a thin film transistor (TFT, Thin) Film
  • TFT thin film transistor
  • Transistor is fabricated on the display panel together with the pixel TFT.
  • the integrated display driving method can not only reduce the number of peripheral driving chips and its sealing process, reduce the cost, but also make the display
  • the outer periphery is slimmer, the module is more compact, and the mechanical and electrical reliability is enhanced.
  • the shift register is an important circuit module for implementing an integrated gate (row) driver circuit and an integrated data (column) driver circuit.
  • the shift register circuit based on amorphous silicon TFT is limited by the low mobility of amorphous silicon TFT, and the operating frequency is difficult to increase. On the other hand, the area occupied by the circuit tends to be large, so it is increasingly difficult to meet the actual situation. Need. Oxide semiconductor TFTs have become the TFT technology attracting attention in recent years due to their advantages of uniform characteristics, high mobility, good stability, and low fabrication cost.
  • the integrated shift register circuit based on oxide semiconductor (TFT) has also been obtained. Preliminary research.
  • the effect of the capacitor bootstrap is generally used to increase the driving capability of the driving tube, thereby accelerating the charging of the output load.
  • the control electrode of the driving transistor is often unable to bootstrap to a higher potential, and the rise time of the output pulse Larger, which in turn limits the increase in the operating frequency of the circuit. Especially when the temperature is high and the threshold voltage of the TFT is small, the effect will be more significant.
  • the conventional shift register when the output of the shift register is heavily loaded, the conventional shift register usually requires a large-sized pull-down tube to discharge the load, so the area of the circuit tends to be large, which is not suitable for application on a high-resolution display. .
  • the technical problem to be solved by the present invention is to provide a shift register to solve the above problems.
  • the present invention provides a shift register comprising a multi-stage shift register unit, wherein at least one stage shift register unit comprises: a driving module comprising: an input terminal connected to the first clock signal; and a control terminal for receiving the driver a control signal; a first output end for outputting a driving signal, the driving module charging and discharging the driving signal through the first clock signal according to the driving control signal; the input module is connected to the control end, and the input module is based on the second clock signal and the first a control signal output driving control signal; a low level maintaining module connected to the first output terminal for maintaining a level of the driving signal according to the first reference voltage, the third clock signal, the first clock signal, and the first control signal a low level of the second reference voltage; wherein the driving module includes a first thin film transistor and a first capacitor, the first end of the first thin film transistor is connected to the first clock signal, and the second end of the first thin film transistor is connected to the input module a third end of the first thin film transistor is configured to output a driving signal,
  • the shift register unit further includes an initialization module respectively connected to the control terminal and the second reference voltage, and the initialization module is configured to pull the driving control signal to a low level of the second reference voltage.
  • the initialization module includes a ninth thin film transistor, the first end of the ninth thin film transistor is connected to the second end of the first thin film transistor, the second end of the ninth thin film transistor is connected to the initialization pulse signal, and the third end of the ninth thin film transistor is connected.
  • the terminal is connected to the second reference voltage.
  • the driving module further includes: a second output terminal connected to the shift register unit of the next stage for providing an input signal to the shift register unit of the next stage.
  • the second output end includes a tenth thin film transistor, the first end of the tenth thin film transistor is connected to the first clock signal, the second end of the tenth thin film transistor is connected to the second end of the first thin film transistor, and the tenth thin film transistor is connected
  • the third end is connected to the shift register unit of the next stage.
  • the low level maintenance module further includes an eleventh thin film transistor, the first end of the eleventh thin film transistor is connected to the third end of the tenth thin film transistor, and the second end of the eleventh thin film transistor and the eighth thin film transistor are The second end is connected, and the third end of the eleventh thin film transistor is connected to the second reference voltage.
  • the transistor and the eleventh thin film transistor are N-type thin film transistors.
  • the present invention also provides a shift register comprising a multi-stage shift register unit, wherein at least one stage shift register unit comprises: a driving module comprising: an input terminal connected to the first clock signal; and a control terminal for receiving a driving control signal; a first output end for outputting a driving signal, the driving module charging and discharging the driving signal through the first clock signal according to the driving control signal; the input module is connected to the control end, and the input module is configured according to the second clock signal and the a control signal output driving control signal; a low level maintaining module connected to the first output terminal for maintaining a level of the driving signal according to the first reference voltage, the third clock signal, the first clock signal, and the first control signal The low level of the second reference voltage.
  • a driving module comprising: an input terminal connected to the first clock signal; and a control terminal for receiving a driving control signal; a first output end for outputting a driving signal, the driving module charging and discharging the driving signal through the first clock signal according to the driving control signal; the input module is
  • the driving module includes a first thin film transistor and a first capacitor.
  • the first end of the first thin film transistor is connected to the first clock signal, and the second end of the first thin film transistor is connected to the input module, and the third end of the first thin film transistor
  • one end of the first capacitor is connected to the second end of the first thin film transistor, and the other end of the first capacitor is connected to the third end of the first thin film transistor.
  • the input module includes: a second thin film transistor and a third thin film transistor, the first end of the second thin film transistor is connected to the first end of the third thin film transistor, and the second end of the second thin film transistor is connected to the second clock signal, The third end of the second thin film transistor and the third end of the third thin film transistor are connected to the second end of the first thin film transistor, and the first end and the second end of the third thin film transistor are connected to the first control signal.
  • the low level maintenance module includes: a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, and a second capacitor, the first end and the fifth thin film of the fourth thin film transistor
  • the first end of the transistor is connected to the first reference voltage
  • the second end of the fourth thin film transistor is connected to the first end of the sixth thin film transistor
  • the second end of the fifth thin film transistor is connected
  • the second end of the fifth thin film transistor is connected to the third clock signal
  • the first end of the sixth thin film transistor is connected to the first clock signal through the second capacitor
  • the second end of the sixth thin film transistor The second end of the terminal and the seventh thin film transistor are connected to the first control signal
  • the third end of the sixth thin film transistor, the third end of the seventh thin film transistor, and the third end of the eighth thin film transistor are connected to the second reference voltage
  • the first end of the seventh thin film transistor is connected
  • the shift register unit further includes an initialization module respectively connected to the control terminal and the second reference voltage, and the initialization module is configured to pull the driving control signal to a low level of the second reference voltage.
  • the initialization module includes a ninth thin film transistor, the first end of the ninth thin film transistor is connected to the second end of the first thin film transistor, the second end of the ninth thin film transistor is connected to the initialization pulse signal, and the third end of the ninth thin film transistor is connected.
  • the terminal is connected to the second reference voltage.
  • the driving module further includes: a second output terminal connected to the shift register unit of the next stage for providing an input signal to the shift register unit of the next stage.
  • the second output end includes a tenth thin film transistor, the first end of the tenth thin film transistor is connected to the first clock signal, the second end of the tenth thin film transistor is connected to the second end of the first thin film transistor, and the tenth thin film transistor is connected
  • the third end is connected to the shift register unit of the next stage.
  • the low level maintenance module further includes an eleventh thin film transistor, the first end of the eleventh thin film transistor is connected to the third end of the tenth thin film transistor, and the second end of the eleventh thin film transistor and the eighth thin film transistor are The second end is connected, and the third end of the eleventh thin film transistor is connected to the second reference voltage.
  • the transistor and the eleventh thin film transistor are N-type thin film transistors.
  • the beneficial effect of the present invention is that the shift register of the present invention comprises a multi-stage shift register unit, and each stage shift register unit comprises: a driving module, an input module and a low level maintaining module, and the driving module is controlled according to the driving.
  • the signal is charged and discharged by the first clock signal; the input module outputs a driving control signal according to the second clock signal and the first control signal; and the low level maintaining module is configured according to the first reference voltage, the third clock signal, and the first clock signal And the first control signal maintains the level of the driving signal at a low level of the second reference voltage; when the first clock signal charges the driving signal, the low level maintaining module is disconnected from the first output end, avoiding the first Leakage of an output terminal reduces the rise time of the drive signal; when the first clock signal discharges the drive signal, the low level maintenance module is connected to the first output end, and the drive signal is rapidly discharged through the first clock signal and the low level maintenance module
  • the circuit area of the shift register is small.
  • FIG. 1 is a circuit diagram of a shift register unit of a first embodiment of the present invention
  • Figure 2 is a timing diagram of the shift register unit of Figure 1;
  • Figure 3 is a circuit diagram of a shift register unit of a second embodiment of the present invention.
  • Figure 4 is a timing diagram of the shift register unit of Figure 3;
  • Figure 5 is a circuit diagram of a shift register unit of a third embodiment of the present invention.
  • Figure 6 is a timing diagram of the shift register unit of Figure 5;
  • FIG. 7 is a schematic structural diagram of a shift register according to a first embodiment of the present invention.
  • Figure 8 is a timing diagram of the shift register of Figure 7;
  • Figure 9 is a block diagram showing the structure of a shift register in accordance with a second embodiment of the present invention.
  • FIG. 1 is a circuit diagram of a shift register unit of a first embodiment of the present invention.
  • the shift register unit disclosed in this embodiment is applied to a shift register including a multi-stage shift register unit.
  • at least one stage shift register unit includes a driving module 11 , an input module 12 , and a low level maintaining module 13 .
  • the driving module 11 includes an input end 111, a control end 112, and a first output end 113.
  • the input end 111 is connected to the first clock signal Vc.
  • the control end 112 is connected to the input module 12 for receiving the driving control signal Qn.
  • the output terminal 113 is connected to the load for outputting the driving signal Vout1, wherein the driving module 11 charges and discharges the driving signal Vout1 through the first clock signal Vc according to the driving control signal Qn.
  • the input module 12 outputs a driving control signal Qn according to the second clock signal Vb and the first control signal V11; the low level maintaining module 13 is connected to the first output terminal 113 for passing the first clock according to the driving control signal Qn at the driving module 11
  • the signal Vc discharges the driving signal Vout1
  • the level of the driving signal Vout1 is maintained at a low level of the second reference voltage Vss according to the first reference voltage Vdd, the third clock signal Va, the first clock signal Vc, and the first control signal V11. Level.
  • the driving circuit 11 includes a first thin film transistor T1 and a first capacitor C1.
  • the first end of the first thin film transistor T1 is connected to the first clock signal Vc, and the second end of the first thin film transistor T1 is connected to the input module 12.
  • the third end of the first thin film transistor T1 is for outputting the driving signal Vout1, one end of the first capacitor C1 is connected to the second end of the first thin film transistor T1, and the other end of the first capacitor C1 is opposite to the first thin film transistor T2.
  • the first end of the first thin film transistor T1 is the control end 112, and the third end of the first thin film transistor T1 is the first output end 113.
  • the input module 12 includes a second thin film transistor T2 and a third thin film transistor T3.
  • the first end of the second thin film transistor T2 is connected to the first end of the third thin film transistor T3, and the second end of the second thin film transistor T2 is connected to the second clock.
  • the signal Vb is connected, the third end of the second thin film transistor T2 and the third end of the third thin film transistor T3 are connected to the second end of the first thin film transistor T1, and the first end and the second end of the third thin film transistor T3 are connected
  • a control signal V11 is connected.
  • the third end of the second thin film transistor T2 and the third end of the third thin film transistor T3 output a driving control signal Qn.
  • the low level maintenance module 13 includes a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7, an eighth thin film transistor T8, and a second capacitor C2, and the first of the fourth thin film transistor T4
  • the first end of the terminal and the fifth thin film transistor T5 are connected to the first reference voltage Vdd
  • the second end of the fourth thin film transistor T4 is connected to the first end of the sixth thin film transistor T6, and the third end of the fourth thin film transistor T4 is
  • the third end of the fifth thin film transistor T5 is connected to the second end of the eighth thin film transistor T8, the second end of the fifth thin film transistor T5 is connected to the third clock signal Va, and the first end of the sixth thin film transistor T6 is passed through the second end.
  • the capacitor C2 is connected to the first clock signal Vc, the second end of the sixth thin film transistor T6 and the second end of the seventh thin film transistor T7 are connected to the first control signal V11, and the third end and the seventh film of the sixth thin film transistor T6 are connected.
  • the third end of the transistor T7 and the third end of the eighth thin film transistor T8 are connected to the second reference voltage Vss, the first end of the seventh thin film transistor T7 is connected to the second end of the eighth thin film transistor T8, and the eighth thin film transistor T8 is connected.
  • a first end connected to the third terminal of the first thin film transistor T1.
  • the first clock signal Vc, the second clock signal Vb, and the third clock signal Va are clock signals of the same period, and the high level of the first clock signal Vc, the second clock signal Vb, and the third clock signal Va is VH.
  • the low level of the first clock signal Vc, the second clock signal Vb, and the third clock signal Va is VL, and the third clock signal Va is advanced by 1/4 clock cycle than the second clock signal Vb, and the third clock signal Va is
  • the first clock signal Vc is advanced by 1/2 clock cycle; the first reference voltage Vdd is high and the voltage is VH; the second reference voltage Vss is low and the voltage is VL.
  • the shift register unit is in the precharge phase
  • the first control signal V11 and the second clock signal Vb simultaneously rise to a high level VH
  • the second thin film transistor T2 and the third thin film transistor T3 Turning on, the first control signal V11 charges the driving control signal Qn such that the driving control signal Qn is charged to VH-Vth3, and Vth3 is the voltage threshold of the third thin film transistor T3, that is, the voltage VQ of the control terminal 112 is VH-Vth3.
  • the driving control signal Qn is VH-Vth3
  • the first thin film transistor T1 is turned on, and at this time, the first clock signal Vc is at a low level VL, and the first clock signal Vc pulls down the driving signal Vout1 outputted from the first output terminal 113 to The low level VL, that is, the driving module 11 discharges the driving signal Vout1 through the first clock signal Vc according to the driving control signal Qn.
  • the sixth thin film transistor T6 and the seventh thin film transistor T7 are turned on, the second end of the fourth thin film transistor T4 is at a low level VL, and the fourth thin film transistor T4 is turned off; the third clock signal Va is at a high level VH, and a fifth
  • the thin film transistor T5 is turned on, and the potential of the second end of the eighth thin film transistor T8 (ie, the control terminal Qb of the low level sustaining module 13) is pulled down by the second reference voltage Vss to a low level close to the low level VL.
  • the eighth thin film transistor T8 is turned off.
  • the shift register unit is in the pull-up phase, the first control signal V11 and the second clock signal Vb are maintained at the high level VH, the drive control signal Qn is VH-Vth3, and the first thin film transistor T1 is turned on;
  • a clock signal Vc rises from a low level VL to a high level VH, and pulls the driving signal Vout1 outputted by the first output terminal 113 to a high level VH through the first thin film transistor T1, that is, the driving module 11 according to the driving control signal Qn
  • the driving signal Vout1 is charged by the first clock signal Vc, and the voltage of the driving signal Vout1 rises rapidly.
  • the third clock signal Va is lowered from the high level VH to the low level VL, the fifth thin film transistor T5 is turned off; the sixth thin film transistor T6 and the seventh thin film transistor T7 are turned on, and the fourth thin film transistor T4 is turned off, the eighth thin film
  • the potential of the second end of the transistor T8 ie, the control terminal Qb of the low level sustaining module 13
  • the eighth thin film transistor T8 is in a completely open state, and the first output end 113 is reduced.
  • the output of the drive signal Vout1 is leaked, and the rise time of the drive signal Vout1 outputted by the first output terminal 113 is reduced.
  • the first control signal V11 and the second clock signal Vb simultaneously drop to the low level VL, and the second thin film transistor T2 and the third thin film transistor T3 are turned off to make the control terminal 112 (first The second end of the thin film transistor T1 is in a floating state, and the voltage VQ of the control terminal 112 rises as the voltage of the driving signal Vout1 rises, and rises to a voltage of VH+Vth1, and Vth1 is a voltage threshold of the first thin film transistor T1. , is the bootstrap effect; at this time, the voltage of the driving signal Vout1 can rise to VH quickly.
  • the shift register unit is in the pull-down phase, the first control signal V11 and the second clock signal Vb are at a low level VL, the second thin film transistor T2 and the third thin film transistor T3 are turned off, and the first thin film transistor T1 is turned on.
  • the first clock signal Vc falls from the high level VH to the low level VL
  • the third clock signal Va rises from the low level VL to the high level VH
  • the first clock signal Vc outputs the first output end 113.
  • the driving signal Vout1 is pulled down to the low level VL, that is, the driving module 11 discharges the driving signal Vout1 through the first clock signal Vc according to the driving control signal Qn, and the driving signal Vout1 rapidly falls to the low level VL. Due to the bootstrap effect of the first capacitor C1, the voltage VQ of the control terminal 112 drops to VH-Vth3.
  • the first control signal V11 and the second clock signal Vb are at a low level VL, the sixth thin film transistor T6 and the seventh thin film transistor T7 are turned off; the third clock signal Vc rises to a high level VH, and the fifth thin film transistor T5 is turned on.
  • the first reference voltage Vdd charges the second end of the eighth thin film transistor T8, so that the second end of the eighth thin film transistor T8 is quickly charged to the high level VH, and the eighth thin film transistor T8 is turned on, so the driving signal Vout1 can also be
  • the discharge is performed by the eighth thin film transistor T8, and the time during which the drive signal Vout1 falls is further reduced.
  • the driving signal Vout1 outputted from the first output terminal 113 of the shift register unit of the present embodiment is rapidly discharged through the first thin film transistor T1 and the eighth thin film transistor T8, and the pull-down transistor is not required to be specially set, so the shift register unit has a small Circuit area.
  • the shift register unit After the shift register unit is in the pull-down phase, the shift register unit completely outputs a pulse signal as shown by Vout1 in FIG.
  • the drive signal Vout1 should be maintained at a low level VL, but there is a parasitic capacitance between the third end (drain) and the second end (gate) of the first thin film transistor T1, and the first clock signal Vc is low.
  • the level VL transitions to the high level VH, a coupling voltage is generated at the control terminal 112 due to the clock feedthrough effect.
  • the coupling voltage is too large, the first thin film transistor T1 may be turned on, the first clock signal. Vc erroneously charges the drive signal Vout1, and the drive signal Vout1 cannot be maintained at the low level VL.
  • the sixth thin film transistor T6 and the seventh thin film transistor T7 are both kept off.
  • the first clock signal Vc is at the high level VH
  • the first clock signal Vc is coupled to the high level through the second capacitor C2.
  • the first reference voltage Vdd charges the second end of the eighth thin film transistor T8.
  • the third clock signal Va is at the high level VH
  • the fifth thin film transistor T5 is turned on, and the first reference voltage Vdd charges the second end of the eighth thin film transistor T8, thereby implementing the fourth thin film transistor T4 and the fifth thin film.
  • the transistor T5 is alternately turned on to maintain the second end of the eighth thin film transistor T8 at a high level VH.
  • the shift register unit is in the low level sustain phase, and the eighth thin film transistor T8 is turned on to maintain the drive signal Vout1 at the low level VL.
  • the first thin film transistor T1 is periodically turned on when the third clock signal Va is at a high level, thereby pulling the first control signal V11 to a low level.
  • VL can effectively suppress the clock feedthrough effect of the control terminal 112.
  • the present invention also provides a shift register unit of the second embodiment, which is different from the shift register unit disclosed in the first embodiment in that, as shown in FIG. 3, the shift register unit of the present embodiment further includes initialization.
  • the module 34, the initialization module 34 is connected to the control terminal 312 and the second reference voltage Vss, respectively, and the initialization module 34 is used to pull the driving control signal Qn to the low level VL of the second reference voltage Vss.
  • the initialization module 34 includes a ninth thin film transistor T9.
  • the first end of the ninth thin film transistor T9 is connected to the second end of the first thin film transistor T1, and the second end of the ninth thin film transistor T9 is connected to the initialization pulse signal Vr.
  • the third end of the transistor T9 is connected to the second reference voltage Vss.
  • the high level VH of the initialization pulse signal Vr is ahead of the first control signal V11 by at least one pulse width, and the rising edge of the initialization pulse signal Vr is ahead of the first clock signal Vc, A rising edge of the first one of the second clock signal Vb and the third clock signal Va.
  • the initialization pulse signal Vr is at the high level VH, and the ninth thin film transistor T9 is turned on.
  • the second reference voltage Vss pulls the drive control signal Qn of the control terminal 312 to a low level VL.
  • the shift register unit disclosed in the embodiment can better suppress the clock feedthrough effect of the control terminal 312 to make the operation of the shift register unit more stable.
  • the present invention further provides a shift register unit of the third embodiment, which is different from the shift register unit disclosed in the second embodiment in that the shift register unit disclosed in the embodiment is applied to a load or a temperature.
  • the drive module 51 further includes a second output 514 coupled to the shift register unit of the next stage for providing an input signal to the shift register unit of the next stage.
  • the second output terminal 514 includes a tenth thin film transistor T10.
  • the first end of the tenth thin film transistor T10 is connected to the first clock signal Vc, and the second end of the tenth thin film transistor T10 is connected to the second end of the first thin film transistor T1.
  • the third end of the tenth thin film transistor T10 is connected to the shift register unit of the next stage.
  • the low level maintaining module 53 further includes an eleventh thin film transistor T11, the first end of the eleventh thin film transistor T11 is connected to the third end of the tenth thin film transistor T10, and the second end and the eighth end of the eleventh thin film transistor T11 The second end of the thin film transistor T8 is connected, and the third end of the eleventh thin film transistor T11 is connected to the second reference voltage Vss.
  • the shift register unit is in the pull-up phase, the tenth thin film transistor T10 is turned on, and the first clock signal Vc is output to the second output terminal 514.
  • the drive signal Vout2 is charged.
  • the shift register unit is in the pull-down phase, the tenth thin film transistor T10 and the eleventh thin film transistor T11 are simultaneously turned on, and the driving signal Vout2 outputted by the second output terminal 514 passes through the tenth thin film transistor T10 and the The eleven thin film transistor T11 is discharged.
  • the shift register unit After time t4, the shift register unit is in the low level sustain phase, the eleventh thin film transistor T11 is turned on, and the second reference voltage Vss maintains the drive signal Vout2 output from the second output terminal 514 at a low level.
  • the driving signal Vout1 outputted by the third terminal of the first thin film transistor T1 is the same as the timing chart of the driving signal Vout2 output by the second output terminal 514. Since the load of the second output terminal 514 is smaller than the load of the first output terminal 513, the time during which the drive signal Vout2 rises is less than the time when the drive signal Vout1 rises.
  • the second output terminal 514 is configured to provide an input signal to the shift register unit of the next stage, and the driving control signal Qn of the control terminal 512 can be quickly charged to VH-Vth3 during the precharge phase, so that the first thin film transistor T1 has a more
  • the driving capability of the shift register unit disclosed in this embodiment is suitable for the load of the first output terminal 513 being large or the temperature is low.
  • the initialization module 54 can be completely removed by one of ordinary skill in the art.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, the seventh thin film transistor T7, and the eighth thin film transistor T8, ninth thin film transistor T9, tenth thin film transistor T10, and eleventh thin film transistor T11 are N-type thin film transistors.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 can be completely used by those skilled in the art.
  • the seventh thin film transistor T7, the eighth thin film transistor T8, the ninth thin film transistor T9, the tenth thin film transistor T10, and the eleventh thin film transistor T11 are provided as P-type thin film transistors.
  • the present invention further provides a shift register of the first embodiment.
  • the mobile bit register disclosed in this embodiment includes an N-stage cascaded shift register unit 70, a first clock line CK1, and a second clock line CK2. a third clock line CK3, a fourth clock line CK4, a common ground line 701, and a start signal ST, wherein the first stage shift register unit 70 and the second shift register unit 70 are both disclosed in the first embodiment.
  • the shift register unit, the third stage shift register unit 70 to the Nth stage shift register unit 70 are all the shift register units disclosed in the second embodiment, and are not described herein again.
  • the first clock signal Vc of the first stage shift register unit 70 is connected to the first clock line CK1, and the second clock signal Vb of the first stage shift register unit 70 is connected to the fourth clock line CK4, the first stage shift
  • the third clock signal Va of the bit register unit 70 is connected to the third clock line CK3, and the first control signal V11 of the first stage shift register unit 70 is connected to the start signal ST.
  • the second reference voltage Vss of the N-stage cascaded shift register unit 70 is connected to the common ground line 701, and the common ground line 701 is used to provide the low level VL for the second reference voltage Vss.
  • the signals output from the first output terminal 113 of the first stage shift register unit 70 to the Nth stage shift register unit 70 are Vg1 - Vgn.
  • the first control signals V11 of the second stage shift register unit 70 to the Nth stage shift register unit 70 are all connected to the first output terminal 113 of the shift register unit 70 of the previous stage, for example, the nth stage shift register unit
  • the first control signal V11 of 70 is connected to the first output terminal 113 of the n-1th stage shift register unit 70.
  • the first clock signal Vc of the second stage shift register unit 70 is connected to the second clock line CK2, and the second clock signal Vb of the second stage shift register unit 70 is connected to the first clock line CK1, and the second stage shift register
  • the third clock signal Va of the unit 70 is connected to the fourth clock line CK4.
  • the first clock signal Vc of the third stage shift register unit 70 is connected to the third clock line CK3, and the second clock signal Vb of the third stage shift register unit 70 is connected to the second clock line CK2, and the third stage shift register
  • the third clock signal Va of the unit 70 is connected to the first clock line CK1, and the initialization pulse signal Vr of the third stage shift register unit 70 is connected to the start signal ST.
  • the first clock signal Vc of the fourth stage shift register unit 70 is connected to the fourth clock line CK4, and the second clock signal Vb of the fourth stage shift register unit 70 is connected to the third clock line CK3, and the fourth stage shift register
  • the third clock signal Va of the unit 70 is connected to the second clock line CK2.
  • the initialization pulse signal Vr of the fourth stage shift register unit 70 is connected to the start signal ST.
  • the first clock signal Vc of the N-1th shift register unit 70 is connected to the third clock line CK3, and the second clock signal Vb of the N-1th shift register unit 70 is connected to the second clock line CK2, the Nth The third clock signal Va of the -1 shift register unit 70 is connected to the first clock line CK1.
  • the initialization pulse signal Vr of the N-1th stage shift register unit 70 is connected to the start signal ST.
  • the first clock signal Vc of the Nth stage shift register unit 70 is connected to the fourth clock line CK4, and the second clock signal Vb of the Nth stage shift register unit 70 is connected to the third clock line CK3, the Nth stage shift register
  • the third clock signal Va of the unit 70 is connected to the second clock line CK2.
  • the initialization pulse signal Vr of the Nth stage shift register unit 70 is connected to the start signal ST.
  • the timing chart of the mobile bit register disclosed in this embodiment is as shown in FIG. 8.
  • the first frame it is triggered by the start signal ST, so that the first stage shift register unit 70 to the Nth stage shift register unit 70 are sequentially
  • the output signals Vg1 - Vgn; in the second frame, are again triggered by the start signal ST so that the first stage shift register unit 70 to the Nth stage shift register unit 70 sequentially output the signals Vg1 - Vgn.
  • the present invention further provides a shift register of the second embodiment, which is different from the shift register disclosed in the first embodiment in that: as shown in FIG. 9, the first shift of the shift register disclosed in this embodiment
  • the bit register unit 90 to the Nth stage shift register unit 90 are the shift register units disclosed in the third embodiment, and are not described herein again.
  • the timing diagram of the mobile bit register disclosed in this embodiment is shown in FIG.
  • the shift register of the present invention includes a multi-stage shift register unit, each stage shift register unit includes: a driving module, an input module, and a low level maintaining module, and the driving module passes the first clock signal according to the driving control signal. And charging and discharging the driving signal; the input module outputs a driving control signal according to the second clock signal and the first control signal; and the low level maintaining module according to the first reference voltage, the third clock signal, the first clock signal, and the first control signal
  • the level of the driving signal is maintained at a low level of the second reference voltage; when the first clock signal charges the driving signal, the low level maintaining module is disconnected from the first output terminal to avoid leakage of the first output terminal, reducing
  • the driving signal rise time when the first clock signal discharges the driving signal, the low level maintaining module is connected to the first output end, and the driving signal is quickly discharged through the first clock signal and the low level maintaining module, and the circuit of the shift register The area is small.

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Abstract

一种移位寄存器，包括多级移位寄存器单元（70），每级移位寄存器单元（70）包括：驱动模块（11），根据驱动控制信号通过第一时钟信号对驱动信号进行充放电；输入模块（12），根据第二时钟信号和第一控制信号输出驱动控制信号；低电平维持模块（13），用于根据第一参考电压、第三时钟信号、第一时钟信号以及第一控制信号将驱动信号的电平维持在第二参考电压的低电平。通过以上方式，能够避免第一输出端（113）漏电，减少驱动信号上升时间，并且移位寄存器的电路面积小。

Description

一种移位寄存器
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种移位寄存器。
【背景技术】
平板显示器（FPD，Flat-Panel-Display）已成为显示技术的主流，近年来正向高帧频、高分辨率、更窄边框的方向发展。集成显示驱动电路是指将平板显示器的栅极驱动电路和数据驱动电路等外围电路以薄膜晶体管（TFT，Thin Film Transistor）的形式与像素TFT一起制作于显示面板上，与传统的IC驱动方式相比，采用集成显示驱动的方法不仅可以减少外围驱动芯片的数量及其压封程序、降低成本，而且能使得显示器外围更加纤薄，模组更加紧凑，机械和电学可靠性得以增强。
在集成显示驱动电路中，移位寄存器是实现集成栅极(行)驱动电路和集成数据(列)驱动电路的重要电路模块。基于非晶硅TFT的移位寄存器电路，一方面受限于非晶硅TFT的低迁移率，工作频率很难提升，另一方面电路所占用的面积往往较大，因此越来越难满足实际的需要。氧化物半导体TFT由于具有特性均匀、迁移率高、稳定性较好、制作成本低等优势，成为近年来备受关注的TFT技术，基于氧化物半导体（TFT）的集成移位寄存器电路也得到了初步的研究。
在现有的移位寄存器电路结构中，通常采用电容自举的效应增大驱动管的驱动能力，从而加快对输出负载充电的速度。但是，传统的移位寄存器电路中，一方面，由于电路内部存在漏电或者驱动晶体管的控制极电容较大的原因，驱动晶体管的控制极往往不能自举到较高的电位，输出脉冲的上升时间较大，进而限制了电路的工作频率的提高。尤其是当温度较高、TFT的阈值电压较小时，这种影响将会更加显著。另一方面，当移位寄存器的输出端负载较大时，传统的移位寄存器通常需要尺寸较大的下拉管对负载放电，因此电路的面积往往较大，不利于在高分辨率显示器上应用。
【发明内容】
本发明主要解决的技术问题是提供一种移位寄存器，以解决上述问题。
本发明提供一种移位寄存器，其包括多级移位寄存器单元，其中至少一级移位寄存器单元包括：驱动模块，包括：输入端，与第一时钟信号连接；控制端，用于接收驱动控制信号；第一输出端，用于输出驱动信号，驱动模块根据驱动控制信号通过第一时钟信号对驱动信号进行充放电；输入模块，与控制端连接，输入模块根据第二时钟信号和第一控制信号输出驱动控制信号；低电平维持模块，与第一输出端连接，用于根据第一参考电压、第三时钟信号、第一时钟信号以及第一控制信号将驱动信号的电平维持在第二参考电压的低电平；其中，驱动模块包括第一薄膜晶体管和第一电容，第一薄膜晶体管的第一端与第一时钟信号连接，第一薄膜晶体管的第二端与输入模块连接，第一薄膜晶体管的第三端用于输出驱动信号，第一电容的一端与第一薄膜晶体管的第二端连接，第一电容的另一端与第一薄膜晶体管的第三端连接；输入模块包括：第二薄膜晶体管以及第三薄膜晶体管，第二薄膜晶体管的第一端与第三薄膜晶体管的第一端连接，第二薄膜晶体管的第二端与第二时钟信号连接，第二薄膜晶体管的第三端和第三薄膜晶体管的第三端与第一薄膜晶体管的第二端连接，第三薄膜晶体管的第一端和第二端与第一控制信号连接；低电平维持模块包括：第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第二电容，第四薄膜晶体管的第一端和第五薄膜晶体管的第一端与第一参考电压连接，第四薄膜晶体管的第二端与第六薄膜晶体管的第一端连接，第四薄膜晶体管的第三端和第五薄膜晶体管的第三端与第八薄膜晶体管的第二端连接，第五薄膜晶体管的第二端与第三时钟信号连接，第六薄膜晶体管的第一端通过第二电容与第一时钟信号连接，第六薄膜晶体管的第二端和第七薄膜晶体管的第二端与第一控制信号连接，第六薄膜晶体管的第三端、第七薄膜晶体管的第三端以及第八薄膜晶体管的第三端与第二参考电压连接，第七薄膜晶体管的第一端与第八薄膜晶体管的第二端连接，第八薄膜晶体管的第一端与第一薄膜晶体管的第三端连接。
其中，移位寄存器单元进一步包括初始化模块，分别与控制端和第二参考电压连接，初始化模块用于将驱动控制信号下拉至第二参考电压的低电平。
其中，初始化模块包括第九薄膜晶体管，第九薄膜晶体管的第一端与第一薄膜晶体管的第二端连接，第九薄膜晶体管的第二端与初始化脉冲信号连接，第九薄膜晶体管的第三端与第二参考电压连接。
其中，驱动模块进一步包括：第二输出端，与下一级的移位寄存器单元连接，用于为下一级的移位寄存器单元提供输入信号。
其中，第二输出端包括第十薄膜晶体管，第十薄膜晶体管的第一端与第一时钟信号连接，第十薄膜晶体管的第二端与第一薄膜晶体管的第二端连接，第十薄膜晶体管的第三端与下一级的移位寄存器单元连接。
其中，低电平维持模块进一步包括第十一薄膜晶体管，第十一薄膜晶体管的第一端与第十薄膜晶体管的第三端连接，第十一薄膜晶体管的第二端与第八薄膜晶体管的第二端连接，第十一薄膜晶体管的第三端与第二参考电压连接。
其中，第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管以及第十一薄膜晶体管为N型薄膜晶体管。
本发明还提供一种移位寄存器，其包括多级移位寄存器单元，其中至少一级移位寄存器单元包括：驱动模块，包括：输入端，与第一时钟信号连接；控制端，用于接收驱动控制信号；第一输出端，用于输出驱动信号，驱动模块根据驱动控制信号通过第一时钟信号对驱动信号进行充放电；输入模块，与控制端连接，输入模块根据第二时钟信号和第一控制信号输出驱动控制信号；低电平维持模块，与第一输出端连接，用于根据第一参考电压、第三时钟信号、第一时钟信号以及第一控制信号将驱动信号的电平维持在第二参考电压的低电平。
其中，驱动模块包括第一薄膜晶体管和第一电容，第一薄膜晶体管的第一端与第一时钟信号连接，第一薄膜晶体管的第二端与输入模块连接，第一薄膜晶体管的第三端用于输出驱动信号，第一电容的一端与第一薄膜晶体管的第二端连接，第一电容的另一端与第一薄膜晶体管的第三端连接。
其中，输入模块包括：第二薄膜晶体管以及第三薄膜晶体管，第二薄膜晶体管的第一端与第三薄膜晶体管的第一端连接，第二薄膜晶体管的第二端与第二时钟信号连接，第二薄膜晶体管的第三端和第三薄膜晶体管的第三端与第一薄膜晶体管的第二端连接，第三薄膜晶体管的第一端和第二端与第一控制信号连接。
其中，低电平维持模块包括：第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第二电容，第四薄膜晶体管的第一端和第五薄膜晶体管的第一端与第一参考电压连接，第四薄膜晶体管的第二端与第六薄膜晶体管的第一端连接，第四薄膜晶体管的第三端和第五薄膜晶体管的第三端与第八薄膜晶体管的第二端连接，第五薄膜晶体管的第二端与第三时钟信号连接，第六薄膜晶体管的第一端通过第二电容与第一时钟信号连接，第六薄膜晶体管的第二端和第七薄膜晶体管的第二端与第一控制信号连接，第六薄膜晶体管的第三端、第七薄膜晶体管的第三端以及第八薄膜晶体管的第三端与第二参考电压连接，第七薄膜晶体管的第一端与第八薄膜晶体管的第二端连接，第八薄膜晶体管的第一端与第一薄膜晶体管的第三端连接。
其中，移位寄存器单元进一步包括初始化模块，分别与控制端和第二参考电压连接，初始化模块用于将驱动控制信号下拉至第二参考电压的低电平。
其中，初始化模块包括第九薄膜晶体管，第九薄膜晶体管的第一端与第一薄膜晶体管的第二端连接，第九薄膜晶体管的第二端与初始化脉冲信号连接，第九薄膜晶体管的第三端与第二参考电压连接。
其中，驱动模块进一步包括：第二输出端，与下一级的移位寄存器单元连接，用于为下一级的移位寄存器单元提供输入信号。
其中，第二输出端包括第十薄膜晶体管，第十薄膜晶体管的第一端与第一时钟信号连接，第十薄膜晶体管的第二端与第一薄膜晶体管的第二端连接，第十薄膜晶体管的第三端与下一级的移位寄存器单元连接。
其中，低电平维持模块进一步包括第十一薄膜晶体管，第十一薄膜晶体管的第一端与第十薄膜晶体管的第三端连接，第十一薄膜晶体管的第二端与第八薄膜晶体管的第二端连接，第十一薄膜晶体管的第三端与第二参考电压连接。
其中，第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管以及第十一薄膜晶体管为N型薄膜晶体管。
通过上述方案，本发明的有益效果是：本发明的移位寄存器包括多级移位寄存器单元，每级移位寄存器单元包括：驱动模块、输入模块以及低电平维持模块，驱动模块根据驱动控制信号通过第一时钟信号对驱动信号进行充放电；输入模块根据第二时钟信号和第一控制信号输出驱动控制信号；低电平维持模块根据第一参考电压、第三时钟信号、第一时钟信号以及第一控制信号将驱动信号的电平维持在第二参考电压的低电平；在第一时钟信号对驱动信号进行充电时，低电平维持模块断开与第一输出端连接，避免第一输出端漏电，减少驱动信号上升时间；在第一时钟信号对驱动信号进行放电时，低电平维持模块与第一输出端连接，驱动信号通过第一时钟信号和低电平维持模块快速放电，移位寄存器的电路面积小。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本发明第一实施例的移位寄存器单元的电路图；
图2是图1中移位寄存器单元的时序图；
图3是本发明第二实施例的移位寄存器单元的电路图；
图4是图3中移位寄存器单元的时序图；
图5是本发明第三实施例的移位寄存器单元的电路图；
图6是图5中移位寄存器单元的时序图；
图7是本发明第一实施例的移位寄存器的结构示意图；
图8是图7中移位寄存器的时序图；
图9是本发明第二实施例的移位寄存器的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1所示，图1是本发明第一实施例的移位寄存器单元的电路图。本实施例所揭示的移位寄存器单元应用于移位寄存器，移位寄存器包括多级移位寄存器单元。如图1所示，其中至少一级移位寄存器单元包括：驱动模块11、输入模块12以及低电平维持模块13。
其中，驱动模块11包括输入端111、控制端112以及第一输出端113，输入端111与第一时钟信号Vc连接；控制端112与输入模块12连接，用于接收驱动控制信号Qn；第一输出端113连接负载，用于输出驱动信号Vout1，其中驱动模块11根据驱动控制信号Qn通过第一时钟信号Vc对驱动信号Vout1进行充放电。输入模块12根据第二时钟信号Vb和第一控制信号V11输出驱动控制信号Qn；低电平维持模块13与第一输出端113连接，用于在驱动模块11根据驱动控制信号Qn通过第一时钟信号Vc对驱动信号Vout1进行放电时，根据第一参考电压Vdd、第三时钟信号Va、第一时钟信号Vc以及第一控制信号V11将驱动信号Vout1的电平维持在第二参考电压Vss的低电平。
具体而言，驱动电路11包括第一薄膜晶体管T1和第一电容C1，第一薄膜晶体管T1的第一端与第一时钟信号Vc连接，第一薄膜晶体管T1的第二端与输入模块12连接，第一薄膜晶体管T1的第三端用于输出驱动信号Vout1，第一电容C1的一端与第一薄膜晶体管T1的第二端连接，第一电容C1的另一端与第一薄膜晶体管T2的第三端连接。其中，第一薄膜晶体管T1的第一端为输入端111，第一薄膜晶体管T1的第二端为控制端112，第一薄膜晶体管T1的第三端为第一输出端113。
输入模块12包括第二薄膜晶体管T2以及第三薄膜晶体管T3，第二薄膜晶体管T2的第一端与第三薄膜晶体管T3的第一端连接，第二薄膜晶体管T2的第二端与第二时钟信号Vb连接，第二薄膜晶体管T2的第三端和第三薄膜晶体管T3的第三端与第一薄膜晶体管T1的第二端连接，第三薄膜晶体管T3的第一端和第二端与第一控制信号V11连接。其中，第二薄膜晶体管T2的第三端和第三薄膜晶体管T3的第三端输出驱动控制信号Qn。
低电平维持模块13包括第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8以及第二电容C2，第四薄膜晶体管T4的第一端和第五薄膜晶体管T5的第一端与第一参考电压Vdd连接，第四薄膜晶体管T4的第二端与第六薄膜晶体管T6的第一端连接，第四薄膜晶体管T4的第三端和第五薄膜晶体管T5的第三端与第八薄膜晶体管T8的第二端连接，第五薄膜晶体管T5的第二端与第三时钟信号Va连接，第六薄膜晶体管T6的第一端通过第二电容C2与第一时钟信号Vc连接，第六薄膜晶体管T6的第二端和第七薄膜晶体管T7的第二端与第一控制信号V11连接，第六薄膜晶体管T6的第三端、第七薄膜晶体管T7的第三端以及第八薄膜晶体管T8的第三端与第二参考电压Vss连接，第七薄膜晶体管T7的第一端与第八薄膜晶体管T8的第二端连接，第八薄膜晶体管T8的第一端与第一薄膜晶体管T1的第三端连接。
请一并参见图2所示的时序图，详细描述本实施例所揭示的移位寄存器单元的工作原理。其中，第一时钟信号Vc、第二时钟信号Vb以及第三时钟信号Va为周期相同的时钟信号，第一时钟信号Vc、第二时钟信号Vb以及第三时钟信号Va的高电平为VH，第一时钟信号Vc、第二时钟信号Vb以及第三时钟信号Va的低电平为VL，并且第三时钟信号Va比第二时钟信号Vb超前1/4个时钟周期，第三时钟信号Va比第一时钟信号Vc超前1/2个时钟周期；第一参考电压Vdd为高电位，电压为VH；第二参考电压Vss为低电位，电压为VL。
如图2所示，在时刻t1时，移位寄存器单元处于预充阶段，第一控制信号V11和第二时钟信号Vb同时上升到高电平VH，第二薄膜晶体管T2和第三薄膜晶体管T3导通，第一控制信号V11对驱动控制信号Qn进行充电，使得驱动控制信号Qn充电至VH-Vth3，Vth3为第三薄膜晶体管T3的电压阈值，即控制端112的电压VQ为VH-Vth3。在驱动控制信号Qn为VH-Vth3时，第一薄膜晶体管T1导通，此时第一时钟信号Vc为低电平VL，第一时钟信号Vc将第一输出端113输出的驱动信号Vout1下拉至低电平VL，即驱动模块11根据驱动控制信号Qn通过第一时钟信号Vc对驱动信号Vout1进行放电。第六薄膜晶体管T6和第七薄膜晶体管T7导通，第四薄膜晶体管T4的第二端为低电平VL，第四薄膜晶体管T4断开；第三时钟信号Va为高电平VH，第五薄膜晶体管T5导通，第八薄膜晶体管T8的第二端（即低电平维持模块13的控制端Qb）的电位被第二参考电压Vss下拉至与低电平VL相接近的低电平，第八薄膜晶体管T8断开。
在时刻t2时，移位寄存器单元处于上拉阶段，第一控制信号V11和第二时钟信号Vb保持为高电平VH，驱动控制信号Qn为VH-Vth3，第一薄膜晶体管T1导通；第一时钟信号Vc由低电平VL上升为高电平VH，并通过第一薄膜晶体管T1将第一输出端113输出的驱动信号Vout1上拉至高电平VH，即驱动模块11根据驱动控制信号Qn通过第一时钟信号Vc对驱动信号Vout1进行充电，驱动信号Vout1的电压快速上升。第三时钟信号Va由高电平VH下降至低电平VL，第五薄膜晶体管T5断开；第六薄膜晶体管T6和第七薄膜晶体管T7导通，第四薄膜晶体管T4断开，第八薄膜晶体管T8的第二端（即低电平维持模块13的控制端Qb）的电位能够完全被下拉至低电平VL，即第八薄膜晶体管T8处于完全断开的状态，减少第一输出端113输出的驱动信号Vout1的漏电，并且减少第一输出端113输出的驱动信号Vout1的上升时间。
在时刻t2至时刻t3之间，第一控制信号V11和第二时钟信号Vb同时下降至低电平VL，第二薄膜晶体管T2和第三薄膜晶体管T3断开，以使控制端112（第一薄膜晶体管T1的第二端）处于浮空状态，控制端112的电压VQ随着驱动信号Vout1的电压升高而升高，升至电压为VH+Vth1，Vth1为第一薄膜晶体管T1的电压阈值，为自举效应；此时驱动信号Vout1的电压能够快速地上升至VH。
其中，控制端112的电压VQ被自举得越高，第一薄膜晶体管T1的驱动能力越强，驱动信号Vout1的电压上升时间就越短。由于电容C1、第一薄膜晶体T1的控制极电容、第二薄膜晶体管T2的寄生电容以及第三薄膜晶体管T3的寄生电容较小，并且在控制端112进行自举的过程中，第二薄膜晶体管T2和第三薄膜晶体管T3完全断开，避免第二薄膜晶体管T2和第三薄膜晶体管T3产生漏电，因此控制端112的电压能够被自举到较高的电压。
在时刻t3时，移位寄存器单元处于下拉阶段，第一控制信号V11和第二时钟信号Vb为低电平VL，第二薄膜晶体管T2和第三薄膜晶体管T3断开，第一薄膜晶体管T1导通，此时第一时钟信号Vc由高电平VH下降至低电平VL，第三时钟信号Va由低电平VL上升至高电平VH，第一时钟信号Vc将第一输出端113输出的驱动信号Vout1下拉至低电平VL，即驱动模块11根据驱动控制信号Qn通过第一时钟信号Vc对驱动信号Vout1进行放电，驱动信号Vout1快速下降至低电平VL。由于第一电容C1的自举效应，控制端112的电压VQ下降至VH-Vth3。
第一控制信号V11和第二时钟信号Vb为低电平VL，第六薄膜晶体管T6和第七薄膜晶体管T7断开；第三时钟信号Vc上升至高电平VH，第五薄膜晶体管T5导通，第一参考电压Vdd对第八薄膜晶体管T8的第二端进行充电，以使第八薄膜晶体管T8的第二端快速充电至高电平VH，第八薄膜晶体管T8导通，因此驱动信号Vout1还可以通过第八薄膜晶体管T8进行放电，进一步减少驱动信号Vout1下降的时间。
在本实施例移位寄存器单元的第一输出端113输出的驱动信号Vout1通过第一薄膜晶体管T1和第八薄膜晶体管T8进行快速放电，无需专门设置下拉晶体管，因此该移位寄存器单元具有较小的电路面积。
移位寄存器单元在下拉阶段之后，移位寄存器单元完整地输出一个脉冲信号，如图2中的Vout1所示。理论上，驱动信号Vout1应当维持在低电平VL，但是第一薄膜晶体管T1的第三端（漏极）和第二端（栅极）之间存在寄生电容，在第一时钟信号Vc从低电平VL跳变到高电平VH时，由于时钟馈通效应的作用下，在控制端112产生一个耦合电压，当耦合电压过大时可能导致第一薄膜晶体管T1导通，第一时钟信号Vc对驱动信号Vout1进行错误充电，驱动信号Vout1无法维持在低电平VL。
因此在时刻t4之后，第六薄膜晶体管T6和第七薄膜晶体管T7均保持断开，在第一时钟信号Vc为高电平VH时，第一时钟信号Vc通过第二电容C2将高电平耦合至第四薄膜晶体管T4的第二端，以使第四薄膜晶体管T4导通，第一参考电压Vdd对第八薄膜晶体管T8的第二端进行充电。在第三时钟信号Va为高电平VH时，第五薄膜晶体管T5导通，第一参考电压Vdd对第八薄膜晶体管T8的第二端进行充电，进而实现第四薄膜晶体管T4和第五薄膜晶体管T5交替导通，以将第八薄膜晶体管T8的第二端维持在高电平VH。移位寄存器单元在低电平维持阶段，第八薄膜晶体管T8导通，以将驱动信号Vout1维持在低电平VL。
此外，本实施的移位寄存器单元在低电平维持阶段，第一薄膜晶体管T1在第三时钟信号Va为高电平产生周期性的导通，因此将第一控制信号V11下拉至低电平VL，能够有效地抑制控制端112的时钟馈通效应。
本发明还提供第二实施例的移位寄存器单元，其与第一实施例所揭示的移位寄存器单元的不同之处在于：如图3所示，本实施例的移位寄存器单元还包括初始化模块34，初始化模块34分别与控制端312和第二参考电压Vss连接，初始化模块34用于将驱动控制信号Qn下拉至第二参考电压Vss的低电平VL。
初始化模块34包括第九薄膜晶体管T9，第九薄膜晶体管T9的第一端与第一薄膜晶体管T1的第二端连接，第九薄膜晶体管T9的第二端与初始化脉冲信号Vr连接，第九薄膜晶体管T9的第三端与第二参考电压Vss连接。
请一并参见图4所示的时序图，初始化脉冲信号Vr的高电平VH超前于第一控制信号V11至少一个脉冲宽度，并且初始化脉冲信号Vr的上升沿超前于第一时钟信号Vc、第二时钟信号Vb以及第三时钟信号Va中的第一个脉冲的上升沿。
在时刻t0时，即在第一时钟信号Vc、第二时钟信号Vb以及第三时钟信号Va上升到高电平VH之前，初始化脉冲信号Vr为高电平VH，第九薄膜晶体管T9导通，第二参考电压Vss将控制端312的驱动控制信号Qn下拉至低电平VL。
相对于第一实施例所揭示的移位寄存器单元，本实施例所揭示的移位寄存器单元能够更好地抑制控制端312的时钟馈通效应，以使移位寄存器单元的工作更加稳定。
本发明还提供第三实施例的移位寄存器单元，其与第二实施例所揭示的移位寄存器单元的不同之处在于：本实施例所揭示的移位寄存器单元应用于负载较大或者温度较低，如图5所示，驱动模块51进一步包括第二输出端514，与下一级的移位寄存器单元连接，用于为下一级的移位寄存器单元提供输入信号。
第二输出端514包括第十薄膜晶体管T10，第十薄膜晶体管T10的第一端与第一时钟信号Vc连接，第十薄膜晶体管T10的第二端与第一薄膜晶体管T1的第二端连接，第十薄膜晶体管T10的第三端与下一级的移位寄存器单元连接。
低电平维持模块53进一步包括第十一薄膜晶体管T11，第十一薄膜晶体管T11的第一端与第十薄膜晶体管T10的第三端连接，第十一薄膜晶体管T11的第二端与第八薄膜晶体管T8的第二端连接，第十一薄膜晶体管T11的第三端与第二参考电压Vss连接。
请一并参见图6所示的时序图，在时刻t2至时刻t3时，移位寄存器单元处于上拉阶段，第十薄膜晶体管T10导通，第一时钟信号Vc对第二输出端514输出的驱动信号Vout2进行充电。
在时刻t3至时刻t4时，移位寄存器单元处于下拉阶段，第十薄膜晶体管T10和第十一薄膜晶体管T11同时导通，第二输出端514输出的驱动信号Vout2通过第十薄膜晶体管T10和第十一薄膜晶体管T11进行放电。
在时刻t4之后，移位寄存器单元处于低电平维持阶段，第十一薄膜晶体管T11导通，第二参考电压Vss将第二输出端514输出的驱动信号Vout2维持在低电平。
其中，第一薄膜晶体管T1的第三端输出的驱动信号Vout1与第二输出端514输出的驱动信号Vout2的时序图相同。由于第二输出端514的负载小于第一输出端513的负载，导致驱动信号Vout2上升的时间小于驱动信号Vout1上升的时间。第二输出端514用于为下一级的移位寄存器单元提供输入信号，控制端512的驱动控制信号Qn在预充阶段时可以快速充电至VH-Vth3，以使第一薄膜晶体管T1具有更好的驱动能力，因此本实施例所揭示的移位寄存器单元适用于第一输出端513的负载较大或者温度较低。
在其他实施例中，本领域的普通技术人员完全可以将初始化模块54去掉。
在发明中，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10以及第十一薄膜晶体管T11为N型薄膜晶体管。在其他实施例中，本领域的普通技术人员完全可以将第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10以及第十一薄膜晶体管T11设置为P型薄膜晶体管。
本发明还提供第一实施例的移位寄存器，如图7所示，本实施例所揭示移动位寄存器包括N级级联的移位寄存单元70、第一时钟线CK1、第二时钟线CK2、第三时钟线CK3、第四时钟线CK4、公共地线701以及起始信号ST，其中第一级移位寄存单元70和第二移位寄存单元70均为上述第一实施例所揭示的移位寄存单元，第三级移位寄存单元70至第N级移位寄存单元70均为上述第二实施例所揭示的移位寄存单元，在此不再赘述。
其中，第一级移位寄存单元70的第一时钟信号Vc与第一时钟线CK1连接，第一级移位寄存单元70的第二时钟信号Vb与第四时钟线CK4连接，第一级移位寄存单元70的第三时钟信号Va与第三时钟线CK3连接，第一级移位寄存单元70的第一控制信号V11与起始信号ST连接。
N级级联的移位寄存单元70的第二参考电压Vss均与公共地线701连接，公共地线701用于为第二参考电压Vss提供低电平VL。第一级移位寄存单元70至第N级移位寄存单元70的第一输出端113输出的信号为Vg1-Vgn。
第二级移位寄存单元70至第N级移位寄存单元70的第一控制信号V11均与上一级的移位寄存单元70的第一输出端113连接，例如第n级移位寄存单元70的第一控制信号V11与第n-1级移位寄存单元70的第一输出端113连接。
第二级移位寄存单元70的第一时钟信号Vc与第二时钟线CK2连接，第二级移位寄存单元70的第二时钟信号Vb与第一时钟线CK1连接，第二级移位寄存单元70的第三时钟信号Va与第四时钟线CK4连接。
第三级移位寄存单元70的第一时钟信号Vc与第三时钟线CK3连接，第三级移位寄存单元70的第二时钟信号Vb与第二时钟线CK2连接，第三级移位寄存单元70的第三时钟信号Va与第一时钟线CK1连接，第三级移位寄存单元70的初始化脉冲信号Vr与起始信号ST连接。
第四级移位寄存单元70的第一时钟信号Vc与第四时钟线CK4连接，第四级移位寄存单元70的第二时钟信号Vb与第三时钟线CK3连接，第四级移位寄存单元70的第三时钟信号Va与第二时钟线CK2连接。第四级移位寄存单元70的初始化脉冲信号Vr与起始信号ST连接。
第N-1级移位寄存单元70的第一时钟信号Vc与第三时钟线CK3连接，第N-1级移位寄存单元70的第二时钟信号Vb与第二时钟线CK2连接，第N-1级移位寄存单元70的第三时钟信号Va与第一时钟线CK1连接。第N-1级移位寄存单元70的初始化脉冲信号Vr与起始信号ST连接。
第N级移位寄存单元70的第一时钟信号Vc与第四时钟线CK4连接，第N级移位寄存单元70的第二时钟信号Vb与第三时钟线CK3连接，第N级移位寄存单元70的第三时钟信号Va与第二时钟线CK2连接。第N级移位寄存单元70的初始化脉冲信号Vr与起始信号ST连接。
本实施例所揭示移动位寄存器的时序图如图8所示，在第一帧中，通过起始信号ST触发，以使第一级移位寄存单元70至第N级移位寄存单元70依次输出信号Vg1-Vgn；在第二帧中，重新通过起始信号ST触发，以使第一级移位寄存单元70至第N级移位寄存单元70依次输出信号Vg1-Vgn。
本发明还提供第二实施例的移位寄存器，与第一实施例所揭示的移位寄存器的不同之处在于：如图9所示，本实施例所揭示的移位寄存器的第一级移位寄存单元90至第N级移位寄存单元90为上述第三实施例所揭示的移位寄存单元，在此不再赘述。本实施例所揭示移动位寄存器的时序图如图8所示。
综上所述，本发明的移位寄存器包括多级移位寄存器单元，每级移位寄存器单元包括：驱动模块、输入模块以及低电平维持模块，驱动模块根据驱动控制信号通过第一时钟信号对驱动信号进行充放电；输入模块根据第二时钟信号和第一控制信号输出驱动控制信号；低电平维持模块根据第一参考电压、第三时钟信号、第一时钟信号以及第一控制信号将驱动信号的电平维持在第二参考电压的低电平；在第一时钟信号对驱动信号进行充电时，低电平维持模块断开与第一输出端连接，避免第一输出端漏电，减少驱动信号上升时间；在第一时钟信号对驱动信号进行放电时，低电平维持模块与第一输出端连接，驱动信号通过第一时钟信号和低电平维持模块快速放电，移位寄存器的电路面积小。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (17)

  1. 一种移位寄存器，其中，所述移位寄存器包括多级移位寄存器单元，其中至少一级所述移位寄存器单元包括：
    驱动模块，包括：
    输入端，与第一时钟信号连接；
    控制端，用于接收驱动控制信号；
    第一输出端，用于输出驱动信号，所述驱动模块根据所述驱动控制信号通过所述第一时钟信号对所述驱动信号进行充放电；
    输入模块，与所述控制端连接，所述输入模块根据第二时钟信号和第一控制信号输出所述驱动控制信号；
    低电平维持模块，与所述第一输出端连接，用于根据第一参考电压、第三时钟信号、所述第一时钟信号以及所述第一控制信号将所述驱动信号的电平维持在第二参考电压的低电平；
    其中，所述驱动模块包括第一薄膜晶体管和第一电容，所述第一薄膜晶体管的第一端与所述第一时钟信号连接，所述第一薄膜晶体管的第二端与所述输入模块连接，所述第一薄膜晶体管的第三端用于输出驱动信号，所述第一电容的一端与所述第一薄膜晶体管的第二端连接，所述第一电容的另一端与所述第一薄膜晶体管的第三端连接；
    所述输入模块包括：第二薄膜晶体管以及第三薄膜晶体管，所述第二薄膜晶体管的第一端与所述第三薄膜晶体管的第一端连接，所述第二薄膜晶体管的第二端与所述第二时钟信号连接，所述第二薄膜晶体管的第三端和所述第三薄膜晶体管的第三端与所述第一薄膜晶体管的第二端连接，所述第三薄膜晶体管的第一端和第二端与所述第一控制信号连接；
    所述低电平维持模块包括：第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第二电容，所述第四薄膜晶体管的第一端和所述第五薄膜晶体管的第一端与所述第一参考电压连接，所述第四薄膜晶体管的第二端与所述第六薄膜晶体管的第一端连接，所述第四薄膜晶体管的第三端和所述第五薄膜晶体管的第三端与所述第八薄膜晶体管的第二端连接，所述第五薄膜晶体管的第二端与所述第三时钟信号连接，所述第六薄膜晶体管的第一端通过所述第二电容与所述第一时钟信号连接，所述第六薄膜晶体管的第二端和所述第七薄膜晶体管的第二端与所述第一控制信号连接，所述第六薄膜晶体管的第三端、所述第七薄膜晶体管的第三端以及所述第八薄膜晶体管的第三端与所述第二参考电压连接，所述第七薄膜晶体管的第一端与所述第八薄膜晶体管的第二端连接，所述第八薄膜晶体管的第一端与所述第一薄膜晶体管的第三端连接。
  2. 根据权利要求1所述的移位寄存器，其中，所述移位寄存器单元进一步包括初始化模块，分别与所述控制端和所述第二参考电压连接，所述初始化模块用于将所述驱动控制信号下拉至所述第二参考电压的低电平。
  3. 根据权利要求2所述的移位寄存器，其中，所述初始化模块包括第九薄膜晶体管，所述第九薄膜晶体管的第一端与所述第一薄膜晶体管的第二端连接，所述第九薄膜晶体管的第二端与初始化脉冲信号连接，所述第九薄膜晶体管的第三端与所述第二参考电压连接。
  4. 根据权利要求3所述的移位寄存器，其中，所述驱动模块进一步包括：第二输出端，与下一级的移位寄存器单元连接，用于为所述下一级的移位寄存器单元提供输入信号。
  5. 根据权利要求4所述的移位寄存器，其中，所述第二输出端包括第十薄膜晶体管，所述第十薄膜晶体管的第一端与所述第一时钟信号连接，所述第十薄膜晶体管的第二端与所述第一薄膜晶体管的第二端连接，所述第十薄膜晶体管的第三端与所述下一级的移位寄存器单元连接。
  6. 根据权利要求5所述的移位寄存器，其中，所述低电平维持模块进一步包括第十一薄膜晶体管，所述第十一薄膜晶体管的第一端与所述第十薄膜晶体管的第三端连接，所述第十一薄膜晶体管的第二端与所述第八薄膜晶体管的第二端连接，所述第十一薄膜晶体管的第三端与所述第二参考电压连接。
  7. 根据权利要求6所述的移位寄存器，其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管以及第十一薄膜晶体管为N型薄膜晶体管。
  8. 一种移位寄存器，其中，所述移位寄存器包括多级移位寄存器单元，其中至少一级所述移位寄存器单元包括：
    驱动模块，包括：
    输入端，与第一时钟信号连接；
    控制端，用于接收驱动控制信号；
    第一输出端，用于输出驱动信号，所述驱动模块根据所述驱动控制信号通过所述第一时钟信号对所述驱动信号进行充放电；
    输入模块，与所述控制端连接，所述输入模块根据第二时钟信号和第一控制信号输出所述驱动控制信号；
    低电平维持模块，与所述第一输出端连接，用于根据第一参考电压、第三时钟信号、所述第一时钟信号以及所述第一控制信号将所述驱动信号的电平维持在第二参考电压的低电平。
  9. 根据权利要求8所述的移位寄存器，其中，所述驱动模块包括第一薄膜晶体管和第一电容，所述第一薄膜晶体管的第一端与所述第一时钟信号连接，所述第一薄膜晶体管的第二端与所述输入模块连接，所述第一薄膜晶体管的第三端用于输出驱动信号，所述第一电容的一端与所述第一薄膜晶体管的第二端连接，所述第一电容的另一端与所述第一薄膜晶体管的第三端连接。
  10. 根据权利要求9所述的移位寄存器，其中，所述输入模块包括：第二薄膜晶体管以及第三薄膜晶体管，所述第二薄膜晶体管的第一端与所述第三薄膜晶体管的第一端连接，所述第二薄膜晶体管的第二端与所述第二时钟信号连接，所述第二薄膜晶体管的第三端和所述第三薄膜晶体管的第三端与所述第一薄膜晶体管的第二端连接，所述第三薄膜晶体管的第一端和第二端与所述第一控制信号连接。
  11. 根据权利要求9所述的移位寄存器，其中，所述低电平维持模块包括：第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第二电容，所述第四薄膜晶体管的第一端和所述第五薄膜晶体管的第一端与所述第一参考电压连接，所述第四薄膜晶体管的第二端与所述第六薄膜晶体管的第一端连接，所述第四薄膜晶体管的第三端和所述第五薄膜晶体管的第三端与所述第八薄膜晶体管的第二端连接，所述第五薄膜晶体管的第二端与所述第三时钟信号连接，所述第六薄膜晶体管的第一端通过所述第二电容与所述第一时钟信号连接，所述第六薄膜晶体管的第二端和所述第七薄膜晶体管的第二端与所述第一控制信号连接，所述第六薄膜晶体管的第三端、所述第七薄膜晶体管的第三端以及所述第八薄膜晶体管的第三端与所述第二参考电压连接，所述第七薄膜晶体管的第一端与所述第八薄膜晶体管的第二端连接，所述第八薄膜晶体管的第一端与所述第一薄膜晶体管的第三端连接。
  12. 根据权利要求11所述的移位寄存器，其中，所述移位寄存器单元进一步包括初始化模块，分别与所述控制端和所述第二参考电压连接，所述初始化模块用于将所述驱动控制信号下拉至所述第二参考电压的低电平。
  13. 根据权利要求12所述的移位寄存器，其中，所述初始化模块包括第九薄膜晶体管，所述第九薄膜晶体管的第一端与所述第一薄膜晶体管的第二端连接，所述第九薄膜晶体管的第二端与初始化脉冲信号连接，所述第九薄膜晶体管的第三端与所述第二参考电压连接。
  14. 根据权利要求13所述的移位寄存器，其中，所述驱动模块进一步包括：第二输出端，与下一级的移位寄存器单元连接，用于为所述下一级的移位寄存器单元提供输入信号。
  15. 根据权利要求14所述的移位寄存器，其中，所述第二输出端包括第十薄膜晶体管，所述第十薄膜晶体管的第一端与所述第一时钟信号连接，所述第十薄膜晶体管的第二端与所述第一薄膜晶体管的第二端连接，所述第十薄膜晶体管的第三端与所述下一级的移位寄存器单元连接。
  16. 根据权利要求15所述的移位寄存器，其中，所述低电平维持模块进一步包括第十一薄膜晶体管，所述第十一薄膜晶体管的第一端与所述第十薄膜晶体管的第三端连接，所述第十一薄膜晶体管的第二端与所述第八薄膜晶体管的第二端连接，所述第十一薄膜晶体管的第三端与所述第二参考电压连接。
  17. 根据权利要求16所述的移位寄存器，其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管以及第十一薄膜晶体管为N型薄膜晶体管。
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