CN104299589B - 移位寄存器单元电路、移位寄存器、驱动方法及显示装置 - Google Patents

移位寄存器单元电路、移位寄存器、驱动方法及显示装置 Download PDF

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CN104299589B
CN104299589B CN201410594545.XA CN201410594545A CN104299589B CN 104299589 B CN104299589 B CN 104299589B CN 201410594545 A CN201410594545 A CN 201410594545A CN 104299589 B CN104299589 B CN 104299589B
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grid
clock
output
transistor
memory capacitance
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CN104299589A (zh
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姚树林
李承珉
孙志华
吴行吉
崔文海
刘宝玉
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Beijing BOE Display Technology Co Ltd
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Priority to US14/785,689 priority patent/US9741304B2/en
Priority to EP15777857.2A priority patent/EP3038099B1/en
Priority to PCT/CN2015/075253 priority patent/WO2016065834A1/zh
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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Abstract

本发明涉及显示技术领域，公开了一种移位寄存器单元电路，包括：栅极启动端、第一时钟端、第二时钟端、复位端、低电平端、栅极输出端、存储电容、充电模块、输出控制模块及复位模块。还公开了移位寄存器、驱动方法及显示装置，本发明的移位寄存器单元电路中，由于第二晶体管和第五晶体管一起作用控制复位端，即使复位端信号出现的不稳定的情况，也不会出现错误的复位操作。

Description

移位寄存器单元电路、移位寄存器、驱动方法及显示装置
技术领域
本发明涉及显示技术领域，特别涉及一种移位寄存器单元电路、移位寄存器、驱动方法及显示装置。
背景技术
GOA(GateDriveonArray)技术是将栅极驱动电路IC的功能做在阵列基板上，提高了液晶显示面板的集成度，降低了材料成本和制作工艺成本。如图1所示，GOA电路包括多个GOA单元，每个GOA单元对应一个栅极驱动输出，从而实现栅极驱动电路IC的功能。
但是GOA单元电路存在一个问题，在Reset信号本身可能会出现不稳定的情况，导致晶体管M2误开启，从而出现错误的Reset操作。
发明内容
(一)要解决的技术问题
本发明要解决的技术问题是：如何避免GOA单元电路的Reset端的误操作。
(二)技术方案
为解决上述技术问题，本发明提供了一种移位寄存器单元电路，包括：栅极启动端、第一时钟端、第二时钟端、复位端、低电平端、栅极输出端、存储电容、充电模块、输出控制模块及复位模块；
所述充电模块连接栅极启动端、第一时钟端和存储电容，用于在所述栅极启动端和第一时钟端的控制下对所述存储电容充电至高电平；
所述输出控制模块连接所述第二时钟端、存储电容和栅极输出端，用于在所述存储电容为高电平时将所述第二时钟端的电平信号输出至所述栅极输出端；
所述复位模块包括：第二晶体管、第四晶体管和第五晶体管，所述第二晶体管的栅极连接所述复位端，源极连接所述存储电容的第一端，漏极连接所述第五晶体管的栅极，所述第四晶体管的栅极连接所述复位端，源极连接所述栅极输出端，漏极连接所述低电平端，所述第五晶体管的源极连接所述存储电容的第一端，漏极连接所述低电平端；所述第二晶体管和第五晶体管用于在复位端的控制下将所述存储电容第一端连接至所述低电平端，所述第四晶体管用于在复位端的控制下将所述栅极输出端连接至所述低电平端。
其中，所述第五晶体管的栅极开启电压大于所述第二晶体管的栅极开启电压。
其中，所述充电模块包括：第一晶体管和第六晶体管，所述第一晶体管的栅极和源极连接所述栅极启动端，漏极连接所述存储电容的第一端，用于在栅极启动端为高电平时对所述存储电容充电，所述第六晶体管的栅极连接所述第一时钟端，源极连接所述栅极启动端，漏极连接所述存储电容的第一端，用于在栅极启动端和第一时钟端为高电平时对所述存储电容充电。
其中，所述输出控制模块包括：第三晶体管，所述第三晶体管的栅极连接所述存储电容的第一端，源极连接所述第二时钟端、漏极连接所述栅极输出端，栅极输出端连接所述存储电容的第二端，所述第三晶体管用于在所述存储电容第一端为高电平时将所述第二时钟端的电平信号输出至所述栅极输出端。
本发明还提供了一种上述任一项所述的移位寄存器单元电路驱动方法，包括：
对所述栅极启动端和第一时钟端施加高电平，第二时钟端施加低电平，使所述充电模块在所述栅极启动端和第一时钟端的控制下对所述存储电容充电至高电平，且使栅极输出端输出第二时钟端的低电平；
对所述栅极启动端和第一时钟端施加低电平，第二时钟端施加高电平，存储电容保持高电平，使输出控制模块控制栅极输出端输出第二时钟端的高电平；
对复位端施加高电平，第二晶体管导通，将存储电容第一端的高电平传输至第五晶体管的栅极，导通第五晶体管，将存储电容的第一端拉至电平，同时第四晶体管导通，使栅极输出端输出低电平。
其中，对所述栅极启动端和第一时钟端施加高电平，第二时钟端施加低电平，使所述充电模块在所述栅极启动端和第一时钟端的控制下对所述存储电容充电至高电平，且使栅极输出端输出第二时钟端的低电平具体包括：
对所述栅极启动端和第一时钟端施加高电平，第一晶体管和第六晶体管导通，将所述存储电容第一端充为高电平，第三晶体管导通，同时对第二时钟端施加低电平，使第二时钟端的低电平输出至所述栅极输出端。
其中，对所述栅极启动端和第一时钟端施加低电平，第二时钟端施加高电平，存储电容保持高电平，使输出控制模块控制栅极输出端输出第二时钟端的高电平具体包括：
对所述栅极启动端和第一时钟端施加低电平，第一晶体管和第六晶体管关闭，存储电容第一端保持高电平，使第三晶体管导通，同时第二时钟端施加高电平，且通过所述第三晶体管输出至所述栅极输出端。
本发明还提供了一种移位寄存器，包括级联的若干上述任一项所述的移位寄存器单元电路，下一级移位寄存器单元电路的栅极输出端信号反馈至所述上一级移位寄存器单元电路的复位端。
本发明还提供了一种显示装置，包括上述的移位寄存器。
(三)有益效果
本发明的移位寄存器单元电路中，由于第二晶体管和第五晶体管一起作用控制复位端，即使复位端信号出现的不稳定的情况，也不会出现错误的复位操作。
附图说明
图1是移位寄存器结构示意图；
图2是本发明实施例的移位寄存器单元电路结构示意图；
图3是图2中移位寄存器单元电路的工作时序图。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
如图2所示，本发明提供了一种移位寄存器单元电路，包括：栅极启动端STV、第一时钟端CLKB、第二时钟端CLK、复位端Reset、低电平端VSS、栅极输出端OUT、存储电容C1、充电模块、输出控制模块及复位模块。
所述充电模块连接栅极启动端STV、第一时钟端CLKB和存储电容C1，用于在所述栅极启动端STV和第一时钟端CLKB的控制下对所述存储电容C1充电至高电平，即图2中PU点为高电平。
所述输出控制模块连接所述第二时钟端CLK、存储电容C1和栅极输出端OUT，用于在所述存储电容C1为高电平时将所述第二时钟端CLK的电平信号输出至所述栅极输出端OUT。
所述复位模块连接所述复位端Reset、低电平端VSS、存储电容C1和栅极输出端OUT，用于在所述复位端Reset的控制下将所述存储电容C1的两端和栅极输出端OUT连接至所述低电平端VSS。具体地，复位模块包括：第二晶体管M2、第四晶体管M4和第五晶体管M5，所述第二晶体管M2的栅极连接所述复位端Reset，源极连接所述存储电容C1的第一端，漏极连接所述第五晶体管M5的栅极，所述第四晶体管M4的栅极连接所述复位端Reset，源极连接所述栅极输出端OUT，漏极连接所述低电平端VSS，所述第五晶体管M5的源极连接所述存储电容C1的第一端，漏极连接所述低电平端VSS；所述第二晶体管M2和第五晶体管M5用于在复位端Reset的控制下将所述存储电容C1第一端连接至所述低电平端VSS，所述第四晶体管M4用于在复位端Reset的控制下将所述栅极输出端OUT连接至所述低电平端VSS。
当Reset信号不稳定发生波动时，第二晶体管M2处于微导通状态，P1点电压不足以使第五晶体管M5导通，这时存储电容C1的第一端，即PU点的电压不会被拉到低电平端VSS，所以移位寄存器单元电路不会因为Reset信号的不稳定而发生错误的Reset。
本实施例中，所述充电模块包括：第一晶体管M1和第六晶体管M6，所述第一晶体管M1的栅极和源极连接所述栅极启动端STV，漏极连接所述存储电容C1的第一端，用于在栅极启动端STV为高电平时对所述存储电容C1充电，所述第六晶体管M6的栅极连接所述第一时钟端CLKB，源极连接所述栅极启动端STV，漏极连接所述存储电容C1的第一端，用于在栅极启动端STV和第一时钟端CLKB为高电平时对所述存储电容C1充电。
其中，所述输出控制模块包括：第三晶体管M3，所述第三晶体管M3的栅极连接所述存储电容C1的第一端，源极连接所述第二时钟端CLK、漏极连接所述栅极输出端OUT，栅极输出端OUT连接所述存储电容C1的第二端，所述第三晶体管M3用于在所述存储电容C1第一端为高电平时将所述第二时钟端CLK的电平信号输出至所述栅极输出端OUT。
进一步地，所述第五晶体管M5的栅极开启电压大于所述第二晶体管M2的栅极开启电压。这样更能保证在第二晶体管M2微导通时，P1点电压无法打开第五晶体管M5。
本实施例的GOA电路工作时序如图3所示，其具体工作原理如下：
阶段1、STV端和CLKB端为高电平，CLK端为低电平，此时M1和M6导通，PU点被拉高，对电容C1充电。M3导通，OUT端输出为CLK端的低电平。
阶段2、STV端和CLKB端为低电平，CLK端为高电平，电容C1保持PU点的高电平，M3导通，OUT端输出为CLK端的高电平。
阶段3、当下一级单元电路的OUT端的高电平反馈到本级GOA单元时，即Reset端为高电平，此时M2导通，将P1点拉高，同时M5导通，将PU点电压拉到VSS端的低电平，实现GOA单元的Reset。同时M4导通，将OUT端电位拉到VSS端的低电平，关闭GOA单元的输出，即OUT端停止输出高电平。
本实施例中，当Reset信号不稳定，发生波动时，晶体管M2处于微导通状态，P1点电压不足以使晶体管M5导通，这时PU点的电压不会被拉到VSS，所以GOA单元不会因为Reset信号的不稳定而发生错误的Reset。即只有晶体管M2和晶体管M5同时处于导通状态时，GOA单元才能完成正确的Reset。
本发明还提供了一种基于上述移位寄存器单元电路的驱动方法，包括一下三个阶段：
阶段一：对所述栅极启动端STV和第一时钟端CLKB施加高电平，第二时钟端CLK施加低电平，使所述充电模块在所述栅极启动端STV和第一时钟端CLKB的控制下对所述存储电容C1充电至高电平，且使栅极输出端OUT输出第二时钟端CLK的低电平。具体地，对所述栅极启动端STV和第一时钟端CLKB施加高电平，第一晶体管M1和第六晶体管M6导通，将所述存储电容C1第一端充为高电平，第三晶体管M3导通，同时对第二时钟端CLK施加低电平，使第二时钟端CLK的低电平输出至所述栅极输出端OUT。
阶段二：对所述栅极启动端STV和第一时钟端CLKB施加低电平，第二时钟端CLK施加高电平，存储电容C1保持高电平，使输出控制模块控制栅极输出端OUT输出第二时钟端CLK的高电平。具体地，对所述栅极启动端STV和第一时钟端CLKB施加低电平，第一晶体管M1和第六晶体管M6关闭，存储电容C1第一端保持高电平，使第三晶体管M3导通，同时第二时钟端CLK施加高电平，且通过所述第三晶体管M3输出至所述栅极输出端OUT。
阶段三：对复位端Reset施加高电平，第二晶体管M2导通，将存储电容C1第一端的高电平传输至第五晶体管M5的栅极，导通第五晶体管M5，将存储电容C1的第一端拉至低电平，同时第四晶体管M4导通，使栅极输出端OUT输出低电平。
本发明还提供了一种移位寄存器，包括级联的若干上述任一项所述的移位寄存器单元电路，下一级移位寄存器单元电路的栅极输出端信号反馈至所述上一级移位寄存器单元电路的复位端。
本发明还提供了一种显示装置，包括上述的移位寄存器。该显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。

Claims (9)

1.一种移位寄存器单元电路，其特征在于，包括：栅极启动端、第一时钟端、第二时钟端、复位端、低电平端、栅极输出端、存储电容、充电模块、输出控制模块及复位模块；
所述充电模块连接栅极启动端、第一时钟端和存储电容，用于在所述栅极启动端和第一时钟端的控制下对所述存储电容充电至高电平；
所述输出控制模块连接所述第二时钟端、存储电容和栅极输出端，用于在所述存储电容为高电平时将所述第二时钟端的电平信号输出至所述栅极输出端；
所述复位模块包括：第二晶体管、第四晶体管和第五晶体管，所述第二晶体管的栅极连接所述复位端，源极连接所述存储电容的第一端，漏极连接所述第五晶体管的栅极，所述第四晶体管的栅极连接所述复位端，源极连接所述栅极输出端，漏极连接所述低电平端，所述第五晶体管的源极连接所述存储电容的第一端，漏极连接所述低电平端；所述第二晶体管和第五晶体管用于在复位端的控制下将所述存储电容第一端连接至所述低电平端，所述第四晶体管用于在复位端的控制下将所述栅极输出端连接至所述低电平端。
2.如权利要求1所述的移位寄存器单元电路，其特征在于，所述第五晶体管的栅极开启电压大于所述第二晶体管的栅极开启电压。
3.如权利要求1或2所述的移位寄存器单元电路，其特征在于，所述充电模块包括：第一晶体管和第六晶体管，所述第一晶体管的栅极和源极连接所述栅极启动端，漏极连接所述存储电容的第一端，用于在栅极启动端为高电平时对所述存储电容充电，所述第六晶体管的栅极连接所述第一时钟端，源极连接所述栅极启动端，漏极连接所述存储电容的第一端，用于在栅极启动端和第一时钟端为高电平时对所述存储电容充电。
4.如权利要求3所述的移位寄存器单元电路，其特征在于，所述输出控制模块包括：第三晶体管，所述第三晶体管的栅极连接所述存储电容的第一端，源极连接所述第二时钟端、漏极连接所述栅极输出端，栅极输出端连接所述存储电容的第二端，所述第三晶体管用于在所述存储电容第一端为高电平时将所述第二时钟端的电平信号输出至所述栅极输出端。
5.一种如权利要求4所述的移位寄存器单元电路驱动方法，其特征在于，包括：
对所述栅极启动端和第一时钟端施加高电平，第二时钟端施加低电平，使所述充电模块在所述栅极启动端和第一时钟端的控制下对所述存储电容充电至高电平，且使栅极输出端输出第二时钟端的低电平；
对所述栅极启动端和第一时钟端施加低电平，第二时钟端施加高电平，存储电容保持高电平，使输出控制模块控制栅极输出端输出第二时钟端的高电平；
对复位端施加高电平，第二晶体管导通，将存储电容第一端的高电平传输至第五晶体管的栅极，导通第五晶体管，将存储电容的第一端拉至低电平，同时第四晶体管导通，使栅极输出端输出低电平。
6.如权利要求5所述的驱动方法，其特征在于，对所述栅极启动端和第一时钟端施加高电平，第二时钟端施加低电平，使所述充电模块在所述栅极启动端和第一时钟端的控制下对所述存储电容充电至高电平，且使栅极输出端输出第二时钟端的低电平具体包括：
对所述栅极启动端和第一时钟端施加高电平，第一晶体管和第六晶体管导通，将所述存储电容第一端充为高电平，第三晶体管导通，同时对第二时钟端施加低电平，使第二时钟端的低电平输出至所述栅极输出端。
7.如权利要求5所述的驱动方法，其特征在于，对所述栅极启动端和第一时钟端施加低电平，第二时钟端施加高电平，存储电容保持高电平，使输出控制模块控制栅极输出端输出第二时钟端的高电平具体包括：
对所述栅极启动端和第一时钟端施加低电平，第一晶体管和第六晶体管关闭，存储电容第一端保持高电平，使第三晶体管导通，同时第二时钟端施加高电平，且通过所述第三晶体管输出至所述栅极输出端。
8.一种移位寄存器，其特征在于，包括级联的若干如权利要求1～4中任一项所述的移位寄存器单元电路，下一级移位寄存器单元电路的栅极输出端信号反馈至上一级移位寄存器单元电路的复位端。
9.一种显示装置，其特征在于，包括如权利要求8所述的移位寄存器。
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