WO2016070458A1 - 液晶显示面板及其栅极驱动电路 - Google Patents

液晶显示面板及其栅极驱动电路 Download PDF

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Publication number
WO2016070458A1
WO2016070458A1 PCT/CN2014/091255 CN2014091255W WO2016070458A1 WO 2016070458 A1 WO2016070458 A1 WO 2016070458A1 CN 2014091255 W CN2014091255 W CN 2014091255W WO 2016070458 A1 WO2016070458 A1 WO 2016070458A1
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WIPO (PCT)
Prior art keywords
transistor
gate
shift register
circuit
node
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Application number
PCT/CN2014/091255
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English (en)
French (fr)
Inventor
肖军城
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深圳市华星光电技术有限公司
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Priority to US14/426,359 priority Critical patent/US9564090B2/en
Publication of WO2016070458A1 publication Critical patent/WO2016070458A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a liquid crystal display panel and a gate driving circuit thereof.
  • GOA Gate Driver On The Array circuit is a driving method in which a gate scan driving circuit is fabricated on an Array substrate by using an existing OLED process of a thin film transistor liquid crystal display to realize a progressive scan.
  • the GOA circuit includes a pull-up circuit and a pull-up control circuit (Pull-up control) Circuit), transfer circuit, pull-down circuit (Pull-down Holding) Circuit) and the boost circuit responsible for the potential rise.
  • the pull-up circuit is mainly responsible for outputting an input clock signal (Clock) to the gate of the thin film transistor as a driving signal of the liquid crystal display.
  • the pull-up control circuit is responsible for controlling the opening of the pull-up circuit, which is generally a signal transmitted by the upper-level GOA circuit.
  • the pull-down circuit is responsible for quickly pulling the scan signal low to low after the output of the scan signal, that is, the potential of the gate of the thin film transistor is pulled low to a low potential; the pull-down hold circuit is responsible for the signal of the scan signal and the pull-up circuit (commonly called For Q point) Staying in the off state (ie, the set negative potential), there are usually two pull-down holding circuits that alternate.
  • the rising circuit is responsible for the secondary rise of the Q point potential, thus ensuring the normal output of the G(N) of the pull-up circuit.
  • Embodiments of the present invention provide a liquid crystal display panel and a gate driving circuit thereof to improve stability of long-term operation of the gate driving circuit.
  • the present invention provides a gate driving circuit including a plurality of shift register circuits, the plurality of shift register circuits being cascaded in series, each shift register circuit comprising: a pull-up circuit including a first transistor, The gate of the first transistor is coupled to the first node, the source is coupled to the first clock signal, the drain is coupled to the gate signal output of the shift register circuit, and the downstream circuit includes the second transistor.
  • a gate of the second transistor is coupled to the first node, a source is coupled to the first clock signal, a drain is coupled to the output of the drive signal of the shift register circuit, and a pull-up control circuit includes a third transistor, a third The gate of the transistor is coupled to the driving signal output end of the shift register circuit of the first two stages of the shift register circuit where the transistor is located, and the source is coupled to the gate signal output end of the shift register circuit of the first two stages, and the drain
  • the pole is coupled to the first node; the rising circuit is coupled between the first node and the gate signal output end of the shift register circuit for raising the potential of the first node; the first pull-down holding circuit is coupled to First node, first clock a first reference voltage and a second reference voltage for maintaining a low level of the first node; a compensation circuit coupled to the first node or the first pull-down holding circuit for compensating the first node or the first Pull to hold the potential of the circuit.
  • the compensation circuit includes a fourth transistor, and the source and the gate of the fourth transistor are both coupled to the drive signal output end of the shift register circuit of the next stage of the shift register circuit where the shift register circuit is located, and the drain of the fourth transistor And connected to the first node, for raising the potential of the first node according to the driving signal outputted by the driving signal output end of the shift register circuit of the next stage.
  • the compensation circuit further includes a fifth transistor, a sixth transistor, and a first capacitor.
  • One end of the first capacitor is connected to the drain of the third transistor, and the other end of the first capacitor is connected to the drain of the fifth transistor and the sixth transistor.
  • the source is connected, and the gate of the fifth transistor is connected to the driving signal output end of the shift register circuit of the first four stages of the shift register circuit in which the shift transistor is located, and the source of the fifth transistor and the gate of the shift register circuit of the first four stages
  • the pole signal output terminal is connected, the gate of the sixth transistor is connected to the drive signal output end of the shift register circuit of the first two stages, and the drain of the sixth transistor is connected to the first node.
  • the compensation circuit includes a fourth transistor, a fifth transistor and a first capacitor.
  • One end of the first capacitor is connected to the drain of the third transistor, and the other end of the first capacitor is connected to the drain of the fourth transistor and the source of the fifth transistor.
  • the pole is connected, the gate of the fourth transistor is connected to the driving signal output end of the shift register circuit of the first four stages of the shift register circuit, and the source of the fourth transistor and the gate of the shift register circuit of the first four stages
  • the signal output terminal is connected, the gate of the fifth transistor is connected to the drive signal output end of the shift register circuit of the first two stages, and the drain of the fifth transistor is connected to the first node.
  • the first pull-down holding circuit includes: a fourth transistor, a gate and a source of the fourth transistor are connected to the first clock signal, a drain is connected to the second node, and a gate and a driving of the fifth transistor and the fifth transistor are The signal terminal is connected, the source is connected to the second node, and the drain is connected to the second reference voltage; the sixth transistor, the gate of the sixth transistor is connected to the driving signal output end of the shift register circuit of the first two stages, and the source is The second node is connected, the drain is connected to the second reference voltage; the seventh transistor, the gate of the seventh transistor is connected to the second clock signal, the source is connected to the first clock signal, and the drain is connected to the second node; The transistor, the gate of the eighth transistor is connected to the compensation circuit, the source is connected to the gate signal output end of the shift register circuit, the drain is connected to the first reference voltage, and the ninth transistor, the gate of the ninth transistor and the compensation circuit Connected, the source is connected to the first node, the drain is connected to the
  • the compensation circuit includes: a first capacitor, one end of the first capacitor is connected to the second node, and the other end is connected to the gate of the eighth transistor, the gate of the ninth transistor, and the gate of the tenth transistor; the eleventh transistor The gate of the eleventh transistor is connected to the driving signal output end of the shift register circuit of the first two stages of the shift register circuit, the source is connected to the first node, and the drain is connected to the other end of the first capacitor.
  • the compensation circuit includes: a first capacitor, one end of the first capacitor is connected to the second node, and the other end is connected to the gate of the eighth transistor, the gate of the ninth transistor, and the gate of the tenth transistor; the eleventh transistor The gate of the eleventh transistor is connected to the first node of the shift register circuit of the latter two stages of the shift register circuit, the source is connected to the third reference voltage, and the drain is connected to the other end of the first capacitor; a second transistor, the gate of the twelfth transistor is connected to the other end of the first capacitor, the source is connected to the first node of the shift register circuit of the latter two stages; the thirteenth transistor, the gate and the shift of the thirteenth transistor The drive signal output terminal of the shift register circuit of the latter two stages of the bit register circuit is connected, the source is connected to one end of the first capacitor, and the drain is connected to the drain of the twelfth transistor.
  • Each of the shift register circuits further includes a second pull-down holding circuit
  • the second pull-down holding circuit includes: a fourth transistor, a gate of the fourth transistor, and a driving signal of the shift register circuit of the last four stages of the shift register circuit The output terminal is connected, the source is connected to the first node, and the drain is connected to the first reference voltage; the fifth transistor, the gate of the fifth transistor is connected to the driving signal output end of the shift register circuit of the last four stages, and the source is The signal output terminal of the shift register circuit is connected, and the drain is connected to the first reference voltage.
  • Each shift register circuit further includes a pull-down circuit
  • the pull-down circuit includes: a sixth transistor, a gate of the sixth transistor is connected to a driving signal output end of the shift register circuit of the last two stages of the shift register circuit, and the source Connected to the driving signal output end of the shift register circuit, the drain and the second reference voltage are leveled; the seventh transistor, the gate of the seventh transistor is connected to the driving signal output end of the shift register circuit of the latter two stages, the source Connected to the first node, the drain is connected to the first reference voltage; the eighth transistor, the gate of the eighth transistor is connected to the driving signal output end of the shift register circuit of the last two stages, and the signal of the source and the shift register circuit The output is connected, and the drain is connected to the first reference voltage.
  • the present invention also provides a liquid crystal display panel including a gate driving circuit and a plurality of gate lines, wherein the gate lines are respectively connected to gate signal output ends of corresponding shift register circuits in the gate driving circuit, and the gate electrodes
  • the driving circuit includes a plurality of shift register circuits, and the plurality of shift register circuits are cascaded in series.
  • Each shift register circuit includes: a pull-up circuit including a first transistor, the gate of the first transistor being coupled to a first node, a source coupled to the first clock signal, a drain coupled to the gate signal output of the shift register circuit, a lower pass circuit including a second transistor, and a gate coupled to the second transistor a node, the source is coupled to the first clock signal, the drain is coupled to the drive signal output end of the shift register circuit, and the pull-up control circuit includes a third transistor, and the gate of the third transistor is coupled to the a drive signal output end of the shift register circuit of the first two stages of the shift register circuit, the source is coupled to the gate signal output end of the shift register circuit of the first two stages, and the drain is coupled to the first node; Circuit, Connected between the first node and the gate signal output end of the shift register circuit for raising the potential of the first node; the first pull-down holding circuit is coupled to the first node, the first clock signal, and the first reference The voltage and the second reference voltage are used to maintain the
  • the compensation circuit includes a fourth transistor, and the source and the gate of the fourth transistor are both coupled to the drive signal output end of the shift register circuit of the next stage of the shift register circuit where the shift register circuit is located, and the drain of the fourth transistor And connected to the first node, for raising the potential of the first node according to the driving signal outputted by the driving signal output end of the shift register circuit of the next stage.
  • the compensation circuit further includes a fifth transistor, a sixth transistor, and a first capacitor.
  • One end of the first capacitor is connected to the drain of the third transistor, and the other end of the first capacitor is connected to the drain of the fifth transistor and the sixth transistor.
  • the source is connected, and the gate of the fifth transistor is connected to the driving signal output end of the shift register circuit of the first four stages of the shift register circuit in which the shift transistor is located, and the source of the fifth transistor and the gate of the shift register circuit of the first four stages
  • the pole signal output terminal is connected, the gate of the sixth transistor is connected to the drive signal output end of the shift register circuit of the first two stages, and the drain of the sixth transistor is connected to the first node.
  • the compensation circuit includes a fourth transistor, a fifth transistor and a first capacitor.
  • One end of the first capacitor is connected to the drain of the third transistor, and the other end of the first capacitor is connected to the drain of the fourth transistor and the source of the fifth transistor.
  • the pole is connected, the gate of the fourth transistor is connected to the driving signal output end of the shift register circuit of the first four stages of the shift register circuit, and the source of the fourth transistor and the gate of the shift register circuit of the first four stages
  • the signal output terminal is connected, the gate of the fifth transistor is connected to the drive signal output end of the shift register circuit of the first two stages, and the drain of the fifth transistor is connected to the first node.
  • the first pull-down holding circuit includes: a fourth transistor, a gate and a source of the fourth transistor are connected to the first clock signal, a drain is connected to the second node, and a gate and a driving of the fifth transistor and the fifth transistor are The signal terminal is connected, the source is connected to the second node, and the drain is connected to the second reference voltage; the sixth transistor, the gate of the sixth transistor is connected to the driving signal output end of the shift register circuit of the first two stages, and the source is The second node is connected, the drain is connected to the second reference voltage; the seventh transistor, the gate of the seventh transistor is connected to the second clock signal, the source is connected to the first clock signal, and the drain is connected to the second node; The transistor, the gate of the eighth transistor is connected to the compensation circuit, the source is connected to the gate signal output end of the shift register circuit, the drain is connected to the first reference voltage, and the ninth transistor, the gate of the ninth transistor and the compensation circuit Connected, the source is connected to the first node, the drain is connected to the
  • the compensation circuit includes: a first capacitor, one end of the first capacitor is connected to the second node, and the other end is connected to the gate of the eighth transistor, the gate of the ninth transistor, and the gate of the tenth transistor; the eleventh transistor The gate of the eleventh transistor is connected to the driving signal output end of the shift register circuit of the first two stages of the shift register circuit, the source is connected to the first node, and the drain is connected to the other end of the first capacitor.
  • the compensation circuit includes: a first capacitor, one end of the first capacitor is connected to the second node, and the other end is connected to the gate of the eighth transistor, the gate of the ninth transistor, and the gate of the tenth transistor; the eleventh transistor The gate of the eleventh transistor is connected to the first node of the shift register circuit of the latter two stages of the shift register circuit, the source is connected to the third reference voltage, and the drain is connected to the other end of the first capacitor; a second transistor, the gate of the twelfth transistor is connected to the other end of the first capacitor, the source is connected to the first node of the shift register circuit of the latter two stages; the thirteenth transistor, the gate and the shift of the thirteenth transistor The drive signal output terminal of the shift register circuit of the latter two stages of the bit register circuit is connected, the source is connected to one end of the first capacitor, and the drain is connected to the drain of the twelfth transistor.
  • Each of the shift register circuits further includes a second pull-down holding circuit
  • the second pull-down holding circuit includes: a fourth transistor, a gate of the fourth transistor, and a driving signal of the shift register circuit of the last four stages of the shift register circuit The output terminal is connected, the source is connected to the first node, and the drain is connected to the first reference voltage; the fifth transistor, the gate of the fifth transistor is connected to the driving signal output end of the shift register circuit of the last four stages, and the source is The signal output terminal of the shift register circuit is connected, and the drain is connected to the first reference voltage.
  • Each shift register circuit further includes a pull-down circuit
  • the pull-down circuit includes: a sixth transistor, a gate of the sixth transistor is connected to a driving signal output end of the shift register circuit of the last two stages of the shift register circuit, and the source Connected to the driving signal output end of the shift register circuit, the drain and the second reference voltage are leveled; the seventh transistor, the gate of the seventh transistor is connected to the driving signal output end of the shift register circuit of the latter two stages, the source Connected to the first node, the drain is connected to the first reference voltage; the eighth transistor, the gate of the eighth transistor is connected to the driving signal output end of the shift register circuit of the last two stages, and the signal of the source and the shift register circuit The output is connected, and the drain is connected to the first reference voltage.
  • the present invention has the beneficial effects that the present invention is coupled to the first node or the first pull-down holding circuit through the compensation circuit for compensating the potential of the first node or the first pull-down holding circuit, and can improve the gate.
  • the stability of the drive circuit for long-term operation thereby improving the quality of the display panel.
  • FIG. 1 is a schematic structural view of a gate driving circuit according to a first embodiment of the present invention
  • FIG. 2 is a circuit diagram of the gate driving circuit of FIG. 1;
  • Figure 3 is a circuit diagram of a gate driving circuit of a second embodiment of the present invention.
  • FIG. 4 is a timing diagram of various input signals, output signals, and node voltages of the gate driving circuit of FIG. 3;
  • Figure 5 is a circuit diagram of a gate driving circuit of a third embodiment of the present invention.
  • Figure 6 is a circuit diagram of a gate driving circuit of a fourth embodiment of the present invention.
  • FIG. 7 is a timing diagram of various input signals, output signals, and node voltages of the gate driving circuit of FIG. 6;
  • Figure 8 is a circuit diagram of a gate driving circuit of a fifth embodiment of the present invention.
  • Figure 9 is a circuit diagram of a gate driving circuit of a sixth embodiment of the present invention.
  • FIG. 10 is a schematic structural view of a liquid crystal display panel according to a first embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a gate driving circuit according to a first embodiment of the present invention.
  • the gate driving circuit 1 disclosed in this embodiment includes a plurality of shift register circuits 10, and a plurality of shift register circuits 10 are cascaded in series.
  • the plurality of shift register circuits 10 include a pull-up circuit 101, a down-transfer circuit 102, a pull-up control circuit 103, a rising circuit 104, a first pull-down holding circuit 105, and a compensation circuit 106.
  • the pull-up circuit 101 includes a transistor T1.
  • the gate of the transistor T1 is coupled to the first node Q(N) of the shift register circuit 10, that is, the Q(N) point of the shift register circuit 10;
  • the source of T1 is coupled to the first clock signal CK; the drain of the transistor T1 is coupled to the gate signal output terminal G(N) of the shift register circuit 10.
  • the downstream circuit 102 includes a transistor T2.
  • the gate of the transistor T2 is coupled to the first node Q(N), the source of the transistor T2 is coupled to the first clock signal CK, and the drain of the transistor T2 is coupled to the shift register circuit.
  • the pull-up control circuit 103 includes a transistor T3 whose gate is coupled to the drive signal output terminal ST(N-2) of the shift register circuit of the first two stages of the shift register circuit 10 where the transistor T3 is located, and the transistor T3 The source is coupled to the gate signal output terminal G(N-2) of the shift register circuit of the first two stages, and the drain of the transistor T3 is coupled to the first node Q.
  • the rising circuit 104 is coupled between the first node Q(N) and the gate signal output terminal G(N) of the shift register circuit 10 for raising the potential of the first node Q(N).
  • the first pull-down holding circuit 105 is coupled to the first node Q(N), the first clock signal CK, the first reference voltage V1, and the second reference voltage V2 for maintaining the low level of the first node Q(N) .
  • the compensation circuit 106 is coupled to the first node Q(N) or the first pull-down holding circuit 105 for compensating the potential of the first node Q(N) or the first pull-down holding circuit 105.
  • the first reference voltage V1 and the second reference voltage V2 are both negative potentials, and the second reference voltage V2 is smaller than the first reference voltage V1.
  • the compensation circuit 106 is coupled to the first node Q(N) or the first pull-down holding circuit 105 for compensating the potential of the first node Q(N) or the first pull-down holding circuit 105, thereby improving the gate.
  • the present invention also provides a gate driving circuit of the second embodiment, which is described in detail based on the gate driving circuit 1 disclosed in the first embodiment.
  • the compensation circuit 106 includes a transistor T4, and the gate and the source of the transistor T4 are both coupled to the drive signal output terminal ST of the shift register circuit of the next stage of the shift register circuit 10 where the transistor T4 is located ( N+1), the drain of the transistor T4 is connected to the first node Q(N).
  • the compensation circuit 106 is for boosting the potential of the first node Q(N) in accordance with the drive signal output from the drive signal output terminal ST(N+1) of the shift register circuit of the next stage.
  • the rising circuit 104 includes a capacitor C1. One end of the capacitor C1 is connected to the first node Q(N), and the other end of the capacitor C1 is connected to the gate signal output terminal G(N) of the shift register circuit 10.
  • the first pull-down holding circuit 105 includes a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, and a transistor T11. The gate and the source of the transistor T5 are both connected to the first clock signal CK, and the drain of the transistor T5.
  • the node P(N) is connected; the gate of the transistor T7 is connected to the driving signal output terminal ST(N) of the shift register circuit 10, the source of the transistor T7 is connected to the second node P(N), and the drain of the transistor T7 is The second reference voltage V2 is connected; the gate of the transistor T8 is connected to the gate of the transistor T3, the source of the transistor T8 is connected to the second node P(N), and the drain of the transistor T8 is connected to the second reference voltage V2; the transistor T9 The gate is connected to the second node P(N), the source of the transistor T9 is connected to the gate signal output terminal G(N) of the shift register circuit 10, and the drain of the transistor T9 is connected to the first reference voltage V1; Gate of T10
  • the gate driving circuit further includes a second pull-down holding circuit 107 and a pull-down circuit 108.
  • the second pull-down holding circuit 107 includes a transistor T12 and a transistor T13.
  • the gate of the transistor T12 and the gate of the transistor T13 are both under the shift register circuit 10.
  • the driving signal output terminal ST(N+4) of the four-stage shift register circuit is connected, the source of the transistor T12 is connected to the first node Q(N), and the drain of the transistor T12 is connected to the first reference voltage V1, and the transistor T13
  • the source is connected to the gate signal output terminal G(N), and the drain of the transistor T13 is connected to the first reference voltage V1.
  • the pull-down circuit 108 includes a transistor T14, a transistor T15, and a transistor T16.
  • the gate of the transistor T14, the gate of the transistor T15, and the gate of the transistor T16 are both connected to the drive signal output terminal ST of the shift register circuit of the next two stages (N+2).
  • the source of the transistor T14 is connected to the driving signal output terminal ST(N)
  • the drain of the transistor T14 is connected to the second reference voltage V2
  • the source of the transistor T15 is connected to the first node Q(N)
  • the transistor T15 The drain is connected to the first reference voltage V1
  • the source of the transistor T16 is connected to the gate signal output terminal G(N)
  • the drain of the transistor T16 is connected to the first reference voltage V1.
  • FIG. 4 is a timing diagram of various input signals, output signals, and node voltages of the gate driving circuit of FIG.
  • the first clock signal CK and the second clock signal XCK are two sets of signals complementary in phase.
  • the first clock signal CK1 and the second clock signal XCK1 are complementary in phase
  • the first clock signal CK2 and the first The two clock signals XCK2 are phase complementary.
  • the potential of the gate signal output terminal G(N) is pulled low to the low potential by the first reference voltage V1; at the first node Q(N) and the gate signal output terminal G(N) All
  • the gate driving circuit disclosed in this embodiment is coupled to the driving signal output terminal ST of the shift register circuit of the next stage of the shift register circuit 10 where the transistor T4 is located through the gate and the source of the transistor T4 (N+). 1), the drain of the transistor T4 is connected to the first node Q(N), and the compensation circuit 106 is used to raise the first driving signal according to the output of the driving signal output terminal ST(N+1) of the shift register circuit of the next stage.
  • the potential of the node Q(N) in turn, can improve the stability of the long-term operation of the gate drive circuit.
  • the present invention also provides a gate driving circuit of the third embodiment, which is described in detail based on the gate driving circuit 1 disclosed in the first embodiment.
  • the compensation circuit 106 includes a transistor T4, a transistor T5, a transistor T6, and a capacitor C1.
  • the gate and the source of the transistor T4 are both coupled to the drive signal output terminal ST(N+1) of the shift register circuit of the next stage of the shift register circuit 10 where the transistor T4 is located, and the drain of the transistor T4 is The first node Q(N) is connected.
  • One end of the capacitor C1 is connected to the drain of the transistor T3, and the other end of the capacitor C1 is connected to the drain of the transistor T5 and the source of the transistor T6, and the gate of the transistor T5 is shifted from the first four stages of the shift register circuit in which it is located.
  • the drive signal output terminal ST(N-4) of the register circuit is connected, and the source of the transistor T5 is connected to the gate signal output terminal G(N-4) of the shift register circuit of the first four stages, and the gate of the transistor T6 is before
  • the drive signal output terminal ST(N-2) of the two-stage shift register circuit is connected, and the drain of the transistor T6 is connected to the first node Q(N).
  • the rising circuit 104 includes a capacitor C2. One end of the capacitor C2 is connected to the first node Q(N), and the other end of the capacitor C2 is connected to the gate signal output terminal G(N) of the shift register circuit 10.
  • the first pull-down holding circuit 105 includes a transistor T7, a transistor T8, a transistor T9, a transistor T10, a transistor T11, a transistor T12, and a transistor T13.
  • the gate and the source of the transistor T7 are both connected to the first clock signal CK, and the drain of the transistor T7
  • the node P(N) is connected; the gate of the transistor T9 is connected to the driving signal output terminal ST(N) of the shift register circuit 10, the source of the transistor T9 is connected to the second node P(N), and the drain of the transistor T9 is
  • the second reference voltage V2 is connected; the gate of the transistor T10 is connected to the gate of the transistor T3, the source of the transistor T10 is connected to the second node P(N), and the drain of the transistor T10 is connected to the second reference voltage V2; the transistor T11 The gate is connected to the second node P(N), the source of the transistor T11 is connected to the gate signal output
  • the gate driving circuit further includes a second pull-down holding circuit 107 and a pull-down circuit 108.
  • the second pull-down holding circuit 107 includes a transistor T14 and a transistor T15.
  • the gate of the transistor T14 and the gate of the transistor T15 are both under the shift register circuit 10.
  • the driving signal output terminal ST(N+4) of the four-stage shift register circuit is connected, the source of the transistor T14 is connected to the first node Q(N), and the drain of the transistor T14 is connected to the first reference voltage V1, and the transistor T15
  • the source is connected to the gate signal output terminal G(N), and the drain of the transistor T15 is connected to the first reference voltage V1.
  • the pull-down circuit 108 includes a transistor T16, a transistor T17, and a transistor T18.
  • the gate of the transistor T16, the gate of the transistor T17, and the gate of the transistor T18 are both connected to the drive signal output terminal ST of the lower two stages of the shift register circuit (N+2). Connected, the source of the transistor T16 is connected to the drive signal output terminal ST(N), the drain of the transistor T16 is connected to the second reference voltage V2, and the source of the transistor T17 is connected to the first node Q(N), the transistor T17 The drain is connected to the first reference voltage V1, the source of the transistor T18 is connected to the gate signal output terminal G(N), and the drain of the transistor T18 is connected to the first reference voltage V1.
  • the driving signal output terminal ST(N-4) of the shift register circuit of the first four stages and the gate signal output terminal G(N-4) of the shift register circuit of the first four stages perform the first stage charging of the capacitor C1.
  • the drive signal output terminal ST(N-2) of the shift register circuit of the first two stages and the gate signal output terminal G(N-2) of the shift register circuit of the first two stages lift the capacitor C2 twice, Before the first node Q(N) is charged, the first node Q(N) has a better potential in the first stage, that is, equivalent to twice the unprocessed, and the potential rise of the first node Q(N) during the action Will be higher, improve the stability of the long-term operation of the gate drive circuit.
  • the present invention also provides a gate driving circuit of the fourth embodiment, which is described in detail based on the gate driving circuit 1 disclosed in the first embodiment.
  • the compensation circuit 106 includes a transistor T4, a transistor T5, and a capacitor C1.
  • One end of the capacitor C1 is connected to the drain of the transistor T3, the other end of the capacitor C1 is connected to the drain of the transistor T4 and the source of the transistor T5, and the gate of the transistor T4 is shifted with the first four stages of the shift register circuit in which it is located.
  • the drive signal output terminal ST(N-4) of the register circuit is connected, and the source of the transistor T4 is connected to the gate signal output terminal G(N-4) of the shift register circuit of the first four stages, and the gate of the transistor T5 is before and The drive signal output terminal ST(N-2) of the two-stage shift register circuit is connected, and the drain of the transistor T5 is connected to the first node Q(N).
  • the rising circuit 104 includes a capacitor C2 having one end connected to the first node Q(N) and the other end of the capacitor C2 connected to the gate signal output terminal G(N) of the shift register circuit 10.
  • the first pull-down holding circuit 105 includes a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, a transistor T11, and a transistor T12. The gate and the source of the transistor T6 are both connected to the first clock signal CK, and the drain of the transistor T6.
  • the gate driving circuit further includes a second pull-down holding circuit 107 and a pull-down circuit 108.
  • the second pull-down holding circuit 107 includes a transistor T13 and a transistor T14.
  • the gate of the transistor T13 and the gate of the transistor T14 are both under the shift register circuit 10.
  • the driving signal output terminal ST(N+4) of the four-stage shift register circuit is connected, the source of the transistor T13 is connected to the first node Q(N), and the drain of the transistor T13 is connected to the first reference voltage V1, and the transistor T14 The source is connected to the gate signal output terminal G(N), and the drain of the transistor T14 is connected to the first reference voltage V1.
  • the pull-down circuit 108 includes a transistor T15, a transistor T16, and a transistor T17.
  • the gate of the transistor T15, the gate of the transistor T16, and the gate of the transistor T17 are both driven by the drive signal output terminal ST of the lower two stages of the shift register circuit (N+2).
  • the source of the transistor T15 is connected to the drive signal output terminal ST(N)
  • the drain of the transistor T15 is connected to the second reference voltage V2
  • the source of the transistor T16 is connected to the first node Q(N)
  • the transistor T16 The drain is connected to the first reference voltage V1
  • the source of the transistor T17 is connected to the gate signal output terminal G(N)
  • the drain of the transistor T17 is connected to the first reference voltage V1.
  • FIG. 7 is a timing diagram of various input signals, output signals, and node voltages of the gate driving circuit of FIG.
  • the first clock signal CK and the second clock signal XCK are two sets of signals complementary in phase.
  • the first clock signal CK1 and the second clock signal XCK1 are complementary in phase
  • the first clock signal CK2 and the first The two clock signals XCK2 are phase complementary.
  • the driving signal output terminal ST(N-4) of the shift register circuit of the first four stages and the gate signal output terminal G(N-4) of the shift register circuit of the first four stages perform the first stage charging of the capacitor C1.
  • the drive signal output terminal ST(N-2) of the shift register circuit of the first two stages and the gate signal output terminal G(N-2) of the shift register circuit of the first two stages lift the capacitor C2 twice, Before the first node Q(N) is charged, the first node Q(N) has a better potential in the first stage, that is, equivalent to twice the unprocessed, and the potential rise of the first node Q(N) during the action Will be higher, improve the stability of the long-term operation of the gate drive circuit.
  • the present invention also provides a gate driving circuit of the fifth embodiment, which is described in detail based on the gate driving circuit 1 disclosed in the first embodiment.
  • the first pull-down holding circuit 105 includes a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, and a transistor T10.
  • the gate and the source of the transistor T4 are connected to the first clock signal CK, and the drain of the transistor T4 is connected to the second node P(N).
  • the gate of the transistor T5 is connected to the driving signal terminal ST(N), the source of the transistor T5 is connected to the second node P(N), and the drain of the transistor T5 is connected to the second reference voltage V2.
  • the gate of the transistor T6 is connected to the driving signal output terminal ST(N-2) of the shift register circuit of the first two stages, the source of the transistor T6 is connected to the second node P(N), and the drain and the second of the transistor T6 are connected.
  • the reference voltage V2 is connected.
  • the gate of the transistor T7 is connected to the second clock signal XCK, the source of the transistor T7 is connected to the first clock signal CK, and the drain of the transistor T7 is connected to the second node P(N).
  • the gate of the transistor T8 is connected to the compensation circuit 106, the source of the transistor T8 is connected to the gate signal output terminal G(N) of the shift register circuit, and the drain of the transistor T8 is connected to the first reference voltage V1.
  • the gate of the transistor T9 is connected to the compensation circuit 106, the source of the transistor T9 is connected to the first node Q(N), and the drain of the transistor T9 is connected to the first reference voltage V1.
  • the gate of the transistor T10 is connected to the compensation circuit 106, the source of the transistor T10 is connected to the drive signal output terminal ST(N) of the shift register circuit, and the drain of the transistor T10 is connected to the second reference voltage V2.
  • the compensation circuit 106 includes a capacitor C1 and a transistor T11. One end of the capacitor C1 is connected to the second node P(N), and the other end of the capacitor C1 is connected to the gate of the transistor T8, the gate of the transistor T9, and the gate of the transistor T10.
  • the gate of the transistor T11 is connected to the drive signal output terminal ST(N-2) of the shift register circuit of the first two stages of the shift register circuit 10, and the source of the transistor T11 is connected to the first node Q(N), and the transistor T11 The drain is connected to the other end of the capacitor C1.
  • the rising circuit 104 includes a capacitor C2. One end of the capacitor C2 is connected to the first node Q(N), and the other end of the capacitor C2 is connected to the gate signal output terminal G(N) of the shift register circuit 10.
  • the gate driving circuit further includes a second pull-down holding circuit 107 and a pull-down circuit 108.
  • the second pull-down holding circuit 107 includes a transistor T12 and a transistor T13.
  • the gate of the transistor T12 and the gate of the transistor T13 are both under the shift register circuit 10.
  • the driving signal output terminal ST(N+4) of the four-stage shift register circuit is connected, the source of the transistor T12 is connected to the first node Q(N), and the drain of the transistor T12 is connected to the first reference voltage V1, and the transistor T13
  • the source is connected to the gate signal output terminal G(N), and the drain of the transistor T13 is connected to the first reference voltage V1.
  • the pull-down circuit 108 includes a transistor T14, a transistor T15, and a transistor T16.
  • the gate of the transistor T14, the gate of the transistor T15, and the gate of the transistor T16 are both connected to the drive signal output terminal ST of the shift register circuit of the next two stages (N+2).
  • the source of the transistor T14 is connected to the driving signal output terminal ST(N)
  • the drain of the transistor T14 is connected to the second reference voltage V2
  • the source of the transistor T15 is connected to the first node Q(N)
  • the transistor T15 The drain is connected to the first reference voltage V1
  • the source of the transistor T16 is connected to the gate signal output terminal G(N)
  • the drain of the transistor T16 is connected to the first reference voltage V1.
  • the compensation circuit 106 enhances the potential of the second node P(N) through the capacitor C1 and the transistor T11, and can also be turned on when the transistor T8, the transistor T9, and the transistor T10 are severely stressed.
  • the present invention also provides a gate driving circuit of the sixth embodiment, which is described in detail based on the gate driving circuit 1 disclosed in the first embodiment.
  • the first pull-down holding circuit 105 includes a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, and a transistor T10.
  • the gate and the source of the transistor T4 are connected to the first clock signal CK, and the drain of the transistor T4 is connected to the second node P(N).
  • the gate of the transistor T5 is connected to the driving signal terminal ST(N), the source of the transistor T5 is connected to the second node P(N), and the drain of the transistor T5 is connected to the second reference voltage V2.
  • the gate of the transistor T6 is connected to the driving signal output terminal ST(N-2) of the shift register circuit of the first two stages, the source of the transistor T6 is connected to the second node P(N), and the drain and the second of the transistor T6 are connected.
  • the reference voltage V2 is connected.
  • the gate of the transistor T7 is connected to the second clock signal XCK, the source of the transistor T7 is connected to the first clock signal CK, and the drain of the transistor T7 is connected to the second node P(N).
  • the gate of the transistor T8 is connected to the compensation circuit 106, the source of the transistor T8 is connected to the gate signal output terminal G(N) of the shift register circuit, and the drain of the transistor T8 is connected to the first reference voltage V1.
  • the gate of the transistor T9 is connected to the compensation circuit 106, the source of the transistor T9 is connected to the first node Q(N), and the drain of the transistor T9 is connected to the first reference voltage V1.
  • the gate of the transistor T10 is connected to the compensation circuit 106, the source of the transistor T10 is connected to the drive signal output terminal ST(N) of the shift register circuit, and the drain of the transistor T10 is connected to the second reference voltage V2.
  • the compensation circuit 106 includes a capacitor C1, a transistor T11, a transistor T12, and a transistor T13.
  • One end of the capacitor C1 is connected to the second node P(N)
  • the other end of the capacitor C1 is connected to the gate of the transistor T8, the gate of the transistor T9, and
  • the gate of transistor T10 is connected.
  • the gate of the transistor T11 is connected to the first node Q(N+2) of the shift register circuit of the latter two stages of the shift register circuit 10, the source of the transistor T11 is connected to the third reference voltage V3, and the drain of the transistor T11 Connected to the other end of the capacitor C1.
  • the gate of the transistor T12 is connected to the other end of the capacitor C1, and the source of the transistor T12 is connected to the first node Q (N+2) of the shift register capacitor of the latter two stages.
  • the gate of the transistor T13 is connected to the driving signal output terminal ST(N+2) of the shift register circuit of the latter two stages of the shift register circuit 10.
  • the source of the transistor T13 is connected to one end of the capacitor C1, and the drain of the transistor T13 is connected. Connected to the drain of transistor T12.
  • the rising circuit 104 includes a capacitor C2. One end of the capacitor C2 is connected to the first node Q(N), and the other end of the capacitor C2 is connected to the gate signal output terminal G(N) of the shift register circuit 10.
  • the gate driving circuit further includes a second pull-down holding circuit 107 and a pull-down circuit 108.
  • the second pull-down holding circuit 107 includes a transistor T14 and a transistor T15.
  • the gate of the transistor T14 and the gate of the transistor T15 are both under the shift register circuit 10.
  • the driving signal output terminal ST(N+4) of the four-stage shift register circuit is connected, the source of the transistor T14 is connected to the first node Q(N), and the drain of the transistor T14 is connected to the first reference voltage V1, and the transistor T15
  • the source is connected to the gate signal output terminal G(N), and the drain of the transistor T15 is connected to the first reference voltage V1.
  • the pull-down circuit 108 includes a transistor T16, a transistor T17, and a transistor T18.
  • the gate of the transistor T16, the gate of the transistor T17, and the gate of the transistor T18 are both connected to the drive signal output terminal ST of the lower two stages of the shift register circuit (N+2). Connected, the source of the transistor T16 is connected to the drive signal output terminal ST(N), the drain of the transistor T16 is connected to the second reference voltage V2, and the source of the transistor T17 is connected to the first node Q(N), the transistor T17 The drain is connected to the first reference voltage V1, the source of the transistor T18 is connected to the gate signal output terminal G(N), and the drain of the transistor T18 is connected to the first reference voltage V1.
  • the compensation circuit 106 enhances the potential of the second node P(N) through the capacitor C1, the transistor T11, the transistor T12, and the transistor T13, and compensates for the voltage drift of the transistor T8, the transistor T9, and the transistor T10, in the transistor T8, the transistor T9, and the transistor T10. In the case of severe stress, it can also be opened.
  • the present invention enhances the potential of the first node Q(N), implements a third-order charging principle on the first node Q(N), and can ensure the normal output of the gate driving circuit 1;
  • a compensation circuit 106 for the second node P(N) is provided. Avoiding the potential abnormality of the second node P(N) will result in insufficient pull-down capability of the first node Q(N) and the second node G(N), directly resulting in The circuit fails, and the compensation circuit 106 can prevent the problem that the pull-down holding portion of the circuit is not activated due to the threshold voltage drift of the transistor.
  • the present invention also provides a liquid crystal display panel.
  • the liquid crystal display panel 2 includes the above-described gate driving circuit 1 and a plurality of gate lines 20, wherein the gate lines 20 are respectively associated with the gate driving circuit 1.
  • the gate signal output terminal G(N) corresponding to the shift register circuit 10 is connected.
  • the present invention is coupled to the first node or the first pull-down holding circuit through the compensation circuit for compensating the potential of the first node or the first pull-down holding circuit, thereby improving the stability of the long-term operation of the gate driving circuit. Sex, which in turn improves the quality of the display panel.

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Abstract

一种液晶显示面板及其栅极驱动电路。该栅极驱动电路包括多个级联的移位寄存电路（10），每一移位寄存电路（10）包括：上拉电路（101）、下传电路（102）、上拉控制电路（103）、上升电路（104）、第一下拉保持电路（105）以及补偿电路（106）。其中上升电路（104）耦接于第一节点（Q（N））和栅极信号输出端（G（N））之间，用于抬升所述第一节点（Q（N））的电位；补偿电路（106），耦接于所述第一节点（Q（N））或者所述第一下拉保持电路（105），用于补偿所述第一节点（Q（N））或者所述第一下拉保持电路（105）的电位；以此提高了栅极驱动电路长期操作的稳定性，进而提高液晶显示面板的质量。

Description

液晶显示面板及其栅极驱动电路
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种液晶显示面板及其栅极驱动电路。
【背景技术】
GOA（Gate Driver On Array）电路是利用现有的薄膜晶体管液晶显示器Array制程将栅极扫描驱动电路制作在Array基板上，以实现逐行扫描的驱动方式。
其中，GOA电路包括上拉电路（Pull-up circuit）、上拉控制电路（Pull-up control circuit）、下传电路（Transfer circuit）、下拉电路（Pull-down Holding circuit）以及负责电位抬升的上升电路（Boost circuit）。
具体地，上拉电路主要负责将输入的时钟讯号（Clock）输出至薄膜晶体管的栅极，作为液晶显示器的驱动信号。上拉控制电路负责控制上拉电路的打开，一般是由上级GOA电路传递来的信号作用。下拉电路负责在输出扫描信号后，快速将扫描信号拉低为低电位，即薄膜晶体管的栅极的电位拉低为低电位；下拉保持电路则负责将扫描信号和上拉电路的信号（通常称为Q点） 保持在关闭状态（即设定的负电位），通常有两个下拉保持电路交替作用。上升电路则负责Q点电位的二次抬升，这样确保上拉电路的G(N)正常输出。
现有的GOA电路经过长时间的操作，GOA电路的稳定性差，可能会导致GOA电路失效。
【发明内容】
本发明实施例提供了一种液晶显示面板及其栅极驱动电路，以提高栅极驱动电路长期操作的稳定性。
本发明提供一种栅极驱动电路，其包括多个移位寄存电路，多个移位寄存电路以串联方式进行级联，每一移位寄存电路包括：上拉电路，其包括第一晶体管，第一晶体管的栅极耦接于第一节点，源极耦接于第一时钟信号，漏极耦接于移位寄存电路的栅极信号输出端；下传电路，其包括第二晶体管，第二晶体管的栅极耦接于第一节点，源极耦接于第一时钟信号，漏极耦接于移位寄存电路的驱动信号输出端；上拉控制电路，其包括第三晶体管，第三晶体管的栅极耦接于其所在的移位寄存电路的前两级的移位寄存电路的驱动信号输出端，源极耦接于前两级的移位寄存电路的栅极信号输出端，漏极耦接于第一节点；上升电路，耦接于第一节点和移位寄存电路的栅极信号输出端之间，用于抬升第一节点的电位；第一下拉保持电路，耦接于第一节点、第一时钟信号、第一参考电压以及第二参考电压，用于保持第一节点的低电平；补偿电路，耦接于第一节点或者第一下拉保持电路，用于补偿第一节点或者第一下拉保持电路的电位。
其中，补偿电路包括第四晶体管，第四晶体管的源极和栅极均耦接于其所在的移位寄存电路的下一级的移位寄存电路的驱动信号输出端，第四晶体管的漏极与第一节点连接，用于根据下一级的移位寄存电路的驱动信号输出端输出的驱动信号抬升第一节点的电位。
其中，补偿电路还包括第五晶体管、第六晶体管以及第一电容，第一电容的一端与第三晶体管的漏极连接，第一电容的另一端与第五晶体管的漏极和第六晶体管的源极连接，第五晶体管的栅极与其所在的移位寄存电路的前四级的移位寄存电路的驱动信号输出端连接，第五晶体管的源极与前四级的移位寄存电路的栅极信号输出端连接，第六晶体管的栅极与前两级的移位寄存电路的驱动信号输出端连接，第六晶体管的漏极与第一节点连接。
其中，补偿电路包括第四晶体管、第五晶体管以及第一电容，第一电容的一端与第三晶体管的漏极连接，第一电容的另一端与第四晶体管的漏极和第五晶体管的源极连接，第四晶体管的栅极与其所在的移位寄存电路的前四级的移位寄存电路的驱动信号输出端连接，第四晶体管的源极与前四级的移位寄存电路的栅极信号输出端连接，第五晶体管的栅极与前两级的移位寄存电路的驱动信号输出端连接，第五晶体管的漏极与第一节点连接。
其中，第一下拉保持电路包括：第四晶体管，第四晶体管的栅极和源极与第一时钟信号连接，漏极与第二节点连接；第五晶体管，第五晶体管的栅极与驱动信号端连接，源极与第二节点连接，漏极与第二参考电压连接；第六晶体管，第六晶体管的栅极与前两级的移位寄存电路的驱动信号输出端连接，源极与第二节点连接，漏极与第二参考电压连接；第七晶体管，第七晶体管的栅极与第二时钟信号连接，源极与第一时钟信号连接，漏极与第二节点连接；第八晶体管，第八晶体管的栅极与补偿电路连接，源极与移位寄存电路的栅极信号输出端连接，漏极与第一参考电压连接；第九晶体管，第九晶体管的栅极与补偿电路连接，源极与第一节点连接，漏极与第一参考电压连接；第十晶体管，第十晶体管的栅极与补偿电路连接，源极与移位寄存电路的驱动信号出端连接，漏极与第二参考电压连接。
其中，补偿电路包括：第一电容，第一电容的一端与第二节点连接，另一端与第八晶体管的栅极、第九晶体管的栅极以及第十晶体管的栅极连接；第十一晶体管，第十一晶体管的栅极与移位寄存电路的前两级的移位寄存电路的驱动信号输出端连接，源极与第一节点连接，漏极与第一电容的另一端连接。
其中，补偿电路包括：第一电容，第一电容的一端与第二节点连接，另一端与第八晶体管的栅极、第九晶体管的栅极以及第十晶体管的栅极连接；第十一晶体管，第十一晶体管的栅极与移位寄存电路的后两级的移位寄存电路的第一节点连接，源极与第三参考电压连接，漏极与第一电容的另一端连接；第十二晶体管，第十二晶体管的栅极与第一电容的另一端连接，源极与后两级的移位寄存电路的第一节点连接；第十三晶体管，第十三晶体管的栅极与移位寄存电路的后两级的移位寄存电路的驱动信号输出端连接，源极与第一电容的一端连接，漏极与第十二晶体管的漏极连接。
其中，每一移位寄存电路还包括第二下拉保持电路，第二下拉保持电路包括：第四晶体管，第四晶体管的栅极与移位寄存电路的后四级的移位寄存电路的驱动信号输出端连接，源极与第一节点连接，漏极与第一参考电压连接；第五晶体管，第五晶体管的栅极与后四级的移位寄存电路的驱动信号输出端连接，源极与移位寄存电路的信号输出端连接，漏极与第一参考电压连接。
其中，每一移位寄存电路还包括下拉电路，下拉电路包括：第六晶体管，第六晶体管的栅极与移位寄存电路的后两级的移位寄存电路的驱动信号输出端连接，源极与移位寄存电路的驱动信号输出端连接，漏极与第二参考电压练级；第七晶体管，第七晶体管的栅极与后两级的移位寄存电路的驱动信号输出端连接，源极与第一节点连接，漏极与第一参考电压连接；第八晶体管，第八晶体管的栅极与后两级的移位寄存电路的驱动信号输出端连接，源极与移位寄存电路的信号输出端连接，漏极与第一参考电压连接。
本发明还提供一种液晶显示面板，其包括栅极驱动电路以及多条栅极线，其中栅极线分别与栅极驱动电路中的对应移位寄存电路的栅极信号输出端连接，栅极驱动电路包括多个移位寄存电路，多个移位寄存电路以串联方式进行级联，每一移位寄存电路包括：上拉电路，其包括第一晶体管，第一晶体管的栅极耦接于第一节点，源极耦接于第一时钟信号，漏极耦接于移位寄存电路的栅极信号输出端；下传电路，其包括第二晶体管，第二晶体管的栅极耦接于第一节点，源极耦接于第一时钟信号，漏极耦接于移位寄存电路的驱动信号输出端；上拉控制电路，其包括第三晶体管，第三晶体管的栅极耦接于其所在的移位寄存电路的前两级的移位寄存电路的驱动信号输出端，源极耦接于前两级的移位寄存电路的栅极信号输出端，漏极耦接于第一节点；上升电路，耦接于第一节点和移位寄存电路的栅极信号输出端之间，用于抬升第一节点的电位；第一下拉保持电路，耦接于第一节点、第一时钟信号、第一参考电压以及第二参考电压，用于保持第一节点的低电平；补偿电路，耦接于第一节点或者第一下拉保持电路，用于补偿第一节点或者第一下拉保持电路的电位。
其中，补偿电路包括第四晶体管，第四晶体管的源极和栅极均耦接于其所在的移位寄存电路的下一级的移位寄存电路的驱动信号输出端，第四晶体管的漏极与第一节点连接，用于根据下一级的移位寄存电路的驱动信号输出端输出的驱动信号抬升第一节点的电位。
其中，补偿电路还包括第五晶体管、第六晶体管以及第一电容，第一电容的一端与第三晶体管的漏极连接，第一电容的另一端与第五晶体管的漏极和第六晶体管的源极连接，第五晶体管的栅极与其所在的移位寄存电路的前四级的移位寄存电路的驱动信号输出端连接，第五晶体管的源极与前四级的移位寄存电路的栅极信号输出端连接，第六晶体管的栅极与前两级的移位寄存电路的驱动信号输出端连接，第六晶体管的漏极与第一节点连接。
其中，补偿电路包括第四晶体管、第五晶体管以及第一电容，第一电容的一端与第三晶体管的漏极连接，第一电容的另一端与第四晶体管的漏极和第五晶体管的源极连接，第四晶体管的栅极与其所在的移位寄存电路的前四级的移位寄存电路的驱动信号输出端连接，第四晶体管的源极与前四级的移位寄存电路的栅极信号输出端连接，第五晶体管的栅极与前两级的移位寄存电路的驱动信号输出端连接，第五晶体管的漏极与第一节点连接。
其中，第一下拉保持电路包括：第四晶体管，第四晶体管的栅极和源极与第一时钟信号连接，漏极与第二节点连接；第五晶体管，第五晶体管的栅极与驱动信号端连接，源极与第二节点连接，漏极与第二参考电压连接；第六晶体管，第六晶体管的栅极与前两级的移位寄存电路的驱动信号输出端连接，源极与第二节点连接，漏极与第二参考电压连接；第七晶体管，第七晶体管的栅极与第二时钟信号连接，源极与第一时钟信号连接，漏极与第二节点连接；第八晶体管，第八晶体管的栅极与补偿电路连接，源极与移位寄存电路的栅极信号输出端连接，漏极与第一参考电压连接；第九晶体管，第九晶体管的栅极与补偿电路连接，源极与第一节点连接，漏极与第一参考电压连接；第十晶体管，第十晶体管的栅极与补偿电路连接，源极与移位寄存电路的驱动信号出端连接，漏极与第二参考电压连接。
其中，补偿电路包括：第一电容，第一电容的一端与第二节点连接，另一端与第八晶体管的栅极、第九晶体管的栅极以及第十晶体管的栅极连接；第十一晶体管，第十一晶体管的栅极与移位寄存电路的前两级的移位寄存电路的驱动信号输出端连接，源极与第一节点连接，漏极与第一电容的另一端连接。
其中，补偿电路包括：第一电容，第一电容的一端与第二节点连接，另一端与第八晶体管的栅极、第九晶体管的栅极以及第十晶体管的栅极连接；第十一晶体管，第十一晶体管的栅极与移位寄存电路的后两级的移位寄存电路的第一节点连接，源极与第三参考电压连接，漏极与第一电容的另一端连接；第十二晶体管，第十二晶体管的栅极与第一电容的另一端连接，源极与后两级的移位寄存电路的第一节点连接；第十三晶体管，第十三晶体管的栅极与移位寄存电路的后两级的移位寄存电路的驱动信号输出端连接，源极与第一电容的一端连接，漏极与第十二晶体管的漏极连接。
其中，每一移位寄存电路还包括第二下拉保持电路，第二下拉保持电路包括：第四晶体管，第四晶体管的栅极与移位寄存电路的后四级的移位寄存电路的驱动信号输出端连接，源极与第一节点连接，漏极与第一参考电压连接；第五晶体管，第五晶体管的栅极与后四级的移位寄存电路的驱动信号输出端连接，源极与移位寄存电路的信号输出端连接，漏极与第一参考电压连接。
其中，每一移位寄存电路还包括下拉电路，下拉电路包括：第六晶体管，第六晶体管的栅极与移位寄存电路的后两级的移位寄存电路的驱动信号输出端连接，源极与移位寄存电路的驱动信号输出端连接，漏极与第二参考电压练级；第七晶体管，第七晶体管的栅极与后两级的移位寄存电路的驱动信号输出端连接，源极与第一节点连接，漏极与第一参考电压连接；第八晶体管，第八晶体管的栅极与后两级的移位寄存电路的驱动信号输出端连接，源极与移位寄存电路的信号输出端连接，漏极与第一参考电压连接。。
通过上述方案，本发明的有益效果是：本发明通过补偿电路耦接于第一节点或者第一下拉保持电路，用于补偿第一节点或者第一下拉保持电路的电位，能够提高栅极驱动电路长期操作的稳定性，进而提高显示面板的质量。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本发明第一实施例的栅极驱动电路的结构示意图；
图2是图1中栅极驱动电路的电路图；
图3是本发明第二实施例的栅极驱动电路的电路图；
图4是图3中栅极驱动电路的各种输入信号、输出信号和节点电压的时序图；
图5是本发明第三实施例的栅极驱动电路的电路图；
图6是本发明第四实施例的栅极驱动电路的电路图；
图7是图6中栅极驱动电路的各种输入信号、输出信号和节点电压的时序图；
图8是本发明第五实施例的栅极驱动电路的电路图；
图9是本发明第六实施例的栅极驱动电路的电路图；
图10是本发明第一实施例的液晶显示面板的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1所示，图1是本发明第一实施例的栅极驱动电路的结构示意图。如图1所示， 本实施例所揭示的栅极驱动电路1包括多个移位寄存电路10，多个移位寄存电路10以串联方式进行级联。
其中，多个移位寄存电路10包括上拉电路101、下传电路102、上拉控制电路103、上升电路104、第一下拉保持电路105以及补偿电路106。如图2所示，上拉电路101包括晶体管T1，晶体管T1的栅极耦接于移位寄存电路10的第一节点Q（N），即移位寄存电路10的Q（N）点；晶体管T1的源极耦接于第一时钟信号CK；晶体管T1的漏极耦接于移位寄存电路10的栅极信号输出端G（N）。下传电路102包括晶体管T2，晶体管T2的栅极耦接于第一节点Q（N），晶体管T2的源极耦接于第一时钟信号CK，晶体管T2的漏极耦接于移位寄存电路10的驱动信号输出端ST（N）。上拉控制电路103包括晶体管T3，晶体管T3的栅极耦接于晶体管T3所在的移位寄存电路10的前两级的移位寄存电路的驱动信号输出端ST（N-2），晶体管T3的源极耦接于前两级的移位寄存电路的栅极信号输出端G(N-2)，晶体管T3的漏极耦接于第一节点Q。上升电路104耦接于第一节点Q（N）和移位寄存电路10的栅极信号输出端G(N)之间，用于抬升第一节点Q（N）的电位。第一下拉保持电路105耦接于第一节点Q（N）、第一时钟信号CK、第一参考电压V1以及第二参考电压V2，用于保持第一节点Q（N）的低电平。补偿电路106耦接于第一节点Q（N）或者第一下拉保持电路105，用于补偿第一节点Q（N）或者第一下拉保持电路105的电位。
优选地，第一参考电压V1和第二参考电压V2均为负电位，并且第二参考电压V2小于第一参考电压V1。
本实施例通过补偿电路106耦接于第一节点Q（N）或者第一下拉保持电路105，用于补偿第一节点Q（N）或者第一下拉保持电路105的电位，能够提高栅极驱动电路1长期操作的稳定性，进而提高产品的质量。
本发明还提供第二实施例的栅极驱动电路，其在第一实施例所揭示的栅极驱动电路1的基础上进行详细描述。如图3所示，补偿电路106包括晶体管T4，晶体管T4的栅极和源极均耦接于晶体管T4所在的移位寄存电路10的下一级的移位寄存电路的驱动信号输出端ST（N+1），晶体管T4的漏极与第一节点Q（N）连接。补偿电路106用于根据下一级的移位寄存电路的驱动信号输出端ST（N+1）输出的驱动信号抬升第一节点Q（N）的电位。
其中，上升电路104包括电容C1，电容C1的一端与第一节点Q（N）连接，电容C1的另一端与移位寄存电路10的栅极信号输出端G（N）连接。第一下拉保持电路105包括晶体管T5、晶体管T6、晶体管T7、晶体管T8、晶体管T9、晶体管T10以及晶体管T11，晶体管T5的栅极和源极均与第一时钟信号CK连接，晶体管T5的漏极与移位寄存电路10的第二节点P（N）；晶体管T6的栅极与第二时钟信号XCK连接，晶体管T6的源极与第一时钟信号CK连接，晶体管T6的漏极与第二节点P（N）连接；晶体管T7的栅极与移位寄存电路10的驱动信号输出端ST（N）连接，晶体管T7的源极与第二节点P（N）连接，晶体管T7的漏极与第二参考电压V2连接；晶体管T8的栅极与晶体管T3的栅极连接，晶体管T8的源极与第二节点P（N）连接，晶体管T8的漏极与第二参考电压V2连接；晶体管T9的栅极与第二节点P（N）连接，晶体管T9的源极与移位寄存电路10的栅极信号输出端G（N）连接，晶体管T9的漏极与第一参考电压V1连接；晶体管T10的栅极与第二节点P（N）连接，晶体管T10的源极与第一节点Q（N）链接，晶体管T10的漏极与第一参考电压V1连接；晶体管T11的栅极与第二节点Q（N）连接，晶体管T11的源极与驱动信号输出端ST（N）连接，晶体管T11的漏极与第二参考电压V2连接。
栅极驱动电路还包括第二下拉保持电路107和下拉电路108，第二下拉保持电路107包括晶体管T12和晶体管T13，晶体管T12的栅极和晶体管T13的栅极均与移位寄存电路10的下四级的移位寄存电路的驱动信号输出端ST（N+4）连接，晶体管T12的源极与第一节点Q（N）连接，晶体管T12的漏极与第一参考电压V1连接，晶体管T13的源极与栅极信号输出端G（N）连接，晶体管T13的漏极与第一参考电压V1连接。下拉电路108包括晶体管T14、晶体管T15以及晶体管T16，晶体管T14的栅极、晶体管T15的栅极以及晶体管T16的栅极均与下两级的移位寄存电路的驱动信号输出端ST（N+2）连接，晶体管T14的源极与驱动信号输出端ST（N）连接，晶体管T14的漏极与第二参考电压V2连接，晶体管T15的源极与第一节点Q（N）连接，晶体管T15的漏极与第一参考电压V1连接，晶体管T16的源极与栅极信号输出端G（N）连接，晶体管T16的漏极与第一参考电压V1连接。
请再参见图4，图4是图3中栅极驱动电路的各种输入信号、输出信号和节点电压的时序图。如图4所示，第一时钟信号CK和第二时钟信号XCK为相位上互补的两组信号，如图中第一时钟信号CK1与第二时钟信号XCK1相位互补，第一时钟信号CK2与第二时钟信号XCK2相位互补。其中，栅极信号输出端G（N）的电位被第一参考电压V1拉低到低电位；在第一节点Q（N）和栅极信号输出端G(N) 均
本实施例所揭示的栅极驱动电路通过晶体管T4的栅极和源极均耦接于晶体管T4所在的移位寄存电路10的下一级的移位寄存电路的驱动信号输出端ST（N+1），晶体管T4的漏极与第一节点Q（N）连接，补偿电路106用于根据下一级的移位寄存电路的驱动信号输出端ST（N+1）输出的驱动信号抬升第一节点Q（N）的电位，进而能够提高栅极驱动电路长期操作的稳定性。
本发明还提供第三实施例的栅极驱动电路，其在第一实施例所揭示的栅极驱动电路1的基础上进行详细描述。如图5所示，补偿电路106包括晶体管T4、晶体管T5、晶体管T6以及电容C1。其中，晶体管T4的栅极和源极均耦接于晶体管T4所在的移位寄存电路10的下一级的移位寄存电路的驱动信号输出端ST（N+1），晶体管T4的漏极与第一节点Q（N）连接。电容C1的一端与晶体管T3的漏极连接，电容C1的另一端与晶体管T5的漏极和晶体管T6的源极连接，晶体管T5的栅极与其所在的移位寄存电路的前四级的移位寄存电路的驱动信号输出端ST（N-4）连接，晶体管T5的源极与前四级的移位寄存电路的栅极信号输出端G（N-4）连接，晶体管T6的栅极与前两级的移位寄存电路的驱动信号输出端ST（N-2）连接，晶体管T6的漏极与第一节点Q（N）连接。
其中，上升电路104包括电容C2，电容C2的一端与第一节点Q（N）连接，电容C2的另一端与移位寄存电路10的栅极信号输出端G（N）连接。第一下拉保持电路105包括晶体管T7、晶体管T8、晶体管T9、晶体管T10、晶体管T11、晶体管T12以及晶体管T13，晶体管T7的栅极和源极均与第一时钟信号CK连接，晶体管T7的漏极与移位寄存电路10的第二节点P（N）；晶体管T8的栅极与第二时钟信号XCK连接，晶体管T8的源极与第一时钟信号CK连接，晶体管T8的漏极与第二节点P（N）连接；晶体管T9的栅极与移位寄存电路10的驱动信号输出端ST（N）连接，晶体管T9的源极与第二节点P（N）连接，晶体管T9的漏极与第二参考电压V2连接；晶体管T10的栅极与晶体管T3的栅极连接，晶体管T10的源极与第二节点P（N）连接，晶体管T10的漏极与第二参考电压V2连接；晶体管T11的栅极与第二节点P（N）连接，晶体管T11的源极与移位寄存电路10的栅极信号输出端G（N）连接，晶体管T11的漏极与第一参考电压V1连接；晶体管T12的栅极与第二节点P（N）连接，晶体管T12的源极与第一节点Q（N）链接，晶体管T12的漏极与第一参考电压V1连接；晶体管T13的栅极与第二节点Q（N）连接，晶体管T13的源极与驱动信号输出端ST（N）连接，晶体管T13的漏极与第二参考电压V2连接。
栅极驱动电路还包括第二下拉保持电路107和下拉电路108，第二下拉保持电路107包括晶体管T14和晶体管T15，晶体管T14的栅极和晶体管T15的栅极均与移位寄存电路10的下四级的移位寄存电路的驱动信号输出端ST（N+4）连接，晶体管T14的源极与第一节点Q（N）连接，晶体管T14的漏极与第一参考电压V1连接，晶体管T15的源极与栅极信号输出端G（N）连接，晶体管T15的漏极与第一参考电压V1连接。下拉电路108包括晶体管T16、晶体管T17以及晶体管T18，晶体管T16的栅极、晶体管T17的栅极以及晶体管T18的栅极均与下两级的移位寄存电路的驱动信号输出端ST（N+2）连接，晶体管T16的源极与驱动信号输出端ST（N）连接，晶体管T16的漏极与第二参考电压V2连接，晶体管T17的源极与第一节点Q（N）连接，晶体管T17的漏极与第一参考电压V1连接，晶体管T18的源极与栅极信号输出端G（N）连接，晶体管T18的漏极与第一参考电压V1连接。
其中，前四级的移位寄存电路的驱动信号输出端ST（N-4）和前四级的移位寄存电路的栅极信号输出端G（N-4）对电容C1进行第一阶段充电，前两级的移位寄存电路的驱动信号输出端ST（N-2）和前两级的移位寄存电路的栅极信号输出端G(N-2)对电容C2进行两次提升，在第一节点Q（N）充电之前，第一节点Q（N）在第一阶段具有更好的电位，即相当于没有经过处理的两倍，第一节点Q（N）在作用期间的电位抬升将会更高，提高栅极驱动电路长期操作的稳定性。
本发明还提供第四实施例的栅极驱动电路，其在第一实施例所揭示的栅极驱动电路1的基础上进行详细描述。如图6所示，补偿电路106包括晶体管T4、晶体管T5以及电容C1。电容C1的一端与晶体管T3的漏极连接，电容C1的另一端与晶体管T4的漏极和晶体管T5的源极连接，晶体管T4的栅极与其所在的移位寄存电路的前四级的移位寄存电路的驱动信号输出端ST（N-4）连接，晶体管T4的源极与前四级的移位寄存电路的栅极信号输出端G（N-4）连接，晶体管T5的栅极与前两级的移位寄存电路的驱动信号输出端ST（N-2）连接，晶体管T5的漏极与第一节点Q（N）连接。
上升电路104包括电容C2，电容C2的一端与第一节点Q（N）连接，电容C2的另一端与移位寄存电路10的栅极信号输出端G（N）连接。第一下拉保持电路105包括晶体管T6、晶体管T7、晶体管T8、晶体管T9、晶体管T10、晶体管T11以及晶体管T12，晶体管T6的栅极和源极均与第一时钟信号CK连接，晶体管T6的漏极与移位寄存电路10的第二节点P（N）；晶体管T7的栅极与第二时钟信号XCK连接，晶体管T7的源极与第一时钟信号CK连接，晶体管T7的漏极与第二节点P（N）连接；晶体管T8的栅极与移位寄存电路10的驱动信号输出端ST（N）连接，晶体管T8的源极与第二节点P（N）连接，晶体管T8的漏极与第二参考电压V2连接；晶体管T9的栅极与晶体管T3的栅极连接，晶体管T9的源极与第二节点P（N）连接，晶体管T9的漏极与第二参考电压V2连接；晶体管T10的栅极与第二节点P（N）连接，晶体管T10的源极与移位寄存电路10的栅极信号输出端G（N）连接，晶体管T10的漏极与第一参考电压V1连接；晶体管T11的栅极与第二节点P（N）连接，晶体管T11的源极与第一节点Q（N）链接，晶体管T11的漏极与第一参考电压V1连接；晶体管T12的栅极与第二节点Q（N）连接，晶体管T12的源极与驱动信号输出端ST（N）连接，晶体管T12的漏极与第二参考电压V2连接。
栅极驱动电路还包括第二下拉保持电路107和下拉电路108，第二下拉保持电路107包括晶体管T13和晶体管T14，晶体管T13的栅极和晶体管T14的栅极均与移位寄存电路10的下四级的移位寄存电路的驱动信号输出端ST（N+4）连接，晶体管T13的源极与第一节点Q（N）连接，晶体管T13的漏极与第一参考电压V1连接，晶体管T14的源极与栅极信号输出端G（N）连接，晶体管T14的漏极与第一参考电压V1连接。下拉电路108包括晶体管T15、晶体管T16以及晶体管T17，晶体管T15的栅极、晶体管T16的栅极以及晶体管T17的栅极均与下两级的移位寄存电路的驱动信号输出端ST（N+2）连接，晶体管T15的源极与驱动信号输出端ST（N）连接，晶体管T15的漏极与第二参考电压V2连接，晶体管T16的源极与第一节点Q（N）连接，晶体管T16的漏极与第一参考电压V1连接，晶体管T17的源极与栅极信号输出端G（N）连接，晶体管T17的漏极与第一参考电压V1连接。
请再参见图7，图7是图6中栅极驱动电路的各种输入信号、输出信号和节点电压的时序图。如图7所示，第一时钟信号CK和第二时钟信号XCK为相位上互补的两组信号，如图中第一时钟信号CK1与第二时钟信号XCK1相位互补，第一时钟信号CK2与第二时钟信号XCK2相位互补。
其中，前四级的移位寄存电路的驱动信号输出端ST（N-4）和前四级的移位寄存电路的栅极信号输出端G（N-4）对电容C1进行第一阶段充电，前两级的移位寄存电路的驱动信号输出端ST（N-2）和前两级的移位寄存电路的栅极信号输出端G(N-2)对电容C2进行两次提升，在第一节点Q（N）充电之前，第一节点Q（N）在第一阶段具有更好的电位，即相当于没有经过处理的两倍，第一节点Q（N）在作用期间的电位抬升将会更高，提高栅极驱动电路长期操作的稳定性。
本发明还提供第五实施例的栅极驱动电路，其在第一实施例所揭示的栅极驱动电路1的基础上进行详细描述。如图8所示，第一下拉保持电路105包括晶体管T4、晶体管T5、晶体管T6、晶体管T7、晶体管T8、晶体管T9以及晶体管T10。其中，晶体管T4的栅极和源极与第一时钟信号CK连接，晶体管T4的漏极与第二节点P（N）连接。晶体管T5的栅极与驱动信号端ST（N）连接，晶体管T5的源极与第二节点P（N）连接，晶体管T5的漏极与第二参考电压V2连接。晶体管T6的栅极与前两级的移位寄存电路的驱动信号输出端ST（N-2）连接，晶体管T6的源极与第二节点P（N）连接，晶体管T6的漏极与第二参考电压V2连接。晶体管T7的栅极与第二时钟信号XCK连接，晶体管T7的源极与第一时钟信号CK连接，晶体管T7的漏极与第二节点P（N）连接。晶体管T8的栅极与补偿电路106连接，晶体管T8的源极与移位寄存电路的栅极信号输出端G（N）连接，晶体管T8的漏极与第一参考电压V1连接。晶体管T9的栅极与补偿电路106连接，晶体管T9的源极与第一节点Q（N）连接，晶体管T9的漏极与第一参考电压V1连接。晶体管T10的栅极与补偿电路106连接，晶体管T10的源极与移位寄存电路的驱动信号输出端ST（N）连接，晶体管T10的漏极与第二参考电压V2连接。
其中，补偿电路106包括电容C1以及晶体管T11，电容C1的一端与第二节点P（N）连接，电容C1的另一端与晶体管T8的栅极、晶体管T9的栅极以及晶体管T10的栅极连接；晶体管T11的栅极与移位寄存电路10的前两级的移位寄存电路的驱动信号输出端ST（N-2），晶体管T11的源极与第一节点Q（N）连接，晶体管T11的漏极与电容C1的另一端连接。
其中，上升电路104包括电容C2，电容C2的一端与第一节点Q（N）连接，电容C2的另一端与移位寄存电路10的栅极信号输出端G（N）连接。
栅极驱动电路还包括第二下拉保持电路107和下拉电路108，第二下拉保持电路107包括晶体管T12和晶体管T13，晶体管T12的栅极和晶体管T13的栅极均与移位寄存电路10的下四级的移位寄存电路的驱动信号输出端ST（N+4）连接，晶体管T12的源极与第一节点Q（N）连接，晶体管T12的漏极与第一参考电压V1连接，晶体管T13的源极与栅极信号输出端G（N）连接，晶体管T13的漏极与第一参考电压V1连接。下拉电路108包括晶体管T14、晶体管T15以及晶体管T16，晶体管T14的栅极、晶体管T15的栅极以及晶体管T16的栅极均与下两级的移位寄存电路的驱动信号输出端ST（N+2）连接，晶体管T14的源极与驱动信号输出端ST（N）连接，晶体管T14的漏极与第二参考电压V2连接，晶体管T15的源极与第一节点Q（N）连接，晶体管T15的漏极与第一参考电压V1连接，晶体管T16的源极与栅极信号输出端G（N）连接，晶体管T16的漏极与第一参考电压V1连接。
其中，补偿电路106通过电容C1和晶体管T11增强第二节点P（N）的电位，在晶体管T8、晶体管T9以及晶体管T10在stress较严重的情况下，也能打开。
本发明还提供第六实施例的栅极驱动电路，其在第一实施例所揭示的栅极驱动电路1的基础上进行详细描述。如图9所示，第一下拉保持电路105包括晶体管T4、晶体管T5、晶体管T6、晶体管T7、晶体管T8、晶体管T9以及晶体管T10。其中，晶体管T4的栅极和源极与第一时钟信号CK连接，晶体管T4的漏极与第二节点P（N）连接。晶体管T5的栅极与驱动信号端ST（N）连接，晶体管T5的源极与第二节点P（N）连接，晶体管T5的漏极与第二参考电压V2连接。晶体管T6的栅极与前两级的移位寄存电路的驱动信号输出端ST（N-2）连接，晶体管T6的源极与第二节点P（N）连接，晶体管T6的漏极与第二参考电压V2连接。晶体管T7的栅极与第二时钟信号XCK连接，晶体管T7的源极与第一时钟信号CK连接，晶体管T7的漏极与第二节点P（N）连接。晶体管T8的栅极与补偿电路106连接，晶体管T8的源极与移位寄存电路的栅极信号输出端G（N）连接，晶体管T8的漏极与第一参考电压V1连接。晶体管T9的栅极与补偿电路106连接，晶体管T9的源极与第一节点Q（N）连接，晶体管T9的漏极与第一参考电压V1连接。晶体管T10的栅极与补偿电路106连接，晶体管T10的源极与移位寄存电路的驱动信号输出端ST（N）连接，晶体管T10的漏极与第二参考电压V2连接。
其中，补偿电路106包括电容C1、晶体管T11、晶体管T12以及晶体管T13，电容C1的一端与第二节点P（N）连接，电容C1的另一端与晶体管T8的栅极、晶体管T9的栅极以及晶体管T10的栅极连接。晶体管T11的栅极与移位寄存电路10的后两级的移位寄存电路的第一节点Q（N+2）连接，晶体管T11的源极与第三参考电压V3连接，晶体管T11的漏极与电容C1的另一端连接。晶体管T12的栅极与电容C1的另一端连接，晶体管T12的源极与后两级的移位寄存电容的第一节点Q（N+2）连接。晶体管T13的栅极与移位寄存电路10的后两级的移位寄存电路的驱动信号输出端ST（N+2）连接，晶体管T13的源极与电容C1的一端连接，晶体管T13的漏极与晶体管T12的漏极连接。
其中，上升电路104包括电容C2，电容C2的一端与第一节点Q（N）连接，电容C2的另一端与移位寄存电路10的栅极信号输出端G（N）连接。
栅极驱动电路还包括第二下拉保持电路107和下拉电路108，第二下拉保持电路107包括晶体管T14和晶体管T15，晶体管T14的栅极和晶体管T15的栅极均与移位寄存电路10的下四级的移位寄存电路的驱动信号输出端ST（N+4）连接，晶体管T14的源极与第一节点Q（N）连接，晶体管T14的漏极与第一参考电压V1连接，晶体管T15的源极与栅极信号输出端G（N）连接，晶体管T15的漏极与第一参考电压V1连接。下拉电路108包括晶体管T16、晶体管T17以及晶体管T18，晶体管T16的栅极、晶体管T17的栅极以及晶体管T18的栅极均与下两级的移位寄存电路的驱动信号输出端ST（N+2）连接，晶体管T16的源极与驱动信号输出端ST（N）连接，晶体管T16的漏极与第二参考电压V2连接，晶体管T17的源极与第一节点Q（N）连接，晶体管T17的漏极与第一参考电压V1连接，晶体管T18的源极与栅极信号输出端G（N）连接，晶体管T18的漏极与第一参考电压V1连接。
其中，补偿电路106通过电容C1、晶体管T11、晶体管T12以及晶体管T13增强第二节点P（N）的电位，补偿晶体管T8、晶体管T9以及晶体管T10的电压漂移，在晶体管T8、晶体管T9以及晶体管T10在stress较严重的情况下，也能打开。
通过上述实施例，本发明通过对第一节点Q(N)的电位进行增强，对第一节点Q(N)实行三阶充电原理，能够保证栅极驱动电路1的正常输出；此外本发明还提供了对第二节点P(N)的补偿电路106，避免第二节点P(N)的电位异常将导致第一节点Q(N)和第二节点G(N)的下拉能力不足，直接导致电路失效，通过补偿电路106，能够防止由于晶体管的阈值电压漂移导致电路的下拉保持部分启动不佳的问题。
本发明还提供一种液晶显示面板，如图10所述，液晶显示面板2包括上述的栅极驱动电路1以及多条栅极线20，其中栅极线20分别与栅极驱动电路1中的对应移位寄存电路10的栅极信号输出端G（N）连接。
综上所述，本发明通过补偿电路耦接于第一节点或者第一下拉保持电路，用于补偿第一节点或者第一下拉保持电路的电位，能够提高栅极驱动电路长期操作的稳定性，进而提高显示面板的质量。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (18)

  1. 一种栅极驱动电路，其特征在于，所述栅极驱动电路包括多个移位寄存电路，所述多个移位寄存电路以串联方式进行级联，每一所述移位寄存电路包括：
    上拉电路，其包括第一晶体管，所述第一晶体管的栅极耦接于第一节点，源极耦接于第一时钟信号，漏极耦接于所述移位寄存电路的栅极信号输出端；
    下传电路，其包括第二晶体管，所述第二晶体管的栅极耦接于所述第一节点，源极耦接于所述第一时钟信号，漏极耦接于所述移位寄存电路的驱动信号输出端；
    上拉控制电路，其包括第三晶体管，所述第三晶体管的栅极耦接于其所在的所述移位寄存电路的前两级的移位寄存电路的驱动信号输出端，源极耦接于所述前两级的移位寄存电路的栅极信号输出端，漏极耦接于所述第一节点；
    上升电路，耦接于所述第一节点和所述移位寄存电路的栅极信号输出端之间，用于抬升所述第一节点的电位；
    第一下拉保持电路，耦接于所述第一节点、所述第一时钟信号、第一参考电压以及第二参考电压，用于保持所述第一节点的低电平；
    补偿电路，耦接于所述第一节点或者所述第一下拉保持电路，用于补偿所述第一节点或者所述第一下拉保持电路的电位。
  2. 根据权利要求1所述的驱动电路，其特征在于，所述补偿电路包括第四晶体管，所述第四晶体管的源极和栅极均耦接于其所在的所述移位寄存电路的下一级的移位寄存电路的驱动信号输出端，所述第四晶体管的漏极与所述第一节点连接，用于根据所述下一级的移位寄存电路的驱动信号输出端输出的驱动信号抬升所述第一节点的电位。
  3. 根据权利要求2所述的驱动电路，其特征在于，所述补偿电路还包括第五晶体管、第六晶体管以及第一电容，所述第一电容的一端与所述第三晶体管的漏极连接，所述第一电容的另一端与所述第五晶体管的漏极和所述第六晶体管的源极连接，所述第五晶体管的栅极与其所在的所述移位寄存电路的前四级的移位寄存电路的驱动信号输出端连接，所述第五晶体管的源极与所述前四级的移位寄存电路的栅极信号输出端连接，所述第六晶体管的栅极与所述前两级的移位寄存电路的驱动信号输出端连接，所述第六晶体管的漏极与所述第一节点连接。
  4. 根据权利要求1所述的驱动电路，其特征在于，所述补偿电路包括第四晶体管、第五晶体管以及第一电容，所述第一电容的一端与所述第三晶体管的漏极连接，所述第一电容的另一端与所述第四晶体管的漏极和所述第五晶体管的源极连接，所述第四晶体管的栅极与其所在的所述移位寄存电路的前四级的移位寄存电路的驱动信号输出端连接，所述第四晶体管的源极与所述前四级的移位寄存电路的栅极信号输出端连接，所述第五晶体管的栅极与所述前两级的移位寄存电路的驱动信号输出端连接，所述第五晶体管的漏极与所述第一节点连接。
  5. 根据权利要求1所述的驱动电路，其特征在于，所述第一下拉保持电路包括：
    第四晶体管，所述第四晶体管的栅极和源极与所述第一时钟信号连接，漏极与第二节点连接；
    第五晶体管，所述第五晶体管的栅极与所述驱动信号端连接，源极与所述第二节点连接，漏极与所述第二参考电压连接；
    第六晶体管，所述第六晶体管的栅极与所述前两级的移位寄存电路的驱动信号输出端连接，源极与所述第二节点连接，漏极与所述第二参考电压连接；
    第七晶体管，所述第七晶体管的栅极与第二时钟信号连接，源极与所述第一时钟信号连接，漏极与所述第二节点连接；
    第八晶体管，所述第八晶体管的栅极与所述补偿电路连接，源极与所述移位寄存电路的栅极信号输出端连接，漏极与所述第一参考电压连接；
    第九晶体管，所述第九晶体管的栅极与所述补偿电路连接，源极与所述第一节点连接，漏极与所述第一参考电压连接；
    第十晶体管，所述第十晶体管的栅极与所述补偿电路连接，源极与所述移位寄存电路的驱动信号出端连接，漏极与所述第二参考电压连接。
  6. 根据权利要求5所述的驱动电路，其特征在于，所述补偿电路包括：
    第一电容，所述第一电容的一端与所述第二节点连接，另一端与所述第八晶体管的栅极、所述第九晶体管的栅极以及所述第十晶体管的栅极连接；
    第十一晶体管，所述第十一晶体管的栅极与所述移位寄存电路的前两级的移位寄存电路的驱动信号输出端连接，源极与所述第一节点连接，漏极与所述第一电容的另一端连接。
  7. 根据权利要求5所述的驱动电路，其特征在于，所述补偿电路包括：
    第一电容，所述第一电容的一端与所述第二节点连接，另一端与所述第八晶体管的栅极、所述第九晶体管的栅极以及所述第十晶体管的栅极连接；
    第十一晶体管，所述第十一晶体管的栅极与所述移位寄存电路的后两级的移位寄存电路的第一节点连接，源极与第三参考电压连接，漏极与所述第一电容的另一端连接；
    第十二晶体管，所述第十二晶体管的栅极与所述第一电容的另一端连接，源极与所述后两级的移位寄存电路的第一节点连接；
    第十三晶体管，所述第十三晶体管的栅极与所述移位寄存电路的后两级的移位寄存电路的驱动信号输出端连接，源极与所述第一电容的一端连接，漏极与所述第十二晶体管的漏极连接。
  8. 根据权利要求1所述的驱动电路，其特征在于，每一所述移位寄存电路还包括第二下拉保持电路，所述第二下拉保持电路包括：
    第四晶体管，所述第四晶体管的栅极与所述移位寄存电路的后四级的移位寄存电路的驱动信号输出端连接，源极与所述第一节点连接，漏极与所述第一参考电压连接；
    第五晶体管，所述第五晶体管的栅极与所述后四级的移位寄存电路的驱动信号输出端连接，源极与所述移位寄存电路的信号输出端连接，漏极与所述第一参考电压连接。
  9. 根据权利要求8所述的驱动电路，其特征在于，每一所述移位寄存电路还包括下拉电路，所述下拉电路包括：
    第六晶体管，所述第六晶体管的栅极与所述移位寄存电路的后两级的移位寄存电路的驱动信号输出端连接，源极与所述移位寄存电路的驱动信号输出端连接，漏极与所述第二参考电压练级；
    第七晶体管，所述第七晶体管的栅极与所述后两级的移位寄存电路的驱动信号输出端连接，源极与所述第一节点连接，漏极与所述第一参考电压连接；
    第八晶体管，所述第八晶体管的栅极与所述后两级的移位寄存电路的驱动信号输出端连接，源极与所述移位寄存电路的信号输出端连接，漏极与所述第一参考电压连接。
  10. 一种液晶显示面板，其特征在于，所述液晶显示面板包括栅极驱动电路以及多条栅极线，其中所述栅极线分别与所述栅极驱动电路中的对应移位寄存电路的栅极信号输出端连接；所述栅极驱动电路包括多个移位寄存电路，所述多个移位寄存电路以串联方式进行级联，每一所述移位寄存电路包括：
    上拉电路，其包括第一晶体管，所述第一晶体管的栅极耦接于第一节点，源极耦接于第一时钟信号，漏极耦接于所述移位寄存电路的栅极信号输出端；
    下传电路，其包括第二晶体管，所述第二晶体管的栅极耦接于所述第一节点，源极耦接于所述第一时钟信号，漏极耦接于所述移位寄存电路的驱动信号输出端；
    上拉控制电路，其包括第三晶体管，所述第三晶体管的栅极耦接于其所在的所述移位寄存电路的前两级的移位寄存电路的驱动信号输出端，源极耦接于所述前两级的移位寄存电路的栅极信号输出端，漏极耦接于所述第一节点；
    上升电路，耦接于所述第一节点和所述移位寄存电路的栅极信号输出端之间，用于抬升所述第一节点的电位；
    第一下拉保持电路，耦接于所述第一节点、所述第一时钟信号、第一参考电压以及第二参考电压，用于保持所述第一节点的低电平；
    补偿电路，耦接于所述第一节点或者所述第一下拉保持电路，用于补偿所述第一节点或者所述第一下拉保持电路的电位。
  11. 根据权利要求10所述的液晶显示面板，其特征在于，所述补偿电路包括第四晶体管，所述第四晶体管的源极和栅极均耦接于其所在的所述移位寄存电路的下一级的移位寄存电路的驱动信号输出端，所述第四晶体管的漏极与所述第一节点连接，用于根据所述下一级的移位寄存电路的驱动信号输出端输出的驱动信号抬升所述第一节点的电位。
  12. 根据权利要求11所述的液晶显示面板，其特征在于，所述补偿电路还包括第五晶体管、第六晶体管以及第一电容，所述第一电容的一端与所述第三晶体管的漏极连接，所述第一电容的另一端与所述第五晶体管的漏极和所述第六晶体管的源极连接，所述第五晶体管的栅极与其所在的所述移位寄存电路的前四级的移位寄存电路的驱动信号输出端连接，所述第五晶体管的源极与所述前四级的移位寄存电路的栅极信号输出端连接，所述第六晶体管的栅极与所述前两级的移位寄存电路的驱动信号输出端连接，所述第六晶体管的漏极与所述第一节点连接。
  13. 根据权利要求10所述的液晶显示面板，其特征在于，所述补偿电路包括第四晶体管、第五晶体管以及第一电容，所述第一电容的一端与所述第三晶体管的漏极连接，所述第一电容的另一端与所述第四晶体管的漏极和所述第五晶体管的源极连接，所述第四晶体管的栅极与其所在的所述移位寄存电路的前四级的移位寄存电路的驱动信号输出端连接，所述第四晶体管的源极与所述前四级的移位寄存电路的栅极信号输出端连接，所述第五晶体管的栅极与所述前两级的移位寄存电路的驱动信号输出端连接，所述第五晶体管的漏极与所述第一节点连接。
  14. 根据权利要求10所述的液晶显示面板，其特征在于，所述第一下拉保持电路包括：
    第四晶体管，所述第四晶体管的栅极和源极与所述第一时钟信号连接，漏极与第二节点连接；
    第五晶体管，所述第五晶体管的栅极与所述驱动信号端连接，源极与所述第二节点连接，漏极与所述第二参考电压连接；
    第六晶体管，所述第六晶体管的栅极与所述前两级的移位寄存电路的驱动信号输出端连接，源极与所述第二节点连接，漏极与所述第二参考电压连接；
    第七晶体管，所述第七晶体管的栅极与第二时钟信号连接，源极与所述第一时钟信号连接，漏极与所述第二节点连接；
    第八晶体管，所述第八晶体管的栅极与所述补偿电路连接，源极与所述移位寄存电路的栅极信号输出端连接，漏极与所述第一参考电压连接；
    第九晶体管，所述第九晶体管的栅极与所述补偿电路连接，源极与所述第一节点连接，漏极与所述第一参考电压连接；
    第十晶体管，所述第十晶体管的栅极与所述补偿电路连接，源极与所述移位寄存电路的驱动信号出端连接，漏极与所述第二参考电压连接。
  15. 根据权利要求14所述的液晶显示面板，其特征在于，所述补偿电路包括：
    第一电容，所述第一电容的一端与所述第二节点连接，另一端与所述第八晶体管的栅极、所述第九晶体管的栅极以及所述第十晶体管的栅极连接；
    第十一晶体管，所述第十一晶体管的栅极与所述移位寄存电路的前两级的移位寄存电路的驱动信号输出端连接，源极与所述第一节点连接，漏极与所述第一电容的另一端连接。
  16. 根据权利要求14所述的液晶显示面板，其特征在于，所述补偿电路包括：
    第一电容，所述第一电容的一端与所述第二节点连接，另一端与所述第八晶体管的栅极、所述第九晶体管的栅极以及所述第十晶体管的栅极连接；
    第十一晶体管，所述第十一晶体管的栅极与所述移位寄存电路的后两级的移位寄存电路的第一节点连接，源极与第三参考电压连接，漏极与所述第一电容的另一端连接；
    第十二晶体管，所述第十二晶体管的栅极与所述第一电容的另一端连接，源极与所述后两级的移位寄存电路的第一节点连接；
    第十三晶体管，所述第十三晶体管的栅极与所述移位寄存电路的后两级的移位寄存电路的驱动信号输出端连接，源极与所述第一电容的一端连接，漏极与所述第十二晶体管的漏极连接。
  17. 根据权利要求10所述的液晶显示面板，其特征在于，每一所述移位寄存电路还包括第二下拉保持电路，所述第二下拉保持电路包括：
    第四晶体管，所述第四晶体管的栅极与所述移位寄存电路的后四级的移位寄存电路的驱动信号输出端连接，源极与所述第一节点连接，漏极与所述第一参考电压连接；
    第五晶体管，所述第五晶体管的栅极与所述后四级的移位寄存电路的驱动信号输出端连接，源极与所述移位寄存电路的信号输出端连接，漏极与所述第一参考电压连接。
  18. 根据权利要求17所述的液晶显示面板，其特征在于，每一所述移位寄存电路还包括下拉电路，所述下拉电路包括：
    第六晶体管，所述第六晶体管的栅极与所述移位寄存电路的后两级的移位寄存电路的驱动信号输出端连接，源极与所述移位寄存电路的驱动信号输出端连接，漏极与所述第二参考电压练级；
    第七晶体管，所述第七晶体管的栅极与所述后两级的移位寄存电路的驱动信号输出端连接，源极与所述第一节点连接，漏极与所述第一参考电压连接；
    第八晶体管，所述第八晶体管的栅极与所述后两级的移位寄存电路的驱动信号输出端连接，源极与所述移位寄存电路的信号输出端连接，漏极与所述第一参考电压连接。
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