WO2018018724A1 - 扫描驱动电路及具有该电路的平面显示装置 - Google Patents

扫描驱动电路及具有该电路的平面显示装置 Download PDF

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Publication number
WO2018018724A1
WO2018018724A1 PCT/CN2016/099225 CN2016099225W WO2018018724A1 WO 2018018724 A1 WO2018018724 A1 WO 2018018724A1 CN 2016099225 W CN2016099225 W CN 2016099225W WO 2018018724 A1 WO2018018724 A1 WO 2018018724A1
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Prior art keywords
controllable switch
control
signal
scan
controllable
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PCT/CN2016/099225
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English (en)
French (fr)
Inventor
李亚锋
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武汉华星光电技术有限公司
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Priority to US15/312,197 priority Critical patent/US10460652B2/en
Publication of WO2018018724A1 publication Critical patent/WO2018018724A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0213—Addressing of scan or signal lines controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a scan driving circuit and a flat display device having the same.
  • a scan driving circuit that is, a scan driving circuit is fabricated on an array substrate by using a conventional thin film transistor planar display array process to realize a driving method for progressive scanning.
  • the high and low levels of the output of the scan line of the current scan driving circuit are respectively the voltage of the turn-on voltage and the signal of the turn-off voltage, and are two-stage driving.
  • the driving voltage corresponding to the driving mode is relatively large, thereby causing corresponding areas of the panel to correspond.
  • the optimized common mode signal voltage is inconsistent, that is to say, the two-stage driving is likely to cause the uniformity of the common mode signal voltage of the panel to be poor, which affects the quality of the picture display.
  • the technical problem to be solved by the present invention is to provide a scan driving circuit and a flat display device having the same, so as to effectively reduce the induced voltage, thereby improving the uniformity of the common mode signal voltage in the panel and improving the quality of the picture display.
  • the present invention adopts a technical solution to provide a scan driving circuit, wherein the scan driving circuit includes a plurality of cascaded scan driving units, and each of the scan driving units includes:
  • a positive sweep circuit for receiving the upper scan signal and the first clock signal and outputting the first control signal to control the scan drive circuit to perform forward scan, or for receiving the lower scan signal and the second clock signal and outputting the second Controlling signals to control the scan driving circuit to perform reverse scanning;
  • An input circuit connected to the forward and reverse sweep circuit for receiving a third clock signal and receiving the first and second control signals from the forward and reverse sweep circuit and according to the third clock signal, the first The second control signal charges the pull-up control signal point and the pull-down control signal point;
  • An output circuit connected to the input circuit for processing the received third control signal or fourth control signal and data received from the input circuit to generate a scan drive signal output having a two-step high level to the present
  • the scan line is driven to drive the pixel unit.
  • the third control signal includes a fourth clock signal and a reset signal
  • the fourth control signal includes a fourth clock signal, a reset signal, the upper scan signal, and the lower scan signal.
  • the forward/back sweep circuit includes first and second controllable switches, the control end of the first controllable switch receives the first clock signal, and the first end of the first controllable switch receives the first a second scan signal, a second end of the first controllable switch is connected to the first end of the second controllable switch and the input circuit, and a control end of the second controllable switch receives the second clock signal The second end of the second controllable switch receives the lower level scan signal.
  • the present invention adopts a technical solution to provide a scan driving circuit
  • the scan driving circuit includes a plurality of cascaded scan driving units, and each of the scan driving units includes:
  • a positive sweep circuit for receiving the upper scan signal and the first clock signal and outputting the first control signal to control the scan drive circuit to perform forward scan, or for receiving the lower scan signal and the second clock signal and outputting the second Controlling signals to control the scan driving circuit to perform reverse scanning;
  • An input circuit connected to the forward and reverse sweep circuit for receiving a third clock signal and receiving the first and second control signals from the forward and reverse sweep circuit and according to the third clock signal, the first The second control signal charges the pull-up control signal point and the pull-down control signal point;
  • An output circuit connected to the input circuit for processing the received third control signal or fourth control signal and data received from the input circuit to generate a scan drive signal output having a two-step high level to the present
  • the scan line is driven to drive the pixel unit.
  • the third control signal includes a fourth clock signal and a reset signal
  • the fourth control signal includes a fourth clock signal, a reset signal, the upper scan signal, and the lower scan signal.
  • the forward/back sweep circuit includes first and second controllable switches, the control end of the first controllable switch receives the first clock signal, and the first end of the first controllable switch receives the first a second scan signal, a second end of the first controllable switch is connected to the first end of the second controllable switch and the input circuit, and a control end of the second controllable switch receives the second clock signal The second end of the second controllable switch receives the lower level scan signal.
  • the input circuit includes third to seventh controllable switches, first and second capacitors, and a control end of the third controllable switch receives an open voltage terminal signal, and the first end of the third controllable switch Connecting a control end of the fourth controllable switch, a second end of the first controllable switch, and a first end of the second controllable switch, the second end of the third controllable switch being connected to the a first end of the fifth controllable switch and the output circuit, the second end of the fifth controllable switch is connected to the second end of the fourth controllable switch, and the second end of the sixth controllable switch And the second end of the seventh controllable switch receives a signal for closing the voltage end, and the control end of the fifth controllable switch is connected to the first end of the fourth controllable switch and the sixth controllable switch a first end of the sixth controllable switch is connected to the first end of the seventh controllable switch and the output circuit, and a control end of the seventh controllable switch receives the third clock signal
  • the output circuit includes an eighth to twelfth controllable switch and a third capacitor, and a control end of the eighth controllable switch is connected to the second end of the third controllable switch, and the fifth controllable a first end of the switch and a control end of the twelfth controllable switch, the first end of the eighth controllable switch being connected to the second end of the ninth controllable switch, the eighth controllable switch
  • the second end is connected to the first end of the sixth and seventh controllable switches, the second end of the twelfth controllable switch, and the scan line of the current stage, and the control end of the ninth controllable switch receives the a reset signal
  • the first end of the ninth controllable switch is connected to the control end of the tenth controllable switch and the first end, the first end of the eleventh controllable switch, and the first capacitor Receiving, by the second end, the fourth clock signal, the second end of the tenth controllable switch is connected to the control end of the eleventh
  • the first to twelfth controllable switches are N-type thin film transistors, and the control ends, the first ends, and the second ends of the first to twelfth controllable switches respectively correspond to the N-type thin film transistors Gate, drain and source.
  • the output circuit includes an eighth to a fourteen controllable switch and a third capacitor, and a control end of the eighth controllable switch is connected to the second end of the third controllable switch, and the fifth controllable a first end of the switch and a control end of the twelfth controllable switch, the first end of the eighth controllable switch being connected to the second end of the ninth controllable switch, the eighth controllable switch
  • the second end is connected to the first end of the sixth and seventh controllable switches, the second end of the twelfth controllable switch, and the scan line of the current stage, and the control end of the ninth controllable switch receives the a reset signal
  • the first end of the ninth controllable switch is connected to the control end of the tenth controllable switch and the first end, the first end of the eleventh controllable switch, and the first capacitor Receiving, by the second end, the fourth clock signal, the second end of the tenth controllable switch is connected to the control end of the eleventh controll
  • the first to the fourteenth controllable switches are N-type thin film transistors, and the control ends, the first ends and the second ends of the first to fourteenth controllable switches respectively correspond to the N-type thin film transistors Gate, drain and source.
  • a flat display device including a scan driving circuit, the scan driving circuit including a plurality of cascaded scan driving units, each The scan driving unit includes:
  • a positive sweep circuit for receiving the upper scan signal and the first clock signal and outputting the first control signal to control the scan drive circuit to perform forward scan, or for receiving the lower scan signal and the second clock signal and outputting the second Controlling signals to control the scan driving circuit to perform reverse scanning;
  • An input circuit connected to the forward and reverse sweep circuit for receiving a third clock signal and receiving the first and second control signals from the forward and reverse sweep circuit and according to the third clock signal, the first The second control signal charges the pull-up control signal point and the pull-down control signal point;
  • An output circuit connected to the input circuit for processing the received third control signal or fourth control signal and data received from the input circuit to generate a scan drive signal output having a two-step high level to the present
  • the scan line is driven to drive the pixel unit.
  • the third control signal includes a fourth clock signal and a reset signal
  • the fourth control signal includes a fourth clock signal, a reset signal, the upper scan signal, and the lower scan signal.
  • the forward/back sweep circuit includes first and second controllable switches, the control end of the first controllable switch receives the first clock signal, and the first end of the first controllable switch receives the first a second scan signal, a second end of the first controllable switch is connected to the first end of the second controllable switch and the input circuit, and a control end of the second controllable switch receives the second clock signal The second end of the second controllable switch receives the lower level scan signal.
  • the input circuit includes third to seventh controllable switches, first and second capacitors, and a control end of the third controllable switch receives an open voltage terminal signal, and the first end of the third controllable switch Connecting a control end of the fourth controllable switch, a second end of the first controllable switch, and a first end of the second controllable switch, the second end of the third controllable switch being connected to the a first end of the fifth controllable switch and the output circuit, the second end of the fifth controllable switch is connected to the second end of the fourth controllable switch, and the second end of the sixth controllable switch And the second end of the seventh controllable switch receives a signal for closing the voltage end, and the control end of the fifth controllable switch is connected to the first end of the fourth controllable switch and the sixth controllable switch a first end of the sixth controllable switch is connected to the first end of the seventh controllable switch and the output circuit, and a control end of the seventh controllable switch receives the third clock signal
  • the output circuit includes an eighth to twelfth controllable switch and a third capacitor, and a control end of the eighth controllable switch is connected to the second end of the third controllable switch, and the fifth controllable a first end of the switch and a control end of the twelfth controllable switch, the first end of the eighth controllable switch being connected to the second end of the ninth controllable switch, the eighth controllable switch
  • the second end is connected to the first end of the sixth and seventh controllable switches, the second end of the twelfth controllable switch, and the scan line of the current stage, and the control end of the ninth controllable switch receives the a reset signal
  • the first end of the ninth controllable switch is connected to the control end of the tenth controllable switch and the first end, the first end of the eleventh controllable switch, and the first capacitor Receiving, by the second end, the fourth clock signal, the second end of the tenth controllable switch is connected to the control end of the eleventh
  • the first to twelfth controllable switches are N-type thin film transistors, and the control ends, the first ends, and the second ends of the first to twelfth controllable switches respectively correspond to the N-type thin film transistors Gate, drain and source.
  • the output circuit includes an eighth to a fourteen controllable switch and a third capacitor, and a control end of the eighth controllable switch is connected to the second end of the third controllable switch, and the fifth controllable a first end of the switch and a control end of the twelfth controllable switch, the first end of the eighth controllable switch being connected to the second end of the ninth controllable switch, the eighth controllable switch
  • the second end is connected to the first end of the sixth and seventh controllable switches, the second end of the twelfth controllable switch, and the scan line of the current stage, and the control end of the ninth controllable switch receives the a reset signal
  • the first end of the ninth controllable switch is connected to the control end of the tenth controllable switch and the first end, the first end of the eleventh controllable switch, and the first capacitor Receiving, by the second end, the fourth clock signal, the second end of the tenth controllable switch is connected to the control end of the eleventh controll
  • the first to the fourteenth controllable switches are N-type thin film transistors, and the control ends, the first ends and the second ends of the first to fourteenth controllable switches respectively correspond to the N-type thin film transistors Gate, drain and source.
  • the flat display device is an LCD or an OLED.
  • the scan driving circuit of the present invention controls the scan driving circuit to perform forward scanning and reverse scanning through the forward and reverse scanning circuit, and through the input circuit pair Pulling up the control signal point and the pull-down control signal point for charging, and generating, by the output circuit, a scan driving signal having a two-step high level to output to the scan line to drive the pixel unit, thereby effectively reducing the induced voltage, thereby improving the panel
  • the uniformity of the common mode signal voltage improves the quality of the picture display.
  • FIG. 1 is a schematic structural view of a scan driving unit of a scan driving circuit in the prior art
  • Figure 2 is a forward scan waveform diagram of Figure 1;
  • Figure 3 is a reverse scan waveform diagram of Figure 1;
  • FIG. 4 is a schematic structural view of a first embodiment of a scan driving unit of the scan driving circuit of the present invention.
  • Figure 5 is a forward scan waveform diagram of Figure 4.
  • Figure 6 is a reverse scan waveform diagram of Figure 4.
  • FIG. 7 is a schematic structural view of a second embodiment of a scan driving unit of the scan driving circuit of the present invention.
  • Figure 8 is a schematic illustration of a flat display device of the present invention.
  • the working principle (forward scanning) of the scanning driving circuit in the prior art is as follows:
  • Pre-charging stage when the upper-level scanning signal Gn-1 and the clock signal CKV1 are simultaneously at a high level, the thin film transistor T1 is turned on, and the H point is at a high level, so that the thin film transistor T6 is in an on state, and the pull-down control signal point P is pulled low. ;
  • the scanning line Gn of this stage outputs a high level phase: the gate receiving open voltage terminal signal VGH of the thin film transistor T5 is always in an on state, and in the precharge phase, the pull-up control signal point Q is precharged, and the capacitor C3 has a certain charge
  • the scanning line Gn of this stage outputs a low level phase: when the clock signal CKV3 and the lower scanning signal Gn+1 are simultaneously at a high level, the thin film transistor T3 is turned on, and the pull-up control signal point Q is maintained at a high level, and the clock is at this time.
  • the low level of the signal CKV2 pulls the scanning line Gn of the current level low;
  • the pull-up control signal point Q is pulled down to the off voltage terminal signal VGL phase: when the clock signal CKV1 becomes high again, the upper-level scan signal Gn-1 is at a low level, and the thin film transistor T1 is in an on state. Pulling control signal point Q is pulled down to turn off voltage terminal signal VGL;
  • the pull-up control signal point Q and the current-level scan line Gn are in a low-level sustain phase: when the pull-up control signal point Q becomes a low level, the thin film transistor T6 is in an off state, and when the clock signal CKV2 becomes a high level, Due to the bootstrap of the capacitor C1, the pull-down control signal point P becomes a high level, and the thin film transistors T4 and T7 are both in an on state to ensure the stabilization of the low level of the pull-up control signal point Q and the scanning line Gn of the present stage.
  • the working principle (reverse scan) of the scan driving circuit in the prior art is as follows:
  • Pre-charging stage when the lower-level scanning signal Gn+1 and the clock signal CKV3 are simultaneously at a high level, the thin film transistor T3 is turned on, the H point is at a high level, the thin film transistor T6 is in an on state, and the pull-down control signal point P is pulled low;
  • the scanning line Gn of this stage outputs a high level phase: the gate receiving open voltage terminal signal VGH of the thin film transistor T5 is always in an on state, and in the precharge phase, the pull-up control signal point Q is precharged, and the capacitor C3 has a certain charge
  • the scanning line Gn of this stage outputs a low level phase: when the clock signal CKV1 and the lower scanning signal Gn-1 are simultaneously at a high level, the thin film transistor T1 is turned on, and the pull-up control signal point Q is maintained at a high level, and the clock is at this time.
  • the low level of the signal CKV2 pulls the scanning line Gn of the current level low;
  • the pull-up control signal point Q is pulled down to the off voltage terminal signal VGL: when the clock signal CKV3 changes to the high level again, the lower-level scan signal Gn+1 is at a low level, and the thin film transistor T3 is in an on state, and is pulled up.
  • the control signal point Q is pulled down to the off voltage terminal signal VGL;
  • the pull-up control signal point Q and the current-level scan line Gn are in a low-level sustain phase: when the pull-up control signal point Q becomes a low level, the thin film transistor T6 is in an off state, and when the clock signal CKV2 becomes a high level, Due to the bootstrap of the capacitor C1, the pull-down control signal point P becomes a high level, and the thin film transistors T4 and T7 are both in an on state to ensure the stability of the pull-down control signal point Q and the low level of the current scanning line Gn.
  • the high and low levels of the scan line output of the current scan driving circuit are the turn-on voltage end signal VGH and the turn-off voltage end signal VGL, respectively, and are two-order driving.
  • the driving voltage corresponding to the driving mode is large, thereby causing different panels.
  • the optimized common mode signal voltage corresponding to the area is inconsistent, that is to say, the two-stage driving is likely to cause the uniformity of the common mode signal voltage of the panel to be poor, which affects the quality of the display.
  • the scan driving circuit of the present invention includes a plurality of cascaded scan driving units, each of which includes a forward/back sweep circuit 100 for receiving a superior scan signal and a first clock signal and outputting the first a control signal for controlling the scan driving circuit to perform forward scanning, or for receiving a lower scanning signal and a second clock signal and outputting a second control signal to control the scan driving circuit to perform reverse scanning;
  • the input circuit 200, connecting The forward/back sweep circuit 100 is configured to receive a third clock signal and receive the first and second control signals from the forward/back sweep circuit 100, and according to the third clock signal, the first and second The control signal charges the pull-up control signal point and the pull-down control signal point;
  • the output circuit 300 is connected to the input circuit 200 for receiving and receiving the third control signal or the fourth control signal from the input circuit 200
  • the third control signal includes a fourth clock signal and a reset signal; in the second embodiment, the fourth control signal includes a fourth clock signal and a reset signal. And the upper scanning signal and the lower scanning signal.
  • the positive and negative scanning circuit 100 includes first and second controllable switches T1 and T2.
  • the control end of the first controllable switch T1 receives the first clock signal, and the first controllable switch T1 is first.
  • Receiving, by the terminal, the upper scan signal, the second end of the first controllable switch T1 is connected to the first end of the second controllable switch T2 and the input circuit 200, and the control of the second controllable switch T2
  • the terminal receives the second clock signal, and the second end of the second controllable switch T2 receives the lower level scan signal.
  • the input circuit 200 includes third to seventh controllable switches T3-T7, first and second capacitors C1, C2, and a control end of the third controllable switch T3 receives an open voltage terminal signal VGH, the third The first end of the controllable switch T3 is connected to the control end of the fourth controllable switch T4, the second end of the first controllable switch T1, and the first end of the second controllable switch T2, the first The second end of the third controllable switch T3 is connected to the first end of the fifth controllable switch T5 and the output circuit 300, and the second end of the fifth controllable switch T5 is connected to the fourth controllable switch T4
  • the second end of the sixth controllable switch T6 and the second end of the seventh controllable switch T7 receive the closed voltage end signal VGL, and the control end of the fifth controllable switch T5 is connected.
  • the first end of the sixth controllable switch T6 is connected to the first end of the seventh controllable switch T7
  • the control end of the seventh controllable switch T7 receives the third clock signal
  • the first end of the first capacitor C1 is connected to the fifth
  • the control terminal of the switch T5 receives the third clock signal
  • the first end of the first capacitor C1 is connected to the fifth
  • the second end of the first capacitor C1 is connected to the output circuit 300
  • the second capacitor C2 is connected between the control terminal of the sixth controllable switch and a second terminal T6.
  • the output circuit 300 includes eighth to twelfth controllable switches T8-T12 and a third capacitor C3, and the control end of the eighth controllable switch T8 is connected to the second end of the third controllable switch T3. a first end of the fifth controllable switch T5 and a control end of the twelfth controllable switch T12, the first end of the eighth controllable switch T8 is connected to the second end of the ninth controllable switch T9
  • the second end of the eighth controllable switch T8 is connected to the first end of the sixth controllable switch T6 and the seventh controllable switch T7, the second end of the twelfth controllable switch T12, and the second stage a scan line
  • the control end of the ninth controllable switch T9 receives the reset signal
  • the first end of the ninth controllable switch T9 is connected to the control end of the tenth controllable switch T10 and the first end
  • the first to twelfth controllable switches T1-T12 are N-type thin film transistors, and the control ends, the first ends, and the second ends of the first to twelfth controllable switches T1-T12 The terminals respectively correspond to the gate, the drain and the source of the N-type thin film transistor.
  • the first to twelfth controllable switches may also be other types of switches as long as the object of the present invention can be achieved.
  • the upper scan signal is the upper scan signal Gn-1
  • the lower scan signal is the lower scan signal Gn+1
  • the first clock signal is the clock signal CKV1
  • the second clock signal is a clock signal CKV3
  • the third clock signal is a clock signal CKV4
  • the fourth clock signal is a clock signal CKV2
  • the reset signal is a reset signal Reset
  • the pull-up control signal point is a pull-up control signal point Q
  • the pull-down control signal point is a pull-down control signal point P.
  • the working principle (forward scanning) of a scan driving unit of the scan driving circuit can be obtained as follows:
  • Precharge phase when the upper scan signal Gn-1 and the first clock signal CKV1 are simultaneously at a high level, the first controllable switch T1 is turned on, H is a high level, and the fourth controllable switch T4 In the on state, the pull-down control signal point P is pulled low;
  • the first-stage scan line Gn outputs a high-level phase: the control end of the third controllable switch T3 receives the turn-on voltage end signal VGH is always in an on state, and in the pre-charge phase, the pull-up control signal point Q is pre-charged, the third capacitor C3 has a certain holding effect on the electric charge, the eighth controllable switch T8 is in an on state, and when the reset signal Reset is at a high level, the ninth controllable switch T9 is turned on, a high level of the fourth clock signal CKV2 is output to the current-level scan line Gn; when the reset signal Reset is at a low level, the ninth controllable switch T9 is turned off, and at this time
  • the tenth controllable switch T10 and the eleventh controllable switch T11 are both in an on state, and the high level of the fourth clock signal CKV2 charges the M point (by adjusting the ninth controllable switch)
  • the size of T9 and the tenth controllable switch T10
  • the scan line Gn of the current stage outputs a low level phase: when the second clock signal CKV3 and the lower level scan signal Gn+1 are simultaneously at a high level, the second controllable switch T2 is turned on, and the pull-up control signal point Q is maintained at a high level, at which time the reset signal Reset is a high level signal, the ninth controllable switch T9 is turned on, and the low level of the fourth clock signal CKV2 is the current level scan line. Gn is pulled low;
  • the pull-up control signal point Q is pulled down to the off voltage terminal signal VGL: when the first clock signal CKV1 changes to a high level again, the upper level scan signal Gn-1 is at a low level.
  • the first controllable switch T1 is in an on state, and the pull-up control signal point Q is pulled down to the off voltage terminal signal VGL;
  • the pull-up control signal point Q and the local-level scan line Gn are in a low-level sustain phase: when the pull-up control signal point Q becomes a low level, the fourth controllable switch T4 is in an off state When the fourth clock signal CKV2 becomes a high level, the pull-down control signal point P becomes a high level due to the bootstrap of the first capacitor C1, the sixth controllable switch T6 and the The fifth controllable switch T5 is in an on state to ensure the stability of the pull-up control signal point Q and the low level of the local scanning line Gn.
  • the working principle (reverse scan) of a scan driving unit of the scan driving circuit can be obtained as follows:
  • Precharge phase when the lower scan signal Gn+1 and the second clock signal CKV3 are simultaneously at a high level, the second controllable switch T2 is turned on, H is a high level, and the fourth controllable switch T4 In the on state, the P point is pulled low;
  • the scan line Gn of the current stage outputs a high level phase: the control end of the third controllable switch T3 receives the turn-on voltage end signal VGH is always in an on state, and in the precharge phase, the pull-up control signal point Q is Pre-charging, the third capacitor C3 has a certain holding effect on the electric charge, the eighth controllable switch T8 is in an on state, and when the reset signal Reset is at a high level, the ninth controllable switch T9 leads a high level of the fourth clock signal CKV2 is output to the current-level scan line Gn; when the reset signal Reset is at a low level, the ninth controllable switch T9 is turned off, and at this time, the first The ten controllable switch T10 and the eleventh controllable switch T11 are both in an on state, and the high level of the fourth clock signal CKV2 charges the M point (by adjusting the ninth controllable switch T9 and The size of the tenth controllable switch T10 can be reduced by a high
  • the first controllable switch T1 is turned on, and the pull-up control signal is turned on when the first clock signal CKV1 and the upper-level scan signal Gn-1 are simultaneously at a high level.
  • the point Q is maintained at a high level, at which time the reset signal Reset is at a high level, the ninth controllable switch T9 is turned on, and the low level of the fourth clock signal CKV2 is the current level scan line. Gn is pulled low;
  • the pull-up control signal point Q is pulled down to the closed voltage terminal signal VGL stage: when the second clock signal CKV3 changes to a high level again, the lower-level scan signal Gn+1 is at a low level at this time.
  • the second controllable switch T2 is in an on state, the pull-up control signal point Q is pulled down to the off voltage terminal signal VGL;
  • the pull-up control signal point Q and the local-level scan line Gn are in a low-level sustain phase: when the pull-up control signal point Q becomes a low level, the fourth controllable switch T4 is in an off state When the fourth clock signal CKV2 becomes a high level, the pull-down control signal point P becomes a high level due to the bootstrap of the first capacitor C1, the sixth controllable switch T6 and the The fifth controllable switch T5 is in an on state to ensure the stability of the pull-up control signal point Q and the low level of the current-level scan line Gn, thereby effectively reducing the induced voltage, thereby improving the total of the panel.
  • the uniformity of the mode signal voltage improves the quality of the picture display.
  • FIG. 7 is a schematic structural diagram of a second embodiment of a scan driving unit of the scan driving circuit of the present invention.
  • the second embodiment of the scan driving circuit is different from the first embodiment of the scan driving circuit in that the output circuit 300 includes eighth to fourteenth controllable switches T8-T14 and a third capacitor C3.
  • the control end of the eighth controllable switch T8 is connected to the second end of the third controllable switch T3, the first end of the fifth controllable switch T5, and the control of the twelfth controllable switch T12.
  • the first end of the eighth controllable switch T8 is connected to the second end of the ninth controllable switch T9, and the second end of the eighth controllable switch T8 is connected to the sixth controllable switch T6.
  • the first end of the nine controllable switch T9 is connected to the control end of the tenth controllable switch T10 and the first end, the first end of the eleventh controllable switch T11, and the second end of the first capacitor C1
  • the second end of the tenth controllable switch T10 is connected to the control end of the eleventh controllable switch T11, the tenth The second end of the controllable switch T13 and the first end of the fourteenth controllable switch T14, the second end of the eleventh controllable switch T11 is connected to the first end of the twelfth controllable switch T12
  • the control end of the thirteenth controllable switch T13 receives the upper-level scan signal, and the control end of the fourteenth controllable switch
  • the first to fourteen controllable switches T8-T14 are N-type thin film transistors, and the control ends, the first ends and the second ends of the first to fourteenth controllable switches T8-T14 The terminals respectively correspond to the gate, the drain and the source of the N-type thin film transistor.
  • the first to fourteenth controllable switches may also be other types of switches as long as the object of the present invention can be achieved.
  • the operation principle of the second embodiment of the scan driving circuit is different from that of the first embodiment of the scan driving circuit described above in that, in the second embodiment, the scan driving circuit performs positive When scanning, when the upper scanning signal Gn-1 is at a high level, the thirteenth controllable switch T13 is turned on first and the M point is pulled down to prevent accumulation of M point charges due to long-term operation of the circuit. And preventing the eighth controllable switch T8 from being turned on when the pull-up control signal point Q is pre-charged, causing noise interference of the current-level scan line Gn.
  • the fourteenth controllable switch T14 When the scan driving circuit performs reverse scanning, when the lower-level scan signal Gn+1 is at a high level, the fourteenth controllable switch T14 is turned on first and the M point is pulled down to prevent the circuit from being operated for a long time. The accumulation of the M-point charge, thereby preventing the eighth controllable switch T8 from being turned on when the pull-up control signal point Q is pre-charged, causing noise interference of the scanning line Gn of the current stage, thereby effectively reducing the induced voltage. In addition, the uniformity of the common mode signal voltage in the panel is improved, and the quality of the screen display is improved.
  • FIG. 8 is a schematic diagram of a flat display device according to the present invention.
  • the flat display device includes the aforementioned scan driving circuit, and the scan driving circuit is disposed at both ends of the flat display device.
  • the flat display device is an LCD or an OLED.
  • Other devices and functions of the flat display device are the same as those of the existing flat display device, and are not described herein again.
  • the scan driving circuit of the present invention controls the scan driving circuit to perform forward scanning and reverse scanning through the forward/back sweep circuit, and charges the pull-up control signal point and the pull-down control signal point through the input circuit, and passes through the
  • the output circuit generates a scan drive signal having a two-step high level and outputs it to the scan line to drive the pixel unit, thereby effectively reducing the induced voltage, thereby improving the uniformity of the common mode signal voltage in the panel and improving the quality of the picture display.

Abstract

提供了一种扫描驱动电路及平面显示装置。扫描驱动电路包括级联的多个扫描驱动单元，每一扫描驱动单元包括正反扫电路（100），接控制正向扫描或反向扫描；输入电路（200），对上拉控制信号点及下拉控制信号点进行充电；输出电路（300），产生具有两阶高电平的扫描驱动信号输出给本级扫描线来驱动像素单元。

Description

扫描驱动电路及具有该电路的平面显示装置
【技术领域】
本发明涉及显示技术领域，特别是涉及一种扫描驱动电路及具有该电路的平面显示装置。
【背景技术】
目前的平面显示装置中采用扫描驱动电路，也就是利用现有薄膜晶体管平面显示器阵列制程将扫描驱动电路制作在阵列基板上，实现对逐行扫描的驱动方式。现有的扫描驱动电路的本级扫描线输出的高低电平分别为开启电压端信号和关闭电压端信号且为两阶驱动，这种驱动方式对应的感应电压较大，进而造成面板不同区域对应的最佳化共模信号电压不一致，也就是说两阶驱动容易造成面板的共模信号电压的均一性较差，影响画面显示的品质。
【发明内容】
本发明主要解决的技术问题是提供一种扫描驱动电路及具有该电路的平面显示装置，以有效降低感应电压，进而改善面板内共模信号电压的均一性，提高画面显示的品质。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种扫描驱动电路，其中，所述扫描驱动电路包括级联的多个扫描驱动单元，每一所述扫描驱动单元包括：
正反扫电路，用于接收上级扫描信号及第一时钟信号并输出第一控制信号以控制所述扫描驱动电路进行正向扫描，或用于接收下级扫描信号及第二时钟信号并输出第二控制信号以控制所述扫描驱动电路进行反向扫描；
输入电路，连接所述正反扫电路，用于接收第三时钟信号及从所述正反扫电路接收所述第一及第二控制信号并根据所述第三时钟信号、所述第一及第二控制信号对上拉控制信号点及下拉控制信号点进行充电；及
输出电路，连接所述输入电路，用于对接收到的第三控制信号或第四控制信号及从所述输入电路接收的数据进行处理，产生具有两阶高电平的扫描驱动信号输出给本级扫描线来驱动像素单元。
其中，所述第三控制信号包括第四时钟信号及复位信号，所述第四控制信号包括第四时钟信号、复位信号、所述上级扫描信号及所述下级扫描信号。
其中，所述正反扫电路包括第一及第二可控开关，所述第一可控开关的控制端接收所述第一时钟信号，所述第一可控开关的第一端接收所述上级扫描信号，所述第一可控开关的第二端连接所述第二可控开关的第一端及所述输入电路，所述第二可控开关的控制端接收所述第二时钟信号，所述第二可控开关的第二端接收所述下级扫描信号。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种扫描驱动电路，所述扫描驱动电路包括级联的多个扫描驱动单元，每一所述扫描驱动单元包括：
正反扫电路，用于接收上级扫描信号及第一时钟信号并输出第一控制信号以控制所述扫描驱动电路进行正向扫描，或用于接收下级扫描信号及第二时钟信号并输出第二控制信号以控制所述扫描驱动电路进行反向扫描；
输入电路，连接所述正反扫电路，用于接收第三时钟信号及从所述正反扫电路接收所述第一及第二控制信号并根据所述第三时钟信号、所述第一及第二控制信号对上拉控制信号点及下拉控制信号点进行充电；及
输出电路，连接所述输入电路，用于对接收到的第三控制信号或第四控制信号及从所述输入电路接收的数据进行处理，产生具有两阶高电平的扫描驱动信号输出给本级扫描线来驱动像素单元。
其中，所述第三控制信号包括第四时钟信号及复位信号，所述第四控制信号包括第四时钟信号、复位信号、所述上级扫描信号及所述下级扫描信号。
其中，所述正反扫电路包括第一及第二可控开关，所述第一可控开关的控制端接收所述第一时钟信号，所述第一可控开关的第一端接收所述上级扫描信号，所述第一可控开关的第二端连接所述第二可控开关的第一端及所述输入电路，所述第二可控开关的控制端接收所述第二时钟信号，所述第二可控开关的第二端接收所述下级扫描信号。
其中，所述输入电路包括第三至第七可控开关、第一及第二电容，所述第三可控开关的控制端接收开启电压端信号，所述第三可控开关的第一端连接所述第四可控开关的控制端、所述第一可控开关的第二端及所述第二可控开关的第一端，所述第三可控开关的第二端连接所述第五可控开关的第一端及所述输出电路，所述第五可控开关的第二端连接所述第四可控开关的第二端、所述第六可控开关的第二端及所述第七可控开关的第二端并接收关闭电压端信号，所述第五可控开关的控制端连接所述第四可控开关的第一端及所述第六可控开关的控制端，所述第六可控开关的第一端连接所述第七可控开关的第一端及所述输出电路，所述第七可控开关的控制端接收所述第三时钟信号，所述第一电容的第一端连接所述第五可控开关的控制端，所述第一电容的第二端连接所述输出电路，所述第二电容连接在所述第六可控开关的控制端与第二端之间。
其中，所述输出电路包括第八至第十二可控开关及第三电容，所述第八可控开关的控制端连接所述第三可控开关的第二端、所述第五可控开关的第一端及所述第十二可控开关的控制端，所述第八可控开关的第一端连接所述第九可控开关的第二端，所述第八可控开关的第二端连接所述第六及第七可控开关的第一端、所述第十二可控开关的第二端及本级扫描线，所述第九可控开关的控制端接收所述复位信号，所述第九可控开关的第一端连接所述第十可控开关的控制端及第一端、所述第十一可控开关的第一端及所述第一电容的第二端并接收所述第四时钟信号，所述第十可控开关的第二端连接所述第十一可控开关的控制端，所述第十一可控开关的第二端连接所述第十二可控开关的第一端，所述第三电容连接在所述第八可控开关的控制端与第二端之间。
其中，所述第一至第十二可控开关为N型薄膜晶体管，所述第一至第十二可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。
其中，所述输出电路包括第八至第十四可控开关及第三电容，所述第八可控开关的控制端连接所述第三可控开关的第二端、所述第五可控开关的第一端及所述第十二可控开关的控制端，所述第八可控开关的第一端连接所述第九可控开关的第二端，所述第八可控开关的第二端连接所述第六及第七可控开关的第一端、所述第十二可控开关的第二端及本级扫描线，所述第九可控开关的控制端接收所述复位信号，所述第九可控开关的第一端连接所述第十可控开关的控制端及第一端、所述第十一可控开关的第一端及所述第一电容的第二端并接收所述第四时钟信号，所述第十可控开关的第二端连接所述第十一可控开关的控制端、所述第十三可控开关的第二端及所述第十四可控开关的第一端，所述第十一可控开关的第二端连接所述第十二可控开关的第一端，所述第十三可控开关的控制端接收所述上级扫描信号，所述第十四可控开关的控制端接收所述下级扫描信号，所述第十三可控开关的第一端连接所述第十四可控开关的第二端并接收所述关闭电压端信号，所述第三电容连接在所述第八可控开关的控制端与第二端之间。
其中，所述第一至第十四可控开关为N型薄膜晶体管，所述第一至第十四可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种平面显示装置，所述平面显示装置包括扫描驱动电路，所述扫描驱动电路包括级联的多个扫描驱动单元，每一所述扫描驱动单元包括：
正反扫电路，用于接收上级扫描信号及第一时钟信号并输出第一控制信号以控制所述扫描驱动电路进行正向扫描，或用于接收下级扫描信号及第二时钟信号并输出第二控制信号以控制所述扫描驱动电路进行反向扫描；
输入电路，连接所述正反扫电路，用于接收第三时钟信号及从所述正反扫电路接收所述第一及第二控制信号并根据所述第三时钟信号、所述第一及第二控制信号对上拉控制信号点及下拉控制信号点进行充电；及
输出电路，连接所述输入电路，用于对接收到的第三控制信号或第四控制信号及从所述输入电路接收的数据进行处理，产生具有两阶高电平的扫描驱动信号输出给本级扫描线来驱动像素单元。
其中，所述第三控制信号包括第四时钟信号及复位信号，所述第四控制信号包括第四时钟信号、复位信号、所述上级扫描信号及所述下级扫描信号。
其中，所述正反扫电路包括第一及第二可控开关，所述第一可控开关的控制端接收所述第一时钟信号，所述第一可控开关的第一端接收所述上级扫描信号，所述第一可控开关的第二端连接所述第二可控开关的第一端及所述输入电路，所述第二可控开关的控制端接收所述第二时钟信号，所述第二可控开关的第二端接收所述下级扫描信号。
其中，所述输入电路包括第三至第七可控开关、第一及第二电容，所述第三可控开关的控制端接收开启电压端信号，所述第三可控开关的第一端连接所述第四可控开关的控制端、所述第一可控开关的第二端及所述第二可控开关的第一端，所述第三可控开关的第二端连接所述第五可控开关的第一端及所述输出电路，所述第五可控开关的第二端连接所述第四可控开关的第二端、所述第六可控开关的第二端及所述第七可控开关的第二端并接收关闭电压端信号，所述第五可控开关的控制端连接所述第四可控开关的第一端及所述第六可控开关的控制端，所述第六可控开关的第一端连接所述第七可控开关的第一端及所述输出电路，所述第七可控开关的控制端接收所述第三时钟信号，所述第一电容的第一端连接所述第五可控开关的控制端，所述第一电容的第二端连接所述输出电路，所述第二电容连接在所述第六可控开关的控制端与第二端之间。
其中，所述输出电路包括第八至第十二可控开关及第三电容，所述第八可控开关的控制端连接所述第三可控开关的第二端、所述第五可控开关的第一端及所述第十二可控开关的控制端，所述第八可控开关的第一端连接所述第九可控开关的第二端，所述第八可控开关的第二端连接所述第六及第七可控开关的第一端、所述第十二可控开关的第二端及本级扫描线，所述第九可控开关的控制端接收所述复位信号，所述第九可控开关的第一端连接所述第十可控开关的控制端及第一端、所述第十一可控开关的第一端及所述第一电容的第二端并接收所述第四时钟信号，所述第十可控开关的第二端连接所述第十一可控开关的控制端，所述第十一可控开关的第二端连接所述第十二可控开关的第一端，所述第三电容连接在所述第八可控开关的控制端与第二端之间。
其中，所述第一至第十二可控开关为N型薄膜晶体管，所述第一至第十二可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。
其中，所述输出电路包括第八至第十四可控开关及第三电容，所述第八可控开关的控制端连接所述第三可控开关的第二端、所述第五可控开关的第一端及所述第十二可控开关的控制端，所述第八可控开关的第一端连接所述第九可控开关的第二端，所述第八可控开关的第二端连接所述第六及第七可控开关的第一端、所述第十二可控开关的第二端及本级扫描线，所述第九可控开关的控制端接收所述复位信号，所述第九可控开关的第一端连接所述第十可控开关的控制端及第一端、所述第十一可控开关的第一端及所述第一电容的第二端并接收所述第四时钟信号，所述第十可控开关的第二端连接所述第十一可控开关的控制端、所述第十三可控开关的第二端及所述第十四可控开关的第一端，所述第十一可控开关的第二端连接所述第十二可控开关的第一端，所述第十三可控开关的控制端接收所述上级扫描信号，所述第十四可控开关的控制端接收所述下级扫描信号，所述第十三可控开关的第一端连接所述第十四可控开关的第二端并接收所述关闭电压端信号，所述第三电容连接在所述第八可控开关的控制端与第二端之间。
其中，所述第一至第十四可控开关为N型薄膜晶体管，所述第一至第十四可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。
其中，所述平面显示装置为LCD或OLED。
本发明的有益效果是：区别于现有技术的情况，本发明的扫描驱动电路通过所述正反扫电路控制所述扫描驱动电路进行正向扫描及反向扫描，并通过所述输入电路对上拉控制信号点及下拉控制信号点进行充电，通过所述输出电路产生具有两阶高电平的扫描驱动信号输出给扫描线来驱动像素单元，以此实现有效降低感应电压，进而改善面板内共模信号电压的均一性，提高画面显示的品质。
【附图说明】
图1是现有技术中扫描驱动电路的一个扫描驱动单元的结构示意图；
图2是图1的正向扫描波形图；
图3是图1的反向扫描波形图；
图4是本发明的扫描驱动电路的一个扫描驱动单元的第一实施例的结构示意图；
图5是图4的正向扫描波形图；
图6是图4的反向扫描波形图；
图7是本发明的扫描驱动电路的一个扫描驱动单元的第二实施例的结构示意图；
图8是本发明的平面显示装置的示意图。
【具体实施方式】
请参阅图1及图2，现有技术中扫描驱动电路的工作原理（正向扫描）如下：
预充电阶段：上级扫描信号Gn-1与时钟信号CKV1同时为高电平时，薄膜晶体管T1导通，H点为高电平，使得薄膜晶体管T6处于导通状态，下拉控制信号点P被拉低；
本级扫描线Gn输出高电平阶段：薄膜晶体管T5的栅极接收开启电压端信号VGH一直处于导通状态，在预充电阶段，上拉控制信号点Q被预充电，电容C3对电荷具有一定的保持作用，薄膜晶体管T2处于导通状态，时钟信号CKV2的高电平输出到本级扫描线Gn；
本级扫描线Gn输出低电平阶段：时钟信号CKV3与下级扫描信号Gn+1同时为高电平时，薄膜晶体管T3导通，上拉控制信号点Q被保持在高电平，而此时时钟信号CKV2的低电平将本级扫描线Gn拉低；
上拉控制信号点Q被拉低到关闭电压端信号VGL阶段：当时钟信号CKV1再次变为高电平时，此时上级扫描信号Gn-1为低电平，薄膜晶体管T1处于导通状态，上拉控制信号点Q被拉低到关闭电压端信号VGL；
上拉控制信号点Q及本级扫描线Gn处于低电平维持阶段：当上拉控制信号点Q变为低电平后，薄膜晶体管T6处于截止状态，当时钟信号CKV2变为高电平时，由于电容C1的自举，下拉控制信号点P变为高电平，薄膜晶体管T4和T7均处于导通状态，以保证上拉控制信号点Q及本级扫描线Gn的低电平的稳定。
请参阅图1及图3，现有技术中扫描驱动电路的工作原理（反向扫描）如下：
预充电阶段：下级扫描信号Gn+1与时钟信号CKV3同时为高电平时，薄膜晶体管T3导通，H点为高电平，薄膜晶体管T6处于导通状态，下拉控制信号点P被拉低；
本级扫描线Gn输出高电平阶段：薄膜晶体管T5的栅极接收开启电压端信号VGH一直处于导通状态，在预充电阶段，上拉控制信号点Q被预充电，电容C3对电荷具有一定的保持作用，薄膜晶体管T2处于导通状态，时钟信号CKV2的高电平输出到本级扫描线Gn；
本级扫描线Gn输出低电平阶段：时钟信号CKV1与下级扫描信号Gn-1同时为高电平时，薄膜晶体管T1导通，上拉控制信号点Q被保持在高电平，而此时时钟信号CKV2的低电平将本级扫描线Gn拉低；
上拉控制信号点Q被拉低到关闭电压端信号VGL：当时钟信号CKV3再次变为高电平时，此时下级扫描信号Gn+1为低电平，薄膜晶体管T3处于导通状态，上拉控制信号点Q被拉低到关闭电压端信号VGL；
上拉控制信号点Q及本级扫描线Gn处于低电平维持阶段：当上拉控制信号点Q变为低电平后，薄膜晶体管T6处于截止状态，当时钟信号CKV2变为高电平时，由于电容C1的自举，下拉控制信号点P变为高电平，薄膜晶体管T4和T7均处于导通状态，以保证上拉控制信号点Q及本级扫描线Gn的低电平的稳定，现有的扫描驱动电路的本级扫描线输出的高低电平分别为开启电压端信号VGH和关闭电压端信号VGL且为两阶驱动，这种驱动方式对应的感应电压较大，进而造成面板不同区域对应的最佳化共模信号电压不一致，也就是说两阶驱动容易造成面板的共模信号电压的均一性较差，影响显示的品质。
请参阅图4，是本发明的扫描驱动电路的一个扫描驱动单元的第一实施例的结构示意图。在本实施方式中，仅以一个扫描驱动单元为例进行说明。如图4所示，本发明的扫描驱动电路包括级联的多个扫描驱动单元，每一所述扫描驱动单元包括正反扫电路100，用于接收上级扫描信号及第一时钟信号并输出第一控制信号以控制所述扫描驱动电路进行正向扫描，或用于接收下级扫描信号及第二时钟信号并输出第二控制信号以控制所述扫描驱动电路进行反向扫描；输入电路200，连接所述正反扫电路100，用于接收第三时钟信号及从所述正反扫电路100接收所述第一及第二控制信号并根据所述第三时钟信号、所述第一及第二控制信号对上拉控制信号点及下拉控制信号点进行充电；输出电路300，连接所述输入电路200，用于对接收到的第三控制信号或第四控制信号及从所述输入电路200接收的数据进行处理，产生具有两阶高电平的扫描驱动信号输出给本级扫描线来驱动像素单元。
具体地，在所述第一实施例中，所述第三控制信号包括第四时钟信号及复位信号；在所述第二实施例中，所述第四控制信号包括第四时钟信号、复位信号、所述上级扫描信号及所述下级扫描信号。
所述正反扫电路100包括第一及第二可控开关T1、T2，所述第一可控开关T1的控制端接收所述第一时钟信号，所述第一可控开关T1的第一端接收所述上级扫描信号，所述第一可控开关T1的第二端连接所述第二可控开关T2的第一端及所述输入电路200，所述第二可控开关T2的控制端接收所述第二时钟信号，所述第二可控开关T2的第二端接收所述下级扫描信号。
所述输入电路200包括第三至第七可控开关T3-T7、第一及第二电容C1、C2，所述第三可控开关T3的控制端接收开启电压端信号VGH，所述第三可控开关T3的第一端连接所述第四可控开关T4的控制端、所述第一可控开关T1的第二端及所述第二可控开关T2的第一端，所述第三可控开关T3的第二端连接所述第五可控开关T5的第一端及所述输出电路300，所述第五可控开关T5的第二端连接所述第四可控开关T4的第二端、所述第六可控开关T6的第二端及所述第七可控开关T7的第二端并接收关闭电压端信号VGL，所述第五可控开关T5的控制端连接所述第四可控开关T4的第一端及所述第六可控开关T6的控制端，所述第六可控开关T6的第一端连接所述第七可控开关T7的第一端及所述输出电路300，所述第七可控开关T7的控制端接收所述第三时钟信号，所述第一电容C1的第一端连接所述第五可控开关T5的控制端，所述第一电容C1的第二端连接所述输出电路300，所述第二电容C2连接在所述第六可控开关T6的控制端与第二端之间。
所述输出电路300包括第八至第十二可控开关T8-T12及第三电容C3，所述第八可控开关T8的控制端连接所述第三可控开关T3的第二端、所述第五可控开关T5的第一端及所述第十二可控开关T12的控制端，所述第八可控开关T8的第一端连接所述第九可控开关T9的第二端，所述第八可控开关T8的第二端连接所述第六可控开关T6及第七可控开关T7的第一端、所述第十二可控开关T12的第二端及本级扫描线，所述第九可控开关T9的控制端接收所述复位信号，所述第九可控开关T9的第一端连接所述第十可控开关T10的控制端及第一端、所述第十一可控开关T11的第一端及所述第一电容C1的第二端并接收所述第四时钟信号，所述第十可控开关T10的第二端连接所述第十一可控开关T11的控制端，所述第十一可控开关T11的第二端连接所述第十二可控开关T12的第一端，所述第三电容C3连接在所述第八可控开关T8的控制端与第二端之间。
在本实施例中，所述第一至第十二可控开关T1-T12为N型薄膜晶体管，所述第一至第十二可控开关T1-T12的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。在其他实施例中，所述第一至第十二可控开关也可为其他类型的开关，只要能实现本发明的目的即可。
在本实施例中，所述上级扫描信号为上级扫描信号Gn-1，所述下级扫描信号为下级扫描信号Gn+1，所述第一时钟信号为时钟信号CKV1，所述第二时钟信号为时钟信号CKV3，所述第三时钟信号为时钟信号CKV4，所述第四时钟信号为时钟信号CKV2，所述复位信号为复位信号Reset，所述上拉控制信号点为上拉控制信号点Q，所述下拉控制信号点为下拉控制信号点P。
请参阅图4及图5，可以得到所述扫描驱动电路的一个扫描驱动单元的工作原理（正向扫描）如下：
预充电阶段：所述上级扫描信号Gn-1与第一时钟信号CKV1同时为高电平时，所述第一可控开关T1导通，H点为高电平，所述第四可控开关T4处于导通状态，所述下拉控制信号点P被拉低；
所述本级扫描线Gn输出高电平阶段：所述第三可控开关T3的控制端接收所述开启电压端信号VGH一直处于导通状态，在预充电阶段，所述上拉控制信号点Q被预充电，所述第三电容C3对电荷具有一定的保持作用，所述第八可控开关T8处于导通状态，当所述复位信号Reset为高电平时，所述第九可控开关T9导通，所述第四时钟信号CKV2的高电平输出到所述本级扫描线Gn；当所述复位信号Reset为低电平时，所述第九可控开关T9截止，而此时所述第十可控开关T10及所述第十一可控开关T11均处于导通状态，所述第四时钟信号CKV2的高电平会对M点进行充电（通过调整所述第九可控开关T9和所述第十可控开关T10的大小，可以实现M点的高电平相对于所述第四时钟信号CKV2对应的高电平有所降低），通过所述复位信号Reset、所述第十可控开关T10和所述第十一可控开关T11的配合，当所述复位信号Reset为低电平时，使得所述本级扫描线Gn的高电平相比所述第四时钟信号CKV2的高电平有所降低，即实现所述本级扫描线Gn输出两阶高电平；
本级扫描线Gn输出低电平阶段：当所述第二时钟信号CKV3与下级扫描信号Gn+1同时为高电平时，所述第二可控开关T2导通，所述上拉控制信号点Q被保持在高电平，此时所述复位信号Reset为高电平信号，所述第九可控开关T9导通，所述第四时钟信号CKV2的低电平将所述本级扫描线Gn拉低；
所述上拉控制信号点Q被拉低到所述关闭电压端信号VGL：当所述第一时钟信号CKV1再次变为高电平时，此时所述上级扫描信号Gn-1为低电平，所述第一可控开关T1处于导通状态，所述上拉控制信号点Q被拉低到所述关闭电压端信号VGL；
所述上拉控制信号点Q及所述本级扫描线Gn处于低电平维持阶段：当所述上拉控制信号点Q变为低电平后，所述第四可控开关T4处于截止状态，当所述第四时钟信号CKV2变为高电平时，由于所述第一电容C1的自举，所述下拉控制信号点P变为高电平，所述第六可控开关T6和所述第五可控开关T5均处于导通状态，以保证所述上拉控制信号点Q及所述本级扫描线Gn的低电平的稳定。
请参阅图4及图6，可以得到所述扫描驱动电路的一个扫描驱动单元的工作原理（反向扫描）如下：
预充电阶段：所述下级扫描信号Gn+1与第二时钟信号CKV3同时为高电平时，所述第二可控开关T2导通，H点为高电平，所述第四可控开关T4处于导通状态，P点被拉低；
本级扫描线Gn输出高电平阶段：所述第三可控开关T3的控制端接收所述开启电压端信号VGH一直处于导通状态，在预充电阶段，所述上拉控制信号点Q被预充电，所述第三电容C3对电荷具有一定的保持作用，所述第八可控开关T8处于导通状态，当所述复位信号Reset为高电平时，所述第九可控开关T9导通，所述第四时钟信号CKV2的高电平输出到所述本级扫描线Gn；当所述复位信号Reset为低电平时，所述第九可控开关T9截止，而此时所述第十可控开关T10及所述第十一可控开关T11均处于导通状态，所述第四时钟信号CKV2的高电平会对M点进行充电（通过调整所述第九可控开关T9和所述第十可控开关T10的大小，可以实现M点的高电平相对于所述第四时钟信号CKV2对应的高电平有所降低），通过所述复位信号Reset、所述第十可控开关T10和所述第十一可控开关T11的配合，当所述复位信号Reset为低电平时，使得所述本级扫描线Gn的高电平相比所述第四时钟信号CKV2的高电平有所降低，即实现所述本级扫描线Gn输出两阶高电平。
本级扫描线Gn输出低电平阶段：所述第一时钟信号CKV1与所述上级扫描信号Gn-1同时为高电平时，所述第一可控开关T1导通，所述上拉控制信号点Q被保持在高电平，此时所述复位信号Reset为高电平，所述第九可控开关T9导通，所述第四时钟信号CKV2的低电平将所述本级扫描线Gn拉低；
所述上拉控制信号点Q被拉低到关闭电压端信号VGL阶段：当所述第二时钟信号CKV3再次变为高电平时，此时所述下级扫描信号Gn+1为低电平，所述第二可控开关T2处于导通状态，所述上拉控制信号点Q被拉低到所述关闭电压端信号VGL；
所述上拉控制信号点Q及所述本级扫描线Gn处于低电平维持阶段：当所述上拉控制信号点Q变为低电平后，所述第四可控开关T4处于截止状态，当所述第四时钟信号CKV2变为高电平时，由于所述第一电容C1的自举，所述下拉控制信号点P变为高电平，所述第六可控开关T6和所述第五可控开关T5均处于导通状态，以保证所述上拉控制信号点Q及所述本级扫描线Gn的低电平的稳定，以此实现有效降低感应电压，进而改善面板内共模信号电压的均一性，提高画面显示的品质。
请参阅图7，是本发明的扫描驱动电路的一个扫描驱动单元的第二实施例的结构示意图。所述扫描驱动电路的第二实施例与所述扫描驱动电路的第一实施例的区别之处在于：所述输出电路300包括第八至第十四可控开关T8-T14及第三电容C3，所述第八可控开关T8的控制端连接所述第三可控开关T3的第二端、所述第五可控开关T5的第一端及所述第十二可控开关T12的控制端，所述第八可控开关T8的第一端连接所述第九可控开关T9的第二端，所述第八可控开关T8的第二端连接所述第六可控开关T6及第七可控开关T7的第一端、所述第十二可控开关T12的第二端及本级扫描线，所述第九可控开关T9的控制端接收所述复位信号，所述第九可控开关T9的第一端连接所述第十可控开关T10的控制端及第一端、所述第十一可控开关T11的第一端及所述第一电容C1的第二端并接收所述第四时钟信号，所述第十可控开关T10的第二端连接所述第十一可控开关T11的控制端、所述第十三可控开关T13的第二端及所述第十四可控开关T14的第一端，所述第十一可控开关T11的第二端连接所述第十二可控开关T12的第一端，所述第十三可控开关T13的控制端接收所述上级扫描信号，所述第十四可控开关T14的控制端接收所述下级扫描信号，所述第十三可控开关T13的第一端连接所述第十四可控开关T14的第二端并接收所述关闭电压端信号VGL，所述第三电容C3连接在所述第八可控开关T8的控制端与第二端之间。
在本实施例中，所述第一至第十四可控开关T8-T14为N型薄膜晶体管，所述第一至第十四可控开关T8-T14的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。在其他实施例中，所述第一至第十四可控开关也可为其他类型的开关，只要能实现本发明的目的即可。
所述扫描驱动电路的第二实施例的工作原理与上述所述扫描驱动电路的第一实施例的工作原理的不同之处在于：在所述第二实施例中，所述扫描驱动电路进行正向扫描时，当所述上级扫描信号Gn-1为高电平时，所述第十三可控开关T13先导通并且对M点进行拉低处理，防止由于电路长时间工作造成M点电荷的累积，进而防止当所述上拉控制信号点Q被预充电时，所述第八可控开关T8打开而造成所述本级扫描线Gn存在噪声干扰。
所述扫描驱动电路进行反向扫描时，当下级扫描信号Gn+1为高电平时，所述第十四可控开关T14先导通并且对M点进行拉低处理，防止由于电路长时间工作造成M点电荷的累积，进而防止当所述上拉控制信号点Q被预充电时，所述第八可控开关T8打开而造成本级扫描线Gn存在噪声干扰，以此实现有效降低感应电压，进而改善面板内共模信号电压的均一性，提高画面显示的品质。
请参阅图8，为本发明一种平面显示装置的示意图。所述平面显示装置包括前述的扫描驱动电路，所述扫描驱动电路设置在所述平面显示装置的两端。其中，所述平面显示装置为LCD或OLED。所述平面显示装置的其他器件及功能与现有平面显示装置的器件及功能相同，在此不再赘述。
本发明的扫描驱动电路通过所述正反扫电路控制所述扫描驱动电路进行正向扫描及反向扫描，并通过所述输入电路对上拉控制信号点及下拉控制信号点进行充电，通过所述输出电路产生具有两阶高电平的扫描驱动信号输出给扫描线来驱动像素单元，以此实现有效降低感应电压，进而改善面板内共模信号电压的均一性，提高画面显示的品质。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (18)

  1. 一种扫描驱动电路，其中，所述扫描驱动电路包括级联的多个扫描驱动单元，每一所述扫描驱动单元包括：
    正反扫电路，用于接收上级扫描信号及第一时钟信号并输出第一控制信号以控制所述扫描驱动电路进行正向扫描，或用于接收下级扫描信号及第二时钟信号并输出第二控制信号以控制所述扫描驱动电路进行反向扫描；
    输入电路，连接所述正反扫电路，用于接收第三时钟信号及从所述正反扫电路接收所述第一及第二控制信号并根据所述第三时钟信号、所述第一及第二控制信号对上拉控制信号点及下拉控制信号点进行充电；及
    输出电路，连接所述输入电路，用于对接收到的第三控制信号或第四控制信号及从所述输入电路接收的数据进行处理，产生具有两阶高电平的扫描驱动信号输出给本级扫描线来驱动像素单元。
    其中，所述第三控制信号包括第四时钟信号及复位信号，所述第四控制信号包括第四时钟信号、复位信号、所述上级扫描信号及所述下级扫描信号。
    其中，所述正反扫电路包括第一及第二可控开关，所述第一可控开关的控制端接收所述第一时钟信号，所述第一可控开关的第一端接收所述上级扫描信号，所述第一可控开关的第二端连接所述第二可控开关的第一端及所述输入电路，所述第二可控开关的控制端接收所述第二时钟信号，所述第二可控开关的第二端接收所述下级扫描信号。
  2. 一种扫描驱动电路，其中，所述扫描驱动电路包括级联的多个扫描驱动单元，每一所述扫描驱动单元包括：
    正反扫电路，用于接收上级扫描信号及第一时钟信号并输出第一控制信号以控制所述扫描驱动电路进行正向扫描，或用于接收下级扫描信号及第二时钟信号并输出第二控制信号以控制所述扫描驱动电路进行反向扫描；
    输入电路，连接所述正反扫电路，用于接收第三时钟信号及从所述正反扫电路接收所述第一及第二控制信号并根据所述第三时钟信号、所述第一及第二控制信号对上拉控制信号点及下拉控制信号点进行充电；及
    输出电路，连接所述输入电路，用于对接收到的第三控制信号或第四控制信号及从所述输入电路接收的数据进行处理，产生具有两阶高电平的扫描驱动信号输出给本级扫描线来驱动像素单元。
  3. 根据权利要求2所述的扫描驱动电路，其中，所述第三控制信号包括第四时钟信号及复位信号，所述第四控制信号包括第四时钟信号、复位信号、所述上级扫描信号及所述下级扫描信号。
  4. 根据权利要求2所述的扫描驱动电路，其中，所述正反扫电路包括第一及第二可控开关，所述第一可控开关的控制端接收所述第一时钟信号，所述第一可控开关的第一端接收所述上级扫描信号，所述第一可控开关的第二端连接所述第二可控开关的第一端及所述输入电路，所述第二可控开关的控制端接收所述第二时钟信号，所述第二可控开关的第二端接收所述下级扫描信号。
  5. 根据权利要求4述的扫描驱动电路，其中，所述输入电路包括第三至第七可控开关、第一及第二电容，所述第三可控开关的控制端接收开启电压端信号，所述第三可控开关的第一端连接所述第四可控开关的控制端、所述第一可控开关的第二端及所述第二可控开关的第一端，所述第三可控开关的第二端连接所述第五可控开关的第一端及所述输出电路，所述第五可控开关的第二端连接所述第四可控开关的第二端、所述第六可控开关的第二端及所述第七可控开关的第二端并接收关闭电压端信号，所述第五可控开关的控制端连接所述第四可控开关的第一端及所述第六可控开关的控制端，所述第六可控开关的第一端连接所述第七可控开关的第一端及所述输出电路，所述第七可控开关的控制端接收所述第三时钟信号，所述第一电容的第一端连接所述第五可控开关的控制端，所述第一电容的第二端连接所述输出电路，所述第二电容连接在所述第六可控开关的控制端与第二端之间。
  6. 根据权利要求5所述的扫描驱动电路，其中，所述输出电路包括第八至第十二可控开关及第三电容，所述第八可控开关的控制端连接所述第三可控开关的第二端、所述第五可控开关的第一端及所述第十二可控开关的控制端，所述第八可控开关的第一端连接所述第九可控开关的第二端，所述第八可控开关的第二端连接所述第六及第七可控开关的第一端、所述第十二可控开关的第二端及本级扫描线，所述第九可控开关的控制端接收所述复位信号，所述第九可控开关的第一端连接所述第十可控开关的控制端及第一端、所述第十一可控开关的第一端及所述第一电容的第二端并接收所述第四时钟信号，所述第十可控开关的第二端连接所述第十一可控开关的控制端，所述第十一可控开关的第二端连接所述第十二可控开关的第一端，所述第三电容连接在所述第八可控开关的控制端与第二端之间。
  7. 根据权利要求6所述的扫描驱动电路，其中，所述第一至第十二可控开关为N型薄膜晶体管，所述第一至第十二可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。
  8. 根据权利要求6所述的扫描驱动电路，其中，所述输出电路包括第八至第十四可控开关及第三电容，所述第八可控开关的控制端连接所述第三可控开关的第二端、所述第五可控开关的第一端及所述第十二可控开关的控制端，所述第八可控开关的第一端连接所述第九可控开关的第二端，所述第八可控开关的第二端连接所述第六及第七可控开关的第一端、所述第十二可控开关的第二端及本级扫描线，所述第九可控开关的控制端接收所述复位信号，所述第九可控开关的第一端连接所述第十可控开关的控制端及第一端、所述第十一可控开关的第一端及所述第一电容的第二端并接收所述第四时钟信号，所述第十可控开关的第二端连接所述第十一可控开关的控制端、所述第十三可控开关的第二端及所述第十四可控开关的第一端，所述第十一可控开关的第二端连接所述第十二可控开关的第一端，所述第十三可控开关的控制端接收所述上级扫描信号，所述第十四可控开关的控制端接收所述下级扫描信号，所述第十三可控开关的第一端连接所述第十四可控开关的第二端并接收所述关闭电压端信号，所述第三电容连接在所述第八可控开关的控制端与第二端之间。
  9. 根据权利要求8所述的扫描驱动电路，其中，所述第一至第十四可控开关为N型薄膜晶体管，所述第一至第十四可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。
  10. 一种平面显示装置，其中，所述平面显示装置包括扫描驱动电路，所述扫描驱动电路包括级联的多个扫描驱动单元，每一所述扫描驱动单元包括：
    正反扫电路，用于接收上级扫描信号及第一时钟信号并输出第一控制信号以控制所述扫描驱动电路进行正向扫描，或用于接收下级扫描信号及第二时钟信号并输出第二控制信号以控制所述扫描驱动电路进行反向扫描；
    输入电路，连接所述正反扫电路，用于接收第三时钟信号及从所述正反扫电路接收所述第一及第二控制信号并根据所述第三时钟信号、所述第一及第二控制信号对上拉控制信号点及下拉控制信号点进行充电；及
    输出电路，连接所述输入电路，用于对接收到的第三控制信号或第四控制信号及从所述输入电路接收的数据进行处理，产生具有两阶高电平的扫描驱动信号输出给本级扫描线来驱动像素单元。
  11. 根据权利要求10所述的平面显示装置，其中，所述第三控制信号包括第四时钟信号及复位信号，所述第四控制信号包括第四时钟信号、复位信号、所述上级扫描信号及所述下级扫描信号。
  12. 根据权利要求10所述的平面显示装置，其中，所述正反扫电路包括第一及第二可控开关，所述第一可控开关的控制端接收所述第一时钟信号，所述第一可控开关的第一端接收所述上级扫描信号，所述第一可控开关的第二端连接所述第二可控开关的第一端及所述输入电路，所述第二可控开关的控制端接收所述第二时钟信号，所述第二可控开关的第二端接收所述下级扫描信号。
  13. 根据权利要求12所述的平面显示装置，其中，所述输入电路包括第三至第七可控开关、第一及第二电容，所述第三可控开关的控制端接收开启电压端信号，所述第三可控开关的第一端连接所述第四可控开关的控制端、所述第一可控开关的第二端及所述第二可控开关的第一端，所述第三可控开关的第二端连接所述第五可控开关的第一端及所述输出电路，所述第五可控开关的第二端连接所述第四可控开关的第二端、所述第六可控开关的第二端及所述第七可控开关的第二端并接收关闭电压端信号，所述第五可控开关的控制端连接所述第四可控开关的第一端及所述第六可控开关的控制端，所述第六可控开关的第一端连接所述第七可控开关的第一端及所述输出电路，所述第七可控开关的控制端接收所述第三时钟信号，所述第一电容的第一端连接所述第五可控开关的控制端，所述第一电容的第二端连接所述输出电路，所述第二电容连接在所述第六可控开关的控制端与第二端之间。
  14. 根据权利要求13所述的平面显示装置，其中，所述输出电路包括第八至第十二可控开关及第三电容，所述第八可控开关的控制端连接所述第三可控开关的第二端、所述第五可控开关的第一端及所述第十二可控开关的控制端，所述第八可控开关的第一端连接所述第九可控开关的第二端，所述第八可控开关的第二端连接所述第六及第七可控开关的第一端、所述第十二可控开关的第二端及本级扫描线，所述第九可控开关的控制端接收所述复位信号，所述第九可控开关的第一端连接所述第十可控开关的控制端及第一端、所述第十一可控开关的第一端及所述第一电容的第二端并接收所述第四时钟信号，所述第十可控开关的第二端连接所述第十一可控开关的控制端，所述第十一可控开关的第二端连接所述第十二可控开关的第一端，所述第三电容连接在所述第八可控开关的控制端与第二端之间。
  15. 根据权利要求14所述的平面显示装置，其中，所述第一至第十二可控开关为N型薄膜晶体管，所述第一至第十二可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。
  16. 根据权利要求14所述的平面显示装置，其中，所述输出电路包括第八至第十四可控开关及第三电容，所述第八可控开关的控制端连接所述第三可控开关的第二端、所述第五可控开关的第一端及所述第十二可控开关的控制端，所述第八可控开关的第一端连接所述第九可控开关的第二端，所述第八可控开关的第二端连接所述第六及第七可控开关的第一端、所述第十二可控开关的第二端及本级扫描线，所述第九可控开关的控制端接收所述复位信号，所述第九可控开关的第一端连接所述第十可控开关的控制端及第一端、所述第十一可控开关的第一端及所述第一电容的第二端并接收所述第四时钟信号，所述第十可控开关的第二端连接所述第十一可控开关的控制端、所述第十三可控开关的第二端及所述第十四可控开关的第一端，所述第十一可控开关的第二端连接所述第十二可控开关的第一端，所述第十三可控开关的控制端接收所述上级扫描信号，所述第十四可控开关的控制端接收所述下级扫描信号，所述第十三可控开关的第一端连接所述第十四可控开关的第二端并接收所述关闭电压端信号，所述第三电容连接在所述第八可控开关的控制端与第二端之间。
  17. 根据权利要求16所述的平面显示装置，其中，所述第一至第十四可控开关为N型薄膜晶体管，所述第一至第十四可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。
  18. 根据权利要求10所述的平面显示装置，其中，所述平面显示装置为LCD或OLED。
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