WO2017041330A1 - 液晶显示面板及其驱动电路、制造方法 - Google Patents

液晶显示面板及其驱动电路、制造方法 Download PDF

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Publication number
WO2017041330A1
WO2017041330A1 PCT/CN2015/090491 CN2015090491W WO2017041330A1 WO 2017041330 A1 WO2017041330 A1 WO 2017041330A1 CN 2015090491 W CN2015090491 W CN 2015090491W WO 2017041330 A1 WO2017041330 A1 WO 2017041330A1
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Prior art keywords
switching element
switching
liquid crystal
crystal display
display panel
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PCT/CN2015/090491
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English (en)
French (fr)
Inventor
王聪
杜鹏
Original Assignee
深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司, 武汉华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/897,624 priority Critical patent/US10203574B2/en
Publication of WO2017041330A1 publication Critical patent/WO2017041330A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1303—Apparatus specially adapted to the manufacture of LCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements
    • G02F2201/503—Arrangements improving the resistance to shock
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a liquid crystal display panel, a driving circuit thereof, and a manufacturing method.
  • ESD protection In the manufacturing process of the liquid crystal display panel, especially in the array process (array process) stage, multiple dry etching is required, and the dry etching process easily generates a large amount of static electricity. Therefore, in the design of the panel, in order to prevent the circuit from being damaged due to excessive static electricity accumulated inside the panel, electrostatic protection (ESD protection) is usually set.
  • ESD protection electrostatic protection
  • the electrostatic protection structure 102 is usually disposed on the opposite side of the data driving circuit 101 of the liquid crystal display panel 10.
  • the process of generating static electricity is mainly concentrated in the dry etching stage of the array process.
  • the static electricity protection structure 102 on the opposite side of the data driving circuit 101 no longer functions, and the external electrostatic protection structure is assembled after being assembled into a module. 102 still exists, which greatly wastes the space of the frame, which is not conducive to the narrow frame design of the panel.
  • the technical problem to be solved by the present invention is to provide a liquid crystal display panel, a driving circuit thereof and a manufacturing method thereof, which can realize electrostatic protection while effectively saving panel space, and is advantageous for realizing a narrow bezel design of the liquid crystal display panel.
  • a technical solution adopted by the present invention is to provide a driving circuit for a liquid crystal display panel, wherein the liquid crystal display panel is a low temperature polysilicon liquid crystal display panel, wherein the driving circuit includes a plurality of first switches a circuit; each of the first switching circuits includes a first switching element and a second switching element, the first switching element and the second switching element respectively including a control end, a first end, and a second end, the a first switching element and a first end of the second switching element are connected to the same data line of the liquid crystal display panel; wherein, in an array process stage of the liquid crystal display panel, the first switching element and the first The control terminals of the two switching elements are respectively configured to input a first reference voltage and a second reference voltage, and the second ends of the first switching element and the second switching element are respectively used to connect the first discharging circuit and the second discharging circuit
  • the first switching element is turned on when a voltage of the data line is lower than the first reference voltage to pass a voltage of
  • the method further includes a plurality of second switch circuits; each of the second switch circuits includes a third switch element and a fourth switch element, each of the second switch circuits corresponding to at least two first switch circuits, The second end of the first switching element of the at least two first switching circuits is connected to or receives the data signal through the third switching element, the second of the at least two first switching circuits a second end of the switching element is connected to or receives the data signal by the fourth switching element, wherein the third switching element and the fourth switching element respectively comprise a control end, first And a second end, the first end of the third switching element is connected to the second end of the first switching element of the at least two first switching circuits corresponding thereto, and the first end of the fourth switching element is connected to the second end a second end of the second switching element of the at least two first switching circuits; in the array processing stage of the liquid crystal display panel, the control ends of the third switching element and the fourth switching element are respectively used Entering the first reference voltage and the second reference voltage, the first ends of
  • the first reference voltage and the second reference voltage are ground voltages, and the first discharge circuit and the second discharge circuit are grounded short circuits; wherein, the array process of the liquid crystal display panel a control unit of the first switching element, the second switching element, the third switching element, and the fourth switching element are all connected to the short circuit, the third switching element, the fourth switch a second end of the circuit is connected to the short-circuit line, a third switching element of each of the second switching circuits, a first end of the fourth switching element, and a first switching element of the corresponding at least two first switching circuits
  • the second ends of the second switching elements are connected to each other, and the short-circuit lines are cut off during the driving display or test phase of the liquid crystal display panel, and the first switching elements and the second ones in each of the first switching circuits are a control end of at least one of the switching elements inputs the first control signal, and a control end of at least one of the third switching element and the fourth switching element of each of the second switching circuits inputs the second control A second end of
  • first switching element and the third switching element are N-type thin film transistors
  • the second switching element and the fourth switching element are P-type thin film transistors
  • a gate and a source of the thin film transistor And a drain as a control terminal, a first end, and a second end of the switching element, respectively.
  • a liquid crystal display panel including a driving circuit, the driving circuit including a plurality of first switching circuits; each of the first switching circuits includes a first a switching element, the first switching element includes a control end, a first end and a second end, the first end of the first switching element is connected to a data line of the liquid crystal display panel; wherein, the liquid crystal display panel
  • the array processing stage, the control end of the first switching element is for inputting a first reference voltage
  • the second end of the first switching element is for connecting a first discharge circuit
  • the first switching element is in the data Turning on when the voltage of the line is higher or lower than the first reference voltage to discharge the voltage of the data line through the first discharge circuit, in a driving display or test stage of the liquid crystal display panel, a control unit of a switching element inputs a first control signal, and a second end of the first switching element inputs a data signal to control the first switching element at the first control signal
  • the data to control the first switching element at the first control signal
  • each of the first switch circuits further includes a second switch element
  • the second switch element includes a control end, a first end and a second end
  • the first switch element and the second switch element One end is connected to the same data line of the liquid crystal display panel
  • the control ends of the first switching element and the second switching element are respectively used for inputting the first a reference voltage and a second reference voltage
  • the second ends of the first switching element and the second switching element are respectively used to connect a first discharge circuit and a second discharge circuit
  • the first switching element being in the data line Turning on when the voltage is lower than the first reference voltage to cause the voltage of the data line to be discharged through the first discharge circuit, and the voltage of the second switching element at the data line is higher than the second reference Turning on a voltage to cause a voltage of the data line to be discharged through the second discharge circuit, in a driving display or test phase of the liquid crystal display panel, to the first of the first switching element and the second switching element a control unit of
  • the method further includes a plurality of second switch circuits; each of the second switch circuits includes a third switch element and a fourth switch element, each of the second switch circuits corresponding to at least two first switch circuits, The second end of the first switching element of the at least two first switching circuits is connected to or receives the data signal through the third switching element, the second of the at least two first switching circuits a second end of the switching element is connected to or receives the data signal by the fourth switching element, wherein the third switching element and the fourth switching element respectively comprise a control end, first And a second end, the first end of the third switching element is connected to the second end of the first switching element of the at least two first switching circuits corresponding thereto, and the first end of the fourth switching element is connected to the second end a second end of the second switching element of the at least two first switching circuits; in the array processing stage of the liquid crystal display panel, the control ends of the third switching element and the fourth switching element are respectively used Entering the first reference voltage and the second reference voltage, the first ends of
  • the first reference voltage and the second reference voltage are ground voltages, and the first discharge circuit and the second discharge circuit are grounded short circuits; wherein, the array process of the liquid crystal display panel a control unit of the first switching element, the second switching element, the third switching element, and the fourth switching element are all connected to the short circuit, the third switching element, the fourth switch a second end of the circuit is connected to the short-circuit line, a third switching element of each of the second switching circuits, a first end of the fourth switching element, and a first switching element of the corresponding at least two first switching circuits
  • the second ends of the second switching elements are connected to each other, and the short-circuit lines are cut off during the driving display or test phase of the liquid crystal display panel, and the first switching elements and the second ones in each of the first switching circuits are a control end of at least one of the switching elements inputs the first control signal, and a control end of at least one of the third switching element and the fourth switching element of each of the second switching circuits inputs the second control A second end of
  • first switching element and the third switching element are N-type thin film transistors
  • the second switching element and the fourth switching element are P-type thin film transistors
  • a gate and a source of the thin film transistor And a drain as a control terminal, a first end, and a second end of the switching element, respectively.
  • another technical solution adopted by the present invention is to provide a method for manufacturing a liquid crystal display panel, comprising: forming a driving circuit of a liquid crystal display panel, the driving circuit comprising a plurality of first switching circuits, each The first switching circuit includes a first switching element, the first switching element includes a control end, a first end and a second end, and the first end of the first switching element is connected to a data line of the liquid crystal display panel
  • the control end of the first switching element is input to the first reference voltage
  • the second end of the first switching element is connected to the first discharge circuit to be the first a switching element causes a voltage of the data line to be discharged through the first discharging circuit when a voltage of the data line is higher or lower than the first reference voltage is turned on; after the array processing stage, Driving display or test phase of the liquid crystal display panel, disconnecting the second end of the first switching element from the first discharging circuit to control the first switching element Inputting a
  • the step of forming a driving circuit of the liquid crystal display panel includes: forming a driving circuit of the liquid crystal display panel, the driving circuit further comprising a plurality of second switching elements, the second switching element comprising a control end, the first end, and a second end, the first end of the first switching element and the second switching element are connected to the same data line of the liquid crystal display panel; and in the array processing stage of the liquid crystal display panel, the method further includes the steps of: The control terminal of the second switching element is input to the second reference voltage, and the second end of the second switching element is connected to the second discharge circuit, so that when the voltage of the second switching element is higher than the data line When the second reference voltage is turned on, the voltage of the data line is released by the second discharge circuit, wherein the first switching element is when the voltage of the data line is lower than the first reference voltage
  • the invention has the beneficial effects that, in the driving circuit of the present invention, in the array processing stage of the liquid crystal display panel, the data line is connected to the first discharge circuit through the first switching element to pass the first
  • the discharge circuit releases the electric charge on the data line, thereby realizing the electrostatic discharge of the data line, and the data signal is input to the data line through the first switching element during the driving display or test phase of the liquid crystal display panel, thereby realizing display or test of the liquid crystal display panel.
  • the first switching element is simultaneously used for electrostatic protection and panel driving display or testing, thereby eliminating the need for additional panel space or requiring less panel space to set the electrostatic protection structure, thereby saving panel space. Conducive to narrow frame.
  • FIG. 1 is a schematic structural view of a liquid crystal display panel having an electrostatic protection structure in the prior art
  • FIG. 2 is a schematic diagram showing a connection structure of a driving circuit for realizing electrostatic discharge of a data line in an array processing stage in a driving circuit of a liquid crystal display panel of the present invention
  • FIG. 3 is a schematic diagram showing a connection structure of a driving circuit for driving a data line in a driving display or test phase of a liquid crystal display panel in an embodiment of a driving circuit of a liquid crystal display panel of the present invention
  • FIG. 4 is a timing waveform diagram of a first control signal in a driving display or test phase of a liquid crystal display panel in an embodiment of a driving circuit of a liquid crystal display panel of the present invention
  • FIG. 5 is a schematic structural view of another embodiment of a driving circuit of a liquid crystal display panel of the present invention.
  • FIG. 6 is a timing waveform diagram of a first control signal and a second control signal in a driving display or test phase of the liquid crystal display panel in the driving circuit of the liquid crystal display panel shown in FIG. 5;
  • Fig. 7 is a flow chart showing an embodiment of a method of manufacturing a liquid crystal display panel of the present invention.
  • the liquid crystal display panel is low temperature polysilicon (Low). Temperature A liquid crystal display panel comprising a plurality of pixels, wherein the plurality of pixels are divided into R sub-pixel columns, G sub-pixel columns and B sub-pixel columns arranged periodically in the row direction, wherein the R sub-pixels, G The sub-pixel and the B sub-pixel constitute one pixel unit. Each sub-pixel column corresponds to one data line Dm, that is, a plurality of sub-pixels in each sub-pixel column are connected to one data line Dm.
  • the drive circuit 20 includes a plurality of first switch circuits 21 and three control lines L1, L3, L5, each of which includes a first switching element Q1.
  • the liquid crystal display panel can also be an amorphous silicon liquid crystal display panel.
  • the first switching element Q1 includes a control end, a first end, and a second end.
  • the first end of the first switching element Q1 is connected to one data line Dm of the liquid crystal display panel, that is, each data line Dm corresponds to one first switching element Q1.
  • the control terminal of the first switching element Q1 corresponding to the sub-pixel column of the same color is connected to the same control line.
  • the control terminals of the plurality of first switching elements Q1 corresponding to the plurality of R sub-pixel columns are respectively connected to the control line L1
  • the control terminals of the plurality of first switching elements Q1 corresponding to the plurality of G sub-pixel columns are respectively connected to the control lines.
  • L3 the control terminals of the plurality of first switching elements Q1 corresponding to the plurality of B sub-pixel columns are respectively connected to the control line L5.
  • the control ends of the first switching elements Q1 of the plurality of first switching circuits 21 are used to input the first reference voltage, specifically through three control lines L1.
  • L3, L5 input a first reference voltage to the control terminal of the first switching element Q1.
  • the first reference voltage may be a ground voltage or a voltage of a predetermined value, such as +0.5v or +1v.
  • the second end of the first switching element Q1 is used to connect the first discharge circuit 23.
  • the first switching element Q1 is an N-type thin film transistor, and the control terminal, the first end, and the second end of the first switching element Q1 correspond to a gate, a source, and a drain of the N-type thin film transistor. Therefore, during the dry etching process of the array process stage, a large amount of negative polarity static electricity is accumulated on the data line Dm, that is, the negative charge accumulated on the data line Dm is large, and the accumulated negative charge causes the voltage of the data line Dm (negative When the voltage is lower than the first reference voltage, the gate-source voltage Vgs (gate voltage-source voltage) is greater than zero, and the first switching element Q1 is turned on, thereby causing the data line Dm to communicate with the first discharge circuit 23, thereby data The negative charge accumulated on the line Dm can be discharged through the first discharge circuit 23 to achieve the purpose of electrostatic protection.
  • the first discharge circuit 23 may be a grounding resistor, or a grounding wire, or a positively charged wire or the like.
  • the first switching element Q1 and the first discharging circuit 23 can be turned off, such as the first discharging circuit 23 can be cut off.
  • the control end of the first switching element Q1 inputs a first control signal, and specifically can pass the three control lines L1, L3, and L5 to the first switching element Q1.
  • the control terminal inputs a first control signal to respectively control whether the first switching element Q1 corresponding to each data line Dm is turned on or off.
  • the waveform diagram of the first control signal received by the control lines L1, L3, and L5 may be as shown in FIG. 4, and the first switching element Q1 is input when a control signal of a high level is input to the control terminal of the first switching element Q1. Turn on.
  • the second end of the first switching element Q1 inputs a data signal.
  • the data signal is input through the second end of the first switching element Q1, and is transmitted to the corresponding data line Dm through the first switching element Q1, thereby realizing liquid crystal display
  • the drive display of the panel, or the data line Dm of the liquid crystal display panel can be tested.
  • a plurality of fifth switching elements Q5 are further included.
  • a plurality of fifth switching elements are disposed on opposite sides of the first switching element Q1, and each of the fifth switching elements Q5 corresponds to one data line Dm.
  • the fifth switching element Q5 is a P-type thin film transistor, the first end of the fifth switching element Q5 is connected to a data line Dm, the second end is connected to a ground line as a discharge circuit, and the control terminal inputs a ground voltage, that is, a fifth switching element.
  • the control terminal and the second terminal of the Q5 are connected to the ground.
  • the first switching element Q1 when the data line accumulates more negative charges, the first switching element Q1 is turned on, so that the negative charge on the data line is released through the first discharge circuit 23, and more accumulated on the data line.
  • the fifth switching element Q5 When the positive charge is applied, the fifth switching element Q5 is turned on, so that the positive charge on the data line is discharged through the ground line, thereby achieving the purpose of electrostatic protection.
  • At least the negative polarity electrostatic discharge in the array process is realized by using the first switching element for driving the display of the liquid crystal display panel to achieve electrostatic protection, thereby requiring less space for setting the positive static electricity.
  • the protective structure can reduce the panel space occupied by the static electricity protection structure, and is favorable for narrow frame.
  • the first switching element may also be a P-type thin film transistor.
  • the first switching element may also be a P-type thin film transistor.
  • the data line accumulates too much positive static electricity, that is, more positive charges are accumulated on the data line.
  • the gate-source voltage Vgs is less than zero, the first switching element is turned on, and the voltage on the data line is discharged through the first discharging circuit. This achieves electrostatic protection.
  • the first discharge circuit may be a grounding resistor, or a negatively charged wire or the like.
  • the control end of the first switching element inputs a first control signal, wherein when the control terminal of the first switching element inputs a low level, the first switching element is turned on, and the data signal is at this time.
  • the display or test of the liquid crystal display panel can be realized by inputting to the data line through the first switching element.
  • each of the first switching circuits 21 further includes a second switching element Q2
  • the driving circuit 20 further includes a plurality of second switching circuits 22, odd pixel data signal input lines L7, and even pixel data signal inputs.
  • Line L8 clock lines CK1 and CK2, and control lines L2, L4, and L6.
  • the second switching circuit 22 includes a third switching element Q3 and a fourth switching element Q4.
  • Each of the second switching circuits 22 corresponds to three first switching circuits 21.
  • the first switching element Q2, the third switching element Q3, and the fourth switching element respectively include a control end, a first end, and a second end.
  • the first ends of the first switching element Q1 and the second switching element Q2 of the same first switching circuit 21 are connected to the same data line Dm of the liquid crystal display panel, and the same of the first switching element Q1 and the second switching element Q2.
  • the two ends are connected, the third switching element Q3 of the same second switching circuit 22 is connected to the first end of the fourth switching element Q4, and the second ends of the same first switching element Q1 and the second switching element Q2 are corresponding thereto.
  • the third switching element Q3 of the second switching circuit 22 is connected to the first end of the fourth switching element Q4, that is, in the present embodiment, the third switching element Q3 and the fourth switching element Q4 of the second switching circuit 22 are One end is connected to the first end of the first switching element Q1 and the second switching element Q2 of the three first switching circuits 21 corresponding thereto, and the three switching circuits 21 are respectively connected to the data lines corresponding to the R sub-pixel columns.
  • the third switching element Q4 of the same second switching circuit 22 is connected to the second terminal of the fourth switching element Q4 and is connected to the data signal input line.
  • one second switching circuit 22 corresponds to one pixel unit, and thus the second switching element Q3 of the second switching circuit 22 corresponding to the odd pixel unit and the second end of the fourth switching element Q4 are connected to the odd pixel data signal input line.
  • L7, the third terminal of the third switching element Q3 and the fourth switching element Q4 of the second switching circuit 22 corresponding to the even pixel unit are connected to the even pixel data signal input line L8.
  • control terminals of all the third switching elements Q3 are connected to the clock line CK1, and the control terminals of all the fourth switching elements Q4 are connected to the clock line CK2.
  • the control terminal of the first switching element Q1 connected to the data line corresponding to the R sub-pixel column is connected to the control line L1
  • the control terminal of the second switching element Q2 connected to the data line corresponding to the R sub-pixel column is connected to the control line L2
  • a control end of the first switching element Q1 connected to the data line corresponding to the G sub-pixel column is connected to the control line L3, and a control end of the second switching element Q2 connected to the data line corresponding to the G sub-pixel column is connected to a control line L4
  • a control end of the first switching element Q1 connected to the data line corresponding to the B sub-pixel column is connected to the control line L5, and a control end of the second switching element Q2 connected to the data line corresponding to the B sub-pixel column Connect to control line L6.
  • the driving circuit 20 further includes a conduction pad P0 ⁇ P9 as a port, an odd pixel data signal input line L7, an even pixel data signal input line L8, clock lines CK1 and CK2, and control lines L1 ⁇ L6 and a conduction pad P0, respectively. ⁇ P9 connection.
  • a ground short-circuit line L9 is further formed on the side of the liquid crystal display panel.
  • the control ends of the first switching element Q1 and the second switching element Q2 are respectively used to input the first reference voltage and the second reference voltage, and the first switching element Q1 and the second switching element Q2 The second ends are respectively used to connect the first discharge circuit and the second discharge circuit.
  • the first reference voltage and the second reference voltage of the embodiment are both ground voltages, and the first discharge circuit and the second discharge circuit are grounded short-circuit lines L9. Therefore, the control lines L1 to L6 are all connected to the short ground.
  • the route L9 inputs a ground voltage as a reference voltage to the control terminals of the first switching element Q1 and the second switching element Q2.
  • the conduction pads P4 to P9 and the short-circuit line L9 may be connected by wires so that the control lines L1 to L6 are connected to the short-circuit line L9.
  • the control terminals of the third switching element Q3 and the fourth switching element Q4 are respectively used for inputting the first reference voltage and the second reference voltage, specifically by connecting the clock lines CK1, CK2 to the grounded short-circuit line L9, to the third The control terminals of the switching element Q3 and the fourth switching element Q4 input a ground voltage.
  • the conduction pads P2 to P3 and the short-circuit line L9 may be connected by wires so that the clock lines CK1 and CK2 and the short-circuit line L9 are connected.
  • the first switching element Q1 and the second switching element Q2 of the same first switching circuit 21 are connected to the short-circuit line L9 as the first discharging circuit and the second discharging circuit through the corresponding second switching circuit 22, that is, the odd-pixel data signal input line
  • Both the L7 and even pixel data signals L8 are connected to the short-circuit line L9, thereby achieving connection of the first switching element Q1 and the second switching element Q2 to the first discharge circuit and the second discharge circuit, respectively.
  • the conduction pads P0 to P1 and the short-circuit line L9 may be connected by wires to realize connection of the odd pixel data signal input line L7 and the even pixel data signal L8 and the short-circuit line L9.
  • the first switching element Q1 and the third switching element Q3 are N-type thin film transistors
  • the second switching element and the fourth switching element Q4 are P-type thin film transistors.
  • the control end, the first end and the second end of the switching element respectively correspond to a gate, a source and a drain of the thin film transistor.
  • the accumulated negative charge causes the voltage on the data line Dm to be lower than the ground voltage (the voltage on the data line). If the value is negative, the value of the ground voltage is zero), that is, the source voltage of the first switching element Q1 corresponding to the data line Dm is smaller than the gate voltage, so that the first switching element Q1 is turned on, and the negative charge will flow to the corresponding The first end of the three switching element Q3, such that the source voltage of the third switching element Q3 is less than the gate voltage, so that the third switching element Q3 is turned on, so that the data line Dm sequentially passes through the corresponding first switching element Q1 and The three-switching element Q3 is connected to the short-circuit line L9, whereby the negative charge on the data line Dm can be released through the grounded short-circuit line L9.
  • the accumulated positive charge causes the voltage on the data line Dm to be higher than the ground voltage, that is, the source voltage of the second switching element Q2 corresponding to the data line Dm is greater than
  • the gate voltage is such that the second switching element Q2 is turned on, and the positive charge will flow to the first end of the corresponding fourth switching element Q4, so that the source voltage of the fourth switching element Q4 is greater than the gate voltage, so that the fourth switching element Q4 is turned on, so that the data line Dm is connected to the short-circuit line L9 through the corresponding second switching element Q2 and fourth switching element Q4, whereby the positive charge on the data line Dm can be released through the grounded short-circuit line L9.
  • the short-circuit line L9 can be removed by cutting or edging process, such as cutting along the dotted line in the figure to remove the short-circuit line, so that the guide
  • the through pads P0 ⁇ P9 are not connected to each other, so in the subsequent process, the odd pixel data signal input line L7, the even pixel data signal input line L8, the clock lines CK1 and CK2, and the control line can be respectively passed through the conductive pads P0 ⁇ P9.
  • the L1 ⁇ L6 input displays or tests the required signals to drive the LCD display panel or to test the LCD panel.
  • the short-circuit line L9 is cut off, and when the liquid crystal display panel is driven to display or test, for example, when a data signal needs to be input to a certain data line Dm, the corresponding second switch circuit 22
  • the control end of at least one of the third switching element Q3 and the fourth switching element Q4 inputs a second control signal, for example, the control end of the third switching element Q3 inputs a second control signal to control the third switching element Q3
  • the second terminal of the third switching element Q3 and the fourth switching element Q4 of the corresponding second switching circuit 22 inputs a data signal, for example, the second terminal input data signal of the third switching element Q3.
  • control terminal of the at least one of the first switching element Q1 and the second switching element Q2 in the first switching circuit 21 corresponding to the data line Dm inputs a first control signal, for example, the first switching element Q1
  • the control terminal inputs a first control signal to control the first switching element Q1 to be turned on, thereby enabling the data signal to pass through the turned-on third switching element Q3 and the first switching element in sequence Q1 is input to the data line Dm.
  • the corresponding first switching element Q1 and second switching element Q2 are turned off.
  • the odd pixel data signal input line L7 the odd pixel data signal input line L8, the clock lines CK1 and CK2, and the control line L1 ⁇
  • the signal waveform diagram input by L6 can be as shown in Fig. 6.
  • the odd pixel data signal and the even pixel data signal are input to the odd pixel data signal input line L7 and the even pixel data signal input line L8 through the conductive pads P0 and P1.
  • the clock line CK1 is at a high level, and the clock line CK2 is at a low level, that is, the second control signal input to the control terminal of the third switching element Q3 of one of the second switch circuits 22 is a high level
  • the second control signal input to the control terminal of the three-switching element Q4 is at a high level, and at this time, the third switching element Q3 and the fourth switching element Q4 are turned on.
  • the control line L1 is at a high level
  • the control line L2 is at a low level, that is, the first control signal input to the control terminal of the first switching element Q1 connected to the data line of the R sub-pixel column is at a high level.
  • the first control signal input to the control terminal of the second switching element Q2 connected to the data line of the R sub-pixel column is at a low level, and at this time, the first switching element Q1 and the second switching element Q2 are turned on, thereby being
  • the data signal is input to the data line corresponding to the R sub-pixel column.
  • the first switching element Q1 and the second switching element Q2 connected to the data line corresponding to the R sub-pixel column are all in a closed state, and the first switching element Q1 and the second connected to the data line of the G sub-pixel column are connected.
  • the switching element Q2 is in an on state, whereby a data line input signal to the corresponding G sub-pixel column can be realized.
  • the first switching element Q1 and the second switching element Q2 connected to the data line corresponding to the G sub-pixel column are in a closed state, and the first switching element Q1 and the second switch connected to the data line of the B sub-pixel column are connected.
  • the element Q2 is in an on state, whereby a data line input data signal to the corresponding B sub-pixel column can be realized.
  • the second control signal may be input only to one of the clock lines, and the first control signal may be input only to the control lines L1, L3, and L5, or The first control signal is input only to the control lines L2, L4, and L6.
  • the first control signal is input only to the control lines L2, L4, and L6.
  • For a data line when it is required to input the data signal to the data line, as long as one of the corresponding first switch circuits 21 can be made The component is turned on, and one of the corresponding second switching circuits 22 is turned on, and when the data signal is not required to be input to the data line, it is required to be in the corresponding first switching circuit 21 Both switching elements are off.
  • one second switching circuit 22 is connected to three first switching circuits 21, that is, three lines are drawn from one second switching circuit 22 to input three data lines through three first switching circuits 21, respectively.
  • the data signal can therefore be used to input data signals to three data lines by one data IC, instead of only one data IC inputting data signals to one data line, thereby saving IC cost.
  • one switching circuit 22 can also correspond to two, four, six or more first switching circuits 21, and correspondingly, each data IC can be implemented for two, four, or six Or more data lines to input data signals.
  • the first switching circuit 21 includes the first switching element Q1 and the second switching element Q2, which can not only realize the driving display of the liquid crystal display panel, but also realize the negative electrostatic discharge of the data line in the array processing stage. And the positive electrostatic discharge, so that no additional panel space is needed to form the electrostatic protection structure during the panel design process, thereby greatly saving the panel space and facilitating the development of the narrow frame of the panel.
  • the first reference voltage and the second reference voltage may be different, for example, the first reference voltage may be -1v, -3v, or +2v, and the second reference voltage may be +1v, +4v, or the like.
  • the first switching element and the third switching element may also be an N-type transistor or a Darlington tube, or an equivalent N-type thin film transistor combined by a plurality of thin film transistors, and the second switching element and the fourth switching element are further It may be a P-type transistor or a Darlington tube, or a P-type thin film transistor equivalently combined by a plurality of thin film transistors.
  • the second switching circuit may not be provided.
  • the second ends of the first switching element Q1 and the second switching element Q2 of the first switching circuit may be respectively connected with different first discharges.
  • the circuit and the second discharge circuit for example, the first discharge circuit may be a ground resistance or a positively charged wire, etc., and the second discharge circuit may be a negatively charged wire or the like.
  • the present invention also provides an embodiment of a liquid crystal display panel comprising the driving circuit according to any of the above embodiments.
  • the liquid crystal display panel may be a low temperature polysilicon liquid crystal display panel.
  • an amorphous silicon liquid crystal display panel may also be used.
  • the manufacturing method is used to form a liquid crystal display panel having the driving circuit according to the foregoing embodiment, and specifically includes the following steps:
  • Step S701 forming a driving circuit of the liquid crystal display panel, the driving circuit includes a plurality of first switching circuits, each of the first switching circuits includes a first switching element, and the first switching element includes a control end, a first end, and a second end, A first end of a switching element is connected to a data line of the liquid crystal display panel.
  • control lines L1, L3, and L5 are formed in addition to the first switching element Q1.
  • the first end of the first switching element Q1 is connected to one data line Dm of the liquid crystal display panel, that is, each data line Dm corresponds to one first switching element Q1.
  • the control terminals of the plurality of first switching elements Q1 corresponding to the plurality of R sub-pixel columns are respectively connected to the control line L1, and the control terminals of the plurality of first switching elements Q1 corresponding to the plurality of G sub-pixel columns are respectively connected to the control lines.
  • L3, the control terminals of the plurality of first switching elements Q1 corresponding to the plurality of B sub-pixel columns are respectively connected to the control line L5.
  • Step S702 In the array processing stage of the liquid crystal display panel, the control end of the first switching element is input to the first reference voltage, so that the second end of the first switching element is connected to the first discharging circuit, so that when the first switching element is in the data line When the voltage is higher or lower than the first reference voltage is turned on, the voltage of the data line is released through the first discharge circuit.
  • the first switching element Q1 is an N-type field effect transistor, and the control end, the first end, and the second end of the first switching element Q1 correspond to a gate, a source, and a drain of the N-type field effect transistor.
  • the control terminals of the first switching elements Q1 of the plurality of first switching circuits 21 are input to the first reference voltage, and the first switching elements Q1 can be specifically passed through the three control lines L1, L3, and L5.
  • the control terminal inputs the first reference voltage and connects the second end of the first switch circuit 21 to the first discharge circuit 23.
  • the first discharge circuit 23 may be a grounding resistor, or a grounding wire, or a positively charged wire or the like.
  • Step S703 After the array processing stage, in the driving display or test phase of the liquid crystal display panel, the second end of the first switching element is disconnected from the first discharging circuit, so that the control end of the first switching element inputs the first control signal. And inputting a data signal to the second end of the first switching element to enable the data signal to be transmitted to the data line through the first switching element when the first control signal controls the first switching element to be turned on, thereby implementing display of the liquid crystal display panel or test.
  • the second terminal of the first switching element Q1 is input with a data signal. Therefore, when the first control signal controls the first switching element Q1 to be turned on, the data signal is input through the second end of the first switching element Q1 and transmitted to the corresponding data line Dm through the first switching element Q1, thereby The driving display of the liquid crystal display panel is realized, or the data line Dm of the liquid crystal display panel can be tested.
  • At least the negative polarity electrostatic discharge in the array process is realized by using the first switching element for driving the display of the liquid crystal display panel to achieve electrostatic protection, thereby requiring less space for setting the positive static electricity.
  • the protective structure can reduce the panel space occupied by the static electricity protection structure, and is favorable for narrow frame.
  • the second switching element Q2 and the second switch are formed.
  • the circuit 22 the odd pixel data signal input line L7, the even pixel data signal input line L8, the clock lines CK1 and CK2, and the control lines L2, L4, and L6.
  • the second switching circuit 22 includes a third switching element Q3 and a fourth switching element Q4. Each of the second switching circuits 22 corresponds to three first switching circuits 21.
  • the first switching element Q2, the third switching element Q3, and the fourth switching element respectively include a control end, a first end, and a second end.
  • the first ends of the first switching element Q1 and the second switching element Q2 of the same first switching circuit 21 are connected to the same data line Dm of the liquid crystal display panel, and the same of the first switching element Q1 and the second switching element Q2.
  • the two ends are connected, the third switching element Q3 of the same second switching circuit 22 is connected to the first end of the fourth switching element Q4, and the second ends of the same first switching element Q1 and the second switching element Q2 are corresponding thereto.
  • the third switching element Q3 of the second switching circuit 22 is connected to the first end of the fourth switching element Q4, that is, in the present embodiment, the third switching element Q3 and the fourth switching element Q4 of the second switching circuit 22 are One end is connected to the first switching element Q1 of the three first switching circuits 21 and the second end of the second switching element Q2, and the three switching circuits 21 are respectively connected to the data lines of the R sub-pixel columns, The data line of the G sub-pixel column and the data line of the B sub-pixel column.
  • the third switching element Q4 of the same second switching circuit 22 is connected to the second end of the fourth switching element Q4, and is connected to the data signal input line.
  • one second switching circuit 22 corresponds to one pixel unit, and thus The second ends of the third switching element Q3 and the fourth switching element Q4 of the second switching circuit 22 corresponding to the odd pixel unit are connected to the odd pixel data signal input line L7, and the third end of the second switching circuit 22 corresponding to the even pixel unit The second ends of the switching element Q3 and the fourth switching element Q4 are connected to the even pixel data signal input line L8.
  • control terminals of all the third switching elements Q3 are connected to the clock line CK1, and the control terminals of all the fourth switching elements Q4 are connected to the clock line CK2.
  • the control terminal of the first switching element Q1 connected to the data line corresponding to the R sub-pixel column is connected to the control line L1
  • the control terminal of the second switching element Q2 connected to the data line corresponding to the R sub-pixel column is connected to the control line L2
  • a control end of the first switching element Q1 connected to the data line corresponding to the G sub-pixel column is connected to the control line L3, and a control end of the second switching element Q2 connected to the data line corresponding to the G sub-pixel column is connected to a control line L4
  • a control end of the first switching element Q1 connected to the data line corresponding to the B sub-pixel column is connected to the control line L5, and a control end of the second switching element Q2 connected to the data line corresponding to the B sub-pixel column Connect to control line L6.
  • the driving circuit 20 further includes a conduction pad P0 ⁇ P9 as a port, an odd pixel data signal input line L7, an even pixel data signal input line L8, clock lines CK1 and CK2, and control lines L1 ⁇ L6 and a conduction pad P0, respectively. ⁇ P9 connection.
  • a ground short-circuit line L9 is further formed on the side of the liquid crystal display panel.
  • the control terminals of the first switching element Q1 and the second switching element Q2 are input to the first reference voltage and the second reference voltage, and the second ends of the first switching element Q1 and the second switching element Q2 are connected to the first discharge.
  • a circuit and a second discharge circuit Specifically, the first reference voltage and the second reference voltage of the embodiment are ground voltages, and the first discharge circuit and the second discharge circuit are grounded short lines L9, so that the control lines L1 L L6 are all connected to the ground.
  • the short-circuit line L9 inputs a ground voltage as a reference voltage to the control terminals of the first switching element Q1 and the second switching element Q2.
  • the conduction pads P4 to P9 and the short-circuit line L9 may be connected by wires so that the control lines L1 to L6 are connected to the short-circuit line L9.
  • control terminals of the third switching element Q3 and the fourth switching element Q4 are input to the first reference voltage and the second reference voltage, specifically by connecting the clock lines CK1, CK2 to the grounded short-circuit line L9, to the third The control terminals of the switching element Q3 and the fourth switching element Q4 input a ground voltage.
  • the conduction pads P2 to P3 and the short-circuit line L9 may be connected by wires so that the clock lines CK1 and CK2 and the short-circuit line L9 are connected.
  • the first switching element Q1 and the second switching element Q2 of the same first switching circuit 21 are connected to the short-circuit line L9 as the first discharging circuit and the second discharging circuit through the corresponding second switching circuit 22, that is, the odd-pixel data signal input line
  • Both the L7 and even pixel data signals L8 are connected to the short-circuit line L9, thereby achieving connection of the first switching element Q1 and the second switching element Q2 to the first discharge circuit and the second discharge circuit, respectively.
  • the conduction pads P0 to P1 and the short-circuit line L9 may be connected by wires to realize connection of the odd pixel data signal input line L7 and the even pixel data signal L8 and the short-circuit line L9.
  • the first switching element Q1 and the third switching element Q3 are N-type thin film transistors
  • the second switching element and the fourth switching element Q4 are P-type thin film transistors.
  • the control end, the first end and the second end of the switching element respectively correspond to a gate, a source and a drain of the thin film transistor.
  • the accumulated negative charge causes the voltage on the data line Dm to be lower than the ground voltage (the voltage on the data line). If the value is negative, the value of the ground voltage is zero), that is, the source voltage of the first switching element Q1 corresponding to the data line Dm is smaller than the gate voltage, so that the first switching element Q1 is turned on, and the negative charge will flow to the corresponding The first end of the three switching element Q3, such that the source voltage of the third switching element Q3 is less than the gate voltage, so that the third switching element Q3 is turned on, so that the data line Dm sequentially passes through the corresponding first switching element Q1 and The three-switching element Q3 is connected to the short-circuit line L9, whereby the negative charge on the data line Dm can be released through the grounded short-circuit line L9.
  • the accumulated positive charge causes the voltage on the data line Dm to be higher than the ground voltage, that is, the source voltage of the second switching element Q2 corresponding to the data line Dm is greater than
  • the gate voltage is such that the second switching element Q2 is turned on, and the positive charge will flow to the first end of the corresponding fourth switching element Q4, so that the source voltage of the fourth switching element Q4 is greater than the gate voltage, so that the fourth switching element Q4 is turned on, so that the data line Dm is connected to the short-circuit line L9 through the corresponding second switching element Q2 and fourth switching element Q4, whereby the positive charge on the data line Dm can be released through the grounded short-circuit line L9.
  • the short-circuit line L9 is removed by cutting or edging the process, for example, it can be cut along the broken line in the figure to remove the short-circuit line, so that the conduction pads P0 ⁇ P9 are not mutually Connection, thereby in the subsequent process, through the conduction pads P0 ⁇ P9 respectively for the odd pixel data signal input line L7, the even pixel data signal input line L8, the clock lines CK1 and CK2, the control lines L1 ⁇ L6 input display or test The required signal to drive the display of the liquid crystal display panel or to test the liquid crystal display panel.
  • the short-circuit line L9 is cut off, and when the liquid crystal display panel is driven to display or test, for example, when a data signal needs to be input to a certain data line Dm, the corresponding second switch circuit 22
  • the control end of at least one of the third switching element Q3 and the fourth switching element Q4 inputs a second control signal, for example, the control end of the third switching element Q3 inputs a second control signal to control the third switching element Q3
  • the second terminal of the third switching element Q3 and the fourth switching element Q4 of the corresponding second switching circuit 22 inputs a data signal, for example, the second terminal input data signal of the third switching element Q3.
  • control terminal of the at least one of the first switching element Q1 and the second switching element Q2 in the first switching circuit 21 corresponding to the data line Dm inputs a first control signal, for example, the first switching element Q1
  • the control terminal inputs a first control signal to control the first switching element Q1 to be turned on, thereby enabling the data signal to pass through the turned-on third switching element Q3 and the first switching element in sequence Q1 is input to the data line Dm.
  • the corresponding first switching element Q1 and second switching element Q2 are turned off.
  • the odd pixel data signal input line L7 the odd pixel data signal input line L8, the clock lines CK1 and CK2, and the control line L1 ⁇
  • the signal waveform diagram input by L6 can be as shown in Fig. 6.
  • the odd pixel data signal and the even pixel data signal are input to the odd pixel data signal input line L7 and the even pixel data signal input line L8 through the conductive pads P0 and P1.
  • the clock line CK1 is at a high level, and the clock line CK2 is at a low level, that is, the second control signal input to the control terminal of the third switching element Q3 of one of the second switch circuits 22 is a high level
  • the second control signal input to the control terminal of the three-switching element Q4 is at a high level, and at this time, the third switching element Q3 and the fourth switching element Q4 are turned on.
  • the control line L1 is at a high level
  • the control line L2 is at a low level, that is, the first control signal input to the control terminal of the first switching element Q1 connected to the data line of the R sub-pixel column is at a high level.
  • the first control signal input to the control terminal of the second switching element Q2 connected to the data line of the R sub-pixel column is at a low level, and at this time, the first switching element Q1 and the second switching element Q2 are turned on, thereby being
  • the data signal is input to the data line corresponding to the R sub-pixel column.
  • the first switching element Q1 and the second switching element Q2 connected to the data line corresponding to the R sub-pixel column are all in a closed state, and the first switching element Q1 and the second connected to the data line of the G sub-pixel column are connected.
  • the switching element Q2 is in an on state, whereby a data line input signal to the corresponding G sub-pixel column can be realized.
  • the first switching element Q1 and the second switching element Q2 connected to the data line corresponding to the G sub-pixel column are in a closed state, and the first switching element Q1 and the second switch connected to the data line of the B sub-pixel column are connected.
  • the element Q2 is in an on state, whereby a data line input data signal to the corresponding B sub-pixel column can be realized.
  • the manufacturing method of the present embodiment not only the driving display of the liquid crystal display panel but also the negative polarity electrostatic discharge and the positive polarity electrostatic discharge of the data line can be realized by the first switching circuit 21, and thus the panel can be realized in the panel manufacturing process. There is no need to additionally set the panel space to form the electrostatic protection structure during the design process, thereby greatly saving the panel space and facilitating the development of the narrow frame of the panel.

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Abstract

提供了一种液晶显示面板及其驱动电路、制造方法。驱动电路（20）包括第一开关元件（Q1），第一开关元件（Q1）的第一端连接液晶显示面板的一条数据线（Dm）；其中，在液晶显示面板的阵列制程阶段，第一开关元件（Q1）的控制端用于输入第一参考电压，第一开关元件（Q1）的第二端用于连接第一放电电路（23）；在液晶显示面板的驱动显示或测试阶段，第一开关元件（Q1）的控制端输入第一控制信号，第一开关元件（Q1）的第二端输入数据信号。通过该方式，在实现静电防护的同时，节省面板空间，有利于窄边框化发展。

Description

液晶显示面板及其驱动电路、制造方法
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种液晶显示面板及其驱动电路、制造方法。
【背景技术】
在液晶显示面板的制造过程中，尤其是阵列制程（array制程）阶段，需要进行多次干蚀刻，而干蚀刻过程容易产生大量静电。因此，在面板设计的时候，为了防止面板内部积累过多的静电而导致线路炸伤，通常会在设置静电防护（ESD防护）。
如图1所示，现有的静电防护设计中，通常是在液晶显示面板10的数据驱动电路101的对侧设置静电防护结构102。然而，产生静电的过程主要是集中在阵列制程的干蚀刻阶段，在阵列制程完成后，数据驱动电路101对侧的静电防护结构102不再起到作用，在组装成模组后外围的静电防护结构102依然存在，如此一来大大浪费了边框的空间，不利于面板的窄边框设计。
【发明内容】
本发明主要解决的技术问题是提供一种液晶显示面板及其驱动电路、制造方法，能够实现静电防护的同时，有效节省面板空间，有利于实现液晶显示面板的窄边框设计。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种液晶显示面板的驱动电路，所述液晶显示面板为低温多晶硅型液晶显示面板，其中，所述驱动电路包括多个第一开关电路；每个所述第一开关电路包括第一开关元件和第二开关元件，所述第一开关元件和所述第二开关元件分别包括控制端、第一端和第二端，所述第一开关元件和所述第二开关元件的的第一端连接所述液晶显示面板的同一条数据线；其中，在所述液晶显示面板的阵列制程阶段，所述第一开关元件和所述第二开关元件的控制端分别用于输入第一参考电压和第二参考电压，所述第一开关元件和所述第二开关元件的第二端分别用于连接第一放电电路和第二放电电路，所述第一开关元件在所述数据线的电压低于所述第一参考电压时导通以使所述数据线的电压通过所述第一放电电路释放，所述第二开关元件在所述数据线的电压高于所述第二参考电压时导通以使所述数据线的电压通过所述第二放电电路释放，在所述液晶显示面板的驱动显示或测试阶段，所述第一开关元件和所述第二开关元件中的至少一个开关元件的控制端输入第一控制信号，所述第一开关元件和所述第二开关元件中的所述至少一个开关元件的第二端输入数据信号，以在所述第一控制信号控制所述第一开关元件和所述第二开关元件中的所述至少一个开关元件导通时所述数据信号通过导通的所述开关元件传输至所述数据线，实现所述液晶显示面板的显示或测试。
其中，还包括多个第二开关电路；每个所述第二开关电路包括第三开关元件和第四开关元件，每个所述第二开关电路与至少两个第一开关电路对应，所述至少两个第一开关电路的第一开关元件的第二端通过所述第三开关元件与所述第一放电电路连接或接收所述数据信号，所述至少两个第一开关电路的第二开关元件的第二端通过所述第四开关元件与所述第二放电电路连接或接收所述数据信号，其中，所述第三开关元件和所述第四开关元件分别包括控制端、第一端和第二端，所述第三开关元件的第一端连接与其对应的至少两个第一开关电路的第一开关元件的第二端，所述第四开关元件的第一端连接与其对应的至少两个第一开关电路的第二开关元件的第二端；在所述液晶显示面板的阵列制程阶段，所述第三开关元件和所述第四开关元件的控制端分别用于输入所述第一参考电压和所述第二参考电压，所述第三开关元件和所述第四开关元件的第一端分别用于连接第一放电电路和第二放电电路，所述第三开关元件在其中一个对应的第一开关电路所连接的数据线的电压低于所述第一参考电压时导通以使得所述其中一个对应的第一开关电路所连接的数据线的电压通过所述第一放电电路释放，所述第四开关元件在其中一个对应的第一开关电路所连接的数据线的电压高于所述第二参考电压时导通以使得所述其中一个对应的第一开关电路所连接的数据线的电压通过所述第二放电电路释放；在所述液晶显示面板的驱动显示或测试阶段，所述第三开关元件和所述第四开关元件中的至少一个开关元件的控制端输入第二控制信号，所述第三开关元件和所述第四开关元件中的所述至少一个开关元件的第二端输入所述数据信号，以实现对应的至少两个第一开关电路的第一开关元件和所述第二开关元件中的至少其中一个开关元件的第二端输入数据信号。
其中，所述第一参考电压和所述第二参考电压为地电压，所述第一放电电路和所述第二放电电路均为接地的短路线；其中，在所述液晶显示面板的阵列制程阶段，所述第一开关元件、所述第二开关元件、所述第三开关元件、所述第四开关元件的控制端均与所述短路线连接，所述第三开关元件、第四开关电路的第二端均与所述短路线连接，每个所述第二开关电路的第三开关元件、第四开关元件的第一端以及对应的至少两个第一开关电路的第一开关元件、第二开关元件的第二端相互连接，在所述液晶显示面板的驱动显示或测试阶段，切除所述短路线，并使每个所述第一开关电路中的第一开关元件和第二开关元件中的至少一个的控制端输入所述第一控制信号，每个所述第二开关电路中的第三开关元件和第四开关元件中的至少一个的控制端输入所述第二控制信号，每个所述第二开关电路中的第三开关元件和第四开关元件中的所述至少一个的第二端输入所述数据信号。
其中，所述第一开关元件和所述第三开关元件为N型薄膜晶体管，所述第二开关元件和所述第四开关元件为P型薄膜晶体管，所述薄膜晶体管的栅极、源极和漏极分别作为所述开关元件的控制端、第一端和第二端。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示面板，包括驱动电路，所述驱动电路包括多个第一开关电路；每个所述第一开关电路包括第一开关元件，所述第一开关元件包括控制端、第一端和第二端，所述第一开关元件的第一端连接所述液晶显示面板的一条数据线；其中，在所述液晶显示面板的阵列制程阶段，所述第一开关元件的控制端用于输入第一参考电压，所述第一开关元件的第二端用于连接第一放电电路，所述第一开关元件在所述数据线的电压高于或低于所述第一参考电压时导通以使所述数据线的电压通过所述第一放电电路释放，在所述液晶显示面板的驱动显示或测试阶段，所述第一开关元件的控制端输入第一控制信号，所述第一开关元件的第二端输入数据信号，以在所述第一控制信号控制所述第一开关元件导通时所述数据信号通过所述第一开关元件传输至所述数据线，实现所述液晶显示面板的显示或测试。
其中，每个所述第一开关电路还包括第二开关元件，所述第二开关元件包括控制端、第一端和第二端，所述第一开关元件和所述第二开关元件的第一端与所述液晶显示面板的同一条数据线连接，其中，在所述液晶显示面板的阵列制程阶段，所述第一开关元件和所述第二开关元件的控制端分别用于输入第一参考电压和第二参考电压，所述第一开关元件和所述第二开关元件的第二端分别用于连接第一放电电路和第二放电电路，所述第一开关元件在所述数据线的电压低于所述第一参考电压时导通以使所述数据线的电压通过所述第一放电电路释放，所述第二开关元件在所述数据线的电压高于所述第二参考电压时导通以使所述数据线的电压通过所述第二放电电路释放，在所述液晶显示面板的驱动显示或测试阶段，所述第一开关元件和所述第二开关元件中的至少一个开关元件的控制端输入第一控制信号，所述第一开关元件和所述第二开关元件中的所述至少一个开关元件的第二端输入数据信号，以实现所述液晶显示面板的显示。
其中，还包括多个第二开关电路；每个所述第二开关电路包括第三开关元件和第四开关元件，每个所述第二开关电路与至少两个第一开关电路对应，所述至少两个第一开关电路的第一开关元件的第二端通过所述第三开关元件与所述第一放电电路连接或接收所述数据信号，所述至少两个第一开关电路的第二开关元件的第二端通过所述第四开关元件与所述第二放电电路连接或接收所述数据信号，其中，所述第三开关元件和所述第四开关元件分别包括控制端、第一端和第二端，所述第三开关元件的第一端连接与其对应的至少两个第一开关电路的第一开关元件的第二端，所述第四开关元件的第一端连接与其对应的至少两个第一开关电路的第二开关元件的第二端；在所述液晶显示面板的阵列制程阶段，所述第三开关元件和所述第四开关元件的控制端分别用于输入所述第一参考电压和所述第二参考电压，所述第三开关元件和所述第四开关元件的第一端分别用于连接第一放电电路和第二放电电路，所述第三开关元件在其中一个对应的第一开关电路所连接的数据线的电压低于所述第一参考电压时导通以使得所述其中一个对应的第一开关电路所连接的数据线的电压通过所述第一放电电路释放，所述第四开关元件在其中一个对应的第一开关电路所连接的数据线的电压高于所述第二参考电压时导通以使得所述其中一个对应的第一开关电路所连接的数据线的电压通过所述第二放电电路释放；在所述液晶显示面板的驱动显示或测试阶段，所述第三开关元件和所述第四开关元件中的至少一个开关元件的控制端输入第二控制信号，所述第三开关元件和所述第四开关元件中的所述至少一个开关元件的第二端输入所述数据信号，以实现对应的至少两个第一开关电路的第一开关元件和所述第二开关元件中的至少其中一个开关元件的第二端输入数据信号。
其中，所述第一参考电压和所述第二参考电压为地电压，所述第一放电电路和所述第二放电电路均为接地的短路线；其中，在所述液晶显示面板的阵列制程阶段，所述第一开关元件、所述第二开关元件、所述第三开关元件、所述第四开关元件的控制端均与所述短路线连接，所述第三开关元件、第四开关电路的第二端均与所述短路线连接，每个所述第二开关电路的第三开关元件、第四开关元件的第一端以及对应的至少两个第一开关电路的第一开关元件、第二开关元件的第二端相互连接，在所述液晶显示面板的驱动显示或测试阶段，切除所述短路线，并使每个所述第一开关电路中的第一开关元件和第二开关元件中的至少一个的控制端输入所述第一控制信号，每个所述第二开关电路中的第三开关元件和第四开关元件中的至少一个的控制端输入所述第二控制信号，每个所述第二开关电路中的第三开关元件和第四开关元件中的所述至少一个的第二端输入所述数据信号。
其中，所述第一开关元件和所述第三开关元件为N型薄膜晶体管，所述第二开关元件和所述第四开关元件为P型薄膜晶体管，所述薄膜晶体管的栅极、源极和漏极分别作为所述开关元件的控制端、第一端和第二端。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示面板的制造方法，包括：形成液晶显示面板的驱动电路，所述驱动电路包括多个第一开关电路，每个所述第一开关电路包括第一开关元件，所述第一开关元件包括控制端、第一端和第二端，所述第一开关元件的第一端连接所述液晶显示面板的一条数据线；在所述液晶显示面板的阵列制程阶段，使所述第一开关元件的控制端输入第一参考电压，使所述第一开关元件的第二端连接第一放电电路，以当所述第一开关元件在所述数据线的电压高于或低于所述第一参考电压导通时使得所述数据线的电压通过所述第一放电电路释放；在所述阵列制程阶段之后，在所述液晶显示面板的驱动显示或测试阶段，使所述第一开关元件的第二端与所述第一放电电路断开，使所述第一开关元件的控制端输入第一控制信号，并使所述第一开关元件的第二端输入数据信号，以当所述第一控制信号控制所述第一开关元件导通时使得所述数据信号通过所述第一开关元件传输至数据线，进而实现液晶显示面板的显示或测试。
其中，所述形成液晶显示面板的驱动电路的步骤包括：形成液晶显示面板的驱动电路，所述驱动电路还包括多个第二开关元件，所述第二开关元件包括控制端、第一端和第二端，所述第一开关元件和所述第二开关元件的第一端与所述液晶显示面板的同一条数据线连接；在所述液晶显示面板的阵列制程阶段中，还包括步骤：使所述第二开关元件的控制端输入第二参考电压，使所述第二开关元件的第二端连接第二放电电路，以当所述第二开关元件在所述数据线的电压高于所述第二参考电压导通时使得所述数据线的电压通过所述第二放电电路释放，其中，所述第一开关元件在所述数据线的电压低于所述第一参考电压时导通；在所述阵列制程阶段之后，在所述液晶显示面板的驱动显示或测试阶段，包括步骤：使所述第一开关元件和所述第二开关元件分别与所述第一放电电路和第二放电电路断开，并使所述第一开关元件和所述第二开关元件中的至少一个开关元件的控制端输入第一控制信号，使所述第一开关元件和所述第二开关元件中的所述至少一个开关元件的第二端输入数据信号，以实现所述液晶显示面板的显示。
本发明的有益效果是：区别于现有技术的情况，本发明的驱动电路中，在液晶显示面板的阵列制程阶段，使数据线通过第一开关元件与第一放电电路连接，以通过第一放电电路释放数据线上的电荷，从而实现数据线的静电释放，在液晶显示面板的驱动显示或测试阶段，使数据信号通过第一开关元件输入至数据线，从而实现液晶显示面板的显示或测试，通过上述方式，使第一开关元件同时用于静电防护和面板驱动显示或测试，由此可以不需要额外的面板空间或只需较少的面板空间设置静电防护结构，从而可以节省面板空间，有利于窄边框化。
【附图说明】
图1是现有技术一种具有静电防护结构的液晶显示面板的结构示意图；
图2是本发明液晶显示面板的驱动电路一实施方式中，在阵列制程阶段驱动电路实现数据线的静电释放的连接结构示意图；
图3是本发明液晶显示面板的驱动电路一实施方式中，在液晶显示面板的驱动显示或测试阶段驱动电路实现数据线的驱动的连接结构示意图；
图4是本发明液晶显示面板的驱动电路一实施方式中，在液晶显示面板的驱动显示或测试阶段第一控制信号的时序波形图；
图5是本发明液晶显示面板的驱动电路另一实施方式结构示意图；
图6是图5所示的液晶显示面板的驱动电路中，在液晶显示面板的驱动显示或测试阶段第一控制信号和第二控制信号的时序波形图；
图7是本发明液晶显示面板的制造方法一实施方式的流程图。
【具体实施方式】
下面将结合附图和实施方式对本发明进行详细说明。
参阅图2和图3，本发明液晶显示面板的驱动电路一实施方式中，液晶显示面板为低温多晶硅（Low Temperature Poly-Silicon，LTPS）液晶显示面板，包括多个像素，多个像素划分为沿行方向周期性依次排列的R子像素列、G子像素列和B子像素列，其中由R子像素、G子像素和B子像素构成一个像素单元。每个子像素列对应一条数据线Dm，即每个子像素列中的多个子像素连接一条数据线Dm。驱动电路20包括多个第一开关电路21和三条控制线L1、L3、L5，每个开关电路21包括一个第一开关元件Q1。当然，液晶显示面板也可以是非晶硅液晶显示面板。
第一开关元件Q1包括控制端、第一端和第二端。第一开关元件Q1的第一端连接液晶显示面板的一条数据线Dm，即每条数据线Dm对应一个第一开关元件Q1。其中，与同种颜色子像素列对应的第一开关元件Q1的控制端连接同一条控制线。例如，分别与多个R子像素列对应的多个第一开关元件Q1的控制端连接控制线L1，分别与多个G子像素列对应的多个第一开关元件Q1的控制端连接控制线L3，分别与多个B子像素列对应的多个第一开关元件Q1的控制端连接控制线L5。
其中，如图2所示，在液晶显示面板的阵列制程阶段，多个第一开关电路21的第一开关元件Q1的控制端均用于输入第一参考电压，具体可通过三条控制线L1、L3、L5对第一开关元件Q1的控制端输入第一参考电压。第一参考电压可以是地电压或预定数值的电压，如+0.5v或+1v等。第一开关元件Q1的第二端用于连接第一放电电路23。
本实施方式中，第一开关元件Q1为N型薄膜晶体管，第一开关元件Q1的控制端、第一端和第二端对应为N型薄膜晶体管的栅极、源极和漏极。因此，在阵列制程阶段的干蚀刻过程中，当数据线Dm上积累了大量的负极性静电，即数据线Dm上积累的负电荷较多，当所积累的负电荷使得数据线Dm的电压（负电压）低于第一参考电压时，栅源电压Vgs（栅极电压-源极电压）大于零，第一开关元件Q1导通，由此使得数据线Dm和第一放电电路23连通，从而数据线Dm上积累的负电荷可通过第一放电电路23释放，达到静电防护的目的。其中，第一放电电路23可以是一接地电阻，或接地线，或者是带正电荷的导线等。
如图3所示，在完成阵列制程之后，进入Cell制程，Cell制程阶段，通常需要对液晶显示面板进行驱动或测试，而在该阶段数据线Dm上不容易产生静电积累，此时不需要对数据线Dm进行静电防护。因此，可将第一开关元件Q1和第一放电电路23断开，如可切除第一放电电路23。在对液晶显示面板进行驱动显示或测试数据线正常与否时，第一开关元件Q1的控制端输入第一控制信号，具体可分别通过三条控制线L1、L3、L5对第一开关元件Q1的控制端输入第一控制信号，以分别控制每条数据线Dm所对应的第一开关元件Q1的导通或断开。其中，控制线L1、L3、L5所接收到的第一控制信号的波形图可以如图4所示，当对第一开关元件Q1的控制端输入高电平的控制信号时第一开关元件Q1导通。
第一开关元件Q1的第二端输入数据信号。当第一控制信号控制第一开关元件Q1导通时，数据信号通过第一开关元件Q1的第二端输入，并通过第一开关元件Q1传输至对应的数据线Dm，由此可实现液晶显示面板的驱动显示，或者可对液晶显示面板的数据线Dm进行测试。
通过第一放电电路23以及第一开关元件Q1，在阵列制程阶段，可以将数据线上积累的负电荷释放。进一步地，本实施方式中，还包括多个第五开关元件Q5。多个第五开关元件设置在第一开关元件Q1的对侧，每个第五开关元件Q5对应一条数据线Dm。其中，第五开关元件Q5为P型薄膜晶体管，第五开关元件Q5的第一端连接一条数据线Dm，第二端连接作为放电电路的地线，控制端输入地电压，即第五开关元件Q5的控制端和第二端均连接地线。因此，在阵列制程阶段，当数据线Dm上积累过多的正极性静电，即数据线上积累了较多的正电荷，当所积累的正电荷使得数据线的电压（正电压）高于地电压时，栅源电压Vgs小于零，第五开关元件Q1导通，此时数据线上的电压通过地线释放，由此实现静电防护。
因此，在阵列制程阶段，当数据线上积累较多的负电荷时第一开关元件Q1导通，以使得数据线上的负电荷通过第一放电电路23释放，当数据线上积累较多的正电荷时第五开关元件Q5导通，以使得数据线上的正电荷通过地线释放，从而达到静电保护的目的。
本实施方式中，通过利用用于驱动液晶显示面板显示的第一开关元件来至少实现阵列制程中的负极性静电释放，以实现静电保护，由此仅需要较少的空间来设置正极性静电的防护结构，从而可以减小静电防护结构所占用的面板空间，有利于窄边框化。
在其他实施方式中，第一开关元件也可以是P型薄膜晶体管，此时，在阵列制程阶段，当数据线上积累过多的正极性静电，即数据线上积累了较多的正电荷，当所积累的负电荷使得数据线的电压（负电压）高于第一参考电压时，栅源电压Vgs小于零，第一开关元件导通，此时数据线上的电压通过第一放电电路释放，由此实现静电防护。此时，第一放电电路可以是一接地电阻，或带负电荷的导线等。而在液晶显示面板的驱动显示或测试阶段，第一开关元件的控制端输入第一控制信号，其中当对第一开关元件的控制端输入低电平时第一开关元件导通，此时数据信号可通过第一开关元件输入至数据线，由此实现液晶显示面板的显示或测试。
参阅图5，在本发明液晶显示面板的驱动电路的另一实施方式中，能够进一步节省面板空间。具体地，如图5所示，每个第一开关电路21还包括第二开关元件Q2，驱动电路20还包括多个第二开关电路22、奇像素数据信号输入线L7、偶像素数据信号输入线L8、时钟线CK1和CK2以及控制线L2、L4、L6。其中第二开关电路22包括第三开关元件Q3和第四开关元件Q4。每个第二开关电路22对应三个第一开关电路21。第一开关元件Q2、第三开关元件Q3和第四开关元件分别包括控制端、第一端和第二端。
其中，同一第一开关电路21的第一开关元件Q1和第二开关元件Q2的第一端与液晶显示面板的同一条数据线Dm连接，同一第一开关元件Q1和第二开关元件Q2的第二端相连接，同一第二开关电路22的第三开关元件Q3和第四开关元件Q4的第一端相连接，且同一第一开关元件Q1和第二开关元件Q2的第二端与其对应的第二开关电路22的第三开关元件Q3和第四开关元件Q4的第一端相连接，即本实施方式中，一个第二开关电路22的第三开关元件Q3和第四开关元件Q4的第一端与其对应的三个第一开关电路21的第一开关元件Q1和第二开关元件Q2的第二端相连接，且该三个开关电路21分别连接的是对应R子像素列的数据线、对应G子像素列的数据线以及对应B子像素列的数据线。同一个第二开关电路22的第三开关元件Q4和第四开关元件Q4的第二端相连接，且连接至数据信号输入线。具体地，一个第二开关电路22对应一个像素单元，因此与奇像素单元对应的第二开关电路22的第三开关元件Q3和第四开关元件Q4的第二端连接至奇像素数据信号输入线L7，与偶像素单元对应的第二开关电路22的第三开关元件Q3和第四开关元件Q4的第二端连接至偶像素数据信号输入线L8。
此外，所有第三开关元件Q3的控制端连接至时钟线CK1，所有第四开关元件Q4的控制端连接至时钟线CK2。与对应R子像素列的数据线所连接的第一开关元件Q1的控制端连接至控制线L1，与对应R子像素列的数据线所连接的第二开关元件Q2的控制端连接至控制线L2；与对应G子像素列的数据线所连接的第一开关元件Q1的控制端连接至控制线L3，与对应G子像素列的数据线所连接的第二开关元件Q2的控制端连接至控制线L4；与对应B子像素列的数据线所连接的第一开关元件Q1的控制端连接至控制线L5，与对应B子像素列的数据线所连接的第二开关元件Q2的控制端连接至控制线L6。
其中，驱动电路20还包括作为端口的导通垫P0~P9，奇像素数据信号输入线L7、偶像素数据信号输入线L8、时钟线CK1和CK2、控制线L1~L6分别与导通垫P0~P9连接。
其中，在液晶显示面板的阵列制程阶段，在液晶显示面板的侧边还形成接地的短路线L9。为了实现静电防护，本实施方式中，第一开关元件Q1和第二开关元件Q2的控制端分别用于输入第一参考电压和第二参考电压，第一开关元件Q1和第二开关元件Q2的第二端分别用于连接第一放电电路和第二放电电路。具体地，本实施方式的第一参考电压和第二参考电压均为地电压，第一放电电路和第二放电电路为接地的短路线L9，因此，控制线L1~L6均连接至接地的短路线L9，以对第一开关元件Q1和第二开关元件Q2的控制端输入作为参考电压的地电压。其中，可通过导线将导通垫P4~P9和短路线L9进行连接，以使得控制线L1~L6与短路线L9连接。
第三开关元件Q3和第四开关元件Q4的控制端分别用于输入第一参考电压和第二参考电压，具体可通过使时钟线CK1、CK2均连接至接地的短路线L9，以对第三开关元件Q3和第四开关元件Q4的控制端输入地电压。其中，可通过导线将导通垫P2~P3和短路线L9连接，以使得时钟线CK1、CK2和短路线L9连接。同一第一开关电路21的第一开关元件Q1和第二开关元件Q2通过对应的第二开关电路22与作为第一放电电路和第二放电电路的短路线L9连接，即奇像素数据信号输入线L7和偶像素数据信号L8均连接至短路线L9，由此实现第一开关元件Q1和第二开关元件Q2分别与第一放电电路和第二放电电路的连接。其中，可通过导线将导通垫P0~P1和短路线L9连接，以实现奇像素数据信号输入线L7和偶像素数据信号L8与短路线L9的连接。
因此，在该阵列制程阶段，只需将导通垫P0~P9通过导线引出并连接至接地的短路线L9即可实现上述各开关元件和放电电路的连接，以及实现对各开关元件的控制端输入参考电压。
本实施方式中，第一开关元件Q1和第三开关元件Q3为N型薄膜晶体管，第二开关元件和第四开关元件Q4为P型薄膜晶体管。开关元件的控制端、第一端、第二端分别对应薄膜晶体管的栅极、源极和漏极。
因此，在阵列制程阶段，在干蚀刻过程中，当某条数据线Dm上积累过多的负电荷时，所积累的负电荷导致数据线Dm上的电压低于地电压（数据线上的电压为负值，地电压的值为零），即该条数据线Dm对应的第一开关元件Q1的源极电压小于栅极电压，使得第一开关元件Q1导通，负电荷将流向对应的第三开关元件Q3的第一端，从而使得第三开关元件Q3的源极电压小于栅极电压，使得第三开关元件Q3导通，从而使得数据线Dm依次通过对应的第一开关元件Q1和第三开关元件Q3而与短路线L9连接，由此可将数据线Dm上的负电荷通过接地的短路线L9释放。当某条数据线Dm上积累过多的正电荷时，所积累的正电荷导致数据线Dm上的电压高于地电压，即该条数据线Dm对应的第二开关元件Q2的源极电压大于栅极电压，使得第二开关元件Q2导通，正电荷将流向对应的第四开关元件Q4的第一端，从而使得第四开关元件Q4的源极电压大于栅极电压，使得第四开关元件Q4导通，从而使得数据线Dm通过对应的第二开关元件Q2和第四开关元件Q4而与短路线L9连接，由此可将数据线Dm上的正电荷通过接地的短路线L9释放。
通过上述方式，可实现阵列制程阶段的静电防护。
在完成阵列制程之后，在进入Cell制程（组立制程）阶段时，可通过切割或磨边制程，将短路线L9去除，如可沿图中的虚线进行切割，以去掉短路线，以使得导通垫P0~P9互不连接，由此在后续制程中，可通过导通垫P0~P9分别对奇像素数据信号输入线L7、偶像素数据信号输入线L8、时钟线CK1和CK2、控制线L1~L6输入显示或测试所需的信号，以驱动液晶显示面板显示或实现液晶显示面板的测试。具体地，进入Cell制程阶段时，切除短路线L9，在对液晶显示面板驱动显示或进行测试时，例如当需要对某条数据线Dm输入数据信号时，所对应的第二开关电路22中的第三开关元件Q3和第四开关元件Q4中的至少一个开关元件的控制端输入第二控制信号，例如第三开关元件Q3的控制端输入第二控制信号，以控制该第三开关元件Q3导通，所对应的第二开关电路22中的第三开关元件Q3和第四开关元件Q4中的至少一个开关元件的第二端输入数据信号，例如第三开关元件Q3的第二端输入数据信号；且该条数据线Dm所对应的第一开关电路21中的第一开关元件Q1和第二开关元件Q2中的至少一个开关元件的控制端输入第一控制信号，例如第一开关元件Q1的控制端输入第一控制信号，以控制该第一开关元件Q1导通，由此可使得数据信号依次通过导通的第三开关元件Q3和第一开关元件Q1输入至数据线Dm中。当不需要对该条数据线Dm输入数据信号时，使其所对应的第一开关元件Q1和第二开关元件Q2均关闭。
因此，在驱动液晶显示面板显示时，当需要对每条数据线Dm单独提供数据信号时，奇像素数据信号输入线L7、偶像素数据信号输入线L8、时钟线CK1和CK2、控制线L1~L6所输入的信号波形图可如图6所示。通过导通垫P0和P1对奇像素数据信号输入线L7和偶像素数据信号输入线L8输入奇像素的数据信号和偶像素数据信号。在t1时刻，时钟线CK1为高电平，时钟线CK2为低电平，即其中一个第二开关电路22中的第三开关元件Q3的控制端输入的第二控制信号为高电平，第三开关元件Q4的控制端输入的第二控制信号为高电平，此时第三开关元件Q3和第四开关元件Q4导通。在t11时刻，控制线L1为高电平，控制线L2为低电平，即对应R子像素列的数据线所连接的第一开关元件Q1的控制端输入的第一控制信号为高电平，对应R子像素列的数据线所连接的第二开关元件Q2的控制端输入的第一控制信号为低电平，此时第一开关元件Q1和第二开关元件Q2导通，由此可使得数据信号输入至对应R子像素列的数据线。在t12时刻，对应R子像素列的数据线所连接的第一开关元件Q1和第二开关元件Q2均处于关闭状态，对应G子像素列的数据线所连接的第一开关元件Q1和第二开关元件Q2处于导通状态，由此可实现对对应G子像素列的数据线输入数据信号。在t13时刻，对应G子像素列的数据线所连接的第一开关元件Q1和第二开关元件Q2处于关闭状态，对应B子像素列的数据线所连接的第一开关元件Q1和第二开关元件Q2处于导通状态，由此可实现对对应B子像素列的数据线输入数据信号。
通过上述方式，可实现对每条数据线输入显示或测试所需的数据信号。
本领域技术人员可以理解的是，在上述驱动液晶显示面板的过程中，可以仅对其中一条时钟线输入第二控制信号，以及可以仅对控制线L1、L3和L5输入第一控制信号，或者是仅对控制线L2、L4、L6输入第一控制信号，对于一条数据线而言，当需要对该条数据线输入数据信号时，只要能够使得对应的第一开关电路21中的其中一个开关元件导通，以及对应的第二开关电路22中的其中一个开关元件导通即可，而当不需要对该条数据线输入数据信号时，则需要使其所对应的第一开关电路21中的两个开关元件均处于关闭状态。
通过本实施方式的驱动电路，使一个第二开关电路22对应三个第一开关电路21，即从一个第二开关电路22引出三条线以分别通过三个第一开关电路21对三条数据线输入数据信号，因此可以利用一个数据IC对三条数据线输入数据信号，而不是仅使一个数据IC对一条数据线输入数据信号，由此可节省IC成本。当然，在其他实施方式中，一个开关电路22还可以对应两个、四个、六个或更多个第一开关电路21，对应地可以实现使每个数据IC能够对两条、四条、六条或更多条数据线输入数据信号。
本实施方式中，第一开关电路21中包括第一开关元件Q1和第二开关元件Q2，不仅能够实现对液晶显示面板的驱动显示，而且能够在阵列制程阶段实现对数据线的负极性静电释放和正极性静电释放，从而在面板设计过程中不需要额外设置面板空间来形成静电防护结构，由此可大大节省面板空间，更有利于面板的窄边框化发展。
在本发明其他实施方式中，第一参考电压和第二参考电压可以不相同，例如第一参考电压可以是-1v、-3v或+2v，第二参考电压可以是+1v、+4v等。此外，第一开关元件和第三开关元件还可以是N型三极管或达林顿管，或由多个薄膜晶体管进行组合所等价的N型薄膜晶体管，第二开关元件和第四开关元件还可以是P型三极管或达林顿管，或由多个薄膜晶体管进行组合所等价的P型薄膜晶体管。
在本发明驱动电路的实施方式中，也可以不设置第二开关电路，此时第一开关电路的第一开关元件Q1和第二开关元件Q2的第二端可以是分别连接不同的第一放电电路和第二放电电路，例如第一放电电路可以是接地电阻或带正电荷的导线等，第二放电电路可以是带负电荷的导线等。
本发明还提供液晶显示面板的一实施方式，液晶显示面板包括前述任一实施方式所述的驱动电路。其中，所述液晶显示面板可以为低温多晶硅液晶显示面板，当然，也可以非晶硅型液晶显示面板。
参阅图7，本发明液晶显示面板的制造方法一实施方式中，所述制造方法用于形成具有前述实施方式所述的驱动电路的液晶显示面板，具体包括如下步骤：
步骤S701：形成液晶显示面板的驱动电路，驱动电路包括多个第一开关电路，每个第一开关电路包括第一开关元件，第一开关元件包括控制端、第一端和第二端，第一开关元件的第一端连接液晶显示面板的一条数据线。
结合图2，本实施方式中，在形成驱动电路20时，除了形成第一开关元件Q1，还形成三条控制线L1、L3、L5。第一开关元件Q1的第一端连接液晶显示面板的一条数据线Dm，即每条数据线Dm对应一个第一开关元件Q1。其中，分别与多个R子像素列对应的多个第一开关元件Q1的控制端连接控制线L1，分别与多个G子像素列对应的多个第一开关元件Q1的控制端连接控制线L3，分别与多个B子像素列对应的多个第一开关元件Q1的控制端连接控制线L5。
步骤S702：在液晶显示面板的阵列制程阶段，使第一开关元件的控制端输入第一参考电压，使第一开关元件的第二端连接第一放电电路，以当第一开关元件在数据线的电压高于或低于第一参考电压导通时使得数据线的电压通过第一放电电路释放。
本实施方式中，第一开关元件Q1为N型场效应管，第一开关元件Q1的控制端、第一端和第二端对应为N型场效应管的栅极、源极和漏极。
继续结合图2，在阵列制程阶段，使多个第一开关电路21的第一开关元件Q1的控制端输入第一参考电压，具体可通过三条控制线L1、L3、L5对第一开关元件Q1的控制端输入第一参考电压，并使第一开关电路21的第二端连接第一放电电路23。由此，在阵列制程的干蚀刻过程中，当数据线Dm上积累了大量的负极性静电，即数据线Dm上积累的负电荷较多，当所积累的负电荷使得数据线Dm的电压（负电压）低于第一参考电压时，栅源电压Vgs（栅极电压-源极电压）大于零，第一开关元件Q1导通，由此使得数据线Dm和第一放电电路23连通，从而数据线Dm上积累的负电荷可通过第一放电电路22释放，达到静电防护的目的。其中，第一放电电路23可以是一接地电阻，或接地线，或者是带正电荷的导线等。
步骤S703：在阵列制程阶段之后，在液晶显示面板的驱动显示或测试阶段，使第一开关元件的第二端与第一放电电路断开，使第一开关元件的控制端输入第一控制信号，并使第一开关元件的第二端输入数据信号，以当第一控制信号控制第一开关元件导通时使得数据信号通过第一开关元件传输至数据线，进而实现液晶显示面板的显示或测试。
结合图3，在完成阵列制程之后，进入Cell制程，Cell制程阶段，通常需要对液晶显示面板进行驱动或测试，而在该阶段数据线Dm上不容易产生静电积累，此时不需要对数据线Dm进行静电防护。因此，在完成阵列制程之后，使第一开关元件Q1的第二端与第一放电电路23断开，并使第一开关元件Q1的控制端输入第一控制信号，具体可分别通过三条控制线L1、L3、L5对第一开关元件Q1的控制端输入第一控制信号，以分别控制每条数据线Dm所对应的第一开关元件Q1的导通或断开。此外，使第一开关元件Q1的第二端输入数据信号。由此，当第一控制信号控制第一开关元件Q1导通时，数据信号通过第一开关元件Q1的第二端输入，并通过第一开关元件Q1传输至对应的数据线Dm，由此可实现液晶显示面板的驱动显示，或者可对液晶显示面板的数据线Dm进行测试。
本实施方式中，通过利用用于驱动液晶显示面板显示的第一开关元件来至少实现阵列制程中的负极性静电释放，以实现静电保护，由此仅需要较少的空间来设置正极性静电的防护结构，从而可以减小静电防护结构所占用的面板空间，有利于窄边框化。
在本发明液晶显示面板的另一制造方法中，结合图5，在形成的液晶显示面板的驱动电路的步骤中，除了形成第一开关元件Q1外，还形成第二开关元件Q2、第二开关电路22、奇像素数据信号输入线L7、偶像素数据信号输入线L8、时钟线CK1和CK2以及控制线L2、L4、L6。其中，第二开关电路22包括第三开关元件Q3和第四开关元件Q4。每个第二开关电路22对应三个第一开关电路21。第一开关元件Q2、第三开关元件Q3和第四开关元件分别包括控制端、第一端和第二端。
其中，同一第一开关电路21的第一开关元件Q1和第二开关元件Q2的第一端与液晶显示面板的同一条数据线Dm连接，同一第一开关元件Q1和第二开关元件Q2的第二端相连接，同一第二开关电路22的第三开关元件Q3和第四开关元件Q4的第一端相连接，且同一第一开关元件Q1和第二开关元件Q2的第二端与其对应的第二开关电路22的第三开关元件Q3和第四开关元件Q4的第一端相连接，即本实施方式中，一个第二开关电路22的第三开关元件Q3和第四开关元件Q4的第一端与其对应的三个第一开关电路21的第一开关元件Q1和第二开关元件Q2的第二端相连接，且该三个开关电路21分别连接的是R子像素列的数据线、G子像素列的数据线以及B子像素列的数据线。同一个第二开关电路22的第三开关元件Q4和第四开关元件Q4的第二端相连接，且连接至数据信号输入线，具体地，一个第二开关电路22对应一个像素单元，因此与奇像素单元对应的第二开关电路22的第三开关元件Q3和第四开关元件Q4的第二端连接至奇像素数据信号输入线L7，与偶像素单元对应的第二开关电路22的第三开关元件Q3和第四开关元件Q4的第二端连接至偶像素数据信号输入线L8。
此外，所有第三开关元件Q3的控制端连接至时钟线CK1，所有第四开关元件Q4的控制端连接至时钟线CK2。与对应R子像素列的数据线所连接的第一开关元件Q1的控制端连接至控制线L1，与对应R子像素列的数据线所连接的第二开关元件Q2的控制端连接至控制线L2；与对应G子像素列的数据线所连接的第一开关元件Q1的控制端连接至控制线L3，与对应G子像素列的数据线所连接的第二开关元件Q2的控制端连接至控制线L4；与对应B子像素列的数据线所连接的第一开关元件Q1的控制端连接至控制线L5，与对应B子像素列的数据线所连接的第二开关元件Q2的控制端连接至控制线L6。
其中，驱动电路20还包括作为端口的导通垫P0~P9，奇像素数据信号输入线L7、偶像素数据信号输入线L8、时钟线CK1和CK2、控制线L1~L6分别与导通垫P0~P9连接。
其中，在液晶显示面板的阵列制程阶段，在液晶显示面板的侧边还形成接地的短路线L9。
在阵列制程阶段，使第一开关元件Q1和第二开关元件Q2的控制端输入第一参考电压和第二参考电压，第一开关元件Q1和第二开关元件Q2的第二端连接第一放电电路和第二放电电路。具体地，本实施方式的第一参考电压和第二参考电压均为地电压，第一放电电路和第二放电电路为接地的短路线L9，因此，使控制线L1~L6均连接至接地的短路线L9，以对第一开关元件Q1和第二开关元件Q2的控制端输入作为参考电压的地电压。其中，可通过导线将导通垫P4~P9和短路线L9进行连接，以使得控制线L1~L6与短路线L9连接。
此外，使第三开关元件Q3和第四开关元件Q4的控制端输入第一参考电压和第二参考电压，具体可通过使时钟线CK1、CK2均连接至接地的短路线L9，以对第三开关元件Q3和第四开关元件Q4的控制端输入地电压。其中，可通过导线将导通垫P2~P3和短路线L9连接，以使得时钟线CK1、CK2和短路线L9连接。同一第一开关电路21的第一开关元件Q1和第二开关元件Q2通过对应的第二开关电路22与作为第一放电电路和第二放电电路的短路线L9连接，即奇像素数据信号输入线L7和偶像素数据信号L8均连接至短路线L9，由此实现第一开关元件Q1和第二开关元件Q2分别与第一放电电路和第二放电电路的连接。其中，可通过导线将导通垫P0~P1和短路线L9连接，以实现奇像素数据信号输入线L7和偶像素数据信号L8与短路线L9的连接。
本实施方式中，第一开关元件Q1和第三开关元件Q3为N型薄膜晶体管，第二开关元件和第四开关元件Q4为P型薄膜晶体管。开关元件的控制端、第一端、第二端分别对应薄膜晶体管的栅极、源极和漏极。
因此，在阵列制程阶段，在干蚀刻过程中，当某条数据线Dm上积累过多的负电荷时，所积累的负电荷导致数据线Dm上的电压低于地电压（数据线上的电压为负值，地电压的值为零），即该条数据线Dm对应的第一开关元件Q1的源极电压小于栅极电压，使得第一开关元件Q1导通，负电荷将流向对应的第三开关元件Q3的第一端，从而使得第三开关元件Q3的源极电压小于栅极电压，使得第三开关元件Q3导通，从而使得数据线Dm依次通过对应的第一开关元件Q1和第三开关元件Q3而与短路线L9连接，由此可将数据线Dm上的负电荷通过接地的短路线L9释放。当某条数据线Dm上积累过多的正电荷时，所积累的正电荷导致数据线Dm上的电压高于地电压，即该条数据线Dm对应的第二开关元件Q2的源极电压大于栅极电压，使得第二开关元件Q2导通，正电荷将流向对应的第四开关元件Q4的第一端，从而使得第四开关元件Q4的源极电压大于栅极电压，使得第四开关元件Q4导通，从而使得数据线Dm通过对应的第二开关元件Q2和第四开关元件Q4而与短路线L9连接，由此可将数据线Dm上的正电荷通过接地的短路线L9释放。
在完成阵列制程后，在后续的制程中，通过切割或磨边制程，将短路线L9去除，如可沿图中的虚线进行切割，以去掉短路线，以使得导通垫P0~P9互不连接，由此在后续制程中，可通过导通垫P0~P9分别对奇像素数据信号输入线L7、偶像素数据信号输入线L8、时钟线CK1和CK2、控制线L1~L6输入显示或测试所需的信号，以驱动液晶显示面板显示或实现液晶显示面板的测试。具体地，进入Cell制程阶段时，切除短路线L9，在对液晶显示面板驱动显示或进行测试时，例如当需要对某条数据线Dm输入数据信号时，所对应的第二开关电路22中的第三开关元件Q3和第四开关元件Q4中的至少一个开关元件的控制端输入第二控制信号，例如第三开关元件Q3的控制端输入第二控制信号，以控制该第三开关元件Q3导通，所对应的第二开关电路22中的第三开关元件Q3和第四开关元件Q4中的至少一个开关元件的第二端输入数据信号，例如第三开关元件Q3的第二端输入数据信号；且该条数据线Dm所对应的第一开关电路21中的第一开关元件Q1和第二开关元件Q2中的至少一个开关元件的控制端输入第一控制信号，例如第一开关元件Q1的控制端输入第一控制信号，以控制该第一开关元件Q1导通，由此可使得数据信号依次通过导通的第三开关元件Q3和第一开关元件Q1输入至数据线Dm中。当不需要对该条数据线Dm输入数据信号时，使其所对应的第一开关元件Q1和第二开关元件Q2均关闭。
因此，在驱动液晶显示面板显示时，当需要对每条数据线Dm单独提供数据信号时，奇像素数据信号输入线L7、偶像素数据信号输入线L8、时钟线CK1和CK2、控制线L1~L6所输入的信号波形图可如图6所示。通过导通垫P0和P1对奇像素数据信号输入线L7和偶像素数据信号输入线L8输入奇像素的数据信号和偶像素数据信号。在t1时刻，时钟线CK1为高电平，时钟线CK2为低电平，即其中一个第二开关电路22中的第三开关元件Q3的控制端输入的第二控制信号为高电平，第三开关元件Q4的控制端输入的第二控制信号为高电平，此时第三开关元件Q3和第四开关元件Q4导通。在t11时刻，控制线L1为高电平，控制线L2为低电平，即对应R子像素列的数据线所连接的第一开关元件Q1的控制端输入的第一控制信号为高电平，对应R子像素列的数据线所连接的第二开关元件Q2的控制端输入的第一控制信号为低电平，此时第一开关元件Q1和第二开关元件Q2导通，由此可使得数据信号输入至对应R子像素列的数据线。在t12时刻，对应R子像素列的数据线所连接的第一开关元件Q1和第二开关元件Q2均处于关闭状态，对应G子像素列的数据线所连接的第一开关元件Q1和第二开关元件Q2处于导通状态，由此可实现对对应G子像素列的数据线输入数据信号。在t13时刻，对应G子像素列的数据线所连接的第一开关元件Q1和第二开关元件Q2处于关闭状态，对应B子像素列的数据线所连接的第一开关元件Q1和第二开关元件Q2处于导通状态，由此可实现对对应B子像素列的数据线输入数据信号。
通过上述方式，可实现对每条数据线输入显示或测试所需的数据信号。
通过本实施方式的制造方法，利用第一开关电路21，不仅能够实现对液晶显示面板的驱动显示，而且能够在阵列制程阶段实现对数据线的负极性静电释放和正极性静电释放，从而在面板设计过程中不需要额外设置面板空间来形成静电防护结构，由此可大大节省面板空间，更有利于面板的窄边框化发展。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (11)

  1. 一种液晶显示面板的驱动电路，所述液晶显示面板为低温多晶硅型液晶显示面板，其中，所述驱动电路包括多个第一开关电路；
    每个所述第一开关电路包括第一开关元件和第二开关元件，所述第一开关元件和所述第二开关元件分别包括控制端、第一端和第二端，所述第一开关元件和所述第二开关元件的的第一端连接所述液晶显示面板的同一条数据线；
    其中，在所述液晶显示面板的阵列制程阶段，所述第一开关元件和所述第二开关元件的控制端分别用于输入第一参考电压和第二参考电压，所述第一开关元件和所述第二开关元件的第二端分别用于连接第一放电电路和第二放电电路，所述第一开关元件在所述数据线的电压低于所述第一参考电压时导通以使所述数据线的电压通过所述第一放电电路释放，所述第二开关元件在所述数据线的电压高于所述第二参考电压时导通以使所述数据线的电压通过所述第二放电电路释放，在所述液晶显示面板的驱动显示或测试阶段，所述第一开关元件和所述第二开关元件中的至少一个开关元件的控制端输入第一控制信号，所述第一开关元件和所述第二开关元件中的所述至少一个开关元件的第二端输入数据信号，以在所述第一控制信号控制所述第一开关元件和所述第二开关元件中的所述至少一个开关元件导通时所述数据信号通过导通的所述开关元件传输至所述数据线，实现所述液晶显示面板的显示或测试。
  2. 根据权利要求1所述的驱动电路，其中，还包括多个第二开关电路；
    每个所述第二开关电路包括第三开关元件和第四开关元件，每个所述第二开关电路与至少两个第一开关电路对应，所述至少两个第一开关电路的第一开关元件的第二端通过所述第三开关元件与所述第一放电电路连接或接收所述数据信号，所述至少两个第一开关电路的第二开关元件的第二端通过所述第四开关元件与所述第二放电电路连接或接收所述数据信号，其中，所述第三开关元件和所述第四开关元件分别包括控制端、第一端和第二端，所述第三开关元件的第一端连接与其对应的至少两个第一开关电路的第一开关元件的第二端，所述第四开关元件的第一端连接与其对应的至少两个第一开关电路的第二开关元件的第二端；
    在所述液晶显示面板的阵列制程阶段，所述第三开关元件和所述第四开关元件的控制端分别用于输入所述第一参考电压和所述第二参考电压，所述第三开关元件和所述第四开关元件的第一端分别用于连接第一放电电路和第二放电电路，所述第三开关元件在其中一个对应的第一开关电路所连接的数据线的电压低于所述第一参考电压时导通以使得所述其中一个对应的第一开关电路所连接的数据线的电压通过所述第一放电电路释放，所述第四开关元件在其中一个对应的第一开关电路所连接的数据线的电压高于所述第二参考电压时导通以使得所述其中一个对应的第一开关电路所连接的数据线的电压通过所述第二放电电路释放；
    在所述液晶显示面板的驱动显示或测试阶段，所述第三开关元件和所述第四开关元件中的至少一个开关元件的控制端输入第二控制信号，所述第三开关元件和所述第四开关元件中的所述至少一个开关元件的第二端输入所述数据信号，以实现对应的至少两个第一开关电路的第一开关元件和所述第二开关元件中的至少其中一个开关元件的第二端输入数据信号。
  3. 根据权利要求2所述的驱动电路，其中，所述第一参考电压和所述第二参考电压为地电压，所述第一放电电路和所述第二放电电路均为接地的短路线；
    其中，在所述液晶显示面板的阵列制程阶段，所述第一开关元件、所述第二开关元件、所述第三开关元件、所述第四开关元件的控制端均与所述短路线连接，所述第三开关元件、第四开关电路的第二端均与所述短路线连接，每个所述第二开关电路的第三开关元件、第四开关元件的第一端以及对应的至少两个第一开关电路的第一开关元件、第二开关元件的第二端相互连接，在所述液晶显示面板的驱动显示或测试阶段，切除所述短路线，并使每个所述第一开关电路中的第一开关元件和第二开关元件中的至少一个的控制端输入所述第一控制信号，每个所述第二开关电路中的第三开关元件和第四开关元件中的至少一个的控制端输入所述第二控制信号，每个所述第二开关电路中的第三开关元件和第四开关元件中的所述至少一个的第二端输入所述数据信号。
  4. 根据权利要求3所述的驱动电路，其中，所述第一开关元件和所述第三开关元件为N型薄膜晶体管，所述第二开关元件和所述第四开关元件为P型薄膜晶体管，所述薄膜晶体管的栅极、源极和漏极分别作为所述开关元件的控制端、第一端和第二端。
  5. 一种液晶显示面板，其中，包括驱动电路，所述驱动电路包括多个第一开关电路；
    每个所述第一开关电路包括第一开关元件，所述第一开关元件包括控制端、第一端和第二端，所述第一开关元件的第一端连接所述液晶显示面板的一条数据线；
    其中，在所述液晶显示面板的阵列制程阶段，所述第一开关元件的控制端用于输入第一参考电压，所述第一开关元件的第二端用于连接第一放电电路，所述第一开关元件在所述数据线的电压高于或低于所述第一参考电压时导通以使所述数据线的电压通过所述第一放电电路释放，在所述液晶显示面板的驱动显示或测试阶段，所述第一开关元件的控制端输入第一控制信号，所述第一开关元件的第二端输入数据信号，以在所述第一控制信号控制所述第一开关元件导通时所述数据信号通过所述第一开关元件传输至所述数据线，实现所述液晶显示面板的显示或测试。
  6. 根据权利要求5所述的液晶显示面板，其中，每个所述第一开关电路还包括第二开关元件，所述第二开关元件包括控制端、第一端和第二端，所述第一开关元件和所述第二开关元件的第一端与所述液晶显示面板的同一条数据线连接，其中，在所述液晶显示面板的阵列制程阶段，所述第一开关元件和所述第二开关元件的控制端分别用于输入第一参考电压和第二参考电压，所述第一开关元件和所述第二开关元件的第二端分别用于连接第一放电电路和第二放电电路，所述第一开关元件在所述数据线的电压低于所述第一参考电压时导通以使所述数据线的电压通过所述第一放电电路释放，所述第二开关元件在所述数据线的电压高于所述第二参考电压时导通以使所述数据线的电压通过所述第二放电电路释放，在所述液晶显示面板的驱动显示或测试阶段，所述第一开关元件和所述第二开关元件中的至少一个开关元件的控制端输入第一控制信号，所述第一开关元件和所述第二开关元件中的所述至少一个开关元件的第二端输入数据信号，以实现所述液晶显示面板的显示。
  7. 根据权利要求6所述的液晶显示面板，其中，还包括多个第二开关电路；
    每个所述第二开关电路包括第三开关元件和第四开关元件，每个所述第二开关电路与至少两个第一开关电路对应，所述至少两个第一开关电路的第一开关元件的第二端通过所述第三开关元件与所述第一放电电路连接或接收所述数据信号，所述至少两个第一开关电路的第二开关元件的第二端通过所述第四开关元件与所述第二放电电路连接或接收所述数据信号，其中，所述第三开关元件和所述第四开关元件分别包括控制端、第一端和第二端，所述第三开关元件的第一端连接与其对应的至少两个第一开关电路的第一开关元件的第二端，所述第四开关元件的第一端连接与其对应的至少两个第一开关电路的第二开关元件的第二端；
    在所述液晶显示面板的阵列制程阶段，所述第三开关元件和所述第四开关元件的控制端分别用于输入所述第一参考电压和所述第二参考电压，所述第三开关元件和所述第四开关元件的第一端分别用于连接第一放电电路和第二放电电路，所述第三开关元件在其中一个对应的第一开关电路所连接的数据线的电压低于所述第一参考电压时导通以使得所述其中一个对应的第一开关电路所连接的数据线的电压通过所述第一放电电路释放，所述第四开关元件在其中一个对应的第一开关电路所连接的数据线的电压高于所述第二参考电压时导通以使得所述其中一个对应的第一开关电路所连接的数据线的电压通过所述第二放电电路释放；
    在所述液晶显示面板的驱动显示或测试阶段，所述第三开关元件和所述第四开关元件中的至少一个开关元件的控制端输入第二控制信号，所述第三开关元件和所述第四开关元件中的所述至少一个开关元件的第二端输入所述数据信号，以实现对应的至少两个第一开关电路的第一开关元件和所述第二开关元件中的至少其中一个开关元件的第二端输入数据信号。
  8. 根据权利要求7所述的液晶显示面板，其中，所述第一参考电压和所述第二参考电压为地电压，所述第一放电电路和所述第二放电电路均为接地的短路线；
    其中，在所述液晶显示面板的阵列制程阶段，所述第一开关元件、所述第二开关元件、所述第三开关元件、所述第四开关元件的控制端均与所述短路线连接，所述第三开关元件、第四开关电路的第二端均与所述短路线连接，每个所述第二开关电路的第三开关元件、第四开关元件的第一端以及对应的至少两个第一开关电路的第一开关元件、第二开关元件的第二端相互连接，在所述液晶显示面板的驱动显示或测试阶段，切除所述短路线，并使每个所述第一开关电路中的第一开关元件和第二开关元件中的至少一个的控制端输入所述第一控制信号，每个所述第二开关电路中的第三开关元件和第四开关元件中的至少一个的控制端输入所述第二控制信号，每个所述第二开关电路中的第三开关元件和第四开关元件中的所述至少一个的第二端输入所述数据信号。
  9. 根据权利要求8所述的驱动电路，其中，所述第一开关元件和所述第三开关元件为N型薄膜晶体管，所述第二开关元件和所述第四开关元件为P型薄膜晶体管，所述薄膜晶体管的栅极、源极和漏极分别作为所述开关元件的控制端、第一端和第二端。
  10. 一种液晶显示面板的制造方法，其中，包括：
    形成液晶显示面板的驱动电路，所述驱动电路包括多个第一开关电路，每个所述第一开关电路包括第一开关元件，所述第一开关元件包括控制端、第一端和第二端，所述第一开关元件的第一端连接所述液晶显示面板的一条数据线；
    在所述液晶显示面板的阵列制程阶段，使所述第一开关元件的控制端输入第一参考电压，使所述第一开关元件的第二端连接第一放电电路，以当所述第一开关元件在所述数据线的电压高于或低于所述第一参考电压导通时使得所述数据线的电压通过所述第一放电电路释放；
    在所述阵列制程阶段之后，在所述液晶显示面板的驱动显示或测试阶段，使所述第一开关元件的第二端与所述第一放电电路断开，使所述第一开关元件的控制端输入第一控制信号，并使所述第一开关元件的第二端输入数据信号，以当所述第一控制信号控制所述第一开关元件导通时使得所述数据信号通过所述第一开关元件传输至数据线，进而实现液晶显示面板的显示或测试。
  11. 根据权利要求10所述的制造方法，其中，所述形成液晶显示面板的驱动电路的步骤包括：
    形成液晶显示面板的驱动电路，所述驱动电路还包括多个第二开关元件，所述第二开关元件包括控制端、第一端和第二端，所述第一开关元件和所述第二开关元件的第一端与所述液晶显示面板的同一条数据线连接；
    在所述液晶显示面板的阵列制程阶段中，还包括步骤：使所述第二开关元件的控制端输入第二参考电压，使所述第二开关元件的第二端连接第二放电电路，以当所述第二开关元件在所述数据线的电压高于所述第二参考电压导通时使得所述数据线的电压通过所述第二放电电路释放，其中，所述第一开关元件在所述数据线的电压低于所述第一参考电压时导通；
    在所述阵列制程阶段之后，在所述液晶显示面板的驱动显示或测试阶段，包括步骤：使所述第一开关元件和所述第二开关元件分别与所述第一放电电路和第二放电电路断开，并使所述第一开关元件和所述第二开关元件中的至少一个开关元件的控制端输入第一控制信号，使所述第一开关元件和所述第二开关元件中的所述至少一个开关元件的第二端输入数据信号，以实现所述液晶显示面板的显示。
PCT/CN2015/090491 2015-09-08 2015-09-24 液晶显示面板及其驱动电路、制造方法 WO2017041330A1 (zh)

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