WO2020056870A1 - 驱动电路、升压芯片及显示装置 - Google Patents

驱动电路、升压芯片及显示装置 Download PDF

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Publication number
WO2020056870A1
WO2020056870A1 PCT/CN2018/113346 CN2018113346W WO2020056870A1 WO 2020056870 A1 WO2020056870 A1 WO 2020056870A1 CN 2018113346 W CN2018113346 W CN 2018113346W WO 2020056870 A1 WO2020056870 A1 WO 2020056870A1
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WIPO (PCT)
Prior art keywords
module
sub
signal
switch module
switch
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PCT/CN2018/113346
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English (en)
French (fr)
Inventor
邱彬
Original Assignee
重庆惠科金渝光电科技有限公司
惠科股份有限公司
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Application filed by 重庆惠科金渝光电科技有限公司, 惠科股份有限公司 filed Critical 重庆惠科金渝光电科技有限公司
Priority to US16/254,617 priority Critical patent/US10783817B2/en
Publication of WO2020056870A1 publication Critical patent/WO2020056870A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present application relates to the technical field of display panels, and in particular, to a driving circuit, a booster chip, and a display device.
  • GOA Gate driver on Array
  • gate driver IC gate driver integrated on array substrates
  • the size of the IC limits further narrowing of the bezel.
  • the GOA circuit is to split the original Gate IC into a boost chip (level shifter IC) and shift register (shift register) two parts, the boost chip is on the driver board, the shift register is on the panel, the boost chip sends CLK to the shift register to complete the drive, thereby saving Gate
  • the IC structure further compresses the frame length.
  • the GOA process will make shift registers on the left and right sides of the panel to achieve bilateral driving.
  • the shift register on one side may be damaged and the display may be abnormal. Damaged, so it is impossible to fix a driving method.
  • the driving board is costly and time-consuming, and if the size of the display panel is too large, the unilateral driving may cause insufficient charging time at the remote end.
  • the main purpose of this application is to provide a driving circuit, which aims to improve the compatibility of the driving board and reduce the design cost.
  • the driving circuit includes:
  • the potential boosting module is configured to divide the clock signal output by the timing controller into two clock signal groups and output them to two shift registers on the display panel.
  • the two clock signal groups include multiple Sub clock signals
  • a switch module connected in series between the potential boosting module and the shift registers at both ends of the display panel, and configured to be correspondingly turned on or off according to the received switch control signal;
  • the current detection module is connected in series between the potential boosting module and the switch module, or is connected in series between the switch module and the shift registers at both ends of the display panel, and is configured to detect the two clock signal groups respectively. Output current of each sub-clock signal, and feedback multiple current signals to the control module;
  • the control module is configured to receive a plurality of the current signals output by the current detection module, and compare the current values corresponding to the plurality of current signals with a preset current threshold. When any one of the clock signal groups When the current value of the clock signal is less than a preset current threshold value, a control signal is output to the switch module to control the switch module to cut off the output of the clock signal group, and to combine the clock signal group with another clock signal group Corresponding superimposed output to another shift register.
  • a signal input terminal of the potential boost module is connected to a signal output terminal of the timing controller
  • a signal output terminal of the potential boost module is connected to a signal input terminal of the electrical detection module
  • the current The signal output terminal of the detection module is connected to the signal input terminal of the switch module
  • the first signal output terminal of the switch module is connected to the signal input terminal of the first shift register of the display panel.
  • the two signal output terminals are connected to the signal input terminal of the second shift register of the display panel.
  • the controlled terminal of the potential boost module, the signal output terminal of the current detection module, and the controlled terminal of the switch module are all It is connected with the signal terminal of the control module.
  • the switch module includes a first sub-switch module, a second sub-switch module, and a third sub-switch module.
  • the first signal output terminal of the current detection module are interconnected, the second signal terminal of the first sub-switch module is connected to the signal terminal of the first shift register of the display panel, and the The first signal terminal, the second signal terminal of the third sub-switch module and the second signal output terminal of the current detection module are interconnected, and the second signal terminal of the second sub-switch module is connected to the right of the display panel.
  • the signal end of the side shift register is connected, and the controlled end of the first sub-switch module, the controlled end of the second sub-switch module, and the controlled end of the third sub-switch module are all connected to the control module. Control terminal connection.
  • the first sub-switch module, the second sub-switch module, and the third sub-switch module each include a plurality of switching circuits, and the first end of the switching circuit of each of the first sub-switch modules passes through the first
  • the corresponding switching circuit of the three sub-switching module is connected to the first end of the corresponding switching circuit of the second sub-switching module, and two clock signal groups including multiple sub-clock signals pass through multiple switches of the first switching module, respectively.
  • the circuit and a plurality of switch circuits of the second switch module are output to two shift registers on the display panel, and a controlled end of each of the switch circuits is respectively connected to a control end of the control module.
  • each of the sub-switch modules is linked.
  • each of the sub-switch modules is a metal-oxide semiconductor field-effect transistor.
  • each of the sub-switch modules is a triode.
  • the current detection module includes a plurality of sub-current detection modules, and each of the sub-current detection modules detects the current of each of the sub-clock signals and feeds back the current signals to the control module respectively.
  • This application also proposes a boost chip, which includes the driving circuit, and the driving circuit includes:
  • the potential boosting module is configured to divide the clock signal output by the timing controller into two clock signal groups and output them to two shift registers on the display panel.
  • the two clock signal groups include multiple Sub clock signals
  • a switch module connected in series between the potential boosting module and the shift registers at both ends of the display panel, and configured to be correspondingly turned on or off according to the received switch control signal;
  • the current detection module is connected in series between the potential boosting module and the switch module, or is connected in series between the switch module and the shift registers at both ends of the display panel, and is configured to detect the two clock signal groups respectively. Output current of each sub-clock signal, and feedback multiple current signals to the control module; and
  • the control module is configured to receive a plurality of the current signals output by the current detection module, and compare the current values corresponding to the plurality of current signals with a preset current threshold. When any one of the clock signal groups When the current value of the clock signal is less than a preset current threshold value, a control signal is output to the switch module to control the switch module to cut off the output of the clock signal group, and to combine the clock signal group with another clock signal group Corresponding superimposed output to another shift register.
  • a signal input terminal of the potential boost module is connected to a signal output terminal of the timing controller
  • a signal output terminal of the potential boost module is connected to a signal input terminal of the electrical detection module
  • the current The signal output terminal of the detection module is connected to the signal input terminal of the switch module
  • the first signal output terminal of the switch module is connected to the signal input terminal of the first shift register of the display panel.
  • the two signal output terminals are connected to the signal input terminal of the second shift register of the display panel.
  • the controlled terminal of the potential boost module, the signal output terminal of the current detection module, and the controlled terminal of the switch module are all It is connected with the signal terminal of the control module.
  • the switch module includes a first sub-switch module, a second sub-switch module, and a third sub-switch module.
  • the first signal output terminal of the current detection module are interconnected, the second signal terminal of the first sub-switch module is connected to the signal terminal of the first shift register of the display panel, and the The first signal terminal, the second signal terminal of the third sub-switch module and the second signal output terminal of the current detection module are interconnected, and the second signal terminal of the second sub-switch module is connected to the right of the display panel.
  • the signal end of the side shift register is connected, and the controlled end of the first sub-switch module, the controlled end of the second sub-switch module, and the controlled end of the third sub-switch module are all connected to the control module. Control terminal connection.
  • the first sub-switch module, the second sub-switch module, and the third sub-switch module each include a plurality of switching circuits, and the first end of the switching circuit of each of the first sub-switch modules passes through the first
  • the corresponding switching circuit of the three sub-switching module is connected to the first end of the corresponding switching circuit of the second sub-switching module, and two clock signal groups including multiple sub-clock signals pass through multiple switches of the first switching module, respectively.
  • the circuit and a plurality of switch circuits of the second switch module are output to two shift registers on the display panel, and a controlled end of each of the switch modules is respectively connected to a control end of the control module.
  • each of the switching circuits is a metal-oxide semiconductor field effect transistor.
  • each of the switching circuits is a transistor.
  • the current detection module includes a plurality of sub-current detection circuits, and each of the sub-current detection modules detects a current of each of the sub-clock signals and feeds back the current signals to the control module respectively.
  • the potential boost module, the current detection module, the switch module, and the control module are integrated on the boost chip.
  • the present application also proposes a display device including the boost chip, the boost chip including the driving circuit, and the driving circuit including:
  • the potential boosting module is configured to divide the clock signal output by the timing controller into two clock signal groups and output them to two shift registers on the display panel.
  • the two clock signal groups include multiple Sub clock signals
  • a switch module connected in series between the potential boosting module and the shift registers at both ends of the display panel, and configured to be correspondingly turned on or off according to the received switch control signal;
  • the current detection module is connected in series between the potential boosting module and the switch module, or is connected in series between the switch module and the shift registers at both ends of the display panel, and is configured to detect the two clock signal groups respectively. Output current of each sub-clock signal, and feedback multiple current signals to the control module; and
  • the control module is configured to receive a plurality of the current signals output by the current detection module, and compare the current values corresponding to the plurality of current signals with a preset current threshold. When any one of the clock signal groups When the current value of the clock signal is less than a preset current threshold value, a control signal is output to the switch module to control the switch module to cut off the output of the clock signal group, and to combine the clock signal group with another clock signal group Corresponding superimposed output to another shift register.
  • the technical solution of the present application adopts the technical solution of the present application to form a driving circuit by using a potential boosting module, a current detection module, a switch module and a control module.
  • the potential boosting module boosts the potential of the low-voltage logic signal input by the timing controller and is divided into two channels.
  • a clock signal group including a plurality of sub clock signals is output to two shift registers on the display panel, thereby driving the display panel bilaterally.
  • the current detection module detects the current of the clock signal of each channel, and then feeds it back to the control module. When one of the shift registers is damaged, the current of the clock signal output to the shift register is abnormal.
  • the control module outputs a control signal to the switch module according to the current signal fed back by the current detection module, thereby turning off the output to the shift register. Clock signal, and superimpose the signal of this clock signal group with another clock signal group to realize unilateral driving. Thereby, different abnormal states of the shift registers at both ends of the display panel are dynamically matched, and the problem that the unilateral driving of the large-size panel may cause insufficient remote charging time is improved, and the compatibility of the driving board is improved.
  • FIG. 1 is a schematic diagram of functional modules of an embodiment of a driving circuit of the present application
  • FIG. 2 is a schematic diagram of a functional module of another embodiment of a driving circuit of the present application.
  • FIG. 3 is a functional module schematic diagram of another embodiment of a driving circuit of the present application.
  • FIG. 4 is a schematic diagram of functional modules of an embodiment of a boost chip.
  • the driving circuit 100 of the present application is suitable for driving a large-sized display panel, the driving circuit 100 is a gate driving circuit, and is configured to output a gate driving signal to a gate line of the display panel to turn on the gate line.
  • the gate line has a large load.
  • GOA uses bilateral driving, that is, for a row of gate lines, there are shift register pairs on the left and right sides to charge. When the shift register on one side is damaged, then There will be insufficient charging. Therefore, the input current of the input signal on the other side must be increased.
  • FIG. 1 is a functional module schematic diagram of an embodiment of a driving circuit of the present application.
  • the driving circuit 100 includes:
  • the potential boosting module 110 is configured to divide the clock signal output by the timing controller 200 into two clock signal groups after potential boosting, and correspondingly output to two shift registers on the display panel.
  • the two clock signal groups are respectively Including multiple sub-clock signals;
  • the switch module 140 is connected in series between the potential boosting module 110 and the shift registers at both ends of the display panel, and is configured to be correspondingly turned on or off according to the received switch control signal;
  • the current detection module 130 is connected in series between the potential boosting module 110 and the switch module 140, or is connected in series between the switch module 140 and the shift registers at both ends of the display panel, and is configured to detect two channels respectively.
  • the output current of each sub-clock signal of the clock signal group is described, and a plurality of current signals are fed back to the control module 120;
  • the control module 120 is configured to receive a plurality of the current signals output by the current detection module 130, and compare a current value corresponding to the plurality of current signals with a preset current threshold. When the current value of a sub-clock signal is less than a preset current threshold, a control signal is output to the switch module 140 to control the switch module 140 to cut off the output of the clock signal group, and connect the clock signal group with another channel.
  • the clock signal group is correspondingly superimposed and output to another shift register.
  • the display panel includes, but is not limited to, a liquid crystal display panel, an organic light emitting diode display panel, a field emission display panel, a plasma display panel, and a curved panel.
  • the liquid crystal panel includes a thin film transistor liquid crystal display panel, TN (Twisted Nematic (Twisted Nematic) panels, VA (Vertical Alignment) panels, IPS (In-Plane Switching, plane switching) panel. Shift registers provided at both ends of the display panel, such as the first shift register 310 and the second shift register 320, receive multiple clock signals output from the driving circuit 100 and drive the pixels inside the display panel to work.
  • the shift registers at both ends receive The clock signals are the same, and each clock signal is a certain period earlier than the previous clock signal. Assuming that the clock signals output by the drive circuit 100 to the shift registers at both ends are CLK1 ⁇ CLK4, CLK2 is 1/4 cycle earlier than CLK1. CLK3 is 1/4 cycle ahead of CLK2.
  • the driving circuit 100 can also output 6 sub-clock signals or 8 sub-clock signals according to demand. Using more CLK signals can reduce the load of each signal line and reduce power consumption. But at the same time, the number of pins of the circuit will be increased. In actual design, the number of clock signals to be output can be selected according to the frame width, product size, integrated circuit design, and resolution of the specific product.
  • the potential boosting module 110 receives the low-level clock signal output from the timing controller 200, and performs level conversion on the clock signal under the modulation of the control module 120. After the low-level clock signal is boosted, it outputs two identical clock signals Each clock signal group includes multiple sub-clock signals. The number of sub-clock signals can be set according to requirements, such as 4, 6, or 8.
  • the clock signal group output by the potential boost module 110 flows through the current detection module 130, The switch module 140 outputs to two shift registers at both ends of the display panel.
  • the current detection module 130 detects the current of each sub-clock signal.
  • the current detection module 130 can select a circuit such as a sampling resistor or a transformer for current detection.
  • the switch module 140 You can choose multiple switching components or switching circuits with switching capabilities, such as relays, field-effect transistors, and triodes. You can choose one switch to control the output of a clock signal group, or one switch to control the output of a sub-clock signal. The controlled end of the switch is connected to the control end of the control module 120. The control signal output by the module 120 is turned on or off.
  • the control module 120 can choose a microprocessor, a programmable single-chip microcomputer, etc., and a comparator circuit can be set up on the periphery for voltage comparison. It can be specifically set according to the actual situation. There are no specific restrictions here.
  • the signal input terminal of the potential boosting module 110 is connected to the signal output terminal of the timing controller 200, and the signal output terminal of the potential boosting module 110 is connected to the signal of the electrical detection module.
  • the input terminal is connected.
  • the signal output terminal of the current detection module 130 is connected to the signal input terminal of the switch module 140.
  • the first signal output terminal of the switch module 140 is connected to the first shift register 310 of the display panel.
  • the signal input terminal is connected, the second signal output terminal of the switch module 140 is connected to the signal input terminal of the second shift register 320 of the display panel, the controlled terminal of the potential boosting module 110, the current detection module
  • the signal output terminal of 130 and the controlled terminal of the switch module 140 are both connected to the signal terminal of the control module 120.
  • the current detection module 130 may be disposed at the front or rear of the switch module 140, and may be specifically set according to the position of the driving board, which is not specifically limited here.
  • the current detection module 130 is disposed at the front of the switch module 140, and the switch
  • the signal output terminals of the module 140 are respectively connected to the signal input terminals of the two shift registers.
  • bilateral driving is realized.
  • the corresponding output is output to the shift register. All or a single subclock signal of the bit register cannot be input normally, which causes abnormal driving.
  • the current detection module 130 detects the current of each subclock signal and feeds back the current value of each subclock signal to the control module 120.
  • the control module 120 compares the current value with a preset current threshold according to the magnitude of the current value. When the current value of one of the sub-clock signals output to the first shift register 310 or the second shift register 320 is less than the preset current threshold, the control module 120 determines the The shift register is abnormal, and outputs a control signal to the switch module 140, the switch module 1
  • the sub-switch module inside 40 corresponds to the on or off action, cuts off the clock signal group output to the shift register, and superimposes the signal group of this clock signal with the signal group of another normal output.
  • CLK1 input to the first shift register 310 is superimposed with CLK1 output to the second shift register 320, and CLK2 and CLK2 are superimposed to achieve high-current unilateral driving and increase the driving current of the display panel. If the two shift registers are damaged, the two clock signal groups are cut off, and the shift registers are repaired or replaced.
  • the driving circuit 100 can be set to drive a large-sized display panel.
  • the drive is bilateral, and when one of the shift registers is abnormal, it automatically switches to the unilateral drive and realizes the corresponding signal. Superimposed to increase the output current of the unilateral drive.
  • the drive circuit 100 is installed on the drive board, which can drive the left, right, and left and right sides normally. There is no need to design three kinds of drive boards, which improves the compatibility of the drive boards and solves the problem. Large-size panel unilateral drive may cause insufficient remote charging time and reduce design costs.
  • the technical solution of the present application adopts the technical solution of the present application to form the driving circuit 100 by using the potential boost module 110, the current detection module 130, the switch module 140, and the control module 120.
  • the potential boost module 110 inputs the low-voltage logic input by the timing controller 200.
  • the signal is boosted and divided into two clock signal groups including multiple sub-clock signals and output to two shift registers on the display panel, thereby driving the display panel bilaterally.
  • the current detection module 130 detects the current of the clock signal of each channel. Then feedback to the control module 120. When one of the shift registers on the display panel is damaged, the current of the clock signal output to the shift register is abnormal.
  • the control module 120 outputs a control signal corresponding to the current signal fed back by the current detection module 130.
  • FIG. 2 is a functional module schematic diagram of another embodiment of the driving circuit of the present application.
  • the switch module 140 includes a first sub-switch module 141, a second sub-switch module 142 and The third sub-switch module 143, the first signal terminal of the first sub-switch module 141, the first signal terminal of the third switch, and the first signal output terminal of the current detection module 130 are interconnected.
  • a second signal terminal of a sub-switch module 141 is connected to a signal terminal of the first shift register 310 of the display panel, a first signal terminal of the second sub-switch module 142, and a third signal terminal of the third sub-switch module 143.
  • the two signal terminals are interconnected with the second signal output terminal of the current detection module 130, and the second signal terminal of the second sub-switch module 142 is connected to the signal terminal of the second shift register 320 of the display panel.
  • the controlled terminal of the first sub-switch module 141, the controlled terminal of the second sub-switch module 142, and the controlled terminal of the third sub-switch module 143 are all connected to the control terminal of the control module 120.
  • the two sets of clock signals are output to the corresponding shift register via the first sub-switch module 141 and the second sub-switch module 142, respectively, to realize bilateral driving.
  • the first sub-switch module 141 and the second sub-switch The module 142 controls the output of multiple sub-clock signals at the same time.
  • the first sub-switch module 141 and the second sub-switch module 142 are kept on at the beginning.
  • the signal input terminal of the first sub-switch module 141 and the second sub-switch module 142 A third sub-switch module 143 is connected in series between the signal input terminals of the switch.
  • the third sub-switch module 143 is initially kept off.
  • the first shift register 310 When one of the two shift registers is damaged, for example, the first shift register 310 is output to The current of the clock signal of the first shift register 310 is abnormal. One of the sub-clock signal currents is too small, or one of the sub-clock signal currents is too small. When the current value is less than a preset current threshold, the control module 120 then Output control signals to the first sub-switch module 141 to the third sub-switch module 143. The first sub-switch module 141 is turned off and cut off and output to the first shift register 310.
  • the third sub-switch module 143 is turned on, and the clock signal group output to the first shift register 310 is output to the second shift register 320 through the third sub-switch module 143, thereby forming a unilateral high-current drive. Therefore, the compatibility of the driver board is improved, and the problem that the unilateral driving of the large-size panel may cause insufficient remote charging time may be solved.
  • the first sub-switch module 141, the second sub-switch module 142, and the third sub-switch module 143 may adopt multiple-input multiple-output relays or other switching components, and may be specifically designed according to actual conditions, and are not specifically limited herein.
  • FIG. 3 is a functional module schematic diagram of another embodiment of the driving circuit of the present application, the first sub-switch module 141, the second sub-switch module 142, and the third sub-switch
  • the modules 143 each include a plurality of switching circuits, and the first end of the switching circuit of each of the first sub-switching modules 141 corresponds to the second sub-switching module 142 through a corresponding switching circuit of the third sub-switching module 143.
  • the first end of the switching circuit is connected, and the two clock signal groups including a plurality of sub-clock signals are respectively output to a plurality of switching circuits of the first switching module 140 and a plurality of switching circuits of the second switching module 140.
  • the two shift registers on the display panel, and the controlled ends of each of the switch circuits are respectively connected to the control ends of the control module 120.
  • each sub-switching module 140 includes multiple switching circuits, such as K1 to K12 in the figure, multiple switching circuits of the first sub-switching module 141 and multiple switching circuits of the second sub-switching module 142.
  • the clock signals output by the potential boosting module 110 correspond one-to-one.
  • the switching circuit of the first sub-switching circuit 141 and the switching circuit of the second sub-switching module 142 are connected in series between the current detection module 130 and the shift register, and are set to control each The output of the sub-clock signal.
  • the multiple switching circuits of the third sub-switching module 143 are connected in series between the switching circuits of the first sub-switching module 141 and the switching circuits of the second sub-switching module 142, and belong to the same sub-switch.
  • Multiple switching circuits of the module 140 all operate simultaneously, for example, K1 ⁇ K4 in Fig. 3 are turned on or off at the same time, K5 ⁇ K8 are turned on or off at the same time, and K9 ⁇ K12 are turned on or off at the same time, thereby realizing the clock signal
  • the multiple sub-clock signals of the group are controlled synchronously, and the automatic switching between the bilateral driving and the high-current unilateral driving is realized under the control of the control module 120.
  • each switching circuit is a metal-oxide semiconductor field effect transistor.
  • each switching circuit may use a metal-oxide semiconductor field-effect transistor, and a gate of the metal-oxide semiconductor field-effect transistor.
  • the controlled terminal of the pole switch module 140 is connected to the control terminal of the control module 120.
  • the metal-oxide semiconductor field-effect transistor can be an N-channel metal-oxide semiconductor field-effect transistor or a P-channel metal-oxide semiconductor. Field-effect transistor. When an N-channel metal-oxide semiconductor field-effect transistor is selected, the control module 120 outputs a high level to the metal-oxide semiconductor field-effect transistor to make it conductive, and outputs a low level to the metal-oxide semiconductor.
  • the MOSFET is turned off.
  • the control module 120 When a P-channel metal-oxide semiconductor field-effect transistor is selected, the control module 120 outputs a low level to the metal-oxide semiconductor field-effect transistor to make it conductive, and outputs a high level to The metal-oxide semiconductor field-effect transistor is turned off, and the type of the metal-oxide semiconductor field-effect transistor can be flexibly selected without specific limitation.
  • each switching circuit is a transistor.
  • each switching circuit may also use a triode, and the base of the triode is the controlled end of the sub-switching module 140 and the same as that of the control module 120.
  • the control terminal is connected.
  • the transistor can be an NPN transistor or a PNP transistor.
  • NPN transistor When an NPN transistor is selected, the control module 120 outputs a high level to the sub-switch module 140 to control its conduction and an output low level to turn it off.
  • a PNP transistor When a PNP transistor is selected, the control module 120 outputs a low level to the sub-switch module 140 to control its conduction and an output high level to turn it off.
  • the type of the transistor can be flexibly selected without specific restrictions.
  • the current detection module 130 includes a plurality of sub-current detection modules 130, and each of the sub-current detection modules 130 detects a current of each of the sub-clock signals and feeds back the current signals to The control module 120.
  • multiple sub-current detection modules 130 are configured to detect the sub-clock signals output by the potential boosting module 110, and the number of sub-current detection modules 130 is equal to the number of sub-clock signals and corresponds one-to-one.
  • Each sub-current detection module 130 detects the corresponding sub-clock signal and feeds back the current signal to the control module 120.
  • the sub-current detection module 130 may use a current transformer or a sampling resistor to perform current detection, and may be set according to specific conditions.
  • FIG. 4 is a schematic diagram of functional modules of an embodiment of the boost chip 400 of the present application.
  • the present application also proposes a boost chip 400 including the driving circuit 100 as described above.
  • the GOA circuit is to split the original Gate IC into a boost chip 400 (level shifter IC) and shift register (shift register) two parts, the boost chip 400 is on the driver board, the shift register is on the panel, the boost chip 400 sends CLK to the shift register to complete the drive, thereby saving Gate
  • the IC structure further reduces the length of the frame. Therefore, the potential boost module 110 in the driving circuit 100 can be used as a boost chip 400 alone, or the potential boost module 110, the current detection module 130, the switch module 140, and the control module 120 can be integrated in the boost.
  • the chip 400 further compresses the frame length.
  • the second method is adopted, that is, the potential boost module 110, the current detection module 130, the switch module 140, and the control module 120 are integrated in the boost chip 400.
  • the present application also proposes a display device.
  • the display device includes a boost chip 400.
  • boost chip 400 For a specific structure of the boost chip 400, refer to the foregoing embodiments. Since the display device adopts all the technical solutions of all the embodiments described above, it has at least the above All the technical effects brought by the technical solutions of the embodiments are not repeated here one by one.

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Abstract

一种驱动电路（100），包括电位提升模块（110）、开关模块（140）、电流检测模块（130）及控制模块（120），控制模块（120）根据电流检测模块（130）输出的电流信号对应控制开关模块（140）导通或者关断。该驱动电路（100）能够提高驱动板的兼容性。还提供了一种包括该驱动电路（100）的升压芯片（400）和显示装置。

Description

驱动电路、升压芯片及显示装置
技术领域
本申请涉及显示面板技术领域，特别涉及一种驱动电路、升压芯片及显示装置。
背景技术
随着大众对电视窄边框的需求越来越强烈，一种新型的GOA（Gate driver on Array，阵列基板上栅驱动集成）驱动架构正越来越受到欢迎。由于传统的显示面板要将Gate IC（门驱动IC）绑定在面板上，而Gate IC的尺寸限制了边框的进一步缩窄。但近些年随着新型GOA技术的问世，逐渐代替了传统的驱动方式，GOA电路是将原本的Gate IC拆分成升压芯片（level shifter IC）和移位寄存器（shift register）两部分，升压芯片做在驱动板上，移位寄存器在了面板上，升压芯片输送CLK给移位寄存器完成驱动，从而节省Gate IC结构，进一步压缩边框长度。
GOA制程会在面板的左右两侧都制作移位寄存器，实现双边驱动，但是由于制程的稳定性及使用过程中可能会造成某一侧的移位寄存器损坏造成显示异常，由于左右侧均有可能受到损伤，所以无法固定一种驱动方式，那么目前只能开发单独驱动左侧，单独驱动右侧，以及左右侧都正常驱动的三个驱动板，然后再根据实际损伤状况去被动地选择对应的驱动板，成本高昂且费时费力，并且若显示面板尺寸偏大，则单边驱动有可能发生远端充电时间不够的情况。
发明内容
本申请的主要目的是提供一种驱动电路，旨在提高驱动板的兼容性，降低设计成本。
为实现上述目的，本申请提出的一种驱动电路，该驱动电路包括：
电位提升模块，设置为将时序控制器输出的时钟信号进行电位提升后分为两路时钟信号组，并对应输出至显示面板上的两个移位寄存器，两路所述时钟信号组分别包括多个子时钟信号；
开关模块，串接在所述电位提升模块与显示面板两端的移位寄存器之间，设置为根据接收到的开关控制信号对应导通或者关断；
电流检测模块，串接在所述电位提升模块与所述开关模块之间，或者串接在所述开关模块与显示面板两端的移位寄存器之间，设置为分别检测两路所述时钟信号组的每一子时钟信号的输出电流，并将多个电流信号反馈至控制模块；
控制模块，设置为接收所述电流检测模块输出的多个所述电流信号，并将多个所述电流信号对应的电流值与预设电流阈值比较，当其中一路时钟信号组中的任一子时钟信号的电流值小于预设电流阈值时，输出控制信号至所述开关模块以控制所述开关模块切断该路时钟信号组的输出，并将该路时钟信号组与另一路所述时钟信号组对应叠加后输出至另一个移位寄存器。
可选地，所述电位提升模块的信号输入端与所述时序控制器的信号输出端连接，所述电位提升模块的信号输出端流与所述电检测模块的信号输入端连接，所述电流检测模块的信号输出端与所述开关模块的信号输入端连接，所述开关模块的第一信号输出端与所述显示面板的第一移位寄存器的信号输入端连接，所述开关模块的第二信号输出端与所述显示面板的第二移位寄存器的信号输入端连接，所述电位提升模块的受控端、所述电流检测模块的信号输出端及所述开关模块的受控端均与所述控制模块的信号端连接。
可选地，所述开关模块包括第一子开关模块、第二子开关模块及第三子开关模块，所述第一子开关模块的第一信号端、所述第三开关的第一信号端及所述电流检测模块的第一信号输出端互连，所述第一子开关模块的第二信号端与所述显示面板第一移位寄存器的信号端连接，所述第二子开关模块的第一信号端、所述第三子开关模块的第二信号端及所述电流检测模块的第二信号输出端互连，所述第二子开关模块的第二信号端与所述显示面板右侧移位寄存器的信号端连接，所述第一子开关模块的受控端、所述第二子开关模块的受控端及所述第三子开关模块的受控端均与所述控制模块的控制端连接。
可选地，所述第一子开关模块、第二子开关模块及第三子开关模块均包括多个开关电路，每一所述第一子开关模块的开关电路的第一端通过所述第三子开关模块的对应的开关电路与所述第二子开关模块对应的开关电路的第一端连接，两路包括多个子时钟信号的时钟信号组分别经所述第一开关模块的多个开关电路及所述第二开关模块的多个开关电路输出至所述显示面板上的两个移位寄存器，每一所述开关电路的受控端分别与所述控制模块的控制端连接。
可选地，各所述子开关模块的多个开关电路联动。可选地，每一所述子开关模块为金属-氧化物半导体场效应管。
可选地，每一所述子开关模块为三极管。
可选地，所述电流检测模块包括多个子电流检测模块，每一所述子电流检测模块分别检测每一所述子时钟信号的电流，并将电流信号分别反馈至所述控制模块。
本申请还提出一种升压芯片，包括所述驱动电路，所述驱动电路包括：
电位提升模块，设置为将时序控制器输出的时钟信号进行电位提升后分为两路时钟信号组，并对应输出至显示面板上的两个移位寄存器，两路所述时钟信号组分别包括多个子时钟信号；
开关模块，串接在所述电位提升模块与显示面板两端的移位寄存器之间，设置为根据接收到的开关控制信号对应导通或者关断；
电流检测模块，串接在所述电位提升模块与所述开关模块之间，或者串接在所述开关模块与显示面板两端的移位寄存器之间，设置为分别检测两路所述时钟信号组的每一子时钟信号的输出电流，并将多个电流信号反馈至控制模块；以及
控制模块，设置为接收所述电流检测模块输出的多个所述电流信号，并将多个所述电流信号对应的电流值与预设电流阈值比较，当其中一路时钟信号组中的任一子时钟信号的电流值小于预设电流阈值时，输出控制信号至所述开关模块以控制所述开关模块切断该路时钟信号组的输出，并将该路时钟信号组与另一路所述时钟信号组对应叠加后输出至另一个移位寄存器。
可选地，所述电位提升模块的信号输入端与所述时序控制器的信号输出端连接，所述电位提升模块的信号输出端流与所述电检测模块的信号输入端连接，所述电流检测模块的信号输出端与所述开关模块的信号输入端连接，所述开关模块的第一信号输出端与所述显示面板的第一移位寄存器的信号输入端连接，所述开关模块的第二信号输出端与所述显示面板的第二移位寄存器的信号输入端连接，所述电位提升模块的受控端、所述电流检测模块的信号输出端及所述开关模块的受控端均与所述控制模块的信号端连接。
可选地，所述开关模块包括第一子开关模块、第二子开关模块及第三子开关模块，所述第一子开关模块的第一信号端、所述第三开关的第一信号端及所述电流检测模块的第一信号输出端互连，所述第一子开关模块的第二信号端与所述显示面板第一移位寄存器的信号端连接，所述第二子开关模块的第一信号端、所述第三子开关模块的第二信号端及所述电流检测模块的第二信号输出端互连，所述第二子开关模块的第二信号端与所述显示面板右侧移位寄存器的信号端连接，所述第一子开关模块的受控端、所述第二子开关模块的受控端及所述第三子开关模块的受控端均与所述控制模块的控制端连接。
可选地，所述第一子开关模块、第二子开关模块及第三子开关模块均包括多个开关电路，每一所述第一子开关模块的开关电路的第一端通过所述第三子开关模块的对应的开关电路与所述第二子开关模块对应的开关电路的第一端连接，两路包括多个子时钟信号的时钟信号组分别经所述第一开关模块的多个开关电路及所述第二开关模块的多个开关电路输出至所述显示面板上的两个移位寄存器，每一所述开关模块的受控端分别与所述控制模块的控制端连接。
可选地，各所述子开关模块的多个开关电路联动。
可选地，每一所述开关电路为金属-氧化物半导体场效应管。
可选地，每一所述开关电路为三极管。
可选地，所述电流检测模块包括多个子电流检测电路，每一所述子电流检测模块分别检测每一所述子时钟信号的电流，并将电流信号分别反馈至所述控制模块。
可选地，所述电位提升模块、所述电流检测模块、所述开关模块及所述控制模块集成在所述升压芯片上。
本申请还提出一种显示装置，包括所述升压芯片，所述升压芯片包括所述驱动电路，所述驱动电路包括：
电位提升模块，设置为将时序控制器输出的时钟信号进行电位提升后分为两路时钟信号组，并对应输出至显示面板上的两个移位寄存器，两路所述时钟信号组分别包括多个子时钟信号；
开关模块，串接在所述电位提升模块与显示面板两端的移位寄存器之间，设置为根据接收到的开关控制信号对应导通或者关断；
电流检测模块，串接在所述电位提升模块与所述开关模块之间，或者串接在所述开关模块与显示面板两端的移位寄存器之间，设置为分别检测两路所述时钟信号组的每一子时钟信号的输出电流，并将多个电流信号反馈至控制模块；以及
控制模块，设置为接收所述电流检测模块输出的多个所述电流信号，并将多个所述电流信号对应的电流值与预设电流阈值比较，当其中一路时钟信号组中的任一子时钟信号的电流值小于预设电流阈值时，输出控制信号至所述开关模块以控制所述开关模块切断该路时钟信号组的输出，并将该路时钟信号组与另一路所述时钟信号组对应叠加后输出至另一个移位寄存器。
本申请技术方案通过采用本申请技术方案通过采用电位提升模块、电流检测模块、开关模块及控制模块组成驱动电路，电位提升模块将时序控制器输入的低压逻辑信号进行电位提升，并分为两路包括多个子时钟信号的时钟信号组输出至显示面板上的两个移位寄存器，从而双边驱动显示面板，电流检测模块检测每一路的时钟信号电流大小，然后反馈给控制模块，当显示面板上的其中一个移位寄存器出现损坏时，输出至该移位寄存器的时钟信号的电流异常，控制模块根据电流检测模块反馈的电流信号对应输出控制信号至开关模块，从而关断输出至该移位寄存器的时钟信号，并将该路时钟信号组与另一路时钟信号组进行信号叠加实现单边驱动。从而动态匹配显示面板的两端移位寄存器的不同异常状态，并解决了大尺寸面板单边驱动有可能发生远端充电时间不够的问题，提高了驱动板的兼容性。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请驱动电路一实施例的功能模块示意图；
图2为本申请驱动电路另一实施例的功能模块示意图；
图3为本申请驱动电路又一实施例的功能模块示意图；
图4为本申请升压芯片一实施例的功能模块示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，在本申请中涉及“第一”、“第二”等的描述仅设置为描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，全文中出现的“和/或”的含义为：包括三个并列的方案，以“A/B”为例，包括A方案，或B方案，或A和B同时满足的方案，另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请驱动电路100适设置为驱动较大尺寸的显示面板，驱动电路100为栅极驱动电路，设置为输出栅极驱动信号至显示面板的栅极线以开启栅极线，对于大尺寸面板其栅极线的负载较大，为了正常开启栅极线，GOA采用双边驱动，即对于一行栅极线，左右两边均有移位寄存器对进行充电，当一侧的移位寄存器出现损坏时，则会出现充电不足的现象，因此，必须加大另一侧输入信号的输入电流，如图1所示，图1为本申请驱动电路一实施例的功能模块示意图，该驱动电路100包括：
电位提升模块110，设置为将时序控制器200输出的时钟信号进行电位提升后分为两路时钟信号组，并对应输出至显示面板上的两个移位寄存器，两路所述时钟信号组分别包括多个子时钟信号；
开关模块140，串接在所述电位提升模块110与显示面板两端的移位寄存器之间，设置为根据接收到的开关控制信号对应导通或者关断；
电流检测模块130，串接在所述电位提升模块110与所述开关模块140之间，或者串接在所述开关模块140与显示面板两端的移位寄存器之间，设置为分别检测两路所述时钟信号组的每一子时钟信号的输出电流，并将多个电流信号反馈至控制模块120；
控制模块120，设置为接收所述电流检测模块130输出的多个所述电流信号，并将多个所述电流信号对应的电流值与预设电流阈值比较，当其中一路时钟信号组中的任一子时钟信号的电流值小于预设电流阈值时，输出控制信号至所述开关模块140以控制所述开关模块140切断该路时钟信号组的输出，并将该路时钟信号组与另一路所述时钟信号组对应叠加后输出至另一个移位寄存器。
本实施例中，所述显示面板包括但不限于液晶显示面板、有机发光二极管显示面板、场发射显示面板、等离子显示面板、曲面型面板，所述液晶面板包括薄膜晶体管液晶显示面板、TN(Twisted Nematic，扭曲向列型)面板、VA(Vertical Alignment，垂直配向技术)类面板、IPS(In-Plane Switching，平面转换)面板等。设置在显示面板两端的移位寄存器，如第一移位寄存器310及第二移位寄存器320，接收驱动电路100输出的多个时钟信号并驱动显示面板内部的像素工作，两端移位寄存器接收的时钟信号相同，并且每一时钟信号比前一时钟信号提前一定周期，假设驱动电路100输出至两端移位寄存器的时钟信号分别均有CLK1~CLK4，则CLK2比CLK1提前1/4周期，CLK3比CLK2提前1/4周期，驱动电路100还可根据需求分别输出6个子时钟信号或者8个子时钟信号，采用更多的CLK信号可以减小每一条信号线的负载，同时可以降低功耗，但同时也会增加电路的管脚数，在实际设计中，可以根据具体产品的边框宽度、产品尺寸、集成电路设计和分辨率等条件选择输出的时钟信号的数量。
电位提升模块110接收时序控制器200输出的低电平时钟信号，并在控制模块120的调制下对时钟信号进行电平转换，将低电平时钟信号进行电位提升后输出两路相同的时钟信号组，每一时钟信号组包括多个子时钟信号，子时钟信号数量可根据需求对应设置，例如4个、6个或者8个等，电位提升模块110输出的时钟信号组流经电流检测模块130、开关模块140输出至显示面板两端的两个移位寄存器，电流检测模块130分别检测每一子时钟信号的电流大小，电流检测模块130可选择采样电阻或者互感器等电路进行电流检测，开关模块140可选择多个具有开关能力的开关元器件或者开关电路，例如继电器、场效应管以及三极管等等，可选择一个开关控制一个时钟信号组的信号输出，或者一个开关控制一个子时钟信号的输出，开关的受控端与控制模块120的控制端连接，根据控制模块120输出的控制信号进行导通或者关断，控制模块120可选择微处理器、可编程控制的单片机等，还可在外围搭建比较器电路进行电压比较，具体可根据实际情况进行具体设置，在此，不做具体限制。
在一可选实施例中，所述电位提升模块110的信号输入端与所述时序控制器200的信号输出端连接，所述电位提升模块110的信号输出端流与所述电检测模块的信号输入端连接，所述电流检测模块130的信号输出端与所述开关模块140的信号输入端连接，所述开关模块140的第一信号输出端与所述显示面板的第一移位寄存器310的信号输入端连接，所述开关模块140的第二信号输出端与所述显示面板的第二移位寄存器320的信号输入端连接，所述电位提升模块110的受控端、所述电流检测模块130的信号输出端及所述开关模块140的受控端均与所述控制模块120的信号端连接。
电流检测模块130可设置在开关模块140的前端或者后端，可根据驱动板的位置具体设置，在此不做具体限制，本实施例中，电流检测模块130设置在开关模块140的前端，开关模块140的信号输出端分别与两个移位寄存器的信号输入端连接，在显示面板两端的移位寄存器均正常时，实现双边驱动，在其中一个移位寄存器出现损坏时，对应输出至该移位寄存器的子时钟信号存在全部或者单个无法正常输入，进而造成驱动异常，电流检测模块130检测每一子时钟信号的电流大小，并将各个子时钟信号的电流值反馈至控制模块120，控制模块120根据电流值的大小与预设电流阈值比较，当输出至第一移位寄存器310或者第二移位寄存器320的其中一个子时钟信号的电流值小于预设电流阈值时，控制模块120判断该移位寄存器处于异常，并输出控制信号至开关模块140，开关模块140内部的子开关模块对应导通或者关断动作，将输出至该移位寄存器的时钟信号组切断，并将该路时钟信号组与另一路正常输出的信号组进行信号叠加，相同的子时钟信号进行叠加，例如输入至第一移位寄存器310的CLK1与输出至第二移位寄存器320的CLK1进行叠加，CLK2与CLK2进行叠加，实现大电流单边驱动，提高显示面板的驱动电流，如果两个移位寄存器均出现损坏，则将两路时钟信号组均切断，并对移位寄存器进行修复或者替换。
驱动电路100可设置为驱动中大尺寸显示面板，在显示面板两端的移位寄存器均正常时，双边驱动，在其中一个移位寄存器出现异常时，自动切换至单边驱动，并实现信号的对应叠加，提高单边驱动的输出电流，驱动电路100安装在驱动板上，可驱动左侧、右侧以及左右侧都正常驱动，无需设计三种驱动板，从而提高驱动板的兼容性，解决了大尺寸面板单边驱动有可能发生远端充电时间不够的问题，以及降低了设计成本。
本申请技术方案通过采用本申请技术方案通过采用电位提升模块110、电流检测模块130、开关模块140及控制模块120控制模块120组成驱动电路100，电位提升模块110将时序控制器200输入的低压逻辑信号进行电位提升，并分为两路包括多个子时钟信号的时钟信号组输出至显示面板上的两个移位寄存器，从而双边驱动显示面板，电流检测模块130检测每一路的时钟信号电流大小，然后反馈给控制模块120，当显示面板上的其中一个移位寄存器出现损坏时，输出至该移位寄存器的时钟信号的电流异常，控制模块120根据电流检测模块130反馈的电流信号对应输出控制信号至开关模块140，从而关断输出至该移位寄存器的时钟信号，并将该路时钟信号组与另一路时钟信号组进行信号叠加实现大电流单边驱动。从而动态匹配显示面板的两端移位寄存器的不同异常状态，并解决了大尺寸面板单边驱动有可能发生远端充电时间不够的问题，提高了驱动板的兼容性。
在一可选实施例中，如图2所示，图2为本申请驱动电路另一实施例的功能模块示意图，所述开关模块140包括第一子开关模块141、第二子开关模块142及第三子开关模块143，所述第一子开关模块141的第一信号端、所述第三开关的第一信号端及所述电流检测模块130的第一信号输出端互连，所述第一子开关模块141的第二信号端与所述显示面板第一移位寄存器310的信号端连接，所述第二子开关模块142的第一信号端、所述第三子开关模块143的第二信号端及所述电流检测模块130的第二信号输出端互连，所述第二子开关模块142的第二信号端与所述显示面板第二移位寄存器320的信号端连接，所述第一子开关模块141的受控端、所述第二子开关模块142的受控端及所述第三子开关模块143的受控端均与所述控制模块120的控制端连接。
在本实施例中，两路时钟信号组分别经第一子开关模块141及第二子开关模块142输出至对应的移位寄存器中，实现双边驱动，第一子开关模块141和第二子开关模块142同时控制多个子时钟信号的输出，第一子开关模块141及第二子开关模块142初始时保持导通状态，同时在第一子开关模块141的信号输入端及第二子开关模块142的信号输入端之间串联了第三子开关模块143，第三子开关模块143初始时保持断开状态，当两个移位寄存器其中一个出现损坏时，例如第一移位寄存器310，输出至第一移位寄存器310的时钟信号的电流出现异常，可能是其中一个子时钟信号电流过小，或者其中多个子时钟信号电流过小，当其电流值小于预设电流阈值时，控制模块120则输出控制信号至第一子开关模块141至第三子开关模块143，第一子开关模块141关断，切断输出至第一移位寄存器310的多个子时钟信号，第三子开关模块143导通，输出至第一移位寄存器310的时钟信号组通过第三子开关模块143输出至第二移位寄存器320，从而形成单边大电流驱动，从而提高驱动板的兼容性，并且解决了大尺寸面板单边驱动有可能发生远端充电时间不够的问题。
第一子开关模块141、第二子开关模块142及第三子开关模块143可采用多输入多输出的继电器或者其它开关元器件，具体可根据实际情况进行设计，在此不做具体限制。
在一可选实施例中，如图3所示，图3为本申请驱动电路又一实施例的功能模块示意图，所述第一子开关模块141、第二子开关模块142及第三子开关模块143均包括多个开关电路，每一所述第一子开关模块141的开关电路的第一端通过所述第三子开关模块143的对应的开关电路与所述第二子开关模块142对应的开关电路的第一端连接，两路包括多个子时钟信号的时钟信号组分别经所述第一开关模块140的多个开关电路及所述第二开关模块140的多个开关电路输出至所述显示面板上的两个移位寄存器，每一所述开关电路的受控端分别与所述控制模块120的控制端连接。
在本实施例中，每一子开关模块140包括多个开关电路，例如图中的K1至K12，第一子开关模块141的多个开关电路及第二子开关模块142的多个开关电路与电位提升模块110输出的时钟信号一一对应，第一子开关电路141的开关电路及第二子开关模块142的开关电路串接在电流检测模块130与移位寄存器之间，设置为控制每一子时钟信号的输出，第三子开关模块143的多个开关电路串接在第一子开关模块141的多个开关电路及第二子开关模块142的多个开关电路之间，属于同一子开关模块140的多个开关电路均同时动作，例如图3中的K1~K4同时导通或者关断，K5~K8同时导通或者关断，K9~K12同时导通或者关断，从而实现时钟信号组的多个子时钟信号的同步控制，并在控制模块120的控制下实现双边驱动与大电流单边驱动的自动切换。
在一可选实施例中，每一开关电路为金属-氧化物半导体场效应管。
在每一子开关模块140包括数量与时钟信号组的子时钟信号数量相同的子开关电路时，每一开关电路可采用金属-氧化物半导体场效应管，金属-氧化物半导体场效应管的栅极为子开关模块140的受控端，并与控制模块120的控制端连接，金属-氧化物半导体场效应管可选用N沟道金属-氧化物半导体场效应管或者P沟道金属-氧化物半导体场效应管，当选用N沟道金属-氧化物半导体场效应管，控制模块120输出高电平至金属-氧化物半导体场效应管以使其导通，输出低电平至金属-氧化物半导体场效应管以使其关断，当选用P沟道金属-氧化物半导体场效应管，控制模块120输出低电平至金属-氧化物半导体场效应管以使其导通，输出高电平至金属-氧化物半导体场效应管以使其关断，金属-氧化物半导体场效应管的类型可灵活选择，不做具体限制。
在一可选实施例中，每一开关电路为三极管。
在每一开关模块140包括数量与时钟信号组的子时钟信号数量相同的开关电路时，每一开关电路还可采用三极管，三极管的基极为子开关模块140的受控端并与控制模块120的控制端连接，三极管可选择NPN三极管或者PNP三极管，当选择NPN三极管时，控制模块120输出高电平至子开关模块140以控制其导通以及输出低电平以使其关断，对应地，当选择PNP三极管时，控制模块120输出低电平至子开关模块140以控制其导通以及输出高电平以使其关断，三极管的类型可灵活选择，不做具体限制。
在一可选实施例中，所述电流检测模块130包括多个子电流检测模块130，每一所述子电流检测模块130分别检测每一所述子时钟信号的电流，并将电流信号分别反馈至所述控制模块120。
需要说明的是，多个子电流检测模块130设置为检测电位提升模块110输出的子时钟信号，并且子电流检测模块130的数量与子时钟信号的数量相等且一一对应，每一子电流检测模块130检测对应的子时钟信号并将电流信号反馈至控制模块120，子电流检测模块130可采用电流互感器或者采样电阻等电路进行电流检测，可根据具体情况进行设置。
进一步地，如图4所示，图4为本申请升压芯片400一实施例的功能模块示意图，本申请还提出一种升压芯片400，包括如上所述的驱动电路100。
需要说明的是，GOA电路是将原本的Gate IC拆分成升压芯片400（level shifter IC）和移位寄存器（shift register）两部分，升压芯片400做在驱动板上，移位寄存器在了面板上，升压芯片400输送CLK给移位寄存器完成驱动，从而节省Gate IC结构，进一步压缩边框长度，因此，驱动电路100中的电位提升模块110单独可作为升压芯片400，或者将电位提升模块110、电流检测模块130、开关模块140以及控制模块120集成在升压芯片400内，进一步压缩边框长度，本实施例中，采用第二种方式，即电位提升模块110、电流检测模块130、开关模块140以及控制模块120集成在升压芯片400内。
本申请还提出一种显示装置，该显示装置包括升压芯片400，该升压芯片400的具体结构参照上述实施例，由于本显示装置采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有技术效果，在此不再一一赘述。
以上所述仅为本申请的优选实施例，并非因此限制本申请的专利范围，凡是在本申请的申请构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (18)

  1. 一种驱动电路，其中，包括：
    电位提升模块，设置为将时序控制器输出的时钟信号进行电位提升后分为两路时钟信号组，并对应输出至显示面板上的两个移位寄存器，两路所述时钟信号组分别包括多个子时钟信号；
    开关模块，串接在所述电位提升模块与显示面板两端的移位寄存器之间，设置为根据接收到的开关控制信号对应导通或者关断；
    电流检测模块，串接在所述电位提升模块与所述开关模块之间，或者串接在所述开关模块与显示面板两端的移位寄存器之间，设置为分别检测两路所述时钟信号组的每一子时钟信号的输出电流，并将多个电流信号反馈至控制模块；以及
    控制模块，设置为接收所述电流检测模块输出的多个所述电流信号，并将多个所述电流信号对应的电流值与预设电流阈值比较，当其中一路时钟信号组中的任一子时钟信号的电流值小于预设电流阈值时，输出控制信号至所述开关模块以控制所述开关模块切断该路时钟信号组的输出，并将该路时钟信号组与另一路所述时钟信号组对应叠加后输出至另一个移位寄存器。
  2. 如权利要求1所述的驱动电路，其中，所述电位提升模块的信号输入端与所述时序控制器的信号输出端连接，所述电位提升模块的信号输出端流与所述电检测模块的信号输入端连接，所述电流检测模块的信号输出端与所述开关模块的信号输入端连接，所述开关模块的第一信号输出端与所述显示面板的第一移位寄存器的信号输入端连接，所述开关模块的第二信号输出端与所述显示面板的第二移位寄存器的信号输入端连接，所述电位提升模块的受控端、所述电流检测模块的信号输出端及所述开关模块的受控端均与所述控制模块的信号端连接。
  3. 如权利要求1所述的驱动电路，其中，所述开关模块包括第一子开关模块、第二子开关模块及第三子开关模块，所述第一子开关模块的第一信号端、所述第三开关的第一信号端及所述电流检测模块的第一信号输出端互连，所述第一子开关模块的第二信号端与所述显示面板第一移位寄存器的信号端连接，所述第二子开关模块的第一信号端、所述第三子开关模块的第二信号端及所述电流检测模块的第二信号输出端互连，所述第二子开关模块的第二信号端与所述显示面板右侧移位寄存器的信号端连接，所述第一子开关模块的受控端、所述第二子开关模块的受控端及所述第三子开关模块的受控端均与所述控制模块的控制端连接。
  4. 如权利要求3所述的驱动电路，其中，所述第一子开关模块、第二子开关模块及第三子开关模块均包括多个开关电路，每一所述第一子开关模块的开关电路的第一端通过所述第三子开关模块的对应的开关电路与所述第二子开关模块对应的开关电路的第一端连接，两路包括多个子时钟信号的时钟信号组分别经所述第一开关模块的多个开关电路及所述第二开关模块的多个开关电路输出至所述显示面板上的两个移位寄存器，每一所述开关电路的受控端分别与所述控制模块的控制端连接。
  5. 如权利要求4所述的驱动电路，其中，各所述子开关模块的多个开关电路联动。
  6. 如权利要求4所述的驱动电路，其中，每一所述开关电路为金属-氧化物半导体场效应管。
  7. 如权利要求4所述的驱动电路，其中，每一所述开关电路为三极管。
  8. 如权利要求1所述的驱动电路，其中，所述电流检测模块包括多个子电流检测模块，每一所述子电流检测模块分别检测每一所述子时钟信号的电流，并将电流信号分别反馈至所述控制模块。
  9. 一种升压芯片，其中，包括所述驱动电路，所述驱动电路包括：
    电位提升模块，设置为将时序控制器输出的时钟信号进行电位提升后分为两路时钟信号组，并对应输出至显示面板上的两个移位寄存器，两路所述时钟信号组分别包括多个子时钟信号；
    开关模块，串接在所述电位提升模块与显示面板两端的移位寄存器之间，设置为根据接收到的开关控制信号对应导通或者关断；
    电流检测模块，串接在所述电位提升模块与所述开关模块之间，或者串接在所述开关模块与显示面板两端的移位寄存器之间，设置为分别检测两路所述时钟信号组的每一子时钟信号的输出电流，并将多个电流信号反馈至控制模块；以及
    控制模块，设置为接收所述电流检测模块输出的多个所述电流信号，并将多个所述电流信号对应的电流值与预设电流阈值比较，当其中一路时钟信号组中的任一子时钟信号的电流值小于预设电流阈值时，输出控制信号至所述开关模块以控制所述开关模块切断该路时钟信号组的输出，并将该路时钟信号组与另一路所述时钟信号组对应叠加后输出至另一个移位寄存器。
  10. 如权利要求9所述的升压芯片，其中，所述电位提升模块的信号输入端与所述时序控制器的信号输出端连接，所述电位提升模块的信号输出端流与所述电检测模块的信号输入端连接，所述电流检测模块的信号输出端与所述开关模块的信号输入端连接，所述开关模块的第一信号输出端与所述显示面板的第一移位寄存器的信号输入端连接，所述开关模块的第二信号输出端与所述显示面板的第二移位寄存器的信号输入端连接，所述电位提升模块的受控端、所述电流检测模块的信号输出端及所述开关模块的受控端均与所述控制模块的信号端连接。
  11. 如权利要求9所述的升压芯片，其中，所述开关模块包括第一子开关模块、第二子开关模块及第三子开关模块，所述第一子开关模块的第一信号端、所述第三开关的第一信号端及所述电流检测模块的第一信号输出端互连，所述第一子开关模块的第二信号端与所述显示面板第一移位寄存器的信号端连接，所述第二子开关模块的第一信号端、所述第三子开关模块的第二信号端及所述电流检测模块的第二信号输出端互连，所述第二子开关模块的第二信号端与所述显示面板右侧移位寄存器的信号端连接，所述第一子开关模块的受控端、所述第二子开关模块的受控端及所述第三子开关模块的受控端均与所述控制模块的控制端连接。
  12. 如权利要求9所述的升压芯片，其中，所述第一子开关模块、第二子开关模块及第三子开关模块均包括多个开关电路，每一所述第一子开关模块的开关电路的第一端通过所述第三子开关模块的对应的开关电路与所述第二子开关模块对应的开关电路的第一端连接，两路包括多个子时钟信号的时钟信号组分别经所述第一开关模块的多个开关电路及所述第二开关模块的多个开关电路输出至所述显示面板上的两个移位寄存器，每一所述开关模块的受控端分别与所述控制模块的控制端连接。
  13. 如权利要求12所述的升压芯片，各所述子开关模块的多个开关电路联动。
  14. 如权利要求12所述的升压芯片，其中，每一所述开关电路为金属-氧化物半导体场效应管。
  15. 如权利要求12所述的升压芯片，其中，每一所述开关电路为三极管。
  16. 如权利要求9所述的升压芯片，其中，所述电流检测模块包括多个子电流检测模块，每一所述子电流检测模块分别检测每一所述子时钟信号的电流，并将电流信号分别反馈至所述控制模块。
  17. 如权利要求9所述的升压芯片，其中，所述电位提升模块、所述电流检测模块、所述开关模块及所述控制模块集成在所述升压芯片上。
  18. 一种显示装置，其中，包括所述升压芯片，所述升压芯片包括所述驱动电路，所述驱动电路包括：
    电位提升模块，设置为将时序控制器输出的时钟信号进行电位提升后分为两路时钟信号组，并对应输出至显示面板上的两个移位寄存器，两路所述时钟信号组分别包括多个子时钟信号；
    开关模块，串接在所述电位提升模块与显示面板两端的移位寄存器之间，设置为根据接收到的开关控制信号对应导通或者关断；
    电流检测模块，串接在所述电位提升模块与所述开关模块之间，或者串接在所述开关模块与显示面板两端的移位寄存器之间，设置为分别检测两路所述时钟信号组的每一子时钟信号的输出电流，并将多个电流信号反馈至控制模块；以及
    控制模块，设置为接收所述电流检测模块输出的多个所述电流信号，并将多个所述电流信号对应的电流值与预设电流阈值比较，当其中一路时钟信号组中的任一子时钟信号的电流值小于预设电流阈值时，输出控制信号至所述开关模块以控制所述开关模块切断该路时钟信号组的输出，并将该路时钟信号组与另一路所述时钟信号组对应叠加后输出至另一个移位寄存器。
PCT/CN2018/113346 2018-09-21 2018-11-01 驱动电路、升压芯片及显示装置 WO2020056870A1 (zh)

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