WO2017015973A1 - 一种阵列基板、显示面板以及显示装置 - Google Patents

一种阵列基板、显示面板以及显示装置 Download PDF

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Publication number
WO2017015973A1
WO2017015973A1 PCT/CN2015/085711 CN2015085711W WO2017015973A1 WO 2017015973 A1 WO2017015973 A1 WO 2017015973A1 CN 2015085711 W CN2015085711 W CN 2015085711W WO 2017015973 A1 WO2017015973 A1 WO 2017015973A1
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WIPO (PCT)
Prior art keywords
goa
signal line
static electricity
array substrate
region
Prior art date
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PCT/CN2015/085711
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English (en)
French (fr)
Inventor
赵莽
田勇
陈彩琴
Original Assignee
深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司, 武汉华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/888,971 priority Critical patent/US10042223B2/en
Publication of WO2017015973A1 publication Critical patent/WO2017015973A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements
    • G02F2201/503—Arrangements improving the resistance to shock
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/22—Antistatic materials or arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display device.
  • Static electricity is ubiquitous in our daily lives. For electronic devices, a slight static electricity that is undetectable at a time can cause serious damage. With the development of electronic technology, the volume of electronic devices is getting smaller and smaller, and the high integration makes the unit lines in electronic devices narrower and narrower. The corresponding ability to withstand electrostatic discharge is getting worse and worse, and the electrostatic sensitivity is getting more and more. high. Therefore, the requirements for electrostatic protection during the production, testing, maintenance and use of electronic devices are getting higher and higher.
  • the invention mainly solves the problem that the electrostatic protection capability of the intermediate region of the signal line of the array substrate is weak in the prior art.
  • the present invention provides an array substrate on which a GND trace and a GOA region are disposed.
  • the GND trace is placed outside the GOA area; the GOA area is provided with a variety of GOA signal lines and N-level GOA circuits.
  • the N-level GOA circuit is electrically connected through a plurality of GOA signal lines, and an intermediate region between the first-stage GOA circuit and the N-th stage GOA circuit is provided with a first static electricity protection circuit for venting the abnormality of the GOA signal line in the middle region. Charge.
  • the first static electricity protection circuit comprises a plurality of electrostatic protection units disposed between the plurality of GOA signal lines and the GND traces.
  • a plurality of electrostatic protection units between the plurality of GOA signal lines and the GND traces are symmetrically disposed in the middle region.
  • the first static electricity protection circuit comprises a plurality of electrostatic protection units disposed between the plurality of GOA signal lines.
  • a plurality of electrostatic protection units between the plurality of GOA signal lines are symmetrically disposed in the intermediate portion.
  • a plurality of GOA signal lines include an STV signal line, a U2D signal line, a CK signal line, a VGH signal line, and a VGL signal line, and a plurality of electrostatic protection units are disposed between the STV signal line and the U2D signal line, the U2D signal line, and the CK. Between the signal lines, between the CK signal line and the VGH signal line or between the VGH signal line and the VGL signal line.
  • the upper edge region of the first stage GOA circuit and the lower edge region of the Nth stage GOA circuit are provided with a second static electricity protection circuit, the plurality of GOA signal lines including the VGH signal line and the VGL signal line; and the second static electricity protection circuit includes the upper side An electrostatic protection unit between the VGH signal line and the VGL signal line, and an electrostatic protection unit between the VGH signal line and the VGL signal line in the lower area.
  • the static electricity protection unit comprises a first diode and a second diode connected in parallel, wherein a positive pole of the first diode is electrically connected to a negative pole of the second diode, and a negative pole of the first diode is electrically connected to the second second The positive pole of the pole tube.
  • the present invention further provides a display panel, the display panel includes an array substrate, and the array substrate is provided with a GND trace and a GOA region.
  • the GND trace is placed outside the GOA area; the GOA area is provided with a variety of GOA signal lines and N-level GOA circuits.
  • the N-level GOA circuit is electrically connected through a plurality of GOA signal lines, and an intermediate region between the first-stage GOA circuit and the N-th stage GOA circuit is provided with a first static electricity protection circuit for venting the abnormality of the GOA signal line in the middle region. Charge.
  • the first static electricity protection circuit comprises a plurality of electrostatic protection units disposed between the plurality of GOA signal lines and the GND traces.
  • a plurality of electrostatic protection units between the plurality of GOA signal lines and the GND traces are symmetrically disposed in the middle region.
  • the first static electricity protection circuit comprises a plurality of electrostatic protection units disposed between the plurality of GOA signal lines.
  • a plurality of electrostatic protection units between the plurality of GOA signal lines are symmetrically disposed in the intermediate portion.
  • the upper edge region of the first stage GOA circuit and the lower edge region of the Nth stage GOA circuit are provided with a second static electricity protection circuit, the plurality of GOA signal lines including the VGH signal line and the VGL signal line; and the second static electricity protection circuit includes the upper side An electrostatic protection unit between the VGH signal line and the VGL signal line, and an electrostatic protection unit between the VGH signal line and the VGL signal line in the lower area.
  • the present invention further provides a display device, the display device comprising a display panel, the display panel comprising an array substrate, the array substrate is provided with a GND trace, and a GOA region, The GND trace is placed outside the GOA area; the GOA area is provided with a variety of GOA signal lines and N-level GOA circuits.
  • the N-level GOA circuit is electrically connected through a plurality of GOA signal lines, and an intermediate region between the first-stage GOA circuit and the N-th stage GOA circuit is provided with a first static electricity protection circuit for venting the abnormality of the GOA signal line in the middle region. Charge.
  • the first static electricity protection circuit comprises a plurality of electrostatic protection units disposed between the plurality of GOA signal lines and the GND traces.
  • a plurality of electrostatic protection units between the plurality of GOA signal lines and the GND traces are symmetrically disposed in the middle region.
  • the first static electricity protection circuit comprises a plurality of electrostatic protection units disposed between the plurality of GOA signal lines.
  • the array substrate of the present invention is provided with a GOA area and a GND trace disposed outside the GOA area; the GOA area is provided with a plurality of GOA signal lines and N stages.
  • the GOA circuit, the N-level GOA circuit is connected by a plurality of GOA signal line points, and the intermediate area between the first-stage GOA circuit and the N-th stage GOA circuit is provided with a first static electricity protection circuit for discharging
  • the abnormal charge of the GOA signal line in the middle region avoids the problem that the intermediate signal line is easily broken when the middle portion of the signal trace has a large static electricity generation, causing the entire panel to fail. It has strong electrostatic protection capability between the entire GOA signal lines.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate according to the present invention.
  • FIG. 2 is a schematic structural view of electrostatic protection of a GOA region on the array substrate shown in FIG. 1;
  • FIG. 3 is a schematic structural view of an electrostatic protection unit of a first static electricity protection circuit in the electrostatic protection of the GOA region shown in FIG. 2;
  • FIG. 4 is a schematic structural view of a second static electricity protection unit of a second static electricity protection circuit in the static electricity protection of the GOA region shown in FIG. 2;
  • FIG. 5 is a schematic structural view of an embodiment of a display panel according to the present invention.
  • FIG. 6 is a schematic structural view of an embodiment of a display device according to the present invention.
  • FIG. 1 is a schematic structural diagram of an embodiment of an array substrate according to the present invention.
  • an array of AA Active
  • Area Area
  • GOA Gate Driver On Array
  • WOA Wire On Array
  • Fanout area 14 IC (Integrated Circuit) area 15
  • FPC Flexible Printed
  • the AA area 11 is provided with a pixel electrode and a TFT for realizing pixel display.
  • the GOA area 12 is configured to generate a gate driving signal of the TFT in the AA area 11 to perform line scanning on the pixel electrode, and a GOA area 12 is respectively disposed on both sides of the AA area 11, and the scanning signal is further driven by bilateral driving. Strong.
  • the WOA region 13 is used for the connection of the traces around the array substrate 100.
  • the Fanout area 14 is used for the routing settings of the data lines of the IC area 15 and the AA area 11.
  • the IC region 15 is used for bonding of the IC, that is, the IC is connected to the array substrate 100 by a bonding process, and the circuit in the array substrate 100 is driven by the IC to drive the pixel electrode to realize display.
  • the FPC area 16 is used for bonding of the FPC, and the array substrate 100 is connected to the main board through the FPC to constitute a display panel to realize display.
  • the array substrate 100 having the six regions is a GOA technology, and the signal line of the GOA region 12 is a majority of the signal lines in the array substrate 100. Therefore, the electrostatic protection design of the array substrate 100 is mainly the signal line to the GOA region 12. Perform static electricity protection.
  • FIG. 2 is a schematic diagram of the electrostatic protection structure of the GOA area on the array substrate shown in FIG. 1.
  • FIG. 3 is an electrostatic protection unit of the first static protection circuit in the electrostatic protection of the GOA area shown in FIG.
  • FIG. 4 is a schematic structural diagram of a second static electricity protection unit of the second static electricity protection circuit in the static protection of the GOA region shown in FIG. 2; wherein the outer side of the GOA region 12 on the array substrate 100 is provided with a GND trace, and the GND trace is surrounded.
  • the array substrate 100 is used for one week as electrostatic protection of the array substrate 100.
  • a plurality of GOA signal lines and N-level GOA circuits are arranged, and the N-level GOA circuit is electrically connected by a plurality of GOA signal lines to realize series connection, that is, signals of the entire GOA circuit are transmitted in one level and one level,
  • the signal of the next stage GOA circuit is provided by the upper level GOA circuit through a plurality of GOA signal lines connecting the two.
  • the GOA circuit provides a row scan signal for the pixel electrode, in general, how many rows of pixel electrodes are in the AA region 11, how many levels of GOA circuits are there in the GOA region. As the requirements for the definition of the display panel are increasing, the number of pixel electrodes is also increased accordingly, and a multi-level GOA circuit is disposed on the array substrate 100 accordingly.
  • N takes a value of 1920, and it is easy to think that in other embodiments, the setting of the N value can be performed according to requirements.
  • the GOA signal lines between the GOA circuits will also be denser. Therefore, it is necessary to focus on protecting the static electricity between the GOA signal lines on the array substrate 100.
  • the GOA signal line in this embodiment includes an STV signal line, a U2D signal line, a CK signal line, a VGH signal line, and a VGL signal line.
  • the STV signal line is the starting signal line of the GOA circuit
  • the U2D signal line is used for the positive scanning control of the GOA circuit
  • the CK signal line is the clock signal line for the generation and control of the gate shift signal
  • the VGH signal line is The high voltage source signal line
  • the VGL signal line is a low voltage source signal line
  • the VGH signal line and the VGL signal line provide electric power for the GOA circuit.
  • the frequency of each signal line in the GOA signal line is different.
  • the VGH signal line and the VGL signal line are used to provide electric driving, and the frequency of use is higher than other signal lines, so the VGH signal line and the VGL signal line are also relative to other signals.
  • the line is thicker.
  • the GOA area 12 is divided into three areas for electrostatic protection setting according to the difference of the signal line routing settings.
  • the three areas are: an upper area 121 above the first stage GOA circuit, an intermediate area 122 between the first stage GOA circuit and the Nth stage GOA circuit, and a lower area 123 below the Nth stage GOA circuit.
  • the GOA signal lines are not overlapped and arranged in parallel with each other.
  • a large current is easily generated between the GOA signal lines, causing the signal lines to be blown; in the upper region 121 and the lower region.
  • VGH signal line and VGL signal line overlap with other signal lines. Under this structure, it is easy to generate a large current at the overlap, which causes the signal line to be blown.
  • the first static electricity protection circuit 124 is disposed in the intermediate portion 122 for discharging the abnormal electric charge generated by the GOA signal line in the intermediate portion 122; and the second static electricity protection circuit 125 is disposed on the upper side region 121 and the lower side region 123, respectively.
  • the abnormal charge generated in the upper region 121 and the lower region 123 of the GOA signal line is discharged.
  • the first static electricity protection circuit 124 includes a plurality of static electricity protection units 1241 between the GOA signal lines and the GND traces, and a plurality of static electricity protection units 1241 between the plurality of GOA signal lines.
  • the plurality of static electricity protection units 1241 between the GOA signal line and the GND signal line are symmetrically disposed in the intermediate portion 122.
  • N is an even number 2n
  • an electrostatic protection unit 1241 is disposed between the N/2th stage, that is, the nth stage GOA circuit and the n+1th stage GOA circuit in the middle of the intermediate area, and then the nth stage GOA is respectively performed according to the principle.
  • the upper side of the circuit and the lower side of the n+1th stage GOA circuit are symmetrically disposed again with the electrostatic protection unit 1241;
  • the electrostatic protection unit 1241 is symmetrically disposed on the upper and lower sides of the n+1th stage GOA circuit, for example, between the nth stage GOA circuit and the n+1th stage GOA circuit, and the nth An electrostatic protection unit 1241 is disposed between the +1 level GOA circuit and the n+2 level GOA circuit.
  • a plurality of ESD units 1241 between the GOA signal lines are also symmetrically disposed within the intermediate region 122.
  • This symmetrical arrangement allows the ESD protection unit 1241 to be more evenly distributed in the intermediate region 122, enabling the use of a minimum of ESD protection unit 1241 for the best ESD protection.
  • the electrostatic protection unit 1241 can also be disposed according to other arrangements.
  • the GOA signal line includes an STV signal line, a U2D signal line, a CK signal line, a VGH signal line, and a VGL signal line. Therefore, the plurality of static electricity protection units 1241 are disposed between the STV signal line and the U2D signal line, and the U2D signal line. Between the CK signal line, the CK signal line and the VGH signal line, or between the VGH signal line and the VGL signal line.
  • the electrostatic protection unit 1241 is disposed between all the GOA signal lines to achieve the discharge of abnormal charges on the respective GOA signal lines.
  • a part of the GOA signal line can also be selected to set the electrostatic protection unit 1241.
  • the static electricity protection unit 1241 includes a first diode 1242 and a second diode 1243 in parallel.
  • the two diodes are of the same type, wherein the anode of the first diode 1242 is electrically connected to the cathode of the second diode 1243.
  • the cathode of the first diode 1242 is electrically connected to the anode of the second diode 1243.
  • the static electricity protection unit 1241 is connected between the two GOA signal lines, and the electrostatic charge is accumulated on the GOA signal line, and the first diode 1242 or the second diode 1243 can be passed to the other.
  • the GOA signal line is vented.
  • the ESD protection unit between the GOA signal lines has no effect on the relatively weak normal operation signal, and only when the electrostatic charge accumulates to a certain extent, it passes through the diode. Release.
  • the electrostatic protection unit 1241 functions like a large resistance in the circuit, and does not affect the operation of the normal signal while discharging the charge. Therefore, the above diode can also be replaced by a triode.
  • a TFT transistor is selected. When an N-type TFT transistor is selected, the drain and the gate are connected to the anode of the diode, and the source is equivalent to the cathode of the diode; when the P-type TFT is selected In the case of a transistor, the source corresponds to the anode of the diode, and the drain and gate are connected to the cathode of the diode.
  • the first static electricity protection unit 1251 is the same as the plurality of static electricity protection units 1241 in the first static electricity protection circuit 124 Electrostatic discharge between the VGH signal line and the VGL signal line arranged in parallel by two diodes connected in parallel.
  • the second static electricity protection circuit 125 further includes a second static electricity protection unit 1252 between the other GOA signal lines and the VGH signal lines and the VGL signal lines, and the second static electricity protection unit 1252 also includes two diodes of the same type, that is, the third Diode 1253 and fourth diode 1254.
  • the second static electricity protection unit 1252 between the STV signal line, the VGH signal line and the VGL signal line as an example, wherein the anode of the third diode 1253 is connected to the VGL signal line, the cathode is connected to the STV signal line, and the fourth diode 1254 is connected.
  • the positive pole is connected to the STV signal line; the negative pole is connected to the VGH signal line.
  • the other GOA signal lines are provided with the same electrostatic protection between the VGH signal line and the VGL signal line, and the diode can also be replaced by a triode.
  • the intermediate region between the first-stage GOA circuit and the N-th stage GOA circuit of the GOA region in the array substrate of the present embodiment is provided with a first static electricity protection circuit capable of discharging an abnormal charge between the GOA signal lines.
  • the electrostatic protection capability of the middle portion of the entire array substrate is improved, and when the static electricity is generated in the middle portion of the signal trace, the intermediate signal line is easily broken, causing the entire panel to fail.
  • an electrostatic protection unit is also disposed between the upper region of the first-stage GOA circuit and the VGH signal line and the VGL signal line of the lower region of the N-th stage GOA circuit, further making the voltage source signal line, that is, the VGH signal line and the VGL signal.
  • the electrostatic protection capability between the lines has also been improved.
  • FIG. 5 is a schematic structural view of an embodiment of a display panel according to the present invention.
  • the display panel 300 includes an array substrate 31, a backlight module 32, a liquid crystal layer 33, and a color filter 34.
  • the array substrate 31 includes a GOA area,
  • the intermediate region between the first-stage GOA circuit and the N-th stage GOA circuit in the GOA region is provided with a first static electricity protection circuit capable of discharging an abnormal charge of the GOA signal line in the intermediate region, which is similar to the array substrate 100 of the above embodiment. , the details will not be described again.
  • the backlight module 32 in the display panel 300 is located at the bottom layer, and the other array substrate 31, liquid crystal layer 33, and color filter 34 are sequentially stacked upward.
  • FIG. 6 is a schematic structural diagram of an embodiment of a display device according to the present invention.
  • the display device 400 may be a device such as a mobile phone, a tablet computer, a television, a computer, or the like provided with an LCD or an OLED.
  • the display device 400 includes a display panel 41 and a frame 42 that supports and protects the display panel 41.
  • the display panel 41 is similar to the embodiment display panel 300, and details are not described herein.
  • the array substrate in the present invention is provided with a GOA region and a GND trace disposed outside the GOA region; the GOA region is provided with a plurality of GOA signal lines and an N-level GOA circuit, and the N-level GOA circuit
  • the first area between the first stage GOA circuit and the Nth stage GOA circuit is electrically connected by a plurality of GOA signal lines, and the first static protection circuit is configured to bleed the GOA signal line in the middle area.
  • the abnormal charge avoids the problem that when the middle of the signal trace has a large static electricity, the intermediate signal line is easy to blow, causing the entire panel to fail, so that the entire GOA signal line has strong electrostatic protection capability.

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Abstract

一种阵列基板（31，100）、显示面板（41，300）以及显示装置（400），其中阵列基板（31，100）上设置有GND走线以及GOA区域（12），GND走线设置在GOA区域（12）的外侧；GOA区域（12）中设置有多种GOA信号线和N级GOA电路，N级GOA电路通过多种GOA信号线电连接，且第1级GOA电路与第N级GOA电路之间的中间区域（122）设置有第一静电防护电路（124），用于泄放GOA信号线在所述中间区域（122）的异常电荷。该阵列基板（31，100）中GOA信号线之间具备较强的静电防护能力。

Description

一种阵列基板、显示面板以及显示装置
【技术领域】
本发明涉及显示技术领域，特别是涉及一种阵列基板、显示面板以及显示装置。
【背景技术】
静电在我们日常生活中无处不见，对于电子器件来说，一次无法察觉的轻微静电就可能对其造成严重伤害。随着电子技术的发展，电子器件的体积越做越小，高的集成度使得电子器件中单元线路越来越窄，相应的耐受静电放电的能力越来越差，静电敏感度越来越高。因此对于电子器件在生产、测试、维修、使用过程中的静电防护要求越来越高。
随着显示技术的发展，很多人投入到SOP（System On Panel）面板系统化的研究中，而面板中集成电路的静电防护也成为了研究重点，特别是对于采用GOA（Gate Driver On Array）技术的阵列基板，其中信号走线中间区域的静电防护容易被忽略，然而在生产测试过程中，中间区域反而容易产生静电，因此当出现较大静电时，中间区域的信号线容易被烧断，继而造成整个面板的失效。
【发明内容】
本发明主要解决现有技术中阵列基板信号走线的中间区域静电防护能力较弱的问题。
为解决上述技术问题，本发明提出一种阵列基板，该阵列基板上设置有GND走线、以及GOA区域， GND走线设置在GOA区域的外侧；GOA区域中设置有多种GOA信号线和N级GOA电路， N级GOA电路通过多种GOA信号线电连接，且第1级GOA电路与第N级GOA电路之间的中间区域设置有第一静电防护电路，用于泄放GOA信号线在中间区域的异常电荷。
其中，第一静电防护电路包括设置在多种GOA信号线和GND走线之间的多个静电防护单元。
其中，多种GOA信号线和GND走线之间的多个静电防护单元在中间区域对称设置。
其中，第一静电防护电路包括设置在多种GOA信号线之间多个静电防护单元。
其中，多种GOA信号线之间的多个静电防护单元在中间区域对称设置。
其中，多种GOA信号线包括STV信号线、U2D信号线、CK信号线、VGH信号线以及VGL信号线，多个静电防护单元设置在STV信号线和U2D信号线之间、U2D信号线和CK信号线之间，CK信号线和VGH信号线之间或VGH信号线和VGL信号线之间。
其中，第一级GOA电路的上边区域和第N级GOA电路的下边区域设置有第二静电防护电路，多种GOA信号线包括VGH信号线和VGL信号线；第二静电防护电路包括设置在上边区域VGH信号线和VGL信号线之间的静电防护单元，以及下边区域的VGH信号线和VGL信号线之间的静电防护单元。
其中，静电防护单元包括并联的第一二极管和第二二极管，其中第一二极管的正极电连接第二二极管的负极，第一二极管的负极电连接第二二极管的正极。
为解决上述技术问题，本发明又提供一种显示面板，该显示面板包括阵列基板，该阵列基板上设置有GND走线、以及GOA区域， GND走线设置在GOA区域的外侧；GOA区域中设置有多种GOA信号线和N级GOA电路， N级GOA电路通过多种GOA信号线电连接，且第1级GOA电路与第N级GOA电路之间的中间区域设置有第一静电防护电路，用于泄放GOA信号线在中间区域的异常电荷。
其中，第一静电防护电路包括设置在多种GOA信号线和GND走线之间的多个静电防护单元。
其中，多种GOA信号线和GND走线之间的多个静电防护单元在中间区域对称设置。
其中，第一静电防护电路包括设置在多种GOA信号线之间多个静电防护单元。
其中，多种GOA信号线之间的多个静电防护单元在中间区域对称设置。
其中，第一级GOA电路的上边区域和第N级GOA电路的下边区域设置有第二静电防护电路，多种GOA信号线包括VGH信号线和VGL信号线；第二静电防护电路包括设置在上边区域VGH信号线和VGL信号线之间的静电防护单元，以及下边区域的VGH信号线和VGL信号线之间的静电防护单元。
为解决上述技术问题，本发明还提供一种显示装置，该显示装置包括显示面板，该显示面板包括阵列基板，该阵列基板上设置有GND走线、以及GOA区域， GND走线设置在GOA区域的外侧；GOA区域中设置有多种GOA信号线和N级GOA电路， N级GOA电路通过多种GOA信号线电连接，且第1级GOA电路与第N级GOA电路之间的中间区域设置有第一静电防护电路，用于泄放GOA信号线在中间区域的异常电荷。
其中，第一静电防护电路包括设置在多种GOA信号线和GND走线之间的多个静电防护单元。
其中，多种GOA信号线和GND走线之间的多个静电防护单元在中间区域对称设置。
其中，第一静电防护电路包括设置在多种GOA信号线之间多个静电防护单元。
本发明的有益效果是，区别于现有技术，本发明中的阵列基板上设置有GOA区域，以及设置在GOA区域外侧的GND走线；该GOA区域中设置有多种GOA信号线和N级GOA电路，N级GOA电路通过多种GOA信号线点连接，第1级GOA电路和第N级GOA电路之间的中间区域设置有第一静电防护电路，该第一静电防护电路用于泄放GOA信号线在中间区域的异常电荷，避免了当信号走线中间区域有较大的静电产生时，中间信号线易炸断，造成整个面板失效的问题。使得整个GOA信号线之间具备较强的静电防护能力。
【附图说明】
图1是本发明一种阵列基板一实施例的结构示意图；
图2是图1所示阵列基板上GOA区域静电防护的结构示意图；
图3是图2所示GOA区域静电防护中第一静电防护电路的静电防护单元的结构示意图；
图4是图2所示GOA区域静电防护中第二静电防护电路的第二静电防护单元的结构示意图；
图5是本发明一种显示面板一实施例的结构示意图；
图6是本发明一种显示装置一实施例的结构示意图。
【具体实施方式】
参阅图1，图1是本发明一种阵列基板一实施例的结构示意图，本实施例中阵列基板100上设置有AA（Active Area）区域11、GOA（Gate Driver On Array）区域12、WOA（Wire On Array）区域13、Fanout区域14、IC（Integrated Circuit）区域15以及FPC（Flexible Printed Circuit）区域16。
其中AA区域11上设置有像素电极以及TFT，用于实现像素显示。
GOA区域12，用于产生AA区域11内TFT的栅极驱动信号，以对像素电极进行行扫描，并且在AA区域11的两侧分别设置有一GOA区域12，采用双边驱动的方式使得扫描信号更为强烈。
WOA区域13用于阵列基板100周围走线的连接。
Fanout区域14用于IC区域15和AA区域11数据线的走线设置。
IC区域15用于IC的bonding，即通过bonding工艺将IC连接在阵列基板100上，并通过IC来驱动阵列基板100内的电路继而驱动像素电极以实现显示。
FPC区域16用于FPC的bonding，阵列基板100通过FPC连接到主板，以构成显示面板，实现显示。
上述具有6个区域的阵列基板100是采用GOA技术的，GOA区域12的信号线为阵列基板100中的信号线的大部分，因此阵列基板100的静电防护设计主要是对GOA区域12的信号线进行静电防护。
请参阅图2、图3及图4，图2是图1所示阵列基板上GOA区域静电防护结构示意图；图3是图2所示GOA区域静电防护中第一静电防护电路的静电防护单元的结构示意图；图4是图2所示GOA区域静电防护中第二静电防护电路的第二静电防护单元的结构示意图；其中阵列基板100上的GOA区域12外侧设置有GND走线，GND走线环绕阵列基板100一周，用作阵列基板100的静电防护。
而在GOA区域12，设置有多种GOA信号线和N级GOA电路，N级GOA电路由多种GOA信号线电连接，实现串联，即整个GOA电路的信号是一级一级传输下来的，下一级GOA电路的信号由上一级GOA电路通过连接两者的多种GOA信号线提供。
由于GOA电路提供了像素电极的行扫描信号，因此一般来说，AA区域11中有多少行像素电极，则在GOA区域中相应的有多少级GOA电路。随着显示面板清晰度的要求日益提高，像素电极数量的设置也相应增多，相应的在阵列基板100上设置有多级GOA电路。在本实施例中，N取值1920，容易想到，在其他实施例中可根据需求进行N值的设置。
当阵列基板100上设置较多级GOA电路时，GOA电路间的GOA信号线也将更为密集，因此需要重点对阵列基板100上的GOA信号线之间的静电进行防护。
本实施例中GOA信号线包括STV信号线、U2D信号线、CK信号线、VGH信号线以及VGL信号线。其中，STV信号线为GOA电路的起始信号线，U2D信号线用于GOA电路的正扫描控制，CK信号线为时钟信号线，用作栅极移位信号的产生和控制，VGH信号线为高电压源信号线，VGL信号线为低电压源信号线，VGH信号线与VGL信号线为GOA电路提供电力驱动。
为方便后续静电防护电路的描述，以上仅仅介绍了几个最基本的GOA信号线，在实际应用中，通常还设置有其他信号线，例如D2U信号线、CK1信号线、CK2信号线等，可根据具体的使用情况进行不同的设置。
并且GOA信号线中的各个信号线使用频率不一样，例如VGH信号线和VGL信号线用于提供电力驱动，其使用频率较其他信号线更高，因此VGH信号线和VGL信号线也相对其他信号线更粗。
在本实施例中，根据信号线走线设置的不同，将GOA区域12划分为三个区域进行静电防护设置。三个区域分别为：第1级GOA电路上方的上边区域121、第1级GOA电路和第N级GOA电路之间的中间区域122、第N级GOA电路下方的下边区域123。
在中间区域122，GOA信号线之间没有交叠，相互平行设置，静电累积到一定程度时，容易在GOA信号线之间产生大电流，导致信号线的烧断；在上边区域121和下边区域123，VGH信号线和VGL信号线与其他信号线交叠设置，这种结构下，则是交叠处容易产生大电流，而导致信号线的烧断。
因此在中间区域122设置有第一静电防护电路124，用于泄放GOA信号线在中间区域122产生的异常电荷；而在上边区域121和下边区域123分别设置有第二静电防护电路125，用于泄放GOA信号线在上边区域121和下边区域123产生的异常电荷。
该第一静电防护电路124中包括GOA信号线和GND走线之间的多个静电防护单元1241，以及多种GOA信号线之间的多个静电防护单元1241。
其中，GOA信号线和GND信号线之间的多个静电防护单元1241在中间区域122对称设置。当N为偶数2n时，则在中间区域中间的第N/2级即第n级GOA电路和第n+1级GOA电路之间设置静电防护单元1241，然后依此原理分别在第n级GOA电路的上侧和第n+1级GOA电路的下侧再次对称设置静电防护单元1241；
当N为基数2n+1时，则在第n+1级GOA电路的上下两侧对称设置静电防护单元1241，例如在第n级GOA电路和第n+1级GOA电路之间、以及第n+1级GOA电路和第n+2级GOA电路之间设置静电防护单元1241。
同样的，GOA信号线之间的多个静电防护单元1241也在中间区域122内对称设置。这种对称设置的方式使得静电防护单元1241在中间区域122分布更为均匀，能够使用最少的静电防护单元1241，而达到最好的静电防护效果。在其他实施例中，也可根据其他的布置规律设置静电防护单元1241。
本实施例中GOA信号线包括STV信号线、U2D信号线、CK信号线、VGH信号线以及VGL信号线，因此多个静电防护单元1241设置在STV信号线与U2D信号线之间、U2D信号线与CK信号线之间、CK信号线与VGH信号线之间或者VGH信号线与VGL信号线之间。
本实施例中上述所有的GOA信号线之间均设置有静电防护单元1241，以实现各个GOA信号线上异常电荷的泄放。为节约材料，并简化GOA区域静电防护电路的复杂度，也可选择部分GOA信号线来设置静电防护单元1241。
具体来说，该静电防护单元1241包括并联的第一二极1242管和第二二极管1243，两二极管类型相同，其中第一二极管1242的正极电连接第二二极管1243的负极，第一二极管1242的负极电连接第二二极管1243的正极。然后再将该静电防护单元1241连接在两GOA信号线之间，无论在那根GOA信号线上积累了静电电荷，都可通过第一二极管1242或第二二极管1243向另一根GOA信号线泄放。
由于二极管在一定的电压条件下才能导通，因此GOA信号线之间的静电防护单元对于相对较弱的正常工作信号并没有影响，并且只有当静电电荷积累到一定程度后，才会通过二极管进行泄放。
基于此原理，静电防护单元1241的作用类似于电路中的大电阻，在对电荷实现泄放的同时，不会影响到正常信号的工作。因此上述二极管也可由三极管代替，本实施例中选择TFT晶体管，当选择N型TFT晶体管时，其中漏极和栅极相连相当于二极管的正极，源极相当于二极管的负极；当选择P型TFT晶体管时，其中源极相当于二极管的正极，漏极和栅极相连相当于二极管的负极。
对于第二静电防护电路125，其包括VGH信号线和VGL信号线之间的第一静电防护单元1251，该第一静电防护单元1251与第一静电防护电路124中的多个静电防护单元1241相同；通过并联的两个二极管实现平行设置的VGH信号线和VGL信号线之间的静电泄放。
第二静电防护电路125中还包括其他GOA信号线与VGH信号线以及VGL信号线之间的第二静电防护单元1252，该第二静电防护单元1252也包括两个类型相同的二极管，即第三二极管1253和第四二极管1254。以STV信号线、VGH信号线以及VGL信号线之间的第二静电防护单元1252为例，其中第三二极管1253的正极连接VGL信号线，负极连接STV信号线；第四二极管1254的正极连接STV信号线；负极连接VGH信号线。其他GOA信号线与VGH信号线、VGL信号线之间作相同静电防护设置，且该二极管也可用三极管代替。
由以上描述可知，本实施例阵列基板中GOA区域的第1级GOA电路和第N级GOA电路之间的中间区域设置有第一静电防护电路，能够泄放GOA信号线之间的异常电荷，提高了整个阵列基板中间区域的静电防护能力，避免了当信号走线中间区域有较大的静电产生时，中间信号线易炸断，造成整个面板失效的问题。并且，在第1级GOA电路的上边区域和第N级GOA电路的下边区域的VGH信号线和VGL信号线之间也设置了静电防护单元，进一步使得电压源信号线即VGH信号线和VGL信号线之间的静电防护能力也得到提升。
请参阅图5，图5是本发明一种显示面板一实施例的结构示意图。显示面板300包括阵列基板31、背光模组32、液晶层33以及彩色滤光片34。
阵列基板31其包括GOA区域， GOA区域中的第1级GOA电路和第N级GOA电路之间的中间区域设置有第一静电防护电路，能够泄放GOA信号线在中间区域的异常电荷，其类似于上述实施例阵列基板100，具体不再赘述。
显示面板300中的背光模块32位于最底层，其他的阵列基板31、液晶层33、彩色滤光片34依次向上叠置。
请参考图6，图6是本发明一种显示装置一实施例的结构示意图。显示装置400可以是手机、平板电脑、电视、电脑等设置有LCD或OLED的装置。该显示装置400包括显示面板41以及支持及保护显示面板41的框架42。
显示面板41类似于实施例显示面板300，具体不在赘述。
区别于现有技术，本发明中的阵列基板上设置有GOA区域，以及设置在GOA区域外侧的GND走线；该GOA区域中设置有多种GOA信号线和N级GOA电路，N级GOA电路通过多种GOA信号线电连接，第1级GOA电路和第N级GOA电路之间的中间区域设置有第一静电防护电路，该第一静电防护电路用于泄放GOA信号线在中间区域的异常电荷，避免了当信号走线中间区域有较大的静电产生时，中间信号线易炸断，造成整个面板失效的问题，使得整个GOA信号线之间具备较强的静电防护能力。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板上设置有GND走线以及GOA区域，所述GND走线设置在所述GOA区域的外侧；所述GOA区域中设置有多种GOA信号线和N级GOA电路，所述N级GOA电路通过所述多种GOA信号线电连接，且第1级GOA电路与第N级GOA电路之间的中间区域设置有第一静电防护电路，用于泄放所述GOA信号线在所述中间区域的异常电荷。
  2. 根据权利要求1所述的阵列基板，其中，所述第一静电防护电路包括设置在所述多种GOA信号线和所述GND走线之间的多个静电防护单元。
  3. 根据权利要求2所述的阵列基板，其中，所述多种GOA信号线和所述GND走线之间的所述多个静电防护单元在所述中间区域对称设置。
  4. 根据权利要求1所述的阵列基板，其中，所述第一静电防护电路包括设置在所述多种GOA信号线之间多个静电防护单元。
  5. 根据权利要求4所述的阵列基板，其中，所述多种GOA信号线之间的所述多个静电防护单元在所述中间区域对称设置。
  6. 根据权利要求4所述的阵列基板，其中，所述多种GOA信号线包括STV信号线、U2D信号线、CK信号线、VGH信号线以及VGL信号线，所述多个静电防护单元设置在所述STV信号线和所述U2D信号线之间、所述U2D信号线和所述CK信号线之间、所述CK信号线和所述VGH信号线之间或所述VGH信号线和所述VGL信号线之间。
  7. 根据权利要求1所述的阵列基板，其中，所述第一级GOA电路的上边区域和所述第N级GOA电路的下边区域设置有第二静电防护电路，所述多种GOA信号线包括VGH信号线和VGL信号线；所述第二静电防护电路包括设置在所述上边区域的所述VGH信号线和所述VGL信号线之间的静电防护单元，以及所述下边区域的所述VGH信号线和所述VGL信号线之间的静电防护单元。
  8. 根据权利要求2所述的阵列基板，其中，所述静电防护单元包括并联的第一二极管和第二二极管，其中所述第一二极管的正极电连接所述第二二极管的负极，所述第一二极管的负极电连接所述第二二极管的正极。
  9. 根据权利要求4所述的阵列基板，其中，所述静电防护单元包括并联的第一二极管和第二二极管，其中所述第一二极管的正极电连接所述第二二极管的负极，所述第一二极管的负极电连接所述第二二极管的正极。
  10. 根据权利要求7所述的阵列基板，其中，所述静电防护单元包括并联的第一二极管和第二二极管，其中所述第一二极管的正极电连接所述第二二极管的负极，所述第一二极管的负极电连接所述第二二极管的正极。
  11. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板上设置有GND走线以及GOA区域，所述GND走线设置在所述GOA区域的外侧；所述GOA区域中设置有多种GOA信号线和N级GOA电路，所述N级GOA电路通过所述多种GOA信号线电连接，且第1级GOA电路与第N级GOA电路之间的中间区域设置有第一静电防护电路，用于泄放所述GOA信号线在所述中间区域的异常电荷。
  12. 根据权利要求11所述的显示面板，其中，所述第一静电防护电路包括设置在所述多种GOA信号线和所述GND走线之间的多个静电防护单元。
  13. 根据权利要求12所述的显示面板，其中，所述多种GOA信号线和所述GND走线之间的所述多个静电防护单元在所述中间区域对称设置。
  14. 根据权利要求11所述的显示面板，其中，所述第一静电防护电路包括设置在所述多种GOA信号线之间多个静电防护单元。
  15. 根据权利要求14所述的显示面板，其中，所述多种GOA信号线之间的所述多个静电防护单元在所述中间区域对称设置。
  16. 根据权利要求11所述的显示面板，其中，所述第一级GOA电路的上边区域和所述第N级GOA电路的下边区域设置有第二静电防护电路，所述多种GOA信号线包括VGH信号线和VGL信号线；所述第二静电防护电路包括设置在所述上边区域的所述VGH信号线和所述VGL信号线之间的静电防护单元，以及所述下边区域的所述VGH信号线和所述VGL信号线之间的静电防护单元。
  17. 一种显示装置，其中，所述显示装置包括显示面板，所述显示面板包括阵列基板，所述阵列基板上设置有GND走线以及GOA区域，所述GND走线设置在所述GOA区域的外侧；所述GOA区域中设置有多种GOA信号线和N级GOA电路，所述N级GOA电路通过所述多种GOA信号线电连接，且第1级GOA电路与第N级GOA电路之间的中间区域设置有第一静电防护电路，用于泄放所述GOA信号线在所述中间区域的异常电荷。
  18. 根据权利要求17所述的显示装置，其中，所述第一静电防护电路包括设置在所述多种GOA信号线和所述GND走线之间的多个静电防护单元。
  19. 根据权利要求18所述的显示装置，其中，所述多种GOA信号线和所述GND走线之间的所述多个静电防护单元在所述中间区域对称设置。
  20. 根据权利要求17所述的显示装置，其中，所述第一静电防护电路包括设置在所述多种GOA信号线之间多个静电防护单元。
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