WO2020134947A1 - 显示模组及显示装置 - Google Patents

显示模组及显示装置 Download PDF

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Publication number
WO2020134947A1
WO2020134947A1 PCT/CN2019/123368 CN2019123368W WO2020134947A1 WO 2020134947 A1 WO2020134947 A1 WO 2020134947A1 CN 2019123368 W CN2019123368 W CN 2019123368W WO 2020134947 A1 WO2020134947 A1 WO 2020134947A1
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WO
WIPO (PCT)
Prior art keywords
array substrate
row drive
drive circuit
substrate row
circuit
Prior art date
Application number
PCT/CN2019/123368
Other languages
English (en)
French (fr)
Inventor
纪飞林
Original Assignee
惠科股份有限公司
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Filing date
Publication date
Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Publication of WO2020134947A1 publication Critical patent/WO2020134947A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • This application relates to the technical field of electronic circuits, in particular to a display module and a display device.
  • Array substrate row driver circuit (Gate Driver on Array, GOA) because it directly makes the gate driver circuit (Gate driver IC) on the array device (Array) substrate of the display device, instead of a driver chip made of external silicon chip kindss of technology.
  • the application of this technology can reduce production process procedures and reduce product process costs, so more and more applications are in display devices.
  • a display panel damaged by a row drive circuit circuit of the single-sided array substrate caused by static electricity damage or other manufacturing factors.
  • Such a display panel is usually only scrapped, resulting in a high defect rate of the display panel.
  • the main purpose of this application is to propose a display module and a display device.
  • the present application proposes a display module, the display module includes:
  • the control chip has a first control signal output terminal and a second control signal output terminal;
  • a display panel the display panel having oppositely disposed sides, the display panel including a pixel array
  • the first array substrate row drive circuit and the second array substrate row drive circuit are separately arranged on both sides of the display panel; both the first array substrate row drive circuit and the second array substrate row drive circuit have an enabling end , The enable end of the first array substrate row drive circuit and the enable end of the second array substrate row drive circuit are in one-to-one correspondence with the first control signal output terminal and the second control signal output terminal;
  • the first array substrate row drive circuit and/or the second array substrate row drive circuit are configured to drive the pixel array to work when receiving a control signal output by the control chip.
  • the present application also proposes a display module.
  • the display module includes:
  • the control chip has a first control signal output terminal and a second control signal output terminal;
  • a display panel the display panel having oppositely disposed sides, the display panel including a pixel array
  • the first array substrate row drive circuit and the second array substrate row drive circuit are separately arranged on both sides of the display panel; both the first array substrate row drive circuit and the second array substrate row drive circuit have an enabling end , The enable end of the first array substrate row drive circuit and the enable end of the second array substrate row drive circuit are in one-to-one correspondence with the first control signal output terminal and the second control signal output terminal;
  • the first array substrate row drive circuit includes a plurality of cascaded first array substrate row drive unit circuits
  • the second array substrate row drive circuit includes a plurality of cascaded second array substrate row drive unit circuits
  • Each of the first array substrate row drive unit circuits is configured to output a first scan signal step by step when receiving the control signal output by the control chip to control the corresponding pixel array to be turned on;
  • Each row drive unit circuit of the second array substrate is configured to output a second scan signal step by step when receiving the control signal output by the control chip to control the corresponding pixel array to be turned on.
  • the present application also proposes a display device including the display module described above; the display module includes: a control chip having a first control signal output terminal and a second control signal output terminal;
  • the display module of the present application divides the first array substrate row drive circuit and the second array substrate row drive circuit on both sides of the display panel, and controls the chip according to the detected first array substrate row drive circuit and the second array substrate row Whether the drive circuit is good or not, so that different control signals are output to the enable terminals of the first array substrate row drive circuit and the second array substrate row drive circuit to control the operation of the first array substrate row drive circuit, and the second array substrate row drive
  • the circuit does not work, or the first array substrate row drive circuit does not work, the second array substrate row drive circuit works, or both the first array substrate row drive circuit and the second array substrate row drive circuit work simultaneously.
  • This application can be controlled independently The working state of the array substrate row drive circuit (the first array substrate row drive circuit and the second array substrate row drive circuit) on the left and right sides, so that the display panel unilateral array substrate row drive circuit and the bilateral array substrate row drive circuit Drive can be realized.
  • This application realizes that when the array substrate row drive circuit is damaged on one side, the other side of the array substrate row drive circuit is used to drive the pixel array of the entire panel, which improves the yield of the display panel and solves the array substrate on one side
  • the row driving circuit cannot work normally, which results in the entire display panel being scrapped only, making the entire display panel unusable, and increasing the problem of the defective rate of the display panel.
  • FIG. 1 is a schematic diagram of a circuit structure of an embodiment of a display module of this application.
  • FIG. 2 is a schematic structural diagram of an embodiment of a display module of this application.
  • FIG. 3 is a schematic structural view of an embodiment of the display panel in FIG. 1;
  • FIG. 4 is a schematic diagram of a circuit structure of an embodiment of the first array substrate row drive circuit in FIG. 1;
  • FIG. 5 is a schematic diagram of a circuit structure of an embodiment of the second array substrate row drive circuit in FIG. 1;
  • FIG. 6 is a schematic diagram of a circuit structure in which the first array substrate row drive circuit and the second array substrate row drive circuit adopt a 4T1C type array substrate row drive circuit drive circuit structure.
  • the present application proposes a display module, which is suitable for a display device with a display panel, such as a computer, mobile phone, projector, or television.
  • the display module includes:
  • the control chip 10 has a first control signal output terminal and a second control signal output terminal;
  • a first array substrate row drive circuit (Gate Driver Array, GPA) circuit and a second array substrate row drive circuit 40 are provided on both sides of the display panel 20; the first array substrate row drive circuit 30 and the The second array substrate row drive circuit 40 each has an enable terminal, the enable terminal of the first array substrate row drive circuit 30 and the enable terminal of the second array substrate row drive circuit 40 and the first control signal
  • the output terminal and the second control signal output terminal are connected in a one-to-one correspondence; the first array substrate row drive circuit 30 and/or the second array substrate row drive circuit 40 are configured to receive the output of the control chip 10 When the signal is controlled, the pixel array 24 is driven to work.
  • the display panel 20 may be an OLED (Organic Light-Emitting Diode) display panel 20 or a TFT-LCD (Thin Film Transistor Liquid Crystal Display) display panel 20.
  • the display panel 20 is divided into a gate driver design (gate driver design), which can be divided into two types: SOC (System on chip) and array substrate row driver circuit (Gate driver on array). Species.
  • the array substrate row drive circuit is a process technology in which the gate driver circuit (Gate driver IC) is directly fabricated on the array substrate of the display device instead of the driver chip made of an external silicon chip. The application of this technology can reduce production process procedures, reduce product process costs, and can improve the integration of the display panel 20.
  • the array substrate row drive circuit type display panel 20 Compared with the SOC type display panel 20, the array substrate row drive circuit type display panel 20 has a narrower border. With the advancement of science and technology and people's higher requirements for visual effects, the narrow border of the display panel 20 is the mainstream trend in the future. Therefore, the array substrate row drive circuit type display panel 20 is a more important application than the SOC type display panel 20.
  • LC Liquid Crystal, Liquid Crystal
  • the liquid crystal is a polymer material, because Its special physical, chemical and optical characteristics are widely used in thin and light display technology.
  • the pixel array 24 of the display panel 20 is composed of a plurality of sub-pixels, and three sub-pixels (red, green, and blue) constitute one pixel.
  • three sub-pixels red, green, and blue
  • each The on-time of one sub-pixel is consistent.
  • the sub-pixels in the same row are turned on at the same time, and the data signal is output to The time of each sub-pixel is the same, which will inevitably lead to the problem of uneven charging of the gate drive and the drive near the gate, resulting in uneven brightness of the display panel 20.
  • gate drivers are often provided on the left and right sides of the display panel 20, and a frame start signal (Start Vertical, STV), a scan clock pulse signal (Clock Pulse Vertical, CPV), and a clock are output through the control chip 10
  • Signals CK1 ⁇ CKx, low frequency signals LC1&LC2 and other array substrate row drive circuit drive signals are transmitted to the array substrate row drive circuit circuit on the left and right sides of the panel (that is, the first array substrate row drive circuit 30 and the second array substrate row drive circuit 40)
  • the scan line gate line in the display panel 20 is turned on row by row to achieve bilateral driving.
  • the display module is further provided with a source driver 50.
  • the source driver 50 is used for inputting a data signal.
  • the source driver 50 is mounted on the driver board PCBA.
  • the source driver 50 and the control chip 10 connection, a plurality of output terminals of the source driver 50 are respectively connected to the corresponding data lines of the pixel array 24, the control chip 10 receives data signals, control signals and clock signals output from external circuit sub-circuits, such as the control system SOC of the television, and Converted to data signals, control signals and clock signals suitable for the first array substrate row drive circuit 30 and the second array substrate row drive circuit 40, the source driver 50, the source driver 50 outputs the data signal to the corresponding through the data line Of pixels to realize the image display of the display panel 20.
  • the number of the source drivers 50 is plural, which can be specifically set according to the size of the display panel 20. In this embodiment, two (50A, 50B) are taken as an example for description.
  • the display panel 20 eg, the first array substrate row drive circuit 30 on the left or the right Two array substrate row drive circuit 40
  • the control chip 10 simultaneously outputs the array substrate row drive circuit drive signal to the array substrate row drive circuit on both sides, once one of the array substrate row drive circuit is damaged, the display panel During operation of 20, the display panel 20 driven by the damaged array substrate row drive circuit may not work properly, and the display panel 20 may work normally on one side but not work normally on the other side, usually only by scrapping treatment, making the entire display panel 20 inoperable Use increases the defect rate of the display panel 20.
  • the display panel 20 is fabricated, that is, after the array substrate row drive circuit is provided on the display panel 20, the display panel 20 is inspected.
  • multiple test points may be provided on the display panel 20 , Provide test signals to the array substrate row drive circuits on both sides through the test points, and determine whether the array substrate row drive circuits on both sides have output signals, if so, it can be determined that the corresponding array substrate row drive circuit to be tested can be normal If it works, it can be determined that the row drive circuit of the array substrate works abnormally.
  • the array substrate row drive unit circuit at the first end and the array substrate row drive unit circuit at the end may be used for the test.
  • the drive signal of the array substrate row drive circuit can be output to the array substrate row drive circuit by using a wire or a needle, to drive the array substrate row drive circuit to work, so as to realize the row drive of the array substrate on both sides Circuit detection.
  • the corresponding control chip 10 is set, which can be specifically implemented by a software program.
  • an enable terminal is added, and operates by a control signal output by the control chip 10, the control signal may be at a high level, The first array substrate row drive circuit 30 and the second array substrate row drive circuit 40 are controlled to operate. When the level is low, the first array substrate row drive circuit 30 and the second array substrate row drive circuit 40 are not operated.
  • the software program written in the control chip 10 is configured to control the operation of the first array substrate row drive circuit 30
  • the first array substrate row drive circuit 30 controls the pixel array 24 of the display panel 20 to be turned on row by row; upon detecting that the second array substrate row drive circuit 40 is good, the first array substrate row drive circuit 30 is damaged, and the control chip
  • the software program written in 10 is configured to control the operation of the second array substrate row drive circuit 40.
  • the second array substrate row drive circuit 40 controls the operation of each pixel in the display panel 20, that is, the pixels in the display panel 20
  • the array 24 is turned on row by row; and when it is detected that both the second array substrate row drive circuit 40 and the first array substrate row drive circuit 30 are good, the software program written in the control chip 10 is configured to control the second array substrate
  • the row drive circuit 40 works, and at this time, the first array substrate row drive circuit 30 and the second array substrate row drive circuit 40 respectively control the operation of each pixel of the display panel 20, that is, the first array substrate row drive circuit 30 and the second array substrate
  • the row driving circuit 40 simultaneously controls the pixel array 24 to be turned on row by row.
  • the display module of the present application divides the first array substrate row drive circuit 30 and the second array substrate row drive circuit 40 on both sides of the display panel 20, and controls the chip 10 according to the detected first array substrate row drive circuit 30 and The second array substrate row drive circuit 40 is good or not, thereby outputting different control signals to the enable ends of the first array substrate row drive circuit 30 and the second array substrate row drive circuit 40 to control the first array substrate row drive circuit 30, the second array substrate row drive circuit 40 does not work, or the first array substrate row drive circuit 30 does not work, the second array substrate row drive circuit 40 works, or the first array substrate row drive circuit 30 and the second array substrate Both row drive circuits 40 work simultaneously.
  • the present application can independently control the working states of the array substrate row drive circuit circuits (the first array substrate row drive circuit 30 and the second array substrate row drive circuit 40) on the left and right sides.
  • the display panel 20 can be driven by a single-sided array substrate row drive circuit and a double-sided array substrate row drive circuit.
  • the present application realizes that when the array substrate row drive circuit is damaged on one side, the other side of the array substrate row drive circuit is used to drive the pixel array 24 of the entire panel, which improves the yield of the display panel 20 and solves the problem
  • the row drive circuit of the array substrate on the side cannot work normally, so that the entire display panel 20 is only scrapped, making the entire display panel 20 unusable and increasing the defect rate of the display panel 20.
  • control chip 10 includes a timing controller 11 and a level shifter 12, a plurality of output terminals of the timing controller 11 and a plurality of input terminals of the level shifter 12 One-to-one connection, the output terminals of the level shifter 12 respectively correspond to the enable end of the first array substrate row drive circuit 30 and the enable end of the second array substrate row drive circuit 40 connection;
  • the timing controller 11 is configured as a control signal
  • the level shifter 12 is configured to perform level conversion on the control signal output by the timing controller 11 and output it to the corresponding first array substrate row drive circuit 30 or the second array substrate row drive circuit 40.
  • the timing controller 11 outputs a frame start signal (Start Vertical, STV), scanning clock pulse signal (Clock Pulse Vertical (CPV), clock signals CK1 ⁇ CKx, low frequency signals LC1&LC2 and other array substrate row drive circuit drive signals, the above signals are level converted by the level shifter 12 and output to the first array substrate row drive circuit 30 and the second Array substrate row drive circuit 40.
  • the timing control signal also outputs a control signal for driving the first array substrate row drive circuit 30 and/or the second array substrate row drive circuit 40 to work, the control signal may be high level enabled or low level enabled can.
  • the first array substrate row drive circuit 30 and/or the second array substrate row drive circuit 40 drives the display panel 20
  • the pixel array 24 is turned on row by row.
  • control signals output by the timing controller 11 include a first control signal, a second control signal, and a third control signal;
  • the first control signal, the second control signal, and the third control signal are converted by the level shifter 12 and then output to the first array substrate row drive circuit 30 or the second array substrate row drive circuit 40 ;
  • the first array substrate row drive circuit 30 drives the pixel array 24 to work; when receiving the second control signal, the second array substrate row drive circuit 40 Driving the pixel array 24 to work; when receiving the third control signal, the first array substrate row drive circuit 30 and the second array substrate row drive circuit 40 simultaneously drive the pixel array 24 to work.
  • control signal output by the timing controller 11 may be a high level to enable the first array substrate row drive circuit 30 and the second array substrate row drive circuit 40 to work, or a low level to enable the first array substrate row The driving circuit 30 and the second array substrate row driving circuit 40 work.
  • high-level enabling is used as an example for description.
  • the timing control signal T_L_EN output to the first array substrate row drive circuit 30 is configured as High level H
  • the first control signal T_R_EN output to the second array substrate row drive circuit 40 is configured as low level L
  • the level shifter 12 converts the received T_L_EN and T_R_EN into analog signals, respectively, and expresses as L_EN Is VGH
  • R_EN is VGL
  • the timing control signal T_L_EN output to the first array substrate row drive circuit 30 is configured as low level L
  • the first control signal T_R_EN output to the second array substrate row drive circuit 40 is configured as high level H
  • the level shifter 12 converts the received T_L_EN and T_R_EN into analog signals, respectively, and indicates that L_EN is VGL and R_EN is VGH, thereby driving the second array substrate row drive circuit 40 to work, and the first array substrate row drive circuit 30 to not work.
  • the timing control signal is output to the first control signal T_L_EN of the first array substrate row drive circuit 30 and to the second array substrate row
  • the configuration of the first control signal T_R_EN of the driving circuit 40 is all high level H, and the level shifter 12 converts the received T_L_EN and T_R_EN into analog signals, respectively, and indicates that L_EN is VGH and R_EN is VGH, thereby driving the second The array substrate row drive circuit 40 and the first array substrate row drive circuit 30 operate simultaneously.
  • the display module further includes a driving power supply 60, and the output end of the driving power supply 60 is connected to the power conversion end of the level shifter 12;
  • the level shifter 12 is further configured to convert the power signal received from the driving power source 60 into a gate-on signal or a gate-off signal.
  • the driving power supply 60 integrates a plurality of DC-DC conversion circuits with different circuit functions, and each conversion circuit outputs a different voltage value.
  • the input voltage of the input terminal of the driving power supply 60 is generally 5V or 12V.
  • the output voltage includes the operating voltage DVDD provided to the timing controller 11, and the gate turn-on voltage VGH and the turn-off voltage VGL provided to the gate driver.
  • the first array substrate row drive circuit 30 includes a plurality of cascaded first array substrate row drive unit circuits (311 ⁇ 31N), and each of the first array substrate row drive unit circuits ( 311 ⁇ 31N) outputs the first scan signal step by step to control the corresponding pixel array 24 to be turned on.
  • each first array substrate row drive unit circuit (311 ⁇ 31N) has multiple input terminals, and the multiple input terminals are respectively connected to the clock signals CLK, CLKB of the timing controller via the level shifter 12, and The power supply signal Vss input from the drive power supply.
  • the output terminals (Output N -1 to Output N+1) of each first array substrate row drive unit circuit (311 to 31N) are respectively connected to a row of thin film transistors in the pixel array 24.
  • Each first array substrate row drive unit circuit (311 ⁇ 31N) includes a pull-up control sub-circuit (M1), a pull-up sub-circuit (M3), a pull-down sub-circuit (M2, M4), and a pull-up control sub-circuit (M1) ) Is mainly used to output pull-up control signals.
  • the input terminal of the pull-up sub-circuit (M3) is connected to the output terminal of the pull-up control sub-circuit (M1), which is mainly used to output the line scan signal Output according to the pull-up control signal Output N -1 N.
  • the pull-down sub-circuits (M2, M4) are respectively connected to the output terminals of the pull-up control sub-circuit (M1) and the pull-up sub-circuit (M3), and after completing the scanning of the sub-pixels in the current row, the pull-up control signal Output N -1 and line scan signal Output N is pulled down to low level.
  • the first array substrate row drive unit circuit (311 ⁇ 31N) may also be provided with a bootstrap capacitor C. The first pole of C is connected to the pull-up control signal Output N-1, and the second pole of the C is connected to the current array substrate row drive unit circuit The line scan signal Output N.
  • the bootstrap capacitor C is used to maintain the voltage between the pull-up sub-circuit (M3) and stabilize the output of the pull-up sub-circuit (M3).
  • the second array substrate row drive circuit 40 includes a plurality of cascaded second array substrate row drive unit circuits (411 ⁇ 41N), each of the second array substrate row drive unit circuits ( The output terminals 411 ⁇ 41N) output the second scan signal step by step to drive the corresponding pixel array 24 to be turned on.
  • Each second array substrate row drive unit circuit (411 ⁇ 41N) has multiple input terminals, and the multiple input terminals are respectively connected to the clock signals CLK, CLKB of the timing controller through the level shifter 12 and the power supply for driving power input Signal Vss.
  • each second array substrate row drive unit circuit (321 ⁇ 32N) includes a pull-up control sub-circuit (M1), a pull-up sub-circuit (M3), a pull-down sub-circuit (M2, M4), and pull-down maintenance Sub-circuit, pull-up control sub-circuit (M1) is mainly used to output pull-up control signal.
  • the input terminal of the pull-up sub-circuit (M3) is connected to the pull-up control signal Output N -1 output by the pull-up control sub-circuit (M1), which is mainly used to output the pull-up control signal N -1 outputs the line scan signal Output N.
  • the pull-down sub-circuits (M2, M4) are respectively connected to the output terminals of the pull-up control sub-circuit (M1) and the pull-up sub-circuit (M3), and after completing the scanning of the sub-pixels in the current row, the pull-up control signal Output N -1 and the line scan signal Output N is pulled down to low level.
  • the row drive unit circuit of the first array substrate may also be provided with a bootstrap capacitor C, the first plate of C is connected to the pull-up control signal Output N -1, and the second plate of the C is connected to the line scan of the row drive unit circuit of the current array substrate Signal Output N.
  • the bootstrap capacitor C is used to maintain the voltage between the pull-up sub-circuit (M3) and stabilize the output of the pull-up sub-circuit (M3).
  • a pull-up control sub-circuit (M1), a pull-up sub-circuit (M3), and a pull-down sub-circuit (M2, M4) It can be implemented with thin film transistors, and depending on the size or type of the display panel 20, it can be implemented with a 4T1C (that is, four thin film transistor TFT and a capacitor C) array substrate row drive circuit drive circuit structure, or 8T1C (That is, eight thin film transistors TFT and one capacitor C) the array substrate row drive circuit drive circuit structure to achieve.
  • 4T1C that is, four thin film transistor TFT and a capacitor C
  • 8T1C (That is, eight thin film transistors TFT and one capacitor C) the array substrate row drive circuit drive circuit structure to achieve.
  • each TFT tube is marked with M1 ⁇ M4, M1 ⁇ M4 constitute the above control sub-circuit (M1), pull-up sub-circuit (M3) and pull-down sub-circuit (M2, M4).
  • the display panel 20 further includes:
  • the first substrate 21 has a display area AA and a non-display area BB; the pixel array 24 is disposed on the first substrate 21 and is located in the display area AA; the first array substrate row drive circuit 30 and the The second array substrate row drive circuit 40 is disposed on the first substrate 21 and located in the non-display area BB;
  • the second substrate 22 is disposed opposite to the first substrate 21;
  • a liquid crystal layer 23 is disposed between the first substrate 21 and the second substrate 22, the liquid crystal layer 23 includes a plurality of liquid crystal molecules, and the pixel array 24 is used to control the actions of the plurality of liquid crystal molecules.
  • the first substrate 21 and the second substrate 22 are generally both light-transmitting substrates such as glass substrates or plastic substrates.
  • the second substrate is disposed opposite to the first substrate 21, and a corresponding circuit can be disposed between the first substrate 21 and the second substrate 22.
  • the pixel array 24 is disposed on the first substrate 21 and located in the display area AA. The pixel array 24 can generate a control signal to control the display under the driving control of the first array substrate row drive circuit 30 and/or the second array substrate row drive circuit 40 The display of the panel 20.
  • the first array substrate row drive circuit 30 and the second array substrate row drive circuit 40 are disposed on the first substrate 21 and are located in the non-display area BB. Accordingly, the first array substrate row drive circuit 30 and the second array substrate row drive circuit 40.
  • the isolation structure may be used to isolate the first array substrate row drive circuit 30 and the second array substrate row drive circuit 40 from the liquid crystal layer 23, so that the first array substrate row drive circuit 30 and the second array substrate row drive circuit 40 A liquid crystal-free region is formed between the second substrate 22 and the second substrate 22, respectively.
  • the display panel 20 further includes a sealant 25 disposed in the non-display area BB between the first substrate 21 and the second substrate 22 and disposed around the liquid crystal layer 23, and the first array substrate row
  • the driving circuit 30 and the second array substrate row driving circuit 40 are located between the sealant 25 and the display area AA.
  • the sealant 25 may be coated on the first substrate 21 or the second substrate 22 with a sealant to connect the first substrate 21 and the second substrate 22, thereby realizing the assembly process of the display panel 20.
  • the pixel array 24 includes multiple sub-pixels, each of which includes an active switch (thin film transistor) and a pixel electrode, the gate of the active switch T and the sub-pixel Corresponding scan lines are electrically connected, the source of the active switch is electrically connected to the data line corresponding to the sub-pixel, and the drain of the active switch is electrically connected to the pixel electrode of the sub-pixel.
  • the pixel array 24 also includes a pixel electrode array connected to the active switching element array.
  • the display panel 20 is composed of a plurality of pixels, and each pixel is composed of three sub-pixels of red, green, and blue.
  • Each sub-pixel structure is generally provided with a thin film transistor and a capacitor, the gate of the thin film transistor is connected to the gate driver through the scan line, the source of the thin film transistor is connected to the source driver 50 through the data line, and the drain of the thin film transistor is connected to the capacitor Connected at one end.
  • a plurality of thin film transistors constitute the thin film transistor array of this embodiment (not shown in the figure).
  • the thin-film transistors 31 located in the same column are connected to the source driver 50 through a data line, and the thin-film transistors located in the same row are connected to the gate driver through a scan line, thus forming a thin-film transistor array.
  • the first array substrate row drive circuit 30 and the second array substrate row drive circuit 40 provide voltages to the gates of several thin film transistors.
  • These thin-film transistors may be a-Si (non-silicon) thin-film transistors or Poly-Si (polycrystalline silicon) thin-film transistors, of which Poly-Si thin-film transistors may use LTPS (Low Temperature Poly-Silicon (low temperature polysilicon) and other technologies to form.
  • the first array substrate row drive circuit 30 and the second array substrate row drive circuit 40 further include a signal bus (not shown), the signal bus is disposed on the first substrate 21 and is located on the non-display In the area BB, the signal bus connects the first array substrate row drive circuit 30 and the timing controller 11, and connects the second array substrate row drive circuit 40 and the timing controller 11, and is located in the first array substrate row drive circuit 30 and the second
  • the array substrate row drive circuit 40 is away from the display area AA.
  • the clock bus enable control signal and the like can be provided to the first array substrate row drive circuit 30 and the second array substrate row drive circuit 40 through the signal bus.
  • the first array substrate row driving circuit 30 and the second array substrate row driving circuit 40 may further include cascaded shift registers, and each stage of the shift register is connected to one scanning line in the display area AA.
  • the present application also proposes a display module.
  • the display module includes:
  • the control chip 10 has a first control signal output terminal and a second control signal output terminal;
  • a first array substrate row drive circuit (Gate Driver on Array, GOA) circuit and a second array substrate row drive circuit 40 are located on both sides of the display panel 20; the first array substrate row drive circuit 30 and the The second array substrate row drive circuit 40 each has an enable terminal, the enable terminal of the first array substrate row drive circuit 30 and the enable terminal of the second array substrate row drive circuit 40 and the first control signal The output terminal and the second control signal output terminal are connected in a one-to-one correspondence;
  • the first array substrate row drive circuit 30 includes a plurality of cascaded first array substrate row drive unit circuits
  • the second array substrate row drive circuit 40 includes a plurality of cascaded second array substrate row drive unit circuits (321 ⁇ 32N);
  • Each of the first array substrate row drive unit circuits is configured to output a first scan signal step by step when receiving the control signal output by the control chip 10 to control the corresponding pixel array 24 to be turned on;
  • Each of the second array substrate row drive unit circuits (321 ⁇ 32N) is configured to output a second scan signal step by step when receiving the control signal output from the control chip 10 to control the corresponding pixel array 24 is on.
  • the display module of the present application divides the first array substrate row drive circuit 30 and the second array substrate row drive circuit 40 on both sides of the display panel 20, and controls the chip 10 according to the detected first array substrate row drive circuit 30 and The second array substrate row drive circuit 40 is good or not, thereby outputting different control signals to the enable ends of the first array substrate row drive circuit 30 and the second array substrate row drive circuit 40 to control the first array substrate row drive circuit 30, the second array substrate row drive circuit 40 does not work, or the first array substrate row drive circuit 30 does not work, the second array substrate row drive circuit 40 works, or the first array substrate row drive circuit 30 and the second array substrate Both row drive circuits 40 work simultaneously.
  • the present application can independently control the working states of the array substrate row drive circuit circuits (the first array substrate row drive circuit 30 and the second array substrate row drive circuit 40) on the left and right sides.
  • the display panel 20 can be driven by a single-sided array substrate row drive circuit and a double-sided array substrate row drive circuit.
  • the present application realizes that when the array substrate row drive circuit is damaged on one side, the other side of the array substrate row drive circuit is used to drive the pixel array 24 of the entire panel, which improves the yield of the display panel 20 and solves the problem
  • the row drive circuit of the array substrate on the side cannot work normally, so that the entire display panel 20 is only scrapped, making the entire display panel 20 unusable and increasing the defect rate of the display panel 20.
  • first array substrate row drive unit circuits and second array substrate row drive unit circuits (321 ⁇ 32N) are used to drive the thin film transistors of the corresponding rows in the pixel array 24 to turn on to charge the pixel capacitance.
  • the present application also includes a display device including the display module as described above.
  • a display device including the display module as described above.
  • the display module For the detailed structure of the display module, reference may be made to the above-mentioned embodiment, which will not be repeated here; it can be understood that, since the above-mentioned display module is used in the display device of the present application, the embodiment of the display device of the present application includes the above-mentioned display All the technical solutions of all the embodiments of the module, and the technical effects achieved are also the same, which will not be repeated here.
  • the display device further includes a backlight module, and the backlight module and the display module may be oppositely arranged, or the backlight module and the display module are integrally provided.

Abstract

一种显示模组及显示装置，该显示模组包括：控制芯片(10)、显示面板(20)、第一阵列基板行驱动单元电路(30)及第二阵列基板行驱动电路(40)，第一阵列基板行驱动电路(30)的使能端及第二阵列基板行驱动电路(40)的使能端与控制芯片(10)的第一控制信号输出端及第二控制信号输出端一一对应连接；第一阵列基板行驱动电路(30)和/或第二阵列基板行驱动电路(40)在接收到控制芯片(10)输出的控制信号时，驱动像素阵列(24)工作。

Description

显示模组及显示装置
相关申请的交叉引用
本申请要求2018年12月24日，申请号为201811586552.X，申请名称为“显示模组及显示装置”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及电子电路技术领域，特别涉及一种显示模组及显示装置。
 背景技术
阵列基板行驱动电路（Gate Driver on Array，GOA）由于其直接将栅极驱动电路(Gate driver IC)制作在显示装置的阵列(Array)基板上，来代替由外接硅片制作的驱动芯片的一种工艺技术。该技术的应用可减少生产工艺程序，降低产品工艺成本，因此越来越多的应用的显示装置中。在实际生产过程中，往往存在被静电击伤或其他制程因素造成的单边阵列基板行驱动电路 circuit损坏的显示面板，这种显示面板通常只有报废处理，而导致显示面板的不良率较高。
 技术解决方案
本申请的主要目的是提出一种显示模组及显示装置。
为实现上述目的，本申请提出一种显示模组，所述显示模组包括：
控制芯片，具有第一控制信号输出端及第二控制信号输出端；
显示面板，所述显示面板具有相对设置的两侧，所述显示面板包括像素阵列；
第一阵列基板行驱动电路及第二阵列基板行驱动电路，分设于所述显示面板的两侧；所述第一阵列基板行驱动电路及所述第二阵列基板行驱动电路均具有使能端，所述第一阵列基板行驱动电路的使能端及所述第二阵列基板行驱动电路的使能端与所述第一控制信号输出端及第二控制信号输出端一一对应连接；
所述第一阵列基板行驱动电路和/或所述第二阵列基板行驱动电路，配置为在接收到所述控制芯片输出的控制信号时，驱动所述像素阵列工作。
本申请还提出一种显示模组，所述显示模组包括：
控制芯片，具有第一控制信号输出端及第二控制信号输出端；
显示面板，所述显示面板具有相对设置的两侧，所述显示面板包括像素阵列；
第一阵列基板行驱动电路及第二阵列基板行驱动电路，分设于所述显示面板的两侧；所述第一阵列基板行驱动电路及所述第二阵列基板行驱动电路均具有使能端，所述第一阵列基板行驱动电路的使能端及所述第二阵列基板行驱动电路的使能端与所述第一控制信号输出端及第二控制信号输出端一一对应连接；
所述第一阵列基板行驱动电路包括多个级联第一阵列基板行驱动单元电路，所述第二阵列基板行驱动电路包括多个级联第二阵列基板行驱动单元电路；
每个所述第一阵列基板行驱动单元电路，配置为在接收到所述控制芯片输出的控制信号时，逐级输出第一扫描信号，以控制对应的所述像素阵列导通；
每个所述第二阵列基板行驱动单元电路，配置为在接收到所述控制芯片输出的控制信号时，逐级输出第二扫描信号，以控制对应的所述像素阵列导通。
本申请还提出一种显示装置，包括如上所述的显示模组；所述显示模组包括：控制芯片，具有第一控制信号输出端及第二控制信号输出端；
显示面板，所述显示面板具有相对设置的两侧，所述显示面板包括像素阵列；第一阵列基板行驱动电路及第二阵列基板行驱动电路，分设于所述显示面板的两侧；所述第一阵列基板行驱动电路及所述第二阵列基板行驱动电路均具有使能端，所述第一阵列基板行驱动电路的使能端及所述第二阵列基板行驱动电路的使能端与所述第一控制信号输出端及第二控制信号输出端一一对应连接；所述第一阵列基板行驱动电路和/或所述第二阵列基板行驱动电路，配置为在接收到所述控制芯片输出的控制信号时，驱动所述像素阵列工作。
本申请显示模组将第一阵列基板行驱动电路和第二阵列基板行驱动电路分设于显示面板的两侧，并通过控制芯片根据检测后的第一阵列基板行驱动电路和第二阵列基板行驱动电路良好与否，从而输出不同的控制信号至第一阵列基板行驱动电路和第二阵列基板行驱动电路的使能端，以控制第一阵列基板行驱动电路工作，第二阵列基板行驱动电路不工作，或者第一阵列基板行驱动电路不工作，第二阵列基板行驱动电路工作，或者第一阵列基板行驱动电路和第二阵列基板行驱动电路两者同时工作，本申请可以独立控制左右两侧的阵列基板行驱动电路（第一阵列基板行驱动电路和第二阵列基板行驱动电路）的工作状态，从而使得对显示面板单边阵列基板行驱动电路驱动和双边阵列基板行驱动电路驱动均可实现。本申请实现了在阵列基板行驱动电路有单边损坏时，使用另一边的阵列基板行驱动电路来驱动整个面板的像素阵列工作，提升了显示面板的良率，解决了在一侧的阵列基板行驱动电路不能正常工作，导致整个显示面板只有报废处理，使得整个显示面板的无法使用，而增大显示面板的不良率的问题。
 附图说明
图1为本申请显示模组一实施例的电路结构示意图；
图2为本申请显示模组一实施例的结构示意图；
图3为图1中显示面板一实施例的结构示意图；
图4为图1中第一阵列基板行驱动电路一实施例的电路结构示意图；
图5为图1中第二阵列基板行驱动电路一实施例的电路结构示意图；
图6为第一阵列基板行驱动电路和第二阵列基板行驱动电路采用4T1C型阵列基板行驱动电路驱动电路结构的电路结构示意图。
 本发明的实施方式
本申请提出一种显示模组，适用于电脑、手机、投影仪或者电视机等具有显示面板的显示装置中。
参照图1，在本申请一实施例中，该显示模组包括：
控制芯片10，具有第一控制信号输出端及第二控制信号输出端；
显示面板20，所述显示面板20具有相对设置的两侧，所述显示面板20包括像素阵列24；
第一阵列基板行驱动电路(Gate Driver on Array，GPA）电路及第二阵列基板行驱动电路40，分设于所述显示面板20的两侧；所述第一阵列基板行驱动电路30及所述第二阵列基板行驱动电路40均具有使能端，所述第一阵列基板行驱动电路30的使能端及所述第二阵列基板行驱动电路40的使能端与所述第一控制信号输出端及第二控制信号输出端一一对应连接；所述第一阵列基板行驱动电路30和/或所述第二阵列基板行驱动电路40，配置为在接收到所述控制芯片10输出的控制信号时，驱动所述像素阵列24工作。
显示面板20可以是OLED（Organic Light-Emitting Diode，有机发光二极管）显示面板20，也可以是TFT-LCD（Thin Film Transistor Liquid Crystal Display)显示面板20。显示面板20以Gate driver design(栅极驱动器设计)来分，可以分为SOC (System on chip，片上系统)型和阵列基板行驱动电路(Gate driver on array，阵列基板上栅极驱动器)型两种。阵列基板行驱动电路由于其直接将栅极驱动电路(Gate driver IC)制作在显示装置的阵列(Array)基板上，来代替由外接硅片制作的驱动芯片的一种工艺技术。该技术的应用可减少生产工艺程序，降低产品工艺成本，并且可以提高显示面板20的集成度。相对于SOC型显示面板20，阵列基板行驱动电路型显示面板20具有更窄的边框(border)。随着科技进步以及人们对视觉效果的更高要求，显示面板20窄边框化是未来的主流趋势。因此，阵列基板行驱动电路型显示面板20相对于SOC型显示面板20是一种更为重要的应用。在阵列基板行驱动电路型显示面板20的范例性的架构中，其上下玻璃基板之间填充LC(Liquid Crystal，液晶)分子且四周用密封材料密封；其中，液晶是一种高分子材料，因为其特殊的物理、化学、光学特性，被广泛应用在轻薄型的显示技术上。
本实施例中，显示面板20的像素阵列24由多个子像素构成，三个子像素（红、绿、蓝）构成一个像素，例如在同一横行上的子像素在分布于显示面板20上时，每一子像素的导通时间是一致的。在一些大尺寸的显示面板20中，由于面板远离栅极驱动的区域与靠近栅极驱动的区域的扫描线走线电阻是不均匀的，在同一行的子像素同时打通，而数据信号输出至各子像素的时间是相同的，这势必会出现原理栅极驱动和靠近栅极驱动充电不均匀的问题而导致显示面板20的亮度不均。因此，往往在显示面板20的左右两侧都设置有栅极驱动gate driver，并通过控制芯片10输出帧起始信号（Start Vertical，STV）、扫描时钟脉冲信号（Clock Pulse Vertical，CPV），时钟信号CK1~CKx、以及低频信号LC1&LC2等阵列基板行驱动电路驱动信号，传输到面板左右两侧的阵列基板行驱动电路 circuit（也即第一阵列基板行驱动电路30和第二阵列基板行驱动电路40），阵列基板行驱动电路正常动作后再逐行开启显示面板20内的扫描线gate line，以实现双边驱动。
在一些实施例中，显示模组还设置有源极驱动器50，源极驱动器50用于输入数据信号的源极驱动器50，源极驱动器50安装与驱动板PCBA 上，源极驱动器50与控制芯片10连接，源极驱动器50的多个输出端分别与像素阵列24对应数据线连接，控制芯片10接收外部电路子电路，例如电视机的控制系统SOC输出的数据信号、控制信号以及时钟信号，并转换成适合于第一阵列基板行驱动电路30和第二阵列基板行驱动电路40、源极驱动器50的数据信号、控制信号以及时钟信号，源极驱动器50的将数据信号通过数据线输出至对应的像素，实现显示面板20的图像显示。源极驱动器50的数量为多个，具体可以根据显示面板20的尺寸进行设置，本实施例以两个（50A、50B）为例进行说明。
在实际生产过程中，往往存在被ESD击伤或其他制程因素造成的单边阵列基板行驱动电路 circuit损坏的显示面板20（例如左侧的第一阵列基板行驱动电路30，或者右侧的第二阵列基板行驱动电路40），由于控制芯片10是同时输出阵列基板行驱动电路驱动信号至两侧的阵列基板行驱动电路的，一旦有一侧的阵列基板行驱动电路被损坏，则在显示面板20工作时，会出现损坏的阵列基板行驱动电路驱动的显示面板20不能正常工作，而出现显示面板20一边正常工作，而另外一边不能正常工作，通常只有报废处理，使得整个显示面板20的无法使用，而增大显示面板20的不良率。
为了解决上述问题，在显示面板20制作完成后，也即阵列基板行驱动电路设置于显示面板20后，对显示面板20进行检测，在具体实施时，可以在显示面板20上设置多个测试点，通过测试点向两侧的阵列基板行驱动电路分别提供测试信号，并判断两侧的阵列基板行驱动电路是否有输出信号，若是，则可以确定对应的待测的阵列基板行驱动电路能够正常工作，若否，则可以确定阵列基板行驱动电路工作异常。在测试时，可以采用阵列基板行驱动电路的首端的阵列基板行驱动单元电路和末端的阵列基板行驱动单元电路来进行测试。在上述检测的过程中，可以采用导线或者采用扎针的方式将阵列基板行驱动电路驱动信号输出至阵列基板行驱动电路，以驱动阵列基板行驱动电路工作，从而实现对两侧的阵列基板行驱动电路的检测。
在检测完后，即可以确定两侧的阵列基板行驱动电路是否良好，并根据两侧阵列基板行驱动电路良好与否，设置对应的控制芯片10，具体可以通过软件程序来实现。并且，在第一阵列基板行驱动电路30和第二阵列基板行驱动电路40中，增加了使能端，并通过控制芯片10输出的控制信号而工作，该控制信号可以在为高电平时，控制第一阵列基板行驱动电路30和第二阵列基板行驱动电路40工作，在为低电平时，第一阵列基板行驱动电路30和第二阵列基板行驱动电路40不工作。如此，可以在检测到第一阵列基板行驱动电路30良好，第二阵列基板行驱动电路40被损坏，控制芯片10的中写入的软件程序则配置为控制第一阵列基板行驱动电路30工作，此时第一阵列基板行驱动电路30控制显示面板20的像素阵列24逐行导通；在检测到第二阵列基板行驱动电路40良好，第一阵列基板行驱动电路30被损坏，控制芯片10的中写入的软件程序则配置为控制第二阵列基板行驱动电路40工作，此时第二阵列基板行驱动电路40控制显示面板20中各像素工作，也即控制显示面板20中的像素阵列24逐行导通；而在检测到第二阵列基板行驱动电路40和第一阵列基板行驱动电路30均为良好时，控制芯片10中写入的软件程序则配置为控制第二阵列基板行驱动电路40工作，此时第一阵列基板行驱动电路30和第二阵列基板行驱动电路40分别控制显示面板20的各像素工作，也即第一阵列基板行驱动电路30和第二阵列基板行驱动电路40同时控制像素阵列24逐行导通。
本申请显示模组将第一阵列基板行驱动电路30和第二阵列基板行驱动电路40分设于显示面板20的两侧，并通过控制芯片10根据检测后的第一阵列基板行驱动电路30和第二阵列基板行驱动电路40良好与否，从而输出不同的控制信号至第一阵列基板行驱动电路30和第二阵列基板行驱动电路40的使能端，以控制第一阵列基板行驱动电路30工作，第二阵列基板行驱动电路40不工作，或者第一阵列基板行驱动电路30不工作，第二阵列基板行驱动电路40工作，或者第一阵列基板行驱动电路30和第二阵列基板行驱动电路40两者同时工作，本申请可以独立控制左右两侧的阵列基板行驱动电路 circuit（第一阵列基板行驱动电路30和第二阵列基板行驱动电路40）的工作状态，从而使得对显示面板20单边阵列基板行驱动电路驱动和双边阵列基板行驱动电路驱动均可实现。本申请实现了在阵列基板行驱动电路 circuit有单边损坏时，使用另一边的阵列基板行驱动电路 circuit来驱动整个面板的像素阵列24工作，提升了显示面板20的良率，解决了在一侧的阵列基板行驱动电路不能正常工作，导致整个显示面板20只有报废处理，使得整个显示面板20的无法使用，而增大显示面板20的不良率的问题。
在一可选实施例中，所述控制芯片10包括时序控制器11及电平转移器12，所述时序控制器11的多个输出端与所述电平转移器12的多个输入端一一对应连接，所述电平转移器12的多个输出端分别与所述第一阵列基板行驱动电路30的使能端及所述第二阵列基板行驱动电路40的使能端一一对应连接；
所述时序控制器11，配置为控制信号；
所述电平转移器12，配置为将所述时序控制器11输出的控制信号进行电平转换后输出至对应的所述第一阵列基板行驱动电路30或所述第二阵列基板行驱动电路40。
本实施例中，时序控制器11在显示模组工作时，输出帧起始信号（Start Vertical，STV）、扫描时钟脉冲信号（Clock Pulse Vertical，CPV），时钟信号CK1~CKx、低频信号LC1&LC2等阵列基板行驱动电路驱动信号，上述信号经电平转移器12进行电平转换后输出至第一阵列基板行驱动电路30和第二阵列基板行驱动电路40。时序控制信号还输出控制信号，用于驱动第一阵列基板行驱动电路30和/或所述第二阵列基板行驱动电路40工作，该控制信号可以是高电平使能，或者低电平使能。在接收到经电平转移器12进行信号转换后的时序控制器11输出的控制信号时，第一阵列基板行驱动电路30和/或所述第二阵列基板行驱动电路40驱动显示面板20中的像素阵列24逐行导通。
在一可选实施例中，所述时序控制器11输出的控制信号包括第一控制信号、第二控制信号及第三控制信号；
所述第一控制信号、第二控制信号及第三控制信号经所述电平转移器12转换后，输出至所述第一阵列基板行驱动电路30或所述第二阵列基板行驱动电路40；
在接收到所述第一控制信号时，所述第一阵列基板行驱动电路30驱动所述像素阵列24工作；在接收到所述第二控制信号时，所述第二阵列基板行驱动电路40驱动所述像素阵列24工作；在接收到第三控制信号时，所述第一阵列基板行驱动电路30和所述第二阵列基板行驱动电路40同时驱动所述像素阵列24工作。
可以理解的是，时序控制器11输出的控制信号可以是高电平使能第一阵列基板行驱动电路30和第二阵列基板行驱动电路40工作，或者低电平使能第一阵列基板行驱动电路30和第二阵列基板行驱动电路40工作，本实施例以高电平使能为例进行说明。
本实施例中，当第一阵列基板行驱动电路30良好，第二阵列基板行驱动电路40被损坏，此时时序控制信号输出至第一阵列基板行驱动电路30的第一控制信号T_L_EN配置为高电平H，输出至第二阵列基板行驱动电路40的第一控制信号T_R_EN配置为低电平L，电平转移器12将接收到的T_L_EN与T_R_EN分别转换为模拟信号，并表示为L_EN为VGH，R_EN为VGL，从而驱动第一阵列基板行驱动电路30工作，第二阵列基板行驱动电路40不工作。
当第二阵列基板行驱动电路40良好，第一阵列基板行驱动电路30被损坏，此时时序控制信号输出至第一阵列基板行驱动电路30的第一控制信号T_L_EN配置为低电平L，输出至第二阵列基板行驱动电路40的第一控制信号T_R_EN配置为高电平H，电平转移器12将接收到的T_L_EN与T_R_EN分别转换为模拟信号，并表示为L_EN为VGL，R_EN为VGH，从而驱动第二阵列基板行驱动电路40工作，第一阵列基板行驱动电路30不工作。
当第一阵列基板行驱动电路30和第二阵列基板行驱动电路40均良好，此时时序控制信号输出至第一阵列基板行驱动电路30的第一控制信号T_L_EN以及输出至第二阵列基板行驱动电路40的第一控制信号T_R_EN配置均为高电平H，电平转移器12将接收到的T_L_EN与T_R_EN分别转换为模拟信号，并表示为L_EN为VGH，R_EN为VGH，从而驱动第二阵列基板行驱动电路40和第一阵列基板行驱动电路30同时工作。
在一可选实施例中，所述显示模组还包括驱动电源60，所述驱动电源60的输出端与所述电平转移器12的电源转换端连接；
所述电平转移器12，还配置为将接收到所述驱动电源60输出的电源信号转换为栅极开启信号或者栅极关断信号。
驱动电源60集成了多个不同电路功能的直流-直流转换电路，每个转换电路输出不同的电压值。驱动电源60的输入端输入的电压一般为5V或12V，输出的电压包括给时序控制器11提供的工作电压DVDD，以及给栅极驱动器提供的栅极开启电压VGH和关断电压VGL。
在一可选实施例中，所述第一阵列基板行驱动电路30包括多个级联第一阵列基板行驱动单元电路（311~31N），每个所述第一阵列基板行驱动单元电路（311~31N）的输出端逐级输出第一扫描信号，以控制对应的所述像素阵列24导通。
本实施例中，每一第一阵列基板行驱动单元电路（311~31N）具有多个输入端，多个输入端分别经电平转移器12接入时序控制器的时钟信号CLK、 CLKB，以及驱动电源输入的电源信号Vss。每一第一阵列基板行驱动单元电路（311~31N）的输出端（Output N -1~Output N+1）分别与像素阵列24中的一行薄膜晶体管连接。
每个第一阵列基板行驱动单元电路（311~31N）均包括上拉控制子电路（M1）、上拉子电路（M3）以及下拉子电路（M2、M4），上拉控制子电路（M1）主要用于输出上拉控制信号。上拉子电路（M3）的输入端与上拉控制子电路（M1）的输出端相连接，主要用于根据该上拉控制信号Output N -1输出行扫描信号Output N。下拉子电路（M2、M4）分别与上拉控制子电路（M1）以及上拉子电路（M3）的输出端相连接，在完成对当前行子像素的扫描后，将上拉控制信号Output N-1以及行扫描信号Output N下拉至低电平。第一阵列基板行驱动单元电路（311~31N）还可以设置有自举电容C，C的第一极连接上拉控制信号Output N-1，其第二极连接当前级阵列基板行驱动单元电路的行扫描信号Output N。自举电容C用于维持上拉子电路（M3）之间的电压，稳定上拉子电路（M3）的输出。
在一可选实施例中，所述第二阵列基板行驱动电路40包括多个级联第二阵列基板行驱动单元电路（411~41N），每个所述第二阵列基板行驱动单元电路（411~41N）的输出端逐级输出第二扫描信号，以驱动对应的所述像素阵列24导通。每一第二阵列基板行驱动单元电路（411~41N）具有多个输入端，多个输入端分别经电平转移器12接入时序控制器的时钟信号CLK、 CLKB，以及驱动电源输入的电源信号Vss。每一第二阵列基板行驱动单元电路（321~32N）的输出端（Output N -1~Output N+1）分别与像素阵列24中的一行薄膜晶体管连接。
本实施例中，每个第二阵列基板行驱动单元电路（321~32N）均包括上拉控制子电路（M1）、上拉子电路（M3）、下拉子电路（M2、M4）以及下拉维持子电路，上拉控制子电路（M1）主要用于输出上拉控制信号。上拉子电路（M3）的输入端与上拉控制子电路（M1）所输出的上拉控制信号Output N -1相连接，主要用于根据该上拉控制信号Output N -1输出行扫描信号Output N。下拉子电路（M2、M4）分别与上拉控制子电路（M1）以及上拉子电路（M3）的输出端相连接，在完成对当前行子像素的扫描后，将上拉控制信号Output N-1以及行扫描信号Output N下拉至低电平。第一阵列基板行驱动单元电路还可以设置有自举电容C，C的第一极板连接上拉控制信号Output N -1，其第二极板连接当前级阵列基板行驱动单元电路的行扫描信号Output N。自举电容C用于维持上拉子电路（M3）之间的电压，稳定上拉子电路（M3）的输出。
在实际应用中，在各第一阵列基板行驱动单元电路和各第二阵列基板行驱动单元电路中，上拉控制子电路（M1）、上拉子电路（M3）以及下拉子电路（M2、M4）可以采用薄膜晶体管来实现，并且根据显示面板20的尺寸或者类型，可以采用4T1C（也即，四个薄膜晶体管TFT和一电容C）阵列基板行驱动电路驱动电路结构来实现，或者采用8T1C（也即，八个薄膜晶体管TFT和一个电容C）阵列基板行驱动电路驱动电路结构来实现。本实施例以各第一阵列基板行驱动单元电路和各第二阵列基板行驱动单元电路采用4T1C阵列基板行驱动电路驱动电路结构来实现为例进行说明。图中，各TFT管均以M1~M4标示，M1~M4构成了上述控制子电路（M1）、上拉子电路（M3）以及下拉子电路（M2、M4）。
在一可选实施例中，所述显示面板20还包括：
第一基板21，具有显示区域AA与非显示区域BB；所述像素阵列24设置于所述第一基板21上且位于所述显示区域AA；所述第一阵列基板行驱动电路30和所述第二阵列基板行驱动电路40设置于所述第一基板21上且位于所述非显示区域BB；
第二基板22，与所述第一基板21相对设置；
液晶层23，设置于所述第一基板21与所述第二基板22之间，所述液晶层23包括若干液晶分子，所述像素阵列24用于控制所述若干液晶分子的动作。
本实施例中，第一基板21与第二基板22通常均为玻璃基板或塑料基板等透光材料基板。第二基板与第一基板21相对设置，在第一基板21与第二基板22之间可以设置对应的电路。像素阵列24设置于第一基板21上且位于显示区域AA，像素阵列24在第一阵列基板行驱动电路30和/或第二阵列基板行驱动电路40的驱动控制下，可以产生控制信号控制显示面板20的显示。
第一阵列基板行驱动电路30和第二阵列基板行驱动电路40设置于第一基板21上且位于非显示区域BB，相应地，第一阵列基板行驱动电路30和第二阵列基板行驱动电路40可以通过隔离结构来实现第一阵列基板行驱动电路30和第二阵列基板行驱动电路40与液晶层23的隔离，从而在第一阵列基板行驱动电路30和第二阵列基板行驱动电路40分别与第二基板22之间形成无液晶区。
可以理解的是，上述实施例中，显示面板20还包括框胶25，设置于第一基板21与第二基板22之间的非显示区域BB内并环绕液晶层23设置，第一阵列基板行驱动电路30和第二阵列基板行驱动电路40位于框胶25与显示区域AA之间。框胶25可以采用密封胶涂布在第一基板21上，或者第二基板22上，以连接第一基板21和第二基板22，从而实现对显示面板20的组装处理。
在一可选实施例中，所述像素阵列24包括多个子像素，每一所述子像素均包括一主动开关（薄膜晶体管）及一像素电极，所述主动开关T的栅极与该子像素对应的扫描线电性连接，所述主动开关的源极与该子像素对应的数据线电性连接，所述主动开关的漏极与该子像素的像素电极电性连接。像素阵列24还包括连接主动开关元件阵列的像素电极阵列。
显示面板20由多个像素组成，每个像素又由红绿蓝三个亚像素组成。每个子像素结构一般设置有一个薄膜晶体管和一个电容，薄膜晶体管的栅极通过扫描线与栅极驱动器连接，薄膜晶体管的源极通过数据线与源极驱动器50连接，薄膜晶体管的漏极与电容的一端连接。其中，多个薄膜晶体管构成了本实施例的薄膜晶体管阵列（图未标示）。位于同一列的薄膜晶体管31通过一数据线与源极驱动器50连接，位于同一行的薄膜晶体管通过一扫描线与栅极驱动器连接，如此以构成薄膜晶体管阵列。第一阵列基板行驱动电路30和第二阵列基板行驱动电路40对若干薄膜晶体管的栅极提供电压。这些薄膜晶体管可以是a-Si(非硅晶)薄膜晶体管或者Poly-Si(多晶硅)薄膜晶体管，其中Poly-Si薄膜晶体管可以采用LTPS(Low Temperature Poly-Silicon，低温多晶硅) 等技术加以形成。
在一可选实施例中，第一阵列基板行驱动电路30和第二阵列基板行驱动电路40还包括信号总线（图未示出），信号总线设置于第一基板21上，且位于非显示区域BB内，信号总线连接第一阵列基板行驱动电路30和时序控制器11，以及连接第二阵列基板行驱动电路40和时序控制器11，并位于第一阵列基板行驱动电路30和第二阵列基板行驱动电路40远离显示区域AA的一侧。通过信号总线可以向第一阵列基板行驱动电路30和第二阵列基板行驱动电路40提供时钟信号使能控制信号等。第一阵列基板行驱动电路30和第二阵列基板行驱动电路40还可以包括级联的移位寄存器，每一级移位寄存器连接显示区域AA内的一条扫描线。
本申请还提出一种显示模组，所述显示模组包括：
控制芯片10，具有第一控制信号输出端及第二控制信号输出端；
显示面板20，所述显示面板20具有相对设置的两侧，所述显示面板20包括像素阵列24；
第一阵列基板行驱动电路(Gate Driver on Array，GOA)电路及第二阵列基板行驱动电路40，分设于所述显示面板20的两侧；所述第一阵列基板行驱动电路30及所述第二阵列基板行驱动电路40均具有使能端，所述第一阵列基板行驱动电路30的使能端及所述第二阵列基板行驱动电路40的使能端与所述第一控制信号输出端及第二控制信号输出端一一对应连接；
所述第一阵列基板行驱动电路30包括多个级联第一阵列基板行驱动单元电路，所述第二阵列基板行驱动电路40包括多个级联第二阵列基板行驱动单元电路（321~32N）；
每个所述第一阵列基板行驱动单元电路，配置为在接收到所述控制芯片10输出的控制信号时，逐级输出第一扫描信号，以控制对应的所述像素阵列24导通；
每个所述第二阵列基板行驱动单元电路（321~32N），配置为在接收到所述控制芯片10输出的控制信号时，逐级输出第二扫描信号，以控制对应的所述像素阵列24导通。
本申请显示模组将第一阵列基板行驱动电路30和第二阵列基板行驱动电路40分设于显示面板20的两侧，并通过控制芯片10根据检测后的第一阵列基板行驱动电路30和第二阵列基板行驱动电路40良好与否，从而输出不同的控制信号至第一阵列基板行驱动电路30和第二阵列基板行驱动电路40的使能端，以控制第一阵列基板行驱动电路30工作，第二阵列基板行驱动电路40不工作，或者第一阵列基板行驱动电路30不工作，第二阵列基板行驱动电路40工作，或者第一阵列基板行驱动电路30和第二阵列基板行驱动电路40两者同时工作，本申请可以独立控制左右两侧的阵列基板行驱动电路 circuit（第一阵列基板行驱动电路30和第二阵列基板行驱动电路40）的工作状态，从而使得对显示面板20单边阵列基板行驱动电路驱动和双边阵列基板行驱动电路驱动均可实现。本申请实现了在阵列基板行驱动电路 circuit有单边损坏时，使用另一边的阵列基板行驱动电路 circuit来驱动整个面板的像素阵列24工作，提升了显示面板20的良率，解决了在一侧的阵列基板行驱动电路不能正常工作，导致整个显示面板20只有报废处理，使得整个显示面板20的无法使用，而增大显示面板20的不良率的问题。其中，多个第一阵列基板行驱动单元电路和第二阵列基板行驱动单元电路（321~32N）用于驱动像素阵列24中对应行的薄膜晶体管导通，以对像素电容进行充电。
本申请还包括一种显示装置，包括如上所述的显示模组。该显示模组的详细结构可参照上述实施例，此处不再赘述；可以理解的是，由于在本申请显示装置中使用了上述显示模组，因此，本申请显示装置的实施例包括上述显示模组全部实施例的全部技术方案，且所达到的技术效果也完全相同，在此不再赘述。
在一些实施例中，显示装置还包括背光模组，该背光模组与显示模组可以相对设置，或者背光模组与显示模组一体设置。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的申请构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (18)

  1. 一种显示模组，其中，所述显示模组包括：
    控制芯片，具有第一控制信号输出端及第二控制信号输出端；
    显示面板，所述显示面板具有相对设置的两侧，所述显示面板包括像素阵列；
    第一阵列基板行驱动电路及第二阵列基板行驱动电路，分设于所述显示面板的两侧；所述第一阵列基板行驱动电路及所述第二阵列基板行驱动电路均具有使能端，所述第一阵列基板行驱动电路的使能端及所述第二阵列基板行驱动电路的使能端与所述第一控制信号输出端及第二控制信号输出端一一对应连接；
    所述第一阵列基板行驱动电路和/或所述第二阵列基板行驱动电路，配置为在接收到所述控制芯片输出的控制信号时，驱动所述像素阵列工作。
  2. 如权利要求1所述的显示模组，其中，所述控制芯片包括时序控制器及电平转移器，所述时序控制器的多个输出端与所述电平转移器的多个输入端一一对应连接，所述电平转移器的多个输出端分别与所述第一阵列基板行驱动电路的使能端及所述第二阵列基板行驱动电路的使能端一一对应连接；
    所述时序控制器，配置为输出控制信号；
    所述电平转移器，配置为将所述时序控制器输出的控制信号进行电平转换后输出至对应的所述第一阵列基板行驱动电路或所述第二阵列基板行驱动电路。
  3. 如权利要求2所述的显示模组，其中，所述时序控制器输出的控制信号包括第一控制信号、第二控制信号及第三控制信号；
    所述第一控制信号、第二控制信号及第三控制信号经所述电平转移器转换后，输出至所述第一阵列基板行驱动电路或所述第二阵列基板行驱动电路；
    在接收到所述第一控制信号时，所述第一阵列基板行驱动电路驱动所述像素阵列工作；
    在接收到所述第二控制信号时，所述第二阵列基板行驱动电路驱动所述像素阵列工作；
    在接收到第三控制信号时，所述第一阵列基板行驱动电路和所述第二阵列基板行驱动电路同时驱动所述像素阵列工作。
  4. 如权利要求2所述的显示模组，其中，所述显示模组还包括驱动电源，所述驱动电源的输出端与所述电平转换器的电源转换端连接；
    所述电平转换器，还配置为将接收到所述驱动电源输出的电源信号转换为栅极开启信号或者栅极关断信号。
  5. 如权利要求1所述的显示模组，其中，所述第一阵列基板行驱动电路包括多个级联第一阵列基板行驱动单元电路，每个所述第一阵列基板行驱动单元电路的输出端逐级输出第一扫描信号，以控制对应的所述像素阵列导通。
  6. 如权利要求5所述的显示模组，其中，每个所述第一阵列基板行驱动单元电路均包括上拉控制子电路、上拉子电路、下拉子电路以及下拉维持子电路，所述上拉子电路的输入端与所述上拉控制子电路输出端连接，所述下拉子电路分别与上拉控制子电路以及上拉子电路的输出端连接。
  7. 如权利要求1所述的显示模组，其中，所述第二阵列基板行驱动电路包括多个级联第二阵列基板行驱动单元电路，每个所述第二阵列基板行驱动单元电路的输出端逐级输出第二扫描信号，以驱动对应的所述像素阵列导通。
  8. 如权利要求7所述的显示模组，其中，每个所述第一阵列基板行驱动单元电路均包括上拉控制子电路、上拉子电路、下拉子电路以及下拉维持子电路，所述上拉子电路的输入端与所述上拉控制子电路输出端连接，所述下拉子电路分别与上拉控制子电路以及上拉子电路的输出端连接。
  9. 如权利要求1所述的显示模组，其中，所述显示面板还包括：
    第一基板，具有显示区域与周边区域；所述像素阵列设置于所述第一基板上且位于所述显示区域；所述第一阵列基板行驱动电路和所述第二阵列基板行驱动电路设置于所述第一基板上且位于所述周边区域；
    第二基板，与所述第一基板相对设置；
    液晶层，设置于所述第一基板与所述第二基板之间，所述液晶层包括若干液晶分子，所述像素阵列用于控制所述若干液晶分子的动作。
  10. 如权利要求9所述的显示模组，其中，所述像素阵列包括多个子像素，每一所述子像素均包括一主动开关及一像素电极，所述主动开关的栅极与该子像素对应的扫描线电性连接，所述主动开关的源极与该子像素对应的数据线电性连接，所述主动开关的漏极与该子像素的像素电极电性连接。
  11. 如权利要求9所述的显示模组，其中，所述第一基板与所述第二基板通常均为透光材料基板。
  12. 如权利要求9所述的显示模组，其中，所述显示面板还包括框胶，所述框胶设置于所述第一基板与所述第二基板之间的非显示区域内并环绕所述液晶层设置，所述第一阵列基板行驱动电路和所述第二阵列基板行驱动电路位于所述框胶与所述显示区域之间。
  13. 如权利要求9所述的显示模组，其中，所述第一阵列基板行驱动电路和所述第二阵列基板行驱动电路还包括信号总线，所述信号总线设置于所述第一基板上，且位于所述非显示区域内，所述信号总线连接所述第一阵列基板行驱动电路和所述时序控制器，以及连接所述第二阵列基板行驱动电路和所述时序控制器。
  14. 如权利要求1所述的显示模组，其中，所述显示面板为有机发光二极管显示面板或者薄膜晶体管液晶显示面板。
  15. 如权利要求1所述的显示模组，其中，所述显示面板的驱动电路包括片上系统驱动电路或者阵列基板行驱动电路。
  16. 一种显示模组，其中，所述显示模组包括：
    控制芯片，具有第一控制信号输出端及第二控制信号输出端；
    显示面板，所述显示面板具有相对设置的两侧，所述显示面板包括像素阵列；
    第一阵列基板行驱动电路及第二阵列基板行驱动电路，分设于所述显示面板的两侧；所述第一阵列基板行驱动电路及所述第二阵列基板行驱动电路均具有使能端，所述第一阵列基板行驱动电路的使能端及所述第二阵列基板行驱动电路的使能端与所述第一控制信号输出端及第二控制信号输出端一一对应连接；
    所述第一阵列基板行驱动电路包括多个级联第一阵列基板行驱动单元电路，所述第二阵列基板行驱动电路包括多个级联第二阵列基板行驱动单元电路；
    每个所述第一阵列基板行驱动单元电路，配置为在接收到所述控制芯片输出的控制信号时，逐级输出第一扫描信号，以控制对应的所述像素阵列导通；
    每个所述第二阵列基板行驱动单元电路，配置为在接收到所述控制芯片输出的控制信号时，逐级输出第二扫描信号，以控制对应的所述像素阵列导通。
  17. 一种显示装置，其中，包括显示模组；所述显示模组包括：
    控制芯片，具有第一控制信号输出端及第二控制信号输出端；
    显示面板，所述显示面板具有相对设置的两侧，所述显示面板包括像素阵列；
    第一阵列基板行驱动电路及第二阵列基板行驱动电路，分设于所述显示面板的两侧；所述第一阵列基板行驱动电路及所述第二阵列基板行驱动电路均具有使能端，所述第一阵列基板行驱动电路的使能端及所述第二阵列基板行驱动电路的使能端与所述第一控制信号输出端及第二控制信号输出端一一对应连接；
    所述第一阵列基板行驱动电路和/或所述第二阵列基板行驱动电路，配置为在接收到所述控制芯片输出的控制信号时，驱动所述像素阵列工作。
  18. 如权利要求17所述的显示装置，其中，所述显示装置还包括背光模组，所述背光模组与所述显示模组相对设置；或者，所述背光模组与所述显示模组一体设置。
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