WO2019056446A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2019056446A1
WO2019056446A1 PCT/CN2017/107176 CN2017107176W WO2019056446A1 WO 2019056446 A1 WO2019056446 A1 WO 2019056446A1 CN 2017107176 W CN2017107176 W CN 2017107176W WO 2019056446 A1 WO2019056446 A1 WO 2019056446A1
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WIPO (PCT)
Prior art keywords
gate signal
array substrate
signal lines
goa
electrostatic conduction
Prior art date
Application number
PCT/CN2017/107176
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English (en)
French (fr)
Inventor
洪光辉
Original Assignee
武汉华星光电技术有限公司
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Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US15/740,239 priority Critical patent/US10833065B2/en
Publication of WO2019056446A1 publication Critical patent/WO2019056446A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/22—Antistatic materials or arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a display panel.
  • the accumulation of static charges is usually generated in the panel due to certain external factors such as continuous process operation and handling or environmental changes. Since the glass itself is an insulating material, the static charge will remain on the surface of the substrate until a suitable discharge path is provided. When the static charge accumulates to a certain amount, a discharge will occur (ESD, Electrostatic) Discharge).
  • ESD Electrostatic
  • Electrostatic discharge occurs for a short period of time. A large amount of charge is transferred in a short period of time, which will generate extremely high current, break down the semiconductor device, or generate enough heat to melt the semiconductor device. This hazard is usually in an imperceptible situation. The downgrading of some components causes or is scrapped, resulting in greater economic losses. Therefore, electrostatic discharge can cause fatal damage to electronic products, which not only reduces the reliability of the product, but also increases the maintenance cost. Each year, electrostatic discharge can cost the electronics manufacturing industry billions of dollars.
  • GOA Gate Driver on Array
  • TFT Thin Film Transistor
  • the GOA circuit has two basic functions: the first is to output the gate scan drive signal, drive the gate line in the panel, open the TFT in the display area to charge the pixel; the second is the shift register function, when a gate After the output of the polar scan drive signal is completed, the output of the next gate scan drive signal is performed by clock control, and is sequentially transmitted.
  • GOA technology can reduce the bonding process of external ICs, have the opportunity to increase production capacity and reduce product cost, and can make LCD panels more suitable for making narrow-frame display products.
  • the existing array substrate is not designed with an anti-static unit, and the Gate layer is easy to attract the circuit. Once a row of Gate generates static electricity, no static electricity is released, which may cause the Pixel (pixel) of the display area to be injured or the GOA circuit to be hit. Injury, this will eventually affect the normal function of the panel and thus reduce the yield of the product.
  • the technical problem to be solved by the present invention is to provide an array substrate and a display panel.
  • the electrostatic conduction device is provided to turn on the gate signal lines to resist static electricity, thereby improving the ability of the array substrate to resist ESD.
  • the first technical solution adopted by the present invention is to provide an array substrate, the array substrate comprising: a GOA unit; a plurality of gate signal lines, the plurality of gate signal lines and the GOA unit Electrical connection; an electrostatic conduction device electrically connected between the plurality of gate signal lines to electrically connect the plurality of gate signal lines to each other; wherein the array substrate comprises a non-display area
  • the GOA unit and the electrostatic conduction device are located in the non-display area, the GOA unit includes a plurality of GOA sub-units, and the plurality of gate signal lines are electrically connected to the plurality of GOA sub-units one by one.
  • the second technical solution adopted by the present invention is to provide an array substrate, the array substrate comprising: a GOA unit; a plurality of gate signal lines, the plurality of gate signal lines and the GOA unit Electrical connection; an electrostatic conduction device electrically connected between the plurality of gate signal lines to electrically connect the plurality of gate signal lines to each other.
  • the third technical solution adopted by the present invention is to provide a display panel, and the display panel includes the above array substrate.
  • the invention has the beneficial effects that: different from the prior art, the present invention provides an electrostatic conduction device between the gate signal lines, electrically connecting the gate signal lines together to resist ESD, thereby improving the ESD resistance of the array substrate. To improve product quality.
  • FIG. 1 is a schematic structural view of a first embodiment of an array substrate of the present invention
  • FIG. 2 is a schematic structural view of a second embodiment of the array substrate of the present invention.
  • FIG. 3 is a schematic structural view of a third embodiment of the array substrate of the present invention.
  • FIG. 4 is a partial structural schematic view of a fourth embodiment of the array substrate of the present invention.
  • Fig. 5 is a partial structural schematic view showing a fifth embodiment of the array substrate of the present invention.
  • FIG. 1 is a schematic structural view of a first embodiment of an array substrate of the present invention.
  • the array substrate is divided into a display area 11 and a non-display area 12.
  • the array substrate includes a GOA unit 101, a plurality of gate signal lines 102, and an electrostatic conduction device.
  • the GOA unit 101 includes a plurality of GOA sub-units 1011, and the gate signal line 102 is electrically connected to the plurality of GOA sub-units 1011.
  • the electrostatic conduction device is electrically connected between the plurality of gate signal lines 102 to electrically connect the gate signal lines 102 to each other.
  • the GOA units are distributed on both sides of the array substrate. In other embodiments, the GOA units may be distributed only on one side of the array substrate, which is not limited in the present invention.
  • the electrostatic conduction device is the TFT device 103.
  • the TFT device 103 and the GOA unit 101 are both located in the non-display area 12.
  • the GOA unit 101 includes a plurality of GOA sub-units 1011 having a plurality of gate signal lines 102, and the GOA sub-units 1011 and the gate signal lines 102 are electrically connected one by one.
  • the TFT device 103 includes a source 1031, a drain 1032, and a gate 1033.
  • the source 1031 is connected to one gate signal line 102
  • the drain 1032 is connected to another adjacent gate signal line 102
  • the gate 1033 is suspended. In normal operation, the resistance between the source 1031 and the drain 1032 is relatively large, and does not affect the normal operation of the panel.
  • the TFT device 103 does not affect the potential between the adjacent gate signal lines 102 during normal operation. However, once ESD occurs in one or several rows of gate signal lines 102, The TFT device 103 acts as a static conduction so that all of the gate signal lines 102 of the entire panel together resist ESD, thereby significantly improving the ESD resistance of the array substrate.
  • the two gate signal lines 102 to which the TFT device 103 is connected may not be adjacent.
  • the number of the TFT devices 103 between the two gate signal lines 102 may be two or more.
  • the two or more TFT devices 103 may be connected in parallel or in series, which is not limited in the present invention.
  • two TFT devices 103 are connected in series and connected between the two gate signal lines 102.
  • two TFT devices 103 are connected in parallel and connected between the two gate signal lines 102, and the other TFT device 103 is directly connected between the two gate signal lines 102.
  • the present invention provides an electrostatic conduction device between the gate signal lines to electrically connect the gate signal lines together to resist ESD, thereby improving the ESD resistance of the array substrate, thereby improving product quality.
  • FIG. 2 is a schematic structural view of a second embodiment of the array substrate of the present invention.
  • the array substrate is divided into a display area 21 and a non-display area 22.
  • the array substrate includes a GOA unit 201, a plurality of gate signal lines 202, and an electrostatic conduction device.
  • the GOA unit 201 includes a plurality of GOA subunits 2011, and the gate signal line 202 is electrically connected to the plurality of GOA subunits 2011.
  • the electrostatic conduction device is electrically connected between the plurality of gate signal lines 202 to electrically connect the gate signal lines 202 to each other.
  • the GOA units are distributed on both sides of the array substrate. In other embodiments, the GOA units may be distributed only on one side of the array substrate, which is not limited in the present invention.
  • the electrostatic conduction device is a diode ring 203.
  • Diode ring 203 and GOA unit 201 are both located in non-display area 22.
  • the GOA unit 201 includes a plurality of GOA sub-units 2011, and there are a plurality of gate signal lines 202.
  • the GOA sub-units 2011 and the gate signal lines 202 form an electrical connection one by one.
  • the diode ring 203 has two conduction paths that can conduct positive and negative charges, respectively. In normal operation, the resistance of the diode ring 203 is relatively large and does not affect the normal operation of the panel. That is, during normal operation, the diode ring 203 does not affect the potential between adjacent gate signal lines 202.
  • the diode ring 203 acts as a static conduction, its positive charge conduction path conducts a positive charge, and the negative charge conduction path conducts a negative charge, so that the entire All of the gate signal lines 202 on the array substrate together resist ESD, thereby significantly increasing the ESD resistance of the array substrate.
  • the connected two gate signal lines 202 of the diode ring 203 may not be adjacent.
  • the number of the diode rings 203 between the two gate signal lines 202 may also be two or more.
  • the two or more diode rings 203 may be connected in parallel or in series, which is not limited in the present invention.
  • two diode rings 203 are connected in series and connected between the two gate signal lines 202.
  • two diode rings 203 are connected in parallel and connected between the two gate signal lines 202, and the other diode ring 203 is directly connected between the two gate signal lines 202.
  • the present invention provides an electrostatic conduction device between the gate signal lines to electrically connect the gate signal lines together to resist ESD, thereby improving the ESD resistance of the array substrate, thereby improving product quality.
  • FIG. 3 is a schematic structural view of a third embodiment of the array substrate of the present invention.
  • the array substrate is divided into a display area 31 and a non-display area 32.
  • the array substrate includes a GOA unit 301, a plurality of gate signal lines 302, and an electrostatic conduction device.
  • the GOA unit 301 includes a plurality of GOA sub-units 3011, and the gate signal line 302 is electrically connected to the plurality of GOA sub-units 3011.
  • the electrostatic conduction device is electrically connected between the plurality of gate signal lines 302 to electrically connect the gate signal lines 302 to each other.
  • the GOA units are distributed on both sides of the array substrate. In other embodiments, the GOA units may be distributed only on one side of the array substrate, which is not limited in the present invention.
  • the electrostatic conduction device is a Poly resistor 303.
  • Poly resistor 303 and GOA unit 301 are both located in non-display area 32.
  • the GOA unit 301 includes a plurality of GOA sub-units 3011, and there are a plurality of gate signal lines 302.
  • the GOA sub-unit 3011 and the gate signal line 302 form an electrical connection one by one.
  • the resistance of the Poly resistor 303 is relatively large and does not affect the normal operation of the panel. That is, during normal operation, the Poly resistor 303 does not affect the potential between adjacent gate signal lines 302.
  • the Poly resistor 303 acts as a static conduction, so that all the gate signal lines 302 on the entire array substrate together resist ESD, thereby significantly increasing the array substrate. Anti-ESD capabilities.
  • the two gate signal lines 302 connected to the Poly resistor 303 may not be adjacent.
  • the number of the Poly resistors 303 between the two gate signal lines 302 may also be two or more.
  • the two or more Poly resistors 303 may be connected in parallel or in series, which is not limited in the present invention.
  • FIG. 4 is a partial structural schematic view of a fourth embodiment of the array substrate of the present invention.
  • the schematic structural view of this embodiment is substantially similar to the structural schematic of the third embodiment. However, this embodiment is partially different from the third embodiment, and a partial schematic view thereof is shown in FIG. 4.
  • the Poly resistor 403 between the two gate signal lines 402 includes a first Poly resistor 4031, a second Poly resistor 4032, and a third Poly resistor 4033.
  • the first Poly resistor 4031 and the second Poly resistor 4032 and the third Poly resistor 4033 are connected in series and connected between the two gate signal lines 402.
  • FIG. 5 is a partial structural schematic view of a fifth embodiment of the array substrate of the present invention.
  • the schematic structural view of this embodiment is substantially similar to the structural schematic of the third embodiment. However, this embodiment is partially different from the third embodiment, and a partial schematic view thereof is shown in FIG. 5.
  • the Poly resistor 503 between the two gate signal lines 502 includes a first Poly resistor 5031, a second Poly resistor 5032, and a third Poly resistor 5033.
  • the first Poly resistor 5031 and the second Poly resistor 5032 and the third Poly resistor 5033 are connected in parallel between the two gate signal lines 502.
  • the resistance is still relatively large with respect to the conductive device in the circuit, and does not affect the normal operation of the panel. That is, during normal operation, the Poly resistor 503 does not affect the potential between adjacent gate signal lines 502. However, once ESD occurs in one or several rows of gate signal lines 502, The Poly resistor 503 acts as a static conduction so that all of the gate signal lines 502 on the entire array substrate together resist ESD. Therefore, the ESD resistance of the array substrate can be significantly improved. At the same time, since there are multiple Ploy resistors connected in parallel, even if one Ploy resistor damages the electrostatic conduction device of the present invention, it can work normally and protect the circuit.
  • the array substrate of the present invention can significantly improve the ESD resistance of the array substrate by providing a Poly resistor between the gate signal lines and connecting the gate signal lines together to resist ESD.
  • the array substrate described in the present invention can be applied to a display panel and a display device.

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Abstract

一种阵列基板及显示面板，该阵列基板包括：GOA单元（101）；若干栅极信号线（102），该若干栅极信号线（102）与该GOA单元（101）电连接；静电导通装置（103），该静电导通装置（103）电连接在该若干栅极信号线（102）之间，使该若干栅极信号线（102）相互形成电连接。阵列基板通过在栅极信号线（102）之间设置静电导通装置（103），将栅极信号线（102）连接在一起共同抵抗ESD，可以明显提高阵列基板的抗ESD能力，提高产品质量。

Description

阵列基板及显示面板
【技术领域】
本发明涉及显示技术领域，特别是涉及一种阵列基板及显示面板。
【背景技术】
在显示面板的生产制程中，由于某些外在因素，例如连续的工艺操作以及搬运或者环境变化等，通常会在面板中产生静电荷的积累。由于玻璃本身是绝缘物质，因此除非有适当的放电通道，否则静电荷会一直停留在基板表面。当静电荷积累到一定数量之后，将会产生放电(ESD，Electrostatic Discharge)。
静电放电发生时的时间很短，大量的电荷在很短的时间内发生转移将产生极高的电流，击穿半导体器件，或者产生足够的热量融化半导体器件，这种危害通常在不易察觉的情况下引起部分元器件的降级或者报废，带来较大的经济损失。因此，静电放电会给电子产品带来致命的危害，它不仅降低了产品的可靠性，还增加了维修成本。每年静电放电会给电子制造工业带来数十亿美元的损失。
GOA(Gate Driver on Array)技术即阵列基板行驱动技术，是利用薄膜晶体管(Thin Film Transistor，TFT)液晶显示器阵列制程将栅极扫描驱动电路制作在薄膜晶体管阵列基板上，以实现逐行扫描的驱动方式，具有降低生产成本和实现面板窄边框设计的优点，为多种显示器所使用。
GOA电路具有两项基本功能：第一是输出栅极扫描驱动信号，驱动面板内的栅极线，打开显示区内的TFT，以对像素进行充电；第二是移位寄存功能，当一个栅极扫描驱动信号输出完成后，通过时钟控制进行下一个栅极扫描驱动信号的输出，并依次传递下去。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框的显示产品。
现有的阵列基板没有设计防静电单元，而Gate走线层很容易吸引电路，一旦一行Gate发生静电，静电无处释放，就会导致显示区域的Pixel（像素）被击伤或者GOA电路被击伤，这样最终会影响面板的正常功能进而降低产品的良率。
因此，提供一种改进的阵列基板及显示面板实为必要。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及显示面板，通过设置静电导通装置来导通栅极信号线共同抵抗静电，提高阵列基板抗ESD的能力。
为解决上述技术问题，本发明采用的第一个技术方案是：提供一种阵列基板，所述阵列基板包括：GOA单元；若干栅极信号线，所述若干栅极信号线与所述GOA单元电连接；静电导通装置，所述静电导通装置电连接在所述若干栅极信号线之间，使所述若干栅极信号线相互形成电连接；其中，所述阵列基板包括非显示区，所述GOA单元和静电导通装置位于所述非显示区,所述GOA单元包括若干GOA子单元，所述若干栅极信号线与所述若干GOA子单元一一形成电连接。
为解决上述技术问题，本发明采用的第二个技术方案是：提供一种阵列基板，所述阵列基板包括：GOA单元；若干栅极信号线，所述若干栅极信号线与所述GOA单元电连接；静电导通装置，所述静电导通装置电连接在所述若干栅极信号线之间，使所述若干栅极信号线相互形成电连接。
为解决上述技术问题，本发明采用的第三个技术方案是：提供一种显示面板，所述显示面板包括上述阵列基板。
本发明的有益效果是：区别于现有技术，本发明在栅极信号线之间设置静电导通装置，将栅极信号线电连接在一起，共同抵抗ESD，从而提高阵列基板的抗ESD能力，从而提高产品质量。
【附图说明】
图1是本发明阵列基板第一实施方式的结构示意图；
图2是本发明阵列基板第二实施方式的结构示意图；
图3是本发明阵列基板第三实施方式的结构示意图；
图4是本发明阵列基板第四实施方式的局部结构示意图；
图5是本发明阵列基板第五实施方式的局部结构示意图。
【具体实施方式】
参阅图1，图1是本发明阵列基板第一实施方式的结构示意图。
如图1所示，该阵列基板分为显示区11和非显示区12。该阵列基板包括GOA单元101、若干栅极信号线102以及静电导通装置。进一步的，GOA单元101包括若干GOA子单元1011，栅极信号线102与若干GOA子单元1011一一形成电连接。静电导通装置电连接在若干栅极信号线102之间，使栅极信号线102相互形成电连接。需要说明的是，在本实施方式中，GOA单元分布于该阵列基板的两侧，其他实施方式中，GOA单元也可以只分布于该阵列基板的一侧，本发明对此不作限定。
在本实施方式中，静电导通装置是TFT器件103。TFT器件103和GOA单元101均位于非显示区12。GOA单元101包括若干GOA子单元1011，栅极信号线102有若干条，GOA子单元1011和栅极信号线102一一形成电连接。TFT器件103包括源极1031、漏极1032以及栅极1033。源极1031与一条栅极信号线102连接，漏极1032与另一条相邻的栅极信号线102连接，栅极1033悬空。在正常工作时，源极1031和漏极1032之间的电阻比较大，不会影响面板的正常工作。也就是说，在正常工作时，TFT器件103对相邻栅极信号线102之间的电位不会有影响。但是，一旦一行或几行栅极信号线102发生ESD时， TFT器件103会起到静电导通作用，使得整个面板的所有栅极信号线102一起抵抗ESD，因此可显著提高阵列基板的抗ESD能力。
在其他实施方式中，TFT器件103所连接的两条栅极信号线102也可以不相邻。两条栅极信号线102之间的TFT器件103的个数也可以是两个或以上，这两个或以上的TFT器件103可以并联也可以串联，本发明对此均不作限定。例如，将2个TFT器件103串联后连接在两条栅极信号线102之间。再例如，将2个TFT器件103并联后连接在两条栅极信号线102之间，另一个TFT器件103直接连接在两条栅极信号线102之间。
区别于现有技术，本发明在栅极信号线之间设置静电导通装置，将栅极信号线电连接在一起，共同抵抗ESD，从而提高阵列基板的抗ESD能力，从而提高产品质量。
参阅图2，图2是本发明阵列基板第二实施方式的结构示意图。
如图2所示，该阵列基板分为显示区21和非显示区22。该阵列基板包括GOA单元201、若干栅极信号线202以及静电导通装置。进一步的，GOA单元201包括若干GOA子单元2011，栅极信号线202与若干GOA子单元2011一一形成电连接。静电导通装置电连接在若干栅极信号线202之间，使栅极信号线202相互形成电连接。需要说明的是，在本实施方式中，GOA单元分布于该阵列基板的两侧，其他实施方式中，GOA单元也可以只分布于该阵列基板的一侧，本发明对此不作限定。
在本实施方式中，静电导通装置是二极管环203。二极管环203和GOA单元201均位于非显示区22。GOA单元201包括多个GOA子单元2011，栅极信号线202有多条，GOA子单元2011和栅极信号线202一一形成电连接。二极管环203有两种导通路径，分别可以导通正电荷和负电荷。在正常工作时，二极管环203的电阻比较大，不会影响面板的正常工作。也就是说，在正常工作时，二极管环203对相邻栅极信号线202之间的电位不会有影响。但是，一旦一行或几行栅极信号线202发生ESD时，二极管环203会起到静电导通作用，其正电荷导通路径导通正电荷，负电荷导通路径导通负电荷，使得整个阵列基板上的所有栅极信号线202一起抵抗ESD，因此可显著提高阵列基板的抗ESD能力。
在其他实施方式中，二极管环203的所连接的两条栅极信号线202也可以不相邻。两条栅极信号线202之间的二极管环203的个数也可以是两个或以上，这两个或以上的二极管环203可以并联也可以串联，本发明对此均不作限定。例如，将两个二极管环203串联后连接在两条栅极信号线202之间。再例如，将两个二极管环203并联后连接在两条栅极信号线202之间，另一个二极管环203直接连接在两条栅极信号线202之间。
区别于现有技术，本发明在栅极信号线之间设置静电导通装置，将栅极信号线电连接在一起，共同抵抗ESD，从而提高阵列基板的抗ESD能力，从而提高产品质量。
参阅图3，图3是本发明阵列基板第三实施方式的结构示意图。
如图3所示，该阵列基板分为显示区31和非显示区32。该阵列基板包括GOA单元301、若干栅极信号线302以及静电导通装置。进一步的，GOA单元301包括若干GOA子单元3011，栅极信号线302与若干GOA子单元3011一一形成电连接。静电导通装置电连接在若干栅极信号线302之间，使栅极信号线302相互形成电连接。需要说明的是，在本实施方式中，GOA单元分布于该阵列基板的两侧，其他实施方式中，GOA单元也可以只分布于该阵列基板的一侧，本发明对此不作限定。
在本实施方式中，静电导通装置是Poly电阻303。Poly电阻303和GOA单元301均位于非显示区32。GOA单元301包括多个GOA子单元3011，栅极信号线302有多条，GOA子单元3011和栅极信号线302一一形成电连接。在正常工作时，Poly电阻303的电阻比较大，不会影响面板的正常工作。也就是说，在正常工作时，Poly电阻303对相邻栅极信号线302之间的电位不会有影响。但是，一旦一行或几行栅极信号线302发生ESD时，Poly电阻303会起到静电导通作用，使得整个阵列基板上的所有栅极信号线302一起抵抗ESD，因此可显著提高阵列基板的抗ESD能力。
在其他实施方式中，Poly电阻303所连接的两条栅极信号线302也可以不相邻。两条栅极信号线302之间的Poly电阻303的个数也可以是两个或以上，这两个或以上Poly电阻303可以并联也可以串联，本发明对此均不作限定。
参阅图4，图4是本发明阵列基板第四实施方式的局部结构示意图。
该实施方式的结构示意图与第三实施方式的结构示意图基本类似。但是该实施方式与第三实施方式局部有所不同，其局部示意图如图4所示。
在本实施例中，两条栅极信号线402之间的Poly电阻403包括第一Poly电阻4031、第二Poly电阻4032和第三Poly电阻4033。第一Poly电阻4031和第二Poly电阻4032以及第三Poly电阻4033串联后连接在两条栅极信号线402之间。
在正常工作时，由于第一Poly电阻4031和第二Poly电阻4032以及第三Poly电阻4033串联，所以电阻相对于电路中的导电装置较大，不会影响面板的正常工作。也就是说，在正常工作时，Poly电阻403对相邻栅极信号线402之间的电位不会有影响。但是，一旦一行或几行栅极信号线402发生ESD时，Poly电阻403会起到静电导通作用，使得整个阵列基板上的所有栅极信号线402一起抵抗ESD。
参阅图5，图5是本发明阵列基板第五实施方式的局部结构示意图。
该实施方式的结构示意图与第三实施方式的结构示意图基本类似。但是该实施方式与第三实施方式局部有所不同，其局部示意图如图5所示。
在本实施例中，两条栅极信号线502之间的Poly电阻503包括第一Poly电阻5031、第二Poly电阻5032和第三Poly电阻5033。第一Poly电阻5031和第二Poly电阻5032以及第三Poly电阻5033并联在在两条栅极信号线502之间。
在正常工作时，虽然第一Poly电阻5031和第二Poly电阻5032以及第三Poly电阻5033并联，但是电阻相对于电路中的导电装置仍然较大，不会影响面板的正常工作。也就是说，在正常工作时，Poly电阻503对相邻栅极信号线502之间的电位不会有影响。但是，一旦一行或几行栅极信号线502发生ESD时， Poly电阻503会起到静电导通作用，使得整个阵列基板上的所有栅极信号线502一起抵抗ESD。因此可显著提高阵列基板的抗ESD能力。同时，由于有多个Ploy电阻并联，即使有一个Ploy电阻损坏本发明的静电导通装置仍然可以正常工作，对电路起保护作用。
区别于现有技术，本发明中的阵列基板通过在栅极信号线之间设置Poly电阻，将栅极信号线连接在一起共同抵抗ESD，可以明显提高阵列基板的抗ESD能力。
本发明中所述的阵列基板可以应用到显示面板和显示装置中。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板包括：
    GOA单元；
    若干栅极信号线，所述若干栅极信号线与所述GOA单元电连接；
    静电导通装置，所述静电导通装置电连接在所述若干栅极信号线之间，使所述若干栅极信号线相互形成电连接；
    其中，所述阵列基板包括非显示区，所述GOA单元和静电导通装置位于所述非显示区,所述GOA单元包括若干GOA子单元，所述若干栅极信号线与所述若干GOA子单元一一形成电连接。
  2. 根据权利要求1所述的阵列基板，其中，所述静电导通装置是TFT器件，所述TFT器件的源极和和漏极分别与相邻两条所述栅极信号线连接，所述TFT器件的栅极悬空。
  3. 一种阵列基板，其中，所述阵列基板包括：
    GOA单元；
    若干栅极信号线，所述若干栅极信号线与所述GOA单元电连接；
    静电导通装置，所述静电导通装置电连接在所述若干栅极信号线之间，使所述若干栅极信号线相互形成电连接。
  4. 根据权利要求3所述的阵列基板，其中，所述GOA单元包括若干GOA子单元，所述若干栅极信号线与所述若干GOA子单元一一形成电连接。
  5. 根据权利要求3所述的阵列基板，其中，所述静电导通装置是TFT器件，所述TFT器件的源极和和漏极分别与相邻两条所述栅极信号线连接，所述TFT器件的栅极悬空。
  6. 根据权利要求5所述的阵列基板，其中，所述TFT器件的个数是两个或以上，且所述TFT器件相互串联。
  7. 根据权利要求3所述的阵列基板，其中，所述静电导通装置是二级管环，所述二极管环有两种静电导通路径，可以导通正电荷和负电荷。
  8. 根据权利要求7所述的阵列基板，其中，所述二极管环的个数是两个或以上，所述二极管环并联。
  9. 根据权利要求3所述的阵列基板，其中，所述静电导通装置是Poly电阻。
  10. 根据权利要求9所述的阵列基板，其中，所述Poly电阻的个数是两个或以上，所述Ploy电阻并联。
  11. 根据权利要求3所述的阵列基板，其中，所述阵列基板包括非显示区，所述GOA单元和静电导通装置位于所述非显示区。
  12. 一种显示面板，其中，所述显示面板包括阵列基板, 所述阵列
    基板包括：
    GOA单元；
    若干栅极信号线，所述若干栅极信号线与所述GOA单元电连接；
    静电导通装置，所述静电导通装置电连接在所述若干栅极信号线之间，使所述若干栅极信号线相互形成电连接。
  13. 根据权利要求12所述的显示面板，其中，所述GOA单元包括若干GOA子单元，所述若干栅极信号线与所述若干GOA子单元一一形成电连接。
  14. 根据权利要求13所述的显示面板，其中，所述静电导通装置TFT器件，所述TFT器件的源极和和漏极分别与相邻两条所述栅极信号线连接，所述TFT器件的栅极悬空。
  15. 根据权利要求14所述的阵列基板，其中，所述TFT器件的个数是两个或以上，且所述TFT器件相互串联。
  16. 根据权利要求12所述的显示面板，其中，所述静电导通装置是二级管环，所述二极管环有两种静电导通路径，可以导通正电荷和负电荷。
  17. 根据权利要求16所述的显示面板，其中，所述二极管环的个数是两个或以上，所述二极管环并联。
  18. 根据权利要求12所述的显示面板，其中，所述静电导通装置是Poly电阻。
  19. 根据权利要求18所述的显示面板，其中，所述Poly电阻的个数是两个或以上，所述Ploy电阻并联。
  20. 根据权利要求12所述的显示面板，其中，所述阵列基板包括非显示区，所述GOA单元和静电导通装置位于所述非显示区。
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