WO2016123797A1 - 一种阵列基板、液晶显示面板及装置 - Google Patents

一种阵列基板、液晶显示面板及装置 Download PDF

Info

Publication number
WO2016123797A1
WO2016123797A1 PCT/CN2015/072423 CN2015072423W WO2016123797A1 WO 2016123797 A1 WO2016123797 A1 WO 2016123797A1 CN 2015072423 W CN2015072423 W CN 2015072423W WO 2016123797 A1 WO2016123797 A1 WO 2016123797A1
Authority
WO
WIPO (PCT)
Prior art keywords
wire
liquid crystal
conductive layer
crystal display
area
Prior art date
Application number
PCT/CN2015/072423
Other languages
English (en)
French (fr)
Inventor
付延峰
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Publication of WO2016123797A1 publication Critical patent/WO2016123797A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells

Definitions

  • the present invention relates to the field of displays, and more particularly to array substrates, liquid crystal display panels, and devices.
  • the display substrate 10 includes a plurality of data lines 11 or a plurality of scan lines 14 .
  • the display chip 12 includes a plurality of data lines 11 or a plurality of scan lines 14 . Data signals can be supplied to the data lines 11 and scan signals can be supplied to the scan lines 14; each of the drive chips 12 is connected to the data lines 11 and the scan lines 14 by wires.
  • the structure of the cross section of the wire 13 is a layered structure including a first metal layer 18, an insulating layer 15, a passivation layer 16, and a second metal layer 17, as shown in FIG.
  • the wires are arranged in a fanout.
  • such an arrangement makes the difference between the length of the wires in the peripheral region and the length of the wires in the intermediate region become larger and larger, and the difference in impedance and the resistance delay is also larger, in two adjacent
  • the wire connecting the peripheral area of the driving chip and the display area has a large impedance and a large delay of the RC, so that the display area corresponding to the lead of the peripheral area is likely to form a block chromatic aberration.
  • an array substrate comprising:
  • a display area which is formed by interleaving a plurality of data lines and a plurality of scan lines;
  • each of the driving chips being connected to the data lines and the scan lines by wires;
  • the conductive layer is disposed on the wire of the preset area, and the preset area is an area where the length of the wire is greater than a preset value.
  • the material of the conductive layer is indium tin oxide or metal.
  • two or more conductive layers are disposed on the wires.
  • the number of layers of the conductive layer is set according to the difference between the length of the wire and a preset value.
  • the thickness of the conductive layer is set according to the length of the wire.
  • the invention also provides a liquid crystal display panel comprising:
  • the array substrate is disposed opposite to the color filter substrate
  • a display area which is formed by interleaving a plurality of data lines and a plurality of scan lines;
  • each of the driving chips being connected to the data lines and the scan lines by wires;
  • the material of the conductive layer is indium tin oxide or metal.
  • liquid crystal display panel of the present invention two or more conductive layers are disposed on the wire.
  • the number of layers of the conductive layer is set according to a difference between a length of the wire and the preset value.
  • the present invention also provides a liquid crystal display device including a backlight module and a liquid crystal display panel;
  • the liquid crystal display panel includes:
  • the array substrate is disposed opposite to the color filter substrate
  • a display area which is formed by interleaving a plurality of data lines and a plurality of scan lines;
  • each of the driving chips being connected to the data lines and the scan lines by wires;
  • the conductive layer is disposed on the wire of the preset area, and the preset area is an area where the length of the wire is greater than a preset value.
  • the material of the conductive layer is indium tin oxide or a metal.
  • liquid crystal display device of the present invention two or more conductive layers are provided on the wires.
  • the thickness of the conductive layer is set according to the length of the wire.
  • the array substrate, the liquid crystal display panel and the device of the present invention reduce the impedance difference between the wires by providing a conductive layer on the wires having a long length, thereby reducing the block chromatic aberration and improving the display effect.
  • FIG. 1 is a schematic structural view of a prior art array substrate
  • FIG. 2 is a schematic cross-sectional structural view of a prior art wire
  • FIG. 3 is a schematic structural view of an array substrate of the present invention.
  • FIG. 4 is a schematic cross-sectional view of a wire of the present invention.
  • FIG. 3 is a schematic structural diagram of an array substrate according to the present invention.
  • the array substrate of the present invention includes a display area 10 and a plurality of driving chips 12, the display area 10 being formed by interleaving a plurality of data lines 11 and a plurality of scanning lines 14; a plurality of driving chips 12, Providing a data signal to the data line 11 and a scan signal to the scan line 14; each of the drive chips is connected to the data line 11 and the scan line 14 by a wire; the wires 13, 20
  • the total number of strips is equal to the total number of strips of the data line and the scan line.
  • the display region 10 may further include a thin film transistor (not shown) including a gate, a source, and a drain.
  • a gate of the thin film transistor is connected to the scan line 14, and a source of the thin film transistor is connected to the data line 11.
  • the display area may further include a plurality of pixel units, and the pixel unit may include a main pixel area or a sub-pixel area. The brightness of the main pixel area is greater than the brightness of the sub-pixel area.
  • the display area further includes a pixel electrode.
  • a preset area An area in which the length of the wire is greater than a preset value is referred to as a preset area.
  • the length of the wire 20 is greater than a preset value, and the area composed of the wire 20 is a preset area.
  • the preset value may be set according to the size of the panel, and the preset values of the different sizes of the panel are different, and the conductive layer is disposed on the wire 20 of the preset area, that is, the structure of the cross section of the wire 20 is a layer.
  • the layered structure includes a first metal layer 18, an insulating layer 15, a passivation layer 16, a second metal layer 17, and a conductive layer 21.
  • a portion of the first metal layer 18 corresponding to the display region may be used to form a gate or scan line 14 of the thin film transistor.
  • a portion of the second metal layer 17 corresponding to the display region may be used to form a source or a drain or a data line 11 of the thin film transistor.
  • the insulating layer 15 can be used to form a gate insulating layer.
  • the wire 20 includes two metal layers and one conductive layer, which is equivalent to three resistors in parallel, thereby reducing the resistance of the original wire, so that the resistance of the wire in the preset area is reduced, and further reducing the peripheral area and the inner side.
  • the difference in impedance of the area conductors avoids block chromatic aberration.
  • a plurality of conductive layers may be disposed on the wires 20 of the predetermined area.
  • a passivation layer is further disposed between two adjacent conductive layers.
  • the wires 20 are connected in parallel with a plurality of resistors, so that the resistance of the wires 20 can be further reduced, and the wires can be different according to the length of the wires.
  • the number of layers of the conductive layer is such that the difference in impedance between the conductive layers is smaller, that is, the length of the wire is compared with the predetermined value, and the larger the difference, the more the number of layers of the conductive layer is set.
  • the material of the conductive layer 21 may be metal.
  • the wire 20 has a three-layer metal structure, which is equivalent to three resistors in parallel to reduce the resistance of the original wire, thereby reducing the resistance of the wire in the preset area, and further reducing the peripheral area (the length of the wire in the peripheral area is longer) ) The difference in impedance from the middle area conductor to avoid block chromatic aberration.
  • the material of the conductive layer 21 is indium tin oxide.
  • a via hole connecting the first metal layer or the second metal layer is disposed at an edge of the display area, where the wire is connected to the data line and the scan line, so that the wire is electrically connected to the scan line or a data line, wherein the via hole is filled with a transparent conductive layer, and the material of the transparent conductive layer may be indium tin oxide, so when the material of the conductive layer 21 is the same as the material of the transparent conductive layer, the process is saved, thereby reduce manufacturing cost.
  • the driving chip 12 can be a source driving chip or a gate driving chip.
  • the driving chip 12 is a gate driving chip, it is connected to the scanning line 14.
  • the driving chip 12 is a source driving chip, it is connected to the data line 11. Minimize the difference in the input signal of each scan line or data line in the display area, and obtain a better display effect.
  • the thickness of the conductive layer 21 is set according to the length of the wire, and the longer the wire length near the edge of each driving chip in the preset region, the greater the difference in impedance of the wire, due to resistance and thickness. Correlation, the larger the thickness, the smaller the resistance value. Therefore, the longer the length of the wire, the thicker the conductive layer is formed thereon, the impedance difference can be better reduced, and the multilayer conductive layer can be avoided, thereby saving the process.
  • the array substrate of the present invention reduces the impedance difference between the wires by providing a conductive layer on the wires having a long length, thereby reducing the block chromatic aberration and improving the display effect.
  • the present invention also provides a liquid crystal display panel, comprising: a color filter substrate, a liquid crystal layer, an array substrate; the liquid crystal layer is located between the color film substrate and the array substrate; the array substrate, and the color
  • the substrate of the array substrate and the color filter substrate may be a glass substrate or a flexible plastic substrate, and the color filter substrate may include a red color film, a green color film, and a blue color film.
  • the color filter substrate may further include a black matrix and a common electrode.
  • the display area 10 is formed by a plurality of data lines 11 and a plurality of scanning lines 14 interleaved; and a plurality of driving chips 12 for the data lines 11 Providing a data signal and providing a scan signal to the scan line 14; each of the drive chips being connected to the data line 11 and the scan line 14 by a wire; the total number of the wires 13, 20 and the data The total number of lines and the scan lines is equal.
  • the display region 10 may further include a thin film transistor (not shown) including a gate, a source, and a drain.
  • a gate of the thin film transistor is connected to the scan line 14, and a source of the thin film transistor is connected to the data line 11.
  • the display area may further include a plurality of pixel units, and the pixel unit may include a main pixel area or a sub-pixel area. The brightness of the main pixel area is greater than the brightness of the sub-pixel area.
  • the display area further includes a pixel electrode.
  • a preset area An area in which the length of the wire is greater than a preset value is referred to as a preset area.
  • the length of the wire 20 is greater than a preset value, and the area composed of the wire 20 is a preset area.
  • the preset value may be set according to the size of the panel, and the preset values of the different sizes of the panel are different, and the conductive layer is disposed on the wire 20 of the preset area, that is, the structure of the cross section of the wire 20 is a layer.
  • the layered structure includes a first metal layer 18, an insulating layer 15, a passivation layer 16, a second metal layer 17, and a conductive layer 21.
  • a plurality of conductive layers are disposed on the wires 20 of the predetermined area.
  • a passivation layer is further disposed between two adjacent conductive layers.
  • the wires 20 are connected in parallel with a plurality of resistors, so that the resistance of the wires 20 can be further reduced, and the wires can be different according to the length of the wires.
  • the number of layers of the conductive layer is such that the difference in impedance between the conductive layers is smaller, that is, the length of the wire is compared with the predetermined value, and the larger the difference, the more the number of layers of the conductive layer is set.
  • the material of the conductive layer 21 may be metal.
  • the wire 20 has a three-layer metal structure, which is equivalent to three resistors in parallel to reduce the resistance of the original wire, thereby reducing the resistance of the wire in the preset area, and further reducing the peripheral area (the length of the wire in the peripheral area is longer) ) The difference in impedance from the middle area conductor to avoid block chromatic aberration.
  • the material of the conductive layer 21 is indium tin oxide.
  • a via hole connecting the first metal layer or the second metal layer is disposed at an edge of the display area, where the wire is connected to the data line and the scan line, so that the wire is electrically connected to the scan line or a data line, wherein the via hole is filled with a transparent conductive layer, and the material of the transparent conductive layer may be indium tin oxide, so when the material of the conductive layer 21 is the same as the material of the transparent conductive layer, the process is saved, thereby reduce manufacturing cost.
  • the driving chip 12 can be a source driving chip or a gate driving chip.
  • the driving chip 12 is a gate driving chip, it is connected to the scanning line 14.
  • the driving chip 12 is a source driving chip, it is connected to the data line 11. Minimize the difference in the input signal of each scan line or data line in the display area, and obtain a better display effect.
  • the thickness of the conductive layer 21 is set according to the length of the wire, and the longer the wire length near the edge of each driving chip in the preset region, the greater the difference in impedance of the wire, due to resistance and thickness. Correlation, the larger the thickness, the smaller the resistance value. Therefore, the longer the length of the wire, the thicker the conductive layer is formed thereon, the impedance difference can be better reduced, and the multilayer conductive layer can be avoided, thereby saving the process.
  • the impedance difference between the wires is reduced, the block chromatic aberration is reduced, and the display effect is improved.
  • the present invention also provides a liquid crystal display device including a liquid crystal display panel and a backlight module.
  • the liquid crystal display panel is disposed relative to the backlight module, and the backlight module can be side-lit (side Lighting) Backlight module or Bottom Lighting backlight module to provide backlight to LCD panel.
  • the brightness of the backlight module is adjustable.
  • the liquid crystal display panel includes: a color filter substrate, a liquid crystal layer, and an array substrate; the liquid crystal layer is located between the color film substrate and the array substrate; and the array substrate is disposed opposite to the color film substrate;
  • the substrate material of the array substrate and the color filter substrate may be a glass substrate or a flexible plastic substrate, and the color film substrate may include a red color film, a green color film, and a blue color film.
  • the color filter substrate may further include a black matrix and a common electrode.
  • the array substrate includes:
  • a display area which is formed by interleaving a plurality of data lines and a plurality of scan lines;
  • each of the driving chips being connected to the data lines and the scan lines by wires;
  • a conductive layer is disposed on the wire of the preset area, wherein the predetermined area is an area where the length of the wire is greater than a preset value.
  • the liquid crystal display panel or the liquid crystal display device of the present invention may employ any of the above array substrates, and the above-described array substrate has been described above, and will not be described herein.
  • the liquid crystal display panel and device of the present invention reduces the impedance difference between the wires by providing a conductive layer on the wires having a long length, thereby reducing the block chromatic aberration and improving the display effect.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板、液晶显示面板及装置，所述阵列基板包括：显示区域（10）、多个驱动芯片（12），用于向数据线（11）提供数据信号以及向扫描线（14）提供扫描信号；每个所述驱动芯片（12）通过导线（13、20）与所述数据线（11）以及所述扫描线（14）连接；在预设区域的所述导线（20）上设置有导电层，其中所述预设区域为所述导线的长度大于预设值的区域。

Description

一种阵列基板、液晶显示面板及装置 技术领域
本发明涉及显示器领域，特别是涉及阵列基板、液晶显示面板及装置。
 背景技术
随着液晶显示面板从高清到全高清，再到超低色散的发展，对显示效果的要求越来越高。但是目前的液晶显示面板存在块色差，下面结合附图具体说明形成块色差的原因。图1为现有技术的阵列基板的结构示意图，如图1所示，其包括显示区域10和多个驱动芯片12，显示区域10包括多条数据线11或者多条扫描线14；驱动芯片12能够向所述数据线11提供数据信号以及向所述扫描线14提供扫描信号；每个所述驱动芯片12通过导线与所述数据线11以及所述扫描线14连接。
通常情况下，导线13的截面的结构为层状结构，该层状结构如图2所示，包括第一金属层18，绝缘层15、钝化层16、第二金属层17。导线成扇行排布（Fanout），然而这样的排布使得外围区域导线的长度与中间区域导线的长度差距越来越大，阻抗及阻容延迟差异也越来越大，在两个相邻驱动芯片外围区域与显示区域连接的导线，由于阻抗较大及阻容延迟较严重，因此与外围区域的导线对应的显示区域容易形成块色差。
故，有必要提供一种阵列基板、液晶显示面板及装置，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种阵列基板、液晶显示面板及装置，以解决现有的液晶显示面板由于导线的阻抗差异，容易出现块色差的技术问题。
技术解决方案
为解决上述问题，本发明提供一种阵列基板，其包括：
显示区域，由多条数据线和多条扫描线交错形成；
多个驱动芯片，用于向所述数据线提供数据信号以及向所述扫描线提供扫描信号；每个所述驱动芯片通过导线与所述数据线以及所述扫描线连接；
其中在预设区域的所述导线上设置有导电层，所述预设区域为所述导线的长度大于预设值的区域。
在本发明的阵列基板中，所述导电层的材料为氧化铟锡或者金属。
在本发明的阵列基板中，所述导线上设置有两层或者两层以上导电层。
在本发明的阵列基板中，根据所述导线的长度与预设值之间的差值设置所述导电层的层数。
在本发明的阵列基板中，所述导电层的厚度根据所述导线的长度设置。
本发明还提供一种液晶显示面板，其包括：
彩膜基板；
液晶层，位于所述彩膜基板和阵列基板之间；以及
所述阵列基板，与所述彩膜基板相对设置；其包括：
显示区域，由多条数据线和多条扫描线交错形成；
多个驱动芯片，用于向所述数据线提供数据信号以及向所述扫描线提供扫描信号；每个所述驱动芯片通过导线与所述数据线以及所述扫描线连接；
其中在预设区域的所述导线上设置有导电层，所述预设区域为所述导线的长度大于预设值的区域。
在本发明的液晶显示面板中，所述导电层的材料为氧化铟锡或者金属。
在本发明的液晶显示面板中，所述导线上设置有两层或者两层以上导电层。
在本发明的液晶显示面板中，根据所述导线的长度与所述预设值之间的差值设置所述导电层的层数。
本发明还提供一种液晶显示装置，其包括背光模块及液晶显示面板；
其中液晶显示面板包括：
彩膜基板；
液晶层，位于所述彩膜基板和阵列基板之间；以及
所述阵列基板，与所述彩膜基板相对设置；其包括：
显示区域，由多条数据线和多条扫描线交错形成；
多个驱动芯片，用于向所述数据线提供数据信号以及向所述扫描线提供扫描信号；每个所述驱动芯片通过导线与所述数据线以及所述扫描线连接；
其中在预设区域的所述导线上设置有导电层，所述预设区域为所述导线的长度大于预设值的区域。
在本发明的液晶显示装置中，所述导电层的材料为氧化铟锡或者金属。
在本发明的液晶显示装置中，所述导线上设置有两层或者两层以上导电层。
在本发明的液晶显示装置中，根据所述导线的长度与所述预设值之间的差值设置所述导电层的层数。
在本发明的液晶显示装置中，所述导电层的厚度根据所述导线的长度设置。
 有益效果
本发明的阵列基板、液晶显示面板及装置，通过在长度较长的导线上设置一层导电层，从而降低导线之间的阻抗差异，降低了块色差，提高了显示效果。
 附图说明
图1为现有技术的阵列基板的结构示意图；
图2为现有技术的导线的剖面结构示意图；
图3为本发明的阵列基板的结构示意图；
图4为本发明的导线的剖面结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图3，图3为本发明的阵列基板的结构示意图；
本发明的阵列基板，如图3所示，其包括显示区域10和多个驱动芯片12，所述显示区域10由多条数据线11和多条扫描线14交错形成；多个驱动芯片12，用于向所述数据线11提供数据信号以及向所述扫描线14提供扫描信号；每个所述驱动芯片通过导线与所述数据线11以及所述扫描线14连接；所述导线13、20的总条数和所述数据线和所述扫描线的总条数相等。
所述显示区域10还可包括薄膜晶体管（图中未示出），所述薄膜晶体管包括栅极、源极、漏极。所述薄膜晶体管的栅极连接所述扫描线14，所述薄膜晶体管的源极连接所述数据线11。所述显示区域还可包括多个像素单元，所述像素单元可包括主像素区或者子像素区。所述主像素区的亮度大于所述子像素区的亮度。所述显示区域还包括像素电极。
将所述导线的长度大于预设值的区域称为预设区域，譬如全部导线中，所述导线20的长度大于预设值，由所述导线20所组成的区域为预设区域，所述预设值可根据面板的尺寸设定，不同尺寸的面板所述预设值不同，在所述预设区域的所述导线20上设置有导电层，即所述导线20的截面的结构为层状结构，该层状结构包括第一金属层18，绝缘层15、钝化层16、第二金属层17以及导电层21。
所述第一金属层18中与所述显示区域对应的部分可以用于形成所述薄膜晶体管的栅极或者扫描线14。所述第二金属层17中与所述显示区域对应的部分可以用于形成所述薄膜晶体管的源极或者漏极或者数据线11。所述绝缘层15可以用于制作栅绝缘层。
此时所述导线20包括两层金属层和一层导电层，相当于3个电阻并联，从而能够降低原有导线的电阻，使得预设区域的导线的阻值降低，进一步减少外围区域与内侧区域导线的阻抗差异（譬如导线20与导线13之间的阻抗差异），避免出现块色差。
当然，在所述预设区域的所述导线20上还可设置多层导电层。相邻两个导电层之间还设置有钝化层，此时所述导线20相当于多个电阻并联，从而能够进一步降低所述导线20的电阻，并可以根据所述导线的长度不同设置不同层数的导电层，以使各导电层之间的阻抗差异更小，即将所述导线的长度与所述预设值比较，差值越大的导线，设置导电层的层数越多。
优选地，所述导电层21的材料可为金属。此时所述导线20具有三层金属结构，相当于3个电阻并联能够降低原有导线的电阻，因此使得预设区域的导线的阻值降低，进一步减少外围区域（外围区域导线的长度较长）与中间区域导线的阻抗差异，避免出现块色差。
优选地，所述导电层21的材料为氧化铟锡。由于在所述显示区域边缘，导线与数据线及扫描线相连的地方，还设置有连接所述第一金属层或者所述第二金属层的过孔，以便所述导线电性连接扫描线或者数据线，在所述过孔内填充有透明导电层，所述透明导电层的材料可为氧化铟锡，因此将导电层21的材料与透明导电层的材料相同时，就节省制程工序，从而降低生产成本。
优选地，所述驱动芯片12可为源驱动芯片或者栅驱动芯片。当所述驱动芯片12为栅驱动芯片时，与所述扫描线14连接。当所述驱动芯片12为源驱动芯片时，与所述数据线11连接。最大程度地降低显示区域中每条扫描线或者数据线的输入信号的差异，能够获得更好的显示效果。
优选地，所述导电层21的厚度根据所述导线的长度设置，由于预设区域中越靠近每个驱动芯片最边缘的导线长度越长，导线的阻抗差异也就越大，由于阻值和厚度相关，厚度越大阻值越小，因此长度越长的导线，在其上制作越厚的导电层，可以更好地降低阻抗差异，同时也可避免制作多层导电层，节省制程工序。
本发明的阵列基板，通过在长度较长的导线上设置导电层，从而降低导线之间的阻抗差异，降低了块色差，提高了显示效果。
本发明还提供一种液晶显示面板，其包括：彩膜基板、液晶层、阵列基板；所述液晶层位于所述彩膜基板和所述阵列基板之间；所述阵列基板，与所述彩膜基板相对设置；所述阵列基板和所述彩膜基板的基板材料可为玻璃基板或可挠性塑料基板，所述彩膜基板可包括红色彩膜、绿色彩膜、蓝色彩膜。所述彩膜基板还可包括黑色矩阵以及公共电极。
结合图3，其包括显示区域10和多个驱动芯片12，所述显示区域10由多条数据线11和多条扫描线14交错形成；多个驱动芯片12，用于向所述数据线11提供数据信号以及向所述扫描线14提供扫描信号；每个所述驱动芯片通过导线与所述数据线11以及所述扫描线14连接；所述导线13、20的总条数和所述数据线和所述扫描线的总条数相等。
所述显示区域10还可包括薄膜晶体管（图中未示出），所述薄膜晶体管包括栅极、源极、漏极。所述薄膜晶体管的栅极连接所述扫描线14，所述薄膜晶体管的源极连接所述数据线11。所述显示区域还可包括多个像素单元，所述像素单元可包括主像素区或者子像素区。所述主像素区的亮度大于所述子像素区的亮度。所述显示区域还包括像素电极。
将所述导线的长度大于预设值的区域称为预设区域，譬如全部导线中，所述导线20的长度大于预设值，由所述导线20所组成的区域为预设区域，所述预设值可根据面板的尺寸设定，不同尺寸的面板所述预设值不同，在所述预设区域的所述导线20上设置有导电层，即所述导线20的截面的结构为层状结构，该层状结构包括第一金属层18，绝缘层15、钝化层16、第二金属层17以及导电层21。
所述第一金属层18中与所述显示区域对应的部分可以用于形成所述薄膜晶体管的栅极或者扫描线14。所述第二金属层17中与所述显示区域对应的部分可以用于形成所述薄膜晶体管的源极或者漏极或者数据线11。所述绝缘层15可以用于制作栅绝缘层。
此时所述导线20包括两层金属层和一层导电层，相当于3个电阻并联，从而能够降低原有导线的电阻，使得预设区域的导线的阻值降低，进一步减少外围区域与内侧区域导线的阻抗差异（譬如导线20与导线13之间的阻抗差异），避免出现块色差。
当然在所述预设区域的所述导线20上设置有多层导电层。相邻两个导电层之间还设置有钝化层，此时所述导线20相当于多个电阻并联，从而能够进一步降低所述导线20的电阻，并可以根据所述导线的长度不同设置不同层数的导电层，以使各导电层之间的阻抗差异更小，即将所述导线的长度与所述预设值比较，差值越大的导线，设置的导电层的层数越多。
优选地，所述导电层21的材料可为金属。此时所述导线20具有三层金属结构，相当于3个电阻并联能够降低原有导线的电阻，因此使得预设区域的导线的阻值降低，进一步减少外围区域（外围区域导线的长度较长）与中间区域导线的阻抗差异，避免出现块色差。
优选地，所述导电层21的材料为氧化铟锡。由于在所述显示区域边缘，导线与数据线及扫描线相连的地方，还设置有连接所述第一金属层或者所述第二金属层的过孔，以便所述导线电性连接扫描线或者数据线，在所述过孔内填充有透明导电层，所述透明导电层的材料可为氧化铟锡，因此将导电层21的材料与透明导电层的材料相同时，就节省制程工序，从而降低生产成本。
优选地，所述驱动芯片12可为源驱动芯片或者栅驱动芯片。当所述驱动芯片12为栅驱动芯片时，与所述扫描线14连接。当所述驱动芯片12为源驱动芯片时，与所述数据线11连接。最大程度地降低显示区域中每条扫描线或者数据线的输入信号的差异，能够获得更好的显示效果。
优选地，所述导电层21的厚度根据所述导线的长度设置，由于预设区域中越靠近每个驱动芯片最边缘的导线长度越长，导线的阻抗差异也就越大，由于阻值和厚度相关，厚度越大阻值越小，因此长度越长的导线，在其上制作越厚的导电层，可以更好地降低阻抗差异，同时也可避免制作多层导电层，节省制程工序。
本发明的液晶显示面板，通过在长度较长的导线上设置导电层，从而降低导线之间的阻抗差异，降低了块色差，提高了显示效果。
本发明还提供一种液晶显示装置，其包括液晶显示面板和背光模块。所述液晶显示面板相对于背光模块来设置，此背光模块可为侧光式(side Lighting)背光模块或直下式入光(Bottom Lighting)背光模块，以提供背光至液晶显示面板。背光模块的亮度是可调整的。
所述液晶显示面板包括：彩膜基板、液晶层、阵列基板；所述液晶层位于所述彩膜基板和所述阵列基板之间；所述阵列基板，与所述彩膜基板相对设置；所述阵列基板和所述彩膜基板的基板材料可为玻璃基板或可挠性塑料基板，所述彩膜基板可包括红色彩膜、绿色彩膜、蓝色彩膜。所述彩膜基板还可包括黑色矩阵以及公共电极。
所述阵列基板包括：
显示区域，由多条数据线和多条扫描线交错形成；
多个驱动芯片，用于向所述数据线提供数据信号以及向所述扫描线提供扫描信号；每个所述驱动芯片通过导线与所述数据线以及所述扫描线连接；
在预设区域的所述导线上设置有导电层，其中所述预设区域为所述导线的长度大于预设值的区域。
本发明的液晶显示面板或者液晶显示装置可以采用上述任何一种阵列基板、鉴于所述阵列基板在上文已有描述，在此不再赘述。
本发明的液晶显示面板及装置，通过在长度较长的导线上设置导电层，从而降低导线之间的阻抗差异，降低了块色差，提高了显示效果。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (15)

  1. 一种阵列基板，其包括：
    显示区域，由多条数据线和多条扫描线交错形成；
    多个驱动芯片，用于向所述数据线提供数据信号以及向所述扫描线提供扫描信号；每个所述驱动芯片通过导线与所述数据线以及所述扫描线连接；
    其中在预设区域的所述导线上设置有导电层，所述预设区域为所述导线的长度大于预设值的区域。
  2. 根据权利要求1所述的阵列基板，其中所述导电层的材料为氧化铟锡或者金属。
  3. 根据权利要求1所述的阵列基板，其中所述导线上设置有两层或者两层以上导电层。
  4. 根据权利要求3所述的阵列基板，其中根据所述导线的长度与所述预设值之间的差值设置所述导电层的层数。
  5. 根据权利要求1所述的阵列基板，其中所述导电层的厚度根据所述导线的长度设置。
  6. 一种液晶显示面板，其包括：
    彩膜基板；
    液晶层，位于所述彩膜基板和阵列基板之间；以及
    所述阵列基板，与所述彩膜基板相对设置；其包括：
    显示区域，由多条数据线和多条扫描线交错形成；
    多个驱动芯片，用于向所述数据线提供数据信号以及向所述扫描线提供扫描信号；每个所述驱动芯片通过导线与所述数据线以及所述扫描线连接；
    其中在预设区域的所述导线上设置有导电层，所述预设区域为所述导线的长度大于预设值的区域。
  7. 根据权利要求6所述的液晶显示面板，其中所述导电层的材料为氧化铟锡或者金属。
  8. 根据权利要求6所述的液晶显示面板，其中所述导线上设置有两层或者两层以上导电层。
  9. 根据权利要求8所述的液晶显示面板，其中根据所述导线的长度与所述预设值之间的差值设置所述导电层的层数。
  10. 根据权利要求6所述的液晶显示面板，其中所述导电层的厚度根据所述导线的长度设置。
  11. 一种液晶显示装置，其包括背光模块及液晶显示面板；
    其中液晶显示面板包括：
    彩膜基板；
    液晶层，位于所述彩膜基板和阵列基板之间；以及
    所述阵列基板，与所述彩膜基板相对设置；其包括：
    显示区域，由多条数据线和多条扫描线交错形成；
    多个驱动芯片，用于向所述数据线提供数据信号以及向所述扫描线提供扫描信号；每个所述驱动芯片通过导线与所述数据线以及所述扫描线连接；
    其中在预设区域的所述导线上设置有导电层，所述预设区域为所述导线的长度大于预设值的区域。
  12. 根据权利要求11所述的液晶显示装置，其中所述导电层的材料为氧化铟锡或者金属。
  13. 根据权利要求11所述的液晶显示装置，其中所述导线上设置有两层或者两层以上导电层。
  14. 根据权利要求13所述的液晶显示装置，其中根据所述导线的长度与所述预设值之间的差值设置所述导电层的层数。
  15. 根据权利要求11所述的液晶显示装置，其中所述导电层的厚度根据所述导线的长度设置。
PCT/CN2015/072423 2015-02-02 2015-02-06 一种阵列基板、液晶显示面板及装置 WO2016123797A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510053835.8A CN104614887A (zh) 2015-02-02 2015-02-02 一种阵列基板、液晶显示面板及装置
CN201510053835.8 2015-02-02

Publications (1)

Publication Number Publication Date
WO2016123797A1 true WO2016123797A1 (zh) 2016-08-11

Family

ID=53149405

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/072423 WO2016123797A1 (zh) 2015-02-02 2015-02-06 一种阵列基板、液晶显示面板及装置

Country Status (2)

Country Link
CN (1) CN104614887A (zh)
WO (1) WO2016123797A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106125429A (zh) * 2016-08-23 2016-11-16 深圳市华星光电技术有限公司 液晶显示面板及液晶显示装置
KR102635823B1 (ko) * 2016-08-31 2024-02-08 엘지디스플레이 주식회사 표시패널 및 이를 이용한 표시장치
WO2018191958A1 (zh) * 2017-04-21 2018-10-25 深圳市柔宇科技有限公司 Tft阵列基板、显示面板及显示装置
CN107833908B (zh) * 2017-11-29 2020-05-05 武汉天马微电子有限公司 异形显示面板和液晶显示装置及有机电致发光显示装置
CN111258132A (zh) * 2020-03-31 2020-06-09 深圳市华星光电半导体显示技术有限公司 阵列基板及液晶显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001118847A (ja) * 1999-08-06 2001-04-27 Sharp Corp 配線構造および基板の製造方法ならびに液晶表示装置およびその製造方法
CN1512251A (zh) * 2002-12-30 2004-07-14 ���ǵ�����ʽ���� 具有信号线的显示面板及液晶显示器
CN1832184A (zh) * 2006-02-24 2006-09-13 广辉电子股份有限公司 有源元件阵列基板
US20070152218A1 (en) * 2005-12-30 2007-07-05 Quanta Display Inc. Active component array substrate
KR101466488B1 (ko) * 2013-06-10 2014-11-28 하이디스 테크놀로지 주식회사 표시장치 및 그 제조방법
CN104407477A (zh) * 2014-12-02 2015-03-11 深圳市华星光电技术有限公司 阵列基板及显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100403940B1 (ko) * 1996-10-31 2003-12-18 삼성전자주식회사 Loc 패널의 아웃 리드 본딩패드와 팬 아웃부의 콘택구조
CN100388101C (zh) * 2005-10-12 2008-05-14 友达光电股份有限公司 扇出导线结构
TWI571989B (zh) * 2014-01-28 2017-02-21 友達光電股份有限公司 顯示基板結構
CN104166284B (zh) * 2014-08-27 2018-01-09 深圳市华星光电技术有限公司 液晶显示面板及其扇形区域

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001118847A (ja) * 1999-08-06 2001-04-27 Sharp Corp 配線構造および基板の製造方法ならびに液晶表示装置およびその製造方法
CN1512251A (zh) * 2002-12-30 2004-07-14 ���ǵ�����ʽ���� 具有信号线的显示面板及液晶显示器
US20070152218A1 (en) * 2005-12-30 2007-07-05 Quanta Display Inc. Active component array substrate
CN1832184A (zh) * 2006-02-24 2006-09-13 广辉电子股份有限公司 有源元件阵列基板
KR101466488B1 (ko) * 2013-06-10 2014-11-28 하이디스 테크놀로지 주식회사 표시장치 및 그 제조방법
CN104407477A (zh) * 2014-12-02 2015-03-11 深圳市华星光电技术有限公司 阵列基板及显示装置

Also Published As

Publication number Publication date
CN104614887A (zh) 2015-05-13

Similar Documents

Publication Publication Date Title
WO2014036730A1 (zh) 一种显示面板及液晶显示装置
WO2016123797A1 (zh) 一种阵列基板、液晶显示面板及装置
CN109491121A (zh) 显示面板和显示装置
WO2016090667A1 (zh) 显示面板及其修复方法
WO2017008316A1 (zh) 一种阵列基板及液晶显示面板
WO2016127464A1 (zh) 一种阵列基板及液晶显示面板
WO2016206136A1 (zh) 一种tft基板及显示装置
WO2016078204A1 (zh) 一种液晶显示面板及阵列基板
WO2013181860A1 (zh) 显示面板、平板显示装置及其驱动方法
CN106094272A (zh) 一种显示基板、其制作方法及显示装置
WO2019015078A1 (zh) 一种阵列基板以及显示面板
WO2016101306A1 (zh) 触控显示面板及触控显示装置
US20200176480A1 (en) Display panel and display device
WO2018126510A1 (zh) 一种阵列基板及显示装置
WO2017219431A1 (zh) 阵列基板以及液晶显示器
WO2017088230A1 (zh) Coa基板、液晶显示面板及液晶显示装置
WO2017059606A1 (zh) 一种液晶显示器及其制备方法
WO2022047793A1 (zh) 阵列基板及显示面板
WO2019015008A1 (zh) 一种像素阵列基板及显示器
WO2018214210A1 (zh) 一种阵列基板及其制作方法
WO2019179151A1 (zh) 阵列基板及显示面板
WO2017177537A1 (zh) 一种液晶显示面板及液晶显示器
WO2018145359A1 (zh) 显示面板及其阵列基板
WO2016101292A1 (zh) 一种触控液晶显示面板及触控液晶显示装置
WO2018152903A1 (zh) 阵列基板及液晶显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15880753

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15880753

Country of ref document: EP

Kind code of ref document: A1