WO2018192026A1 - 扫描驱动电路 - Google Patents

扫描驱动电路 Download PDF

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Publication number
WO2018192026A1
WO2018192026A1 PCT/CN2017/084119 CN2017084119W WO2018192026A1 WO 2018192026 A1 WO2018192026 A1 WO 2018192026A1 CN 2017084119 W CN2017084119 W CN 2017084119W WO 2018192026 A1 WO2018192026 A1 WO 2018192026A1
Authority
WO
WIPO (PCT)
Prior art keywords
controllable switch
pull
circuit
control
signal
Prior art date
Application number
PCT/CN2017/084119
Other languages
English (en)
French (fr)
Inventor
石龙强
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US15/540,983 priority Critical patent/US10431135B2/en
Priority to EP17906626.1A priority patent/EP3614369B1/en
Priority to KR1020197034376A priority patent/KR102276808B1/ko
Priority to JP2019556895A priority patent/JP6828186B2/ja
Publication of WO2018192026A1 publication Critical patent/WO2018192026A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a scan driving circuit.
  • Indium gallium zinc oxide has high mobility and good device stability, which can reduce the complexity of the scan driving circuit. Due to the high mobility of IGZO, the size of the thin film transistor in the scan driving circuit is relatively small, which is beneficial to The production of a narrow bezel display; secondly, the device stability of IGZO can reduce the number of power supplies and thin film transistors used to stabilize the performance of the thin film transistor, thereby making the circuit simple and low in power consumption.
  • the initial threshold voltage Vth is easily negative, and the influence of illumination may cause the threshold voltage Vth to drift negatively, which may cause the scan drive circuit to fail.
  • the technical problem to be solved by the present invention is to provide a scan driving circuit to prevent the threshold voltage from being biased to cause the scan driving circuit to fail.
  • the present invention adopts a technical solution to provide a scan driving circuit
  • the scan driving circuit includes a plurality of scan driving units connected in sequence, and each scan driving unit includes:
  • a scan signal output end for outputting a high level scan signal or a low level scan signal
  • a pull-up circuit configured to receive a clock signal of the current stage, and control, according to the clock signal of the current stage, to output a scan signal of a high level at the output end of the scan signal;
  • a downlink circuit connected to the pull-up circuit for outputting a high-level signal of the present stage
  • a pull-up control circuit connected to the downlink circuit for charging the pull-up control signal point to pull up the potential of the pull-up control signal point to a high level
  • a pull-down sustaining circuit connected to the pull-up control circuit, for maintaining a low level of the pull-up control signal point and a low level of a scan signal output by the scan signal output end;
  • a bootstrap circuit for boosting a potential of the pull-up control signal point
  • the pull-down circuit is connected to the downlink circuit and the pull-down maintaining circuit, and configured to receive a lower-level transmission signal and control the scan signal output end to output a low-level scan signal according to the lower-level transmission signal;
  • the pull-up circuit includes a first controllable switch, the first end of the first controllable switch receives the clock signal of the current stage and is connected to the downlink circuit, and the control end of the first controllable switch is connected
  • the second circuit of the first controllable switch is connected to the pull-down maintaining circuit and the scan signal output end.
  • the present invention adopts a technical solution to provide a scan driving circuit
  • the scan driving circuit includes a plurality of scan driving units connected in sequence, and each scan driving unit includes:
  • a scan signal output end for outputting a high level scan signal or a low level scan signal
  • a pull-up circuit configured to receive a clock signal of the current stage, and control, according to the clock signal of the current stage, to output a scan signal of a high level at the output end of the scan signal;
  • a downlink circuit connected to the pull-up circuit for outputting a high-level signal of the present stage
  • a pull-up control circuit connected to the downlink circuit for charging the pull-up control signal point to pull up the potential of the pull-up control signal point to a high level
  • a pull-down sustaining circuit connected to the pull-up control circuit for maintaining a low level of the pull-up control signal point and a low level of a scan signal output by the scan signal output end;
  • the invention has the beneficial effects that the scan driving circuit of the present invention is separated from the prior art by a pull-up circuit, a downlink circuit, a pull-up control circuit, a pull-down sustain circuit, the pull-down circuit and a bootstrap circuit. Prevent leakage, and thus prevent the threshold voltage from being biased to cause the scan drive circuit to fail.
  • FIG. 1 is a circuit diagram of a first embodiment of a scan driving circuit of the present invention
  • Figure 2 is a schematic diagram showing the relationship between the signal waveform and the potential of Figure 1;
  • FIG. 3 is a schematic diagram of signal waveforms of the simulation of FIG. 1;
  • FIG. 4 is a schematic diagram showing signal waveforms of a simulation of a 32nd-stage scan driving unit of the scan driving circuit of the present invention
  • FIG. 5 is a schematic diagram of signal waveforms of the sexual tolerance simulation of FIG. 1;
  • Figure 6 is a circuit diagram showing a second embodiment of the scan driving circuit of the present invention.
  • Figure 7 is a schematic diagram showing the relationship between the signal waveform and the potential of Figure 6;
  • FIG. 8 is a schematic diagram of signal waveforms of the simulation of FIG. 6;
  • FIG. 9 is a schematic diagram showing signal waveforms of a simulation of a 32nd-stage scan driving unit of the scan driving circuit of the present invention.
  • FIG. 10 is a schematic diagram of signal waveforms of the sexual tolerance simulation of FIG. 6.
  • FIG. 10 is a schematic diagram of signal waveforms of the sexual tolerance simulation of FIG. 6.
  • FIG. 1 is a circuit diagram of a first embodiment of a scan driving circuit of the present invention.
  • the scan driving circuit includes a plurality of scan driving units 1 connected in series, each scan driving unit 1 includes a scan signal output terminal G(n) for outputting a high level scan signal or a low level scan signal;
  • the pull-up circuit 10 is configured to receive the clock signal CK(n) of the current stage and control the scan signal output terminal G(n) to output a scan signal of a high level according to the clock signal CK(n) of the current stage;
  • a lower transmission circuit 20 connected to the pull-up circuit 10, for outputting a high-level local level transmission signal ST(n);
  • Pull-up control circuit 30 connected to the lower transmission circuit 20, for charging the pull-up control signal point Q(n) to pull up the potential of the pull-up control signal point Q(n) to a high level;
  • the pull-down maintaining circuit 40 is connected to the pull-up control circuit 30 for maintaining the low level of the pull-up control signal point Q(n) and the low voltage of the scan signal output by the scan signal output terminal G(n) Flat;
  • the bootstrap circuit 50 is for boosting the potential of the pull-up control signal point Q(n).
  • the scan driving unit 1 further includes a pull-down circuit 60, and the pull-down circuit 60 is connected to the downlink circuit 20 and the pull-down maintaining circuit 40 for receiving the lower-level transmission signal ST(n+4) and according to the lower level
  • the level transmission signal ST(n+4) controls the scan signal output terminal G(n) to output a low level scan signal.
  • the pull-up circuit 10 includes a first controllable switch T1, the first end of the first controllable switch T1 receives the local clock signal CK(n) and is connected to the downlink circuit 20, the first The control terminal of the controllable switch T1 is connected to the down circuit 20, and the second end of the first controllable switch T1 is connected to the pull-down maintaining circuit 40 and the scan signal output terminal G(n).
  • the lower transmission circuit 20 includes a second controllable switch T2, the control end of the second controllable switch T2 is connected to the control end of the first controllable switch T1, and the first end of the second controllable switch T2 The first end of the first controllable switch T1 is connected, and the second end of the second controllable switch T2 outputs the local stage transmission signal ST(n).
  • the pull-up control circuit 30 includes third to fifth controllable switches T3-T5, and the control end of the third controllable switch T3 is connected to the control end of the second controllable switch T2 and the fifth controllable switch T5.
  • the second end of the third controllable switch T3 is connected to the second end of the fourth controllable switch T4 and the first end of the fifth controllable switch T5
  • the second end of the third controllable switch T3 is connected to the pull-down maintaining circuit 40, and the first end of the fourth controllable switch T4 receives the upper-level transmission signal ST(n-4), the fourth
  • the control terminal of the control switch T4 is connected to the control terminal of the fifth controllable switch T5 and receives the first clock signal XCK.
  • the pull-down maintaining circuit 40 includes sixth to thirteenth controllable switches T6-T13, and the control end of the sixth controllable switch T6 is connected to the second end of the fifth controllable switch T5, the sixth a first end of the control switch T6 is connected to the second end of the third controllable switch T3, and a second end of the sixth controllable switch T6 is connected to the second end of the seventh controllable switch T7 and the first end a first end of the eight controllable switch T8, a first end of the seventh controllable switch T7 is connected to a second end of the fifth controllable switch T5, and a control end of the seventh controllable switch T7 is connected to the eighth end a control end of the controllable switch T8, the second end of the eighth controllable switch T8 is connected to the second voltage end VSS2, and the control end of the ninth controllable switch T9 is connected to the first end of the ninth controllable switch T9 and The first end of the eleventh controllable switch T11 receives the first clock signal
  • the bootstrap circuit 50 includes a bootstrap capacitor C1, one end of the bootstrap capacitor C1 is connected to the control end of the third controllable switch T3, and the other end of the bootstrap capacitor C1 is connected to the third controllable switch. The second end of T3.
  • the first to thirteenth controllable switches T1-T13 are N-type thin film transistors, and the control ends, the first ends, and the first to thirteen controllable switches T1-T13 The two ends correspond to the gate, the drain and the source of the N-type thin film transistor, respectively.
  • the first to thirteenth controllable switches may also be other types of switches as long as the object of the present invention can be achieved.
  • the phase of the local clock signal CK(n) is opposite to the phase of the first clock signal XCK, which is a set of high frequency AC power.
  • the first voltage terminal VSS1 and the second voltage terminal VSS2 are respectively DC power sources.
  • the invention is described by taking an 8K4K display as an example, wherein 8 clock signals are used, the overlap time between each two clock signals is 3.75 microseconds, the trigger signal STV has one pulse per frame, and the pulse width is 30 microseconds. The overlap time between the trigger signal STV and the clock signal CK is 3.75 microseconds.
  • the high potential of the clock signal CK is 28V, and the low potential is -10V. Since the present invention uses eight clock signals CK, the clock signals CK1 and CK5 are opposite in phase, the clock signals CK2 and CK6 are opposite in phase, the clock signals CK3 and CK7 are opposite in phase, and the clock signals CK4 and CK8 are opposite in phase.
  • the voltage of the first voltage terminal VSS1 is -5V
  • the voltage of the second voltage terminal VSS2 is -10V.
  • the signal CK4 is controlled, and the first clock signal XCK is the clock signal CK4.
  • the clock signal CK4 is high, and the fourth controllable switch T4 and the fifth controllable switch T5 are both turned on, and the level signal ST(28) is high.
  • the potential is transmitted to the pull-up control signal point Q (32).
  • the pull-up control signal point Q (32) is high, and the first controllable switch T1 is turned on.
  • the clock signal is CK8 is low, so the scan signal outputted by the scan signal output terminal G (32) is low, and the ninth controllable switch T9 and the twelfth controllable switch T12 are both turned on, the second Voltage terminal VSS2 will pull down the control signal point P (32)
  • the potential of the thirteenth controllable switch T13, the seventh controllable switch T7 and the eighth controllable switch T8 are all turned off, so the first voltage terminal VSS1 does not pull down The potential of the scan signal outputted by the scan signal output terminal G (32).
  • the clock signal CK4 When the level signal ST(28) is low, the clock signal CK4 is low, and the fourth controllable switch T4 and the fifth controllable switch T5 are both turned off. At this time, the clock signal CK8 is high.
  • the scan signal outputted by the scan signal output terminal G (32) is at a high potential, and the pull-up control signal point Q (32) is raised to a higher potential by the coupling effect of the capacitor C1, and the pull-down control signal point P (32) ) Continue to stay low.
  • the scan driving circuit of the present invention prevents the threshold voltage Vth from being negatively biased to cause the circuit to fail.
  • the threshold voltage Vth of the pull-up control circuit 30 and the pull-down maintaining circuit 40 is excessively negative, and the high potential of the pull-up control signal point Q (32) leaks from the pull-up control circuit 30 and the pull-down maintaining circuit 40.
  • the high potential of the scan signal outputted by the scanning signal output terminal G (32) also leaks to a low potential, thus causing the circuit to fail to output a normal waveform and thus fail.
  • the pull-up control circuit 30 is omitted, and the principle of preventing leakage of the pull-down maintaining circuit 40 is the same, and details are not described herein again.
  • the threshold voltage Vth is not less than -5V, and the fifth controllable switch T5 is in an off state, so the high potential of the scan signal outputted by the scan signal output terminal G (32) does not leak from the thirteenth controllable switch T13. Drop it.
  • the scan signal outputted by the scan signal output terminal G (32) is pulled to a low potential, and at the same time, the clock signal CK4 is at a high potential, and the low potential of the level transfer signal ST (28) is transmitted to The pull-up control signal point Q (32), the pull-up control signal point Q (32) is pulled to a low potential.
  • the clock signal CK8 will be periodically high, and the pull-down control signal point P (32) will be periodically high, then the thirteenth controllable switch T13, the seventh can The control switch T7 and the eighth controllable switch T8 are periodically turned on, and the pull-up control signal point Q (32) can well maintain the potential to the second voltage terminal VSS2, the scan signal The scan signal outputted from the output terminal G (32) can be well maintained to the potential of the first voltage terminal VSS1.
  • FIG. 5 is a schematic diagram of the waveform of the performance of the scan drive circuit of the present invention.
  • the scan driving circuit can still operate normally when the threshold voltage Vth is -7v, indicating that the scan driver circuit of the present application has very good resistance.
  • the scan driving circuit prevents leakage by the pull-up circuit, the pull-down circuit, the pull-up control circuit, the pull-down sustain circuit, and the bootstrap circuit, thereby preventing the threshold voltage from being biased to cause the scan drive circuit to fail.
  • FIG. 6 is a circuit diagram of a second embodiment of the scan driving circuit of the present invention.
  • the second embodiment of the scan driving circuit is different from the first embodiment described above in that the pull-up control circuit 30 includes third to fifth controllable switches T3-T5, and the third controllable switch T3
  • the control terminal is connected to the control end of the second controllable switch T2, the second end of the fifth controllable switch T5, and the pull-down maintaining circuit 40, and the first end of the third controllable switch T3 is connected to the first end a second end of the fourth controllable switch T4 and a first end of the fifth controllable switch T5, the second end of the third controllable switch T3 is connected to the pull-down maintaining circuit 40, the fourth controllable switch
  • the first end of T4 receives the upper level transmission signal ST(n-4), and the control end of the fourth controllable switch T4 is connected to the control end of the fifth controllable switch T5 and receives the upper stage transmission signal ST ( N-4).
  • the pull-down maintaining circuit 40 includes sixth to thirteenth controllable switches T6-T13, and the control end of the sixth controllable switch T6 is connected to the second end of the fifth controllable switch T5, the sixth a first end of the control switch T6 is connected to the second end of the third controllable switch T3, and a second end of the sixth controllable switch T6 is connected to the second end of the seventh controllable switch T7 and the first end a first end of the eighth controllable switch T7, the first end of the seventh controllable switch T7 is connected to the second end of the fifth controllable switch T5, and the control end of the seventh controllable switch T7 is connected to the a control end of the eighth controllable switch T8, the second end of the eighth controllable switch T8 is connected to the second voltage terminal VSS2, and the control end of the ninth controllable switch T9 is connected to the ninth controllable switch T9
  • the first end and the first end of the eleventh controllable switch T11 receive the clock signal CK(n
  • the pull-down circuit 60 includes fourteenth to seventeenth controllable switches T14-T17, and the control end of the fourteenth controllable switch T14 is connected to the first end of the fifteenth controllable switch T15 and the first a control end of the controllable switch T2, the first end of the fourteenth controllable switch T14 is connected to the scan signal output end G(n) and the first end of the thirteenth controllable switch T13, The second end of the fourteenth controllable switch T14 is connected to the second end of the fifteenth controllable switch T15 and the first end of the sixteen controllable switch T16, and the fifteenth controllable switch T15 The control end is connected to the control end of the sixteenth controllable switch T16 and the control end of the seventeenth controllable switch T17 and receives the lower level transmission signal ST(n+4), the sixteenth controllable The second end of the switch T16 is connected to the second voltage terminal VSS2, and the first end of the seventeenth controllable switch T17 is connected to the scan signal output terminal G
  • the first to seventeenth controllable switches T1-T17 are N-type thin film transistors, and the control ends, the first ends, and the first to the seventeenth controllable switches T1-T17 The two ends correspond to the gate, the drain and the source of the N-type thin film transistor, respectively.
  • the first to seventeenth controllable switches may also be other types of switches as long as the object of the present invention can be achieved.
  • the fourth controllable switch T4 of the scan driving unit 1 of each of the first four stages is connected to the trigger signal STV, and the level four signals ST(n+4) of the last four stages are replaced by the trigger signal STV.
  • the voltage of the first voltage terminal VSS1 is -5V
  • the voltage of the second voltage terminal VSS2 is -10V.
  • the CK8 control, the level transfer signal ST (28) is controlled by the clock signal CK4.
  • the clock signal CK4 is at a high potential, and the fourth controllable switch T4 and the fifth controllable switch T5 are both turned on, and the level transmission signal ST(28)
  • the high potential is transmitted to the pull-up control signal point Q (32), the pull-up control signal point Q (32) is high, at which time the first controllable switch T1 is turned on, and the clock signal CK8 is Low, so the scan signal outputted by the scan signal output terminal G (32) is low, and the tenth controllable switch T10 and the twelfth controllable switch T12 are both turned on, so the second voltage Terminal VSS2 will pull down the control signal point P (32)
  • the potential is pulled low, at which time the thirteenth controllable switch T13, the seventh controllable switch T7 and the eighth controllable switch T8 are all turned off, and the low potential of the second voltage terminal VSS2 does not pull down the scan.
  • the clock signal CK4 When the level signal ST(28) is low, the clock signal CK4 is low, and the fourth controllable switch T4 and the fifth controllable switch T5 are both turned off, and the clock signal CK8 is high.
  • the scan signal outputted by the scan signal output terminal G (32) is at a high potential, and the pull-up control signal point Q (32) is raised to a higher potential by the coupling effect of the capacitor C1, and the pull-down control signal point P ( 32) Continue to stay low.
  • the scan driving circuit of the present invention prevents the threshold voltage Vth from being negatively biased to cause the circuit to fail.
  • the pull-down circuit 60, and the pull-down maintaining circuit 40 in the conventional scan driving circuit is excessively negative, the high potential of the pull-up control signal point Q (32) is from the pull-up control circuit 30, The pull-down circuit 60 and the pull-down maintaining circuit 40 leak to a low potential, and the high potential of the scan signal outputted by the scan signal output terminal G (32) leaks from the pull-down circuit 60 and the pull-down sustain circuit 40 to a low potential, so that the scan drive circuit cannot output normally. The waveform is thus invalid.
  • the scan driving circuit of the present invention can effectively prevent leakage, wherein when the threshold voltage Vth of the pull-up control circuit 30 is excessively negative, the third controllable switch T3 is turned on, and the fifth controllable switch T5 is at this time.
  • the threshold voltage Vth of the fifth controllable switch T5 is not less than -38V, the five controllable switches T5 are all in an off state, so the high potential of the pull-up control signal point Q (32) does not
  • the pull-up control circuit 30 is omitted, and the principle of the leakage prevention of the pull-down maintaining circuit 40 is the same, and details are not described herein again.
  • the potential of the pull-down control signal point P (32) is -10V at this time.
  • the level transmission signal ST(36) is -10V
  • VSS1 is -5V
  • the seventeenth controllable switch T17 In a good cut-off state.
  • the fourteenth to seventeenth controllable switches T14-T17 are both turned on, and the scan signal outputted by the scan signal output terminal G (32) and the upper portion The pull control signal point Q (32)) is pulled to a low potential; in the following time, the clock signal CK8 is periodically high, and the pull-down control signal point P (32) is periodically high.
  • the sixth to eighth controllable switches T6-T8 and the thirteenth controllable switch T13 are periodically turned on, and the pull-up control signal point Q (32) can be well maintained to the second The potential of the voltage terminal VSS2, the scan signal outputted by the scan signal output terminal G (32) can be well maintained to the potential of the first voltage terminal VSS1.
  • FIG. 10 is a schematic diagram of the waveform of the sexual tolerance simulation of the scan driving circuit of the present invention.
  • the scan driving circuit can still operate normally when the threshold voltage Vth is -7v, indicating that the performance of the scan driving circuit of the present application is very good.
  • the scan driving circuit prevents leakage by the pull-up circuit, the down-transfer circuit, the pull-up control circuit, the pull-down sustain circuit, the pull-down circuit and the bootstrap circuit, thereby preventing the threshold voltage from being biased to cause the scan drive circuit to fail.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

公开一种扫描驱动电路，包括若干依次连接的扫描驱动单元(1)，每一扫描驱动单元包括扫描信号输出端（G（n）），输出高或低电平的扫描信号；上拉电路（10），控制输出高电平的扫描信号；下传电路（20），输出高电平的本级级传信号；上拉控制电路（30），对上拉控制信号点进行充电以将电位上拉至高电平；下拉维持电路（40），维持上拉控制信号点及扫描信号的低电平；自举电路（50），提升上拉控制信号点的电位，以此来防止漏电，进而防止阈值电压偏负造成扫描驱动电路失效。

Description

扫描驱动电路
【技术领域】
本发明涉及显示技术领域，特别是涉及一种扫描驱动电路。
【背景技术】
GOA(Gate Driver on Array)技术有利于显示屏窄边框设计和成本的降低，得到广泛地应用和研究。铟镓锌氧化物（IGZO）具有高的迁移率和良好的器件稳定性，可减少扫描驱动电路的复杂程度，由于IGZO的高迁移率使得扫描驱动电路中薄膜晶体管的尺寸相对较小，有利于窄边框显示器的制作；其次由于IGZO的器件稳定性可以减少用来稳定薄膜晶体管性能的电源和薄膜晶体管的数量，从而使得电路简单且功耗低，然而由于IGZO材料本身的特点，初始的阈值电压Vth容易为负值，并且受到光照的影响会造成阈值电压Vth负向漂移严重，进而可能造成扫描驱动电路失效。
【发明内容】
本发明主要解决的技术问题是提供一种扫描驱动电路，以防止阈值电压偏负造成扫描驱动电路失效。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种扫描驱动电路，所述扫描驱动电路包括若干依次连接的扫描驱动单元，每一扫描驱动单元包括：
扫描信号输出端，用于输出高电平的扫描信号或者低电平的扫描信号；
上拉电路，用于接收本级时钟信号并根据所述本级时钟信号控制所述扫描信号输出端输出高电平的扫描信号；
下传电路，连接所述上拉电路，用于输出高电平的本级级传信号；
上拉控制电路，连接下传电路，用于对上拉控制信号点进行充电以将所述上拉控制信号点的电位上拉至高电平；
下拉维持电路，连接所述上拉控制电路，用于维持所述上拉控制信号点的低电平及所述扫描信号输出端输出的扫描信号的低电平；
自举电路，用于提升所述上拉控制信号点的电位；及
下拉电路，所述下拉电路连接所述下传电路及所述下拉维持电路，用于接收下级级传信号并根据所述下级级传信号控制所述扫描信号输出端输出低电平的扫描信号；
所述上拉电路包括第一可控开关，所述第一可控开关的第一端接收所述本级时钟信号及连接所述下传电路，所述第一可控开关的控制端连接所述下传电路，所述第一可控开关的第二端连接所述下拉维持电路及所述扫描信号输出端。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种扫描驱动电路，所述扫描驱动电路包括若干依次连接的扫描驱动单元，每一扫描驱动单元包括：
扫描信号输出端，用于输出高电平的扫描信号或者低电平的扫描信号；
上拉电路，用于接收本级时钟信号并根据所述本级时钟信号控制所述扫描信号输出端输出高电平的扫描信号；
下传电路，连接所述上拉电路，用于输出高电平的本级级传信号；
上拉控制电路，连接下传电路，用于对上拉控制信号点进行充电以将所述上拉控制信号点的电位上拉至高电平；
下拉维持电路，连接所述上拉控制电路，用于维持所述上拉控制信号点的低电平及所述扫描信号输出端输出的扫描信号的低电平；及
自举电路，用于提升所述上拉控制信号点的电位。
本发明的有益效果是：区别于现有技术的情况，本发明的所述扫描驱动电路通过上拉电路、下传电路、上拉控制电路、下拉维持电路、所述下拉电路及自举电路来防止漏电，进而防止阈值电压偏负造成扫描驱动电路失效。
【附图说明】
图1是本发明的扫描驱动电路的第一实施例的电路示意图；
图2是图1的信号波形和电位关系示意图；
图3是图1的模拟仿真的信号波形示意图；
图4是本发明的扫描驱动电路的第32级扫描驱动单元的模拟仿真的信号波形示意图；
图5是图1的性耐性模拟仿真的信号波形示意图；
图6是本发明的扫描驱动电路的第二实施例的电路示意图；
图7是图6的信号波形和电位关系示意图；
图8是图6的模拟仿真的信号波形示意图；
图9是本发明的扫描驱动电路的第32级扫描驱动单元的模拟仿真的信号波形示意图；
图10是图6的性耐性模拟仿真的信号波形示意图。
【具体实施方式】
请参阅图1，是本发明的扫描驱动电路的第一实施例的电路示意图。所述扫描驱动电路包括若干依次连接的扫描驱动单元1，每一扫描驱动单元1包括扫描信号输出端G(n)，用于输出高电平的扫描信号或者低电平的扫描信号；
上拉电路10，用于接收本级时钟信号CK(n)并根据所述本级时钟信号CK(n)控制所述扫描信号输出端G(n)输出高电平的扫描信号；
下传电路20，连接所述上拉电路10，用于输出高电平的本级级传信号ST(n)；
上拉控制电路30，连接下传电路20，用于对上拉控制信号点Q(n)进行充电以将所述上拉控制信号点Q(n)的电位上拉至高电平；
下拉维持电路40，连接所述上拉控制电路30，用于维持所述上拉控制信号点Q(n)的低电平及所述扫描信号输出端G(n)输出的扫描信号的低电平；及
自举电路50，用于提升所述上拉控制信号点Q(n)的电位。
所述扫描驱动单元1还包括下拉电路60，所述下拉电路60连接所述下传电路20及所述下拉维持电路40，用于接收下级级传信号ST(n+4)并根据所述下级级传信号ST(n+4)控制所述扫描信号输出端G(n)输出低电平的扫描信号。
所述上拉电路10包括第一可控开关T1，所述第一可控开关T1的第一端接收所述本级时钟信号CK(n)及连接所述下传电路20，所述第一可控开关T1的控制端连接所述下传电路20，所述第一可控开关T1的第二端连接所述下拉维持电路40及所述扫描信号输出端G(n)。
所述下传电路20包括第二可控开关T2，所述第二可控开关T2的控制端连接所述第一可控开关T1的控制端，所述第二可控开关T2的第一端连接所述第一可控开关T1的第一端，所述第二可控开关T2的第二端输出本级级传信号ST(n)。
所述上拉控制电路30包括第三至第五可控开关T3-T5，所述第三可控开关T3的控制端连接所述第二可控开关T2的控制端、第五可控开关T5的第二端及所述下拉维持电路40，所述第三可控开关T3的第一端连接所述第四可控开关T4的第二端及所述第五可控开关T5的第一端，所述第三可控开关T3的第二端连接所述下拉维持电路40，所述第四可控开关T4的第一端接收上级级传信号ST(n-4)，所述第四可控开关T4的控制端连接所述第五可控开关T5的控制端并接收第一时钟信号XCK。
所述下拉维持电路40包括第六至第十三可控开关T6-T13，所述第六可控开关T6的控制端连接所述第五可控开关T5的第二端，所述第六可控开关T6的第一端连接所述第三可控开关T3的第二端，所述第六可控开关T6的第二端连接所述第七可控开关T7的第二端及所述第八可控开关T8的第一端，所述第七可控开关T7的第一端连接所述第五可控开关T5的第二端，第七可控开关T7的控制端连接所述第八可控开关T8的控制端，第八可控开关T8的第二端连接第二电压端VSS2，所述第九可控开关T9的控制端连接所述第九可控开关T9的第一端及所述第十一可控开关T11的第一端并接收本级时钟信号CK(n)，所述第九可控开关T9的第二端连接所述第十可控开关T10的第一端及所述第十一可控开关T11的控制端，第十可控开关T10的控制端连接所述第十二可控开关T12的控制端及所述上拉控制信号点Q(n)，所述第十可控开关T10的第二端连接第一电压端VSS1，第十一可控开关T11的第二端连接所述第十二可控开关T12的第一端、所述第十三可控开关T13的控制端及所述第八可控开关T8的控制端，所述第十二可控开关T12的第二端连接所述第二电压端VSS2，所述第十三可控开关T13的第一端连接所述第一可控开关T1的第二端、所述扫描信号输出端G(n)及所述第六可控开关T6的第一端，所述第十三可控开关T13的第二端连接所述第一电压端VSS1。
所述自举电路50包括自举电容C1，所述自举电容C1的一端连接所述第三可控开关T3的控制端，所述自举电容C1的另一端连接所述第三可控开关T3的第二端。
在本实施例中，所述第一至第十三可控开关T1-T13均为N型薄膜晶体管，所述第一至第十三可控开关T1-T13的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。在其他实施例中，所述第一至第十三可控开关也可为其他类型的开关，只要能实现本发明的目的即可。
在本实施例中，所述本级时钟信号CK(n)的相位与所述第一时钟信号XCK的相位相反，其为一组高频交流电源。所述第一电压端VSS1及所述第二电压端VSS2分别为直流电源。本发明以8K4K显示为例进行说明，其中采用8个时钟信号，每两个时钟信号之间的重叠时间为3.75微秒，触发信号STV每一帧有一个脉冲，且脉宽为30微秒，所述触发信号STV和时钟信号CK之间的重叠时间为3.75微秒。
在本实施例中，时钟信号CK的高电位为28V，低电位为-10V。由于本发明采用8个时钟信号CK，所以时钟信号CK1与CK5相位相反，时钟信号CK2与CK6相位相反，时钟信号CK3与CK7相位相反，时钟信号CK4与CK8相位相反。所述上级级传信号ST(N-4)连接前面第四级的级传信号，例如，当前级为第10级，则ST(N)=ST(10)，ST(N-4)=ST(6)，也就是所述第四可控开关T4的第一端和第6级的级传信号ST(6)相连。其中，前四级每一级的第四可控开关T4的第一端均与触发信号STV相连。所述第一电压端VSS1的电压为-5V，所述第二电压端VSS2的电压为-10V。
请参阅图2至图4，本实施例的扫描驱动电路以第32级扫描驱动单元的工作原理为例进行说明。即G(N)=G(32)，ST(N-4)=ST(28)，扫描信号输出端G(32)输出的扫描信号由时钟信号CK8控制，级传信号ST(28)由时钟信号CK4控制，第一时钟信号XCK为时钟信号CK4。
当级传信号ST(28)为高电位时，时钟信号CK4为高电位，所述第四可控开关T4及所述第五可控开关T5均导通，级传信号ST(28)的高电位传入到所述上拉控制信号点Q(32)，此时所述上拉控制信号点Q(32)为高电位，则所述第一可控开关T1导通，此时，时钟信号CK8是低电位，所以扫描信号输出端G(32)输出的扫描信号为低电位，此时所述第九可控开关T9及所述第十二可控开关T12均导通，所述第二电压端VSS2将所述下拉控制信号点P（32) 的电位拉低，此时所述第十三可控开关T13、所述第七可控开关T7及所述第八可控开关T8均截止，因此所述第一电压端VSS1不会拉低所述扫描信号输出端G(32)输出的扫描信号的电位。
当级传信号ST(28)为低电位时，时钟信号CK4为低电位，所述第四可控开关T4及所述第五可控开关T5均截止，此时，时钟信号CK8为高电位，扫描信号输出端G(32)输出的扫描信号为高电位，所述上拉控制信号点Q(32)受到电容C1的耦合效应被抬升到更高的电位，所述下拉控制信号点P(32)继续保持低电位。
在此，需要说明本发明的所述扫描驱动电路是如何防止阈值电压Vth负偏导致电路失效的。
现有的扫描驱动电路中上拉控制电路30和下拉维持电路40的阈值电压Vth过负，上拉控制信号点Q(32)的高电位会从上拉控制电路30及下拉维持电路40漏到低电位，扫描信号输出端G(32)输出的扫描信号的高电位也会漏到低电位，这样，导致电路不能输出正常的波形，从而失效。
本发明的扫描驱动电路可以有效的防止漏电，其中当上拉控制电路30的阈值电压Vth过负时，所述第三可控开关T3导通，此时所述第五可控开关T5的第一端的电压为28V，因为时钟信号CK4此时为低电位，所以电压为-10V，那么所述第五可控开关T5的栅源极之间的电压Vgs=-10V-28V=-38V，只要所述第五可控开关T5的阈值电压Vth不小于-38V，则所述第五可控开关T5均处于截止状态，所以所述上拉控制信号点Q(32)的高电位不会从所述上拉控制电路30漏掉，所述下拉维持电路40的防止漏电的原理相同，在此不再赘述。
对于所述第十三可控开关T13的漏电，假设所述第一电压端VSS1的电位为-5V，所述第二电压端VSS2的电位为-10V，那么此时所述下拉控制信号点P(32)的电位为-10V，所述第十三可控开关T13的栅源极之间的电压Vgs=-10V-(-5V)=-5V，只要所述第十三可控开关T13的阈值电压Vth不小于-5V，所述第五可控开关T5均为截止状态，所以扫描信号输出端G(32)输出的扫描信号的高电位不会从所述第十三可控开关T13漏掉。
当时钟信号CK8为低电位时，所述扫描信号输出端G(32)输出的扫描信号被拉到低电位，同时，时钟信号CK4为高电位，级传信号ST(28)的低电位传到所述上拉控制信号点Q(32)，所述上拉控制信号点Q(32)被拉到低电位。之后的时间里，时钟信号CK8会周期性的为高电位，所述下拉控制信号点P(32)会周期性的为高电位，那么所述第十三可控开关T13、所述第七可控开关T7及所述第八可控开关T8会周期性的导通，所述上拉控制信号点Q(32)能够很好的维持到所述第二电压端VSS2的电位，所述扫描信号输出端G(32)输出的扫描信号能够很好的维持到所述第一电压端VSS1的电位。
请参阅图5，是本发明的扫描驱动电路的性耐性模拟仿真波形示意图。从图5中可以看出，当阈值电压Vth为-7v时所述扫描驱动电路依然可以正常工作，说明本申请的扫描驱动电路的性耐性非常好。
所述扫描驱动电路通过上拉电路、下传电路、上拉控制电路、下拉维持电路及自举电路来防止漏电，进而防止阈值电压偏负造成扫描驱动电路失效。
请参考图6，是本发明的扫描驱动电路的第二实施例的电路示意图。所述扫描驱动电路的第二实施例与上述第一实施例的区别之处在于：所述上拉控制电路30包括第三至第五可控开关T3-T5，所述第三可控开关T3的控制端连接所述第二可控开关T2的控制端、第五可控开关T5的第二端及所述下拉维持电路40，所述第三可控开关T3的第一端连接所述第四可控开关T4的第二端及所述第五可控开关T5的第一端，所述第三可控开关T3的第二端连接所述下拉维持电路40，所述第四可控开关T4的第一端接收上级级传信号ST(n-4)，所述第四可控开关T4的控制端连接所述第五可控开关T5的控制端并接收所述上级级传信号ST(n-4)。
所述下拉维持电路40包括第六至第十三可控开关T6-T13，所述第六可控开关T6的控制端连接所述第五可控开关T5的第二端，所述第六可控开关T6的第一端连接所述第三可控开关T3的第二端，所述第六可控开关T6的第二端连接所述第七可控开关T7的第二端及所述第八可控开关T8的第一端，所述第七可控开关T7的第一端连接所述第五可控开关T5的第二端，所述第七可控开关T7的控制端连接所述第八可控开关T8的控制端，所述第八可控开关T8的第二端连接第二电压端VSS2，所述第九可控开关T9的控制端连接所述第九可控开关T9的第一端及所述第十一可控开关T11的第一端并接收本级时钟信号CK(n)，所述第九可控开关T9的第二端连接所述第十可控开关T10的第一端及所述第十一可控开关T11的控制端，第十可控开关T10的控制端连接所述第十二可控开关T12的控制端及所述上拉控制信号点Q(n)，所述第十可控开关T10的第二端连接第一电压端VSS1，第十一可控开关T11的第二端连接所述第十二可控开关T12的第一端、所述第十三可控开关T13的控制端及所述第八可控开关T8的控制端，所述第十二可控开关T12的第二端连接所述第二电压端VSS2，所述第十三可控开关T13的第一端连接所述第六可控开关T6的第一端，所述第十三可控开关T13的第二端连接所述第一电压端VSS1。
所述下拉电路60包括第十四至第十七可控开关T14-T17，所述第十四可控开关T14的控制端连接所述第十五可控开关T15的第一端及所述第二可控开关T2的控制端，所述第十四可控开关T14的第一端连接所述扫描信号输出端G(n)及所述第十三可控开关T13的第一端，所述第十四可控开关T14的第二端连接所述第十五可控开关T15的第二端及所述第十六可控开关T16的第一端，所述第十五可控开关T15的控制端连接所述第十六可控开关T16的控制端及所述第十七可控开关T17的控制端并接收所述下级级传信号ST(n+4)，所述第十六可控开关T16的第二端连接所述第二电压端VSS2，所述第十七可控开关T17的第一端连接所述扫描信号输出端G(n)，所述第十七可控开关T17的第二端连接所述第一电压端VSS1。
在本实施例中，所述第一至第十七可控开关T1-T17均为N型薄膜晶体管，所述第一至第十七可控开关T1-T17的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。在其他实施例中，所述第一至第十七可控开关也可为其他类型的开关，只要能实现本发明的目的即可。
在本实施例中，假设时钟信号CK的高电位为28V，低电位为-10V。所述扫描驱动电路采用8个时钟信号CK，所述级传信号ST(N-4)连接前面第四级的级传信号，例如，当前级为第10级，则ST(N)=ST(10)，ST(N-4)=ST(6)，ST(N+4)=ST(10)，也就是所述第四可控开关T4的第一端和第6级的级传信号ST(6)相连。其中，前四级的每一级的扫描驱动单元1的第四可控开关T4均与触发信号STV相连，后四级的级传信号ST(n+4)用触发信号STV代替，这里设所述第一电压端VSS1的电压为-5V，所述第二电压端VSS2的电压为-10V。
请参阅图7至图9，本实施例的扫描驱动电路以第32级扫描驱动单元的工作原理为例进行说明。即G(N)=G(32)，ST(N-4)=ST(28)，ST(N+4)=ST(36)，扫描信号输出端G(32)输出的扫描信号由时钟信号CK8控制，级传信号ST(28)由时钟信号CK4控制。
当级传信号ST(28)为高电位时，时钟信号CK4为高电位，所述第四可控开关T4及所述第五可控开关T5均导通，所述级传信号ST(28)的高电位传入到所述上拉控制信号点Q(32)，所述上拉控制信号点Q(32)为高电位，此时所述第一可控开关T1导通，时钟信号CK8是低电位，所以扫描信号输出端G(32)输出的扫描信号为低电位，同时，所述第十可控开关T10及所述第十二可控开关T12均导通，因此所述第二电压端VSS2将所述下拉控制信号点P（32) 的电位拉低，此时所述第十三可控开关T13、第七可控开关T7及所述第八可控开关T8均截止，所述第二电压端VSS2的低电位不会拉低扫描信号输出端G(32)输出的扫描信号的电位。
当级传信号ST(28)为低电位时，时钟信号CK4为低电位，所述第四可控开关T4及所述第五可控开关T5均截止，此时时钟信号CK8为高电位，所述扫描信号输出端G(32)输出的扫描信号为高电位，所述上拉控制信号点Q(32)受到电容C1的耦合效应被抬升到更高的电位，所述下拉控制信号点P(32)继续保持低电位。
在此，需要说明本发明的扫描驱动电路是如何防止阈值电压Vth负偏导致电路失效的。
现有的扫描驱动电路中的上拉控制电路30、下拉电路60及下拉维持电路40的阈值电压Vth过负时，上拉控制信号点Q(32)的高电位会从上拉控制电路30、下拉电路60及下拉维持电路40漏到低电位，扫描信号输出端G(32)输出的扫描信号的高电位从下拉电路60及下拉维持电路40漏到低电位，这样导致扫描驱动电路不能输出正常的波形，从而失效。
本发明的扫描驱动电路可以有效的防止漏电，其中当所述上拉控制电路30的阈值电压Vth过负时，所述第三可控开关T3导通，此时所述第五可控开关T5的第一端的电压为28V，因为时钟信号CK4此时为低电位，所以电压为-10V，所述第五可控开关T5的栅源极之间的电压Vgs=-10V-28V=-38V，只要所述第五可控开关T5的阈值电压Vth不小于-38V，则所述五可控开关T5均为截止状态，所以所述上拉控制信号点Q(32)的高电位不会从所述上拉控制电路30漏掉，所述下拉维持电路40的防漏电的原理相同，在此不再赘述。
对于所述第十三可控开关T13及所述第十七可控开关T17的漏电，假设所述第一电压端VSS1的电位为-5V，所述第二电压端VSS2的电位为-10V，那么此时所述下拉控制信号点P(32)的电位为-10V, 所述第十三可控开关T13的栅源极之间的电压Vgs=-10V-(-5V)=-5V，只要所述第十三可控开关T13的阈值电压Vth不小于-5V，则所述第五可控开关T5均为截止状态，所以扫描信号输出端G(32)输出的扫描信号的高电位不会从所述下拉维持电路40漏掉。同理，级传信号ST(36)为-10V，VSS1为-5V，所述第十七可控开关T17的栅源极之间的电压Vgs=-5V，所述第十七可控开关T17处于很好的截止状态。
当级传信号ST(36)为高电位时，所述第十四至第十七可控开关T14-T17均导通，所述扫描信号输出端G(32)输出的扫描信号及所述上拉控制信号点Q(32))被拉到低电位；之后的时间里，时钟信号CK8会周期性的为高电位，所述下拉控制信号点P(32)会周期性的为高电位，所述第六至第八可控开关T6-T8及所述第十三可控开关T13会周期性的导通，所述上拉控制信号点Q(32)能够很好的维持到所述第二电压端VSS2的电位，所述扫描信号输出端G(32)输出的扫描信号能够很好的维持到所述第一电压端VSS1的电位。
请参阅图10，是本发明的扫描驱动电路的性耐性模拟仿真波形示意图。从图10中可以看出，当阈值电压Vth为-7v时所述扫描驱动电路依然可以正常工作，说明本申请的扫描驱动电路的性耐性非常好。
所述扫描驱动电路通过上拉电路、下传电路、上拉控制电路、下拉维持电路、所述下拉电路及自举电路来防止漏电，进而防止阈值电压偏负造成扫描驱动电路失效。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (12)

  1. 一种扫描驱动电路，其中，所述扫描驱动电路包括若干依次连接的扫描驱动单元，每一扫描驱动单元包括：
    扫描信号输出端，用于输出高电平的扫描信号或者低电平的扫描信号；
    上拉电路，用于接收本级时钟信号并根据所述本级时钟信号控制所述扫描信号输出端输出高电平的扫描信号；
    下传电路，连接所述上拉电路，用于输出高电平的本级级传信号；
    上拉控制电路，连接下传电路，用于对上拉控制信号点进行充电以将所述上拉控制信号点的电位上拉至高电平；
    下拉维持电路，连接所述上拉控制电路，用于维持所述上拉控制信号点的低电平及所述扫描信号输出端输出的扫描信号的低电平；
    自举电路，用于提升所述上拉控制信号点的电位；及
    下拉电路，所述下拉电路连接所述下传电路及所述下拉维持电路，用于接收下级级传信号并根据所述下级级传信号控制所述扫描信号输出端输出低电平的扫描信号；
    所述上拉电路包括第一可控开关，所述第一可控开关的第一端接收所述本级时钟信号及连接所述下传电路，所述第一可控开关的控制端连接所述下传电路，所述第一可控开关的第二端连接所述下拉维持电路及所述扫描信号输出端。
  2. 一种扫描驱动电路，其中，所述扫描驱动电路包括若干依次连接的扫描驱动单元，每一扫描驱动单元包括：
    扫描信号输出端，用于输出高电平的扫描信号或者低电平的扫描信号；
    上拉电路，用于接收本级时钟信号并根据所述本级时钟信号控制所述扫描信号输出端输出高电平的扫描信号；
    下传电路，连接所述上拉电路，用于输出高电平的本级级传信号；
    上拉控制电路，连接下传电路，用于对上拉控制信号点进行充电以将所述上拉控制信号点的电位上拉至高电平；
    下拉维持电路，连接所述上拉控制电路，用于维持所述上拉控制信号点的低电平及所述扫描信号输出端输出的扫描信号的低电平；及
    自举电路，用于提升所述上拉控制信号点的电位。
  3. 根据权利要求2所述的扫描驱动电路，其中，所述扫描驱动单元还包括下拉电路，所述下拉电路连接所述下传电路及所述下拉维持电路，用于接收下级级传信号并根据所述下级级传信号控制所述扫描信号输出端输出低电平的扫描信号。
  4. 根据权利要求2所述的扫描驱动电路，其中，所述上拉电路包括第一可控开关，所述第一可控开关的第一端接收所述本级时钟信号及连接所述下传电路，所述第一可控开关的控制端连接所述下传电路，所述第一可控开关的第二端连接所述下拉维持电路及所述扫描信号输出端。
  5. 根据权利要求4所述的扫描驱动电路，其中，所述下传电路包括第二可控开关，所述第二可控开关的控制端连接所述第一可控开关的控制端，所述第二可控开关的第一端连接所述第一可控开关的第一端，所述第二可控开关的第二端输出本级级传信号。
  6. 根据权利要求5所述的扫描驱动电路，其中，所述上拉控制电路包括第三至第五可控开关，所述第三可控开关的控制端连接所述第二可控开关的控制端、第五可控开关的第二端及所述下拉维持电路，所述第三可控开关的第一端连接所述第四可控开关的第二端及所述第五可控开关的第一端，所述第三可控开关的第二端连接所述下拉维持电路，所述第四可控开关的第一端接收上级级传信号，所述第四可控开关的控制端连接所述第五可控开关的控制端并接收第一时钟信号。
  7. 根据权利要求6所述的扫描驱动电路，其中，所述下拉维持电路包括第六至第十三可控开关，所述第六可控开关的控制端连接所述第五可控开关的第二端，所述第六可控开关的第一端连接所述第三可控开关的第二端，所述第六可控开关的第二端连接所述第七可控开关的第二端及所述第八可控开关的第一端，所述第七可控开关的第一端连接所述第五可控开关的第二端，第七可控开关的控制端连接所述第八可控开关的控制端，第八可控开关的第二端连接第二电压端，所述第九可控开关的控制端连接所述第九可控开关的第一端及所述第十一可控开关的第一端并接收本级时钟信号，所述第九可控开关的第二端连接所述第十可控开关的第一端及所述第十一可控开关的控制端，第十可控开关的控制端连接所述第十二可控开关的控制端及所述上拉控制信号点，所述第十可控开关的第二端连接第一电压端，第十一可控开关的第二端连接所述第十二可控开关的第一端、所述第十三可控开关的控制端及所述第八可控开关的控制端，所述第十二可控开关的第二端连接所述第二电压端，所述第十三可控开关的第一端连接所述第一可控开关的第二端、所述扫描信号输出端及所述第六可控开关的第一端，所述第十三可控开关的第二端连接所述第一电压端。
  8. 根据权利要求6所述的扫描驱动电路，其中，所述自举电路包括自举电容，所述自举电容的一端连接所述第三可控开关的控制端，所述自举电容的另一端连接所述第三可控开关的第二端。
  9. 根据权利要求6所述的扫描驱动电路，其中，所述上拉控制电路包括第三至第五可控开关，所述第三可控开关的控制端连接所述第二可控开关的控制端、第五可控开关的第二端及所述下拉维持电路，所述第三可控开关的第一端连接所述第四可控开关的第二端及所述第五可控开关的第一端，所述第三可控开关的第二端连接所述下拉维持电路，所述第四可控开关的第一端接收上级级传信号，所述第四可控开关的控制端连接所述第五可控开关的控制端并接收所述上级级传信号。
  10. 根据权利要求9所述的扫描驱动电路，其中，所述下拉维持电路包括第六至第十三可控开关，所述第六可控开关的控制端连接所述第五可控开关的第二端，所述第六可控开关的第一端连接所述第三可控开关的第二端，所述第六可控开关的第二端连接所述第七可控开关的第二端及所述第八可控开关的第一端，所述第七可控开关的第一端连接所述第五可控开关的第二端，所述第七可控开关的控制端连接所述第八可控开关的控制端，所述第八可控开关的第二端连接第二电压端，所述第九可控开关的控制端连接所述第九可控开关的第一端及所述第十一可控开关的第一端并接收本级时钟信号，所述第九可控开关的第二端连接所述第十可控开关的第一端及所述第十一可控开关的控制端，第十可控开关的控制端连接所述第十二可控开关的控制端及所述上拉控制信号点，所述第十可控开关的第二端连接第一电压端，第十一可控开关的第二端连接所述第十二可控开关的第一端、所述第十三可控开关的控制端及所述第八可控开关的控制端，所述第十二可控开关的第二端连接所述第二电压端，所述第十三可控开关的第一端连接所述第六可控开关的第一端，所述第十三可控开关的第二端连接所述第一电压端。
  11. 根据权利要求10所述的扫描驱动电路，其中，所述下拉电路包括第十四至第十七可控开关，所述第十四可控开关的控制端连接所述第十五可控开关的第一端及所述第二可控开关的控制端，所述第十四可控开关的第一端连接所述扫描信号输出端及所述第十三可控开关的第一端，所述第十四可控开关的第二端连接所述第十五可控开关的第二端及所述第十六可控开关的第一端，所述第十五可控开关的控制端连接所述第十六可控开关的控制端及所述第十七可控开关的控制端并接收所述下级级传信号，所述第十六可控开关的第二端连接所述第二电压端，所述第十七可控开关的第一端连接所述扫描信号输出端，所述第十七可控开关的第二端连接所述第一电压端。
  12. 根据权利要求9所述的扫描驱动电路，其中，所述自举电路包括自举电容，所述自举电容的一端连接所述第三可控开关的控制端，所述自举电容的另一端连接所述第三可控开关的第二端。
PCT/CN2017/084119 2017-04-21 2017-05-12 扫描驱动电路 WO2018192026A1 (zh)

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