WO2019100525A1 - 一种 goa 电路及嵌入式触控显示面板 - Google Patents

一种 goa 电路及嵌入式触控显示面板 Download PDF

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Publication number
WO2019100525A1
WO2019100525A1 PCT/CN2017/119414 CN2017119414W WO2019100525A1 WO 2019100525 A1 WO2019100525 A1 WO 2019100525A1 CN 2017119414 W CN2017119414 W CN 2017119414W WO 2019100525 A1 WO2019100525 A1 WO 2019100525A1
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Prior art keywords
node
thin film
film transistor
control signal
goa
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PCT/CN2017/119414
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English (en)
French (fr)
Inventor
龚强
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武汉华星光电技术有限公司
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Priority to US15/742,211 priority Critical patent/US10388240B2/en
Publication of WO2019100525A1 publication Critical patent/WO2019100525A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a GOA circuit and an embedded touch display panel.
  • the technology that is, the array substrate row driving technology, is to use a thin film transistor liquid crystal display array process to fabricate a gate scan driving circuit on a thin film transistor array substrate to realize a progressive scanning driving method.
  • the display panel will choose to embed the touch display panel. Embedded in the touch display panel, because the display refresh time is separated, to free time ( TP The stop time is done in the touch scan, so the working state of the GOA circuit of the panel is not continuous, but a certain number of levels per scan, for a period of time, to continue scanning. In this way, at GOA When the circuit is in the hold state, it is easy to have the problem of insufficient circuit maintenance capability, causing the GOA circuit level transmission to fail and display abnormality.
  • An object of the present invention is to provide a GOA circuit and an embedded touch display panel, which can reduce the GOA circuit in the TP. Insufficient maintenance during the stop, which reduces the risk of failure of the pass, making the GOA circuit more stable.
  • a GOA circuit for use in an embedded touch display panel comprising: a multi-level cascaded GOA unit, an nth level GOA
  • the unit includes: a forward and reverse scan control module, a node control module, an output module, an output control module, and a precharge module;
  • the forward/reverse scan control module is configured to output a first node control signal at a first node and a second node control signal at a second node according to the forward scan DC control signal and the reverse scan DC control signal;
  • the node control module is coupled to the first node and the second node, configured to pull the first node control signal to a constant voltage low potential and raise the second node control signal to a constant voltage high Potential
  • the output module is coupled to the first node and electrically connected to the first clock signal, and configured to output a scan signal according to the first node control signal and the first clock signal;
  • the output control module is electrically connected to the first control signal, and is configured to pull the scan signal to a constant voltage low potential according to the first control signal;
  • the pre-charging module is coupled to the first node and electrically connected to the n+2th GOA
  • the first node of the unit is configured to pre-control the first node control signal on the first node of the n+2th GOA unit when the embedded touch display panel enters the signal and stops the touch scanning phase Charging
  • the pre-charging module includes: a first thin film transistor and a second thin film transistor;
  • the gate and the source of the first thin film transistor are both connected to the first node, the drain of the first thin film transistor is connected to the source of the second thin film transistor, and the drain of the second thin film transistor is Pole and the n+2th level a first node of the GOA unit is connected, and a gate of the second thin film transistor is connected to the first control signal;
  • the first control signal When the embedded touch display panel is normally displayed, the first control signal is low; when the embedded touch display panel enters a signal and stops performing a touch scanning phase, the first control signal It is high potential.
  • the forward-reverse scan control module includes: a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a first capacitor, and a second capacitor;
  • the source of the third thin film transistor is connected to the forward scanning DC control signal, and the gate is connected to the n-2th GOA a scan signal of the cell, the drain being connected to the first node, the drain of the second thin film transistor, and the gate of the third thin film transistor;
  • the source of the fourth thin film transistor is connected to the reverse scan DC control signal, and the gate is connected to the n+2th GOA The scanning signal of the unit;
  • a source of the fifth thin film transistor is connected to a constant voltage low potential, and a drain is connected to the second node;
  • One end of the first capacitor is connected to the first node, and the other end is connected to a constant voltage low potential;
  • One end of the second capacitor is connected to the second node, and the other end is connected to a constant voltage low potential.
  • the node control module includes: a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, and a ninth thin film transistor;
  • a source of the sixth thin film transistor is connected to the second clock signal, a gate is connected to the forward scan DC control signal, and a drain is connected to a gate of the eighth thin film transistor;
  • a source of the seventh thin film transistor is connected to a third clock signal, a gate is connected to the reverse scan DC control signal, and a drain is connected to a gate of the eighth thin film transistor;
  • the source of the eighth thin film transistor is connected to a constant voltage high potential, and the drain is connected to the second node;
  • the source of the ninth thin film transistor is connected to a constant voltage low potential, the gate is connected to the second node, and the drain is connected to the first node.
  • the output module comprises: a tenth thin film transistor
  • the source of the tenth thin film transistor is connected to the first clock signal, the gate is connected to the first node, and the drain is connected to the output end of the output module.
  • the output control module includes an eleventh thin film transistor and a twelfth thin film transistor
  • a source of the eleventh thin film transistor is connected to a constant voltage low potential, a gate is connected to the second node, and a drain is connected to an output end of the output module;
  • the source of the twelfth thin film transistor is connected to a constant voltage low potential, the gate is connected to the first control signal, and the drain is connected to the output end of the output module.
  • the nth level GOA further includes: a reset module; the reset module includes: a thirteenth thin film transistor, a source and a drain of the thirteenth thin film transistor are connected to a reset signal, and a drain is electrically connected to the second node.
  • the GOA The forward scan DC control signal is high when the circuit is being forwardly scanned, and the reverse scan DC control signal is low; the GOA When the circuit is reversely scanned, the forward scan DC control signal is at a low potential, and the reverse scan DC control signal is at a high potential.
  • a GOA circuit for use in an embedded touch display panel comprising: a multi-level cascaded GOA unit, an nth stage
  • the GOA unit includes: a forward and reverse scan control module, a node control module, an output module, an output control module, and a precharge module;
  • the forward/reverse scan control module is configured to output a first node control signal at a first node and a second node control signal at a second node according to the forward scan DC control signal and the reverse scan DC control signal;
  • the node control module is coupled to the first node and the second node, configured to pull the first node control signal to a constant voltage low potential and raise the second node control signal to a constant voltage high Potential
  • the output module is coupled to the first node and electrically connected to the first clock signal, and configured to output a scan signal according to the first node control signal and the first clock signal;
  • the output control module is electrically connected to the first control signal, and is configured to pull the scan signal to a constant voltage low potential according to the first control signal;
  • the pre-charging module is coupled to the first node and electrically connected to the n+2th GOA
  • the first node of the unit is configured to pre-control the first node control signal on the first node of the n+2th GOA unit when the embedded touch display panel enters the signal and stops the touch scanning phase Charging.
  • the pre-charging module includes: a first thin film transistor and a second thin film transistor;
  • the gate and the source of the first thin film transistor are both connected to the first node, the drain of the first thin film transistor is connected to the source of the second thin film transistor, and the drain of the second thin film transistor is Pole and the n+2th level A first node of the GOA unit is connected, and a gate of the second thin film transistor is connected to the first control signal.
  • the forward-reverse scan control module includes: a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a first capacitor, and a second capacitor;
  • the source of the third thin film transistor is connected to the forward scanning DC control signal, and the gate is connected to the n-2th GOA a scan signal of the cell, the drain being connected to the first node, the drain of the second thin film transistor, and the gate of the third thin film transistor;
  • the source of the fourth thin film transistor is connected to the reverse scan DC control signal, and the gate is connected to the n+2th GOA The scanning signal of the unit;
  • a source of the fifth thin film transistor is connected to a constant voltage low potential, and a drain is connected to the second node;
  • One end of the first capacitor is connected to the first node, and the other end is connected to a constant voltage low potential;
  • One end of the second capacitor is connected to the second node, and the other end is connected to a constant voltage low potential.
  • the node control module includes: a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, and a ninth thin film transistor;
  • a source of the sixth thin film transistor is connected to the second clock signal, a gate is connected to the forward scan DC control signal, and a drain is connected to a gate of the eighth thin film transistor;
  • a source of the seventh thin film transistor is connected to a third clock signal, a gate is connected to the reverse scan DC control signal, and a drain is connected to a gate of the eighth thin film transistor;
  • the source of the eighth thin film transistor is connected to a constant voltage high potential, and the drain is connected to the second node;
  • the source of the ninth thin film transistor is connected to a constant voltage low potential, the gate is connected to the second node, and the drain is connected to the first node.
  • the output module comprises: a tenth thin film transistor
  • the source of the tenth thin film transistor is connected to the first clock signal, the gate is connected to the first node, and the drain is connected to the output end of the output module.
  • the output control module includes an eleventh thin film transistor and a twelfth thin film transistor
  • a source of the eleventh thin film transistor is connected to a constant voltage low potential, a gate is connected to the second node, and a drain is connected to an output end of the output module;
  • the source of the twelfth thin film transistor is connected to a constant voltage low potential, the gate is connected to the first control signal, and the drain is connected to the output end of the output module.
  • the nth level GOA further includes: a reset module; the reset module includes: a thirteenth thin film transistor, a source and a drain of the thirteenth thin film transistor are connected to a reset signal, and a drain is electrically connected to the second node.
  • the first control signal when the embedded touch display panel is normally displayed, the first control signal is low; when the embedded touch display panel enters a signal and stops performing a touch scanning phase, the first A control signal is high.
  • the GOA The forward scan DC control signal is high when the circuit is being forwardly scanned, and the reverse scan DC control signal is low; the GOA When the circuit is reversely scanned, the forward scan DC control signal is at a low potential, and the reverse scan DC control signal is at a high potential.
  • An embedded touch display panel comprising a GOA circuit, the GOA
  • the circuit is applied to an embedded touch display panel, which comprises: a multi-level cascaded GOA unit, an nth level GOA
  • the unit includes: a forward and reverse scan control module, a node control module, an output module, an output control module, and a precharge module;
  • the forward/reverse scan control module is configured to output a first node control signal at a first node and a second node control signal at a second node according to the forward scan DC control signal and the reverse scan DC control signal;
  • the node control module is coupled to the first node and the second node, configured to pull the first node control signal to a constant voltage low potential and raise the second node control signal to a constant voltage high Potential
  • the output module is coupled to the first node and electrically connected to the first clock signal, and configured to output a scan signal according to the first node control signal and the first clock signal;
  • the output control module is electrically connected to the first control signal, and is configured to pull the scan signal to a constant voltage low potential according to the first control signal;
  • the pre-charging module is coupled to the first node and electrically connected to the n+2th GOA
  • the first node of the unit is configured to pre-control the first node control signal on the first node of the n+2th GOA unit when the embedded touch display panel enters the signal and stops the touch scanning phase Charging.
  • the pre-charging module includes: a first thin film transistor and a second thin film transistor;
  • the gate and the source of the first thin film transistor are both connected to the first node, the drain of the first thin film transistor is connected to the source of the second thin film transistor, and the drain of the second thin film transistor is Pole and the n+2th level A first node of the GOA unit is connected, and a gate of the second thin film transistor is connected to the first control signal.
  • the first control signal when the embedded touch display panel is normally displayed, the first control signal is low; when the embedded touch display panel enters a signal, it stops and performs The first control signal is at a high potential during the touch scanning phase.
  • the GOA The forward scan DC control signal is high when the circuit is being forwardly scanned, and the reverse scan DC control signal is low; the GOA When the circuit is reversely scanned, the forward scan DC control signal is at a low potential, and the reverse scan DC control signal is at a high potential.
  • the GOA circuit provided by the present invention and the embedded touch display panel are passed through the nth level GOA
  • the unit is provided with a pre-charging module, and when the embedded touch display panel enters the signal and stops the touch scanning phase, the first node control signal on the first node of the n+2th GOA unit is pre-charged, which is reduced.
  • the GOA circuit maintains insufficient capacity during the TP, which reduces the risk of failure of the stage transmission and makes the GOA circuit more stable.
  • FIG. 1 is a circuit diagram of a GOA circuit according to an embodiment of the present invention.
  • FIG. 2 is a first timing diagram of a GOA circuit according to an embodiment of the present invention.
  • FIG. 3 is a second timing diagram of a GOA circuit according to an embodiment of the present invention.
  • FIG. 4 is another circuit diagram of a GOA circuit according to an embodiment of the present invention.
  • FIG. 1 is a circuit diagram of a GOA circuit according to an embodiment of the present invention.
  • a GOA circuit includes a multi-stage cascaded GOA unit, and the nth-level GOA unit includes: a forward-reverse scan control module 101, and a node control module 102.
  • the nth level GOA unit mentioned here is the first level GOA unit and the second level GOA.
  • the forward/reverse scan control module 101 is configured to scan the DC control signal U2D and the reverse scan DC control signal according to the forward direction.
  • D2U outputs a first node control signal at a first node Q(n) and a second node control signal at a second node P(n).
  • the forward and reverse scan control module 101 includes: a third thin film transistor T3 and a fourth thin film transistor T4.
  • the source of the third thin film transistor T3 is connected to the forward scanning DC control signal U2D, and the gate is connected to the n-2 level GOA.
  • the scanning signal G(n-2) of the cell is connected to the gate of the first node Q(n), the drain of the fourth thin film transistor T4, and the gate of the fifth thin film transistor T5; the fourth thin film transistor T4
  • the source is connected to the reverse scan DC control signal D2U, the gate is connected to the scan signal G(n+2) of the n+2th GOA unit; the source of the fifth thin film transistor T5 is connected to the constant voltage low potential VGL
  • the drain is connected to the second node P(n); one end of the first capacitor C1 is connected to the first node Q(n), and the other end is connected to the constant voltage low potential VGL; one end of the second capacitor C2 is connected to the second node P (n) Connect the other end to the constant voltage low potential VGL.
  • the node control module 102 is coupled to the first node Q(n) and the second node P(n). , for pulling the first node control signal to the constant voltage low potential VGL and raising the second node control signal to the constant voltage high potential VGH.
  • the node control module 102 includes: a sixth thin film transistor T6, a seventh thin film transistor T7, and an eighth thin film transistor. T8 and ninth thin film transistor T9.
  • the sixth thin film transistor T6 has a source connected to the second clock signal CK2, the gate is connected to the forward scan DC control signal U2D, and the drain and the eighth thin film transistor T8
  • the gate connection of the seventh thin film transistor T7 is connected to the third clock signal CK3, the gate is connected to the reverse scan DC control signal D2U, and the drain and the eighth thin film transistor T8
  • the gate of the eighth thin film transistor T8 is connected to the constant voltage high potential VGH, the drain is connected to the second node P(n); the source of the ninth thin film transistor T9 is connected to the constant voltage low potential VGL
  • the gate is connected to the second node, and the drain is connected to the first node Q(n).
  • the output module 103 is coupled to the first node Q(n) and electrically connected to the first clock signal CK1. And for outputting the scan signal G(n) according to the first node control signal and the first clock signal CK1.
  • the output module 103 includes: a tenth thin film transistor T10; a tenth thin film transistor T10
  • the source is connected to the first clock signal CK1
  • the gate is connected to the first node Q(n)
  • the drain is connected to the output of the output module 103.
  • the output control module 104 is electrically connected to the first control signal GAS1 for using the first control signal GAS1. Pull the scan signal G(n) down to the constant voltage low potential VGL.
  • the output control module 104 includes: an eleventh thin film transistor T11 and a twelfth thin film transistor T12.
  • the eleventh thin film transistor T11 has a source connected to the constant voltage low potential VGL, the gate is connected to the second node P(n), and the drain is connected to the output terminal of the output module 103; the twelfth thin film transistor T12
  • the source is connected to the constant voltage low potential VGL, the gate is connected to the first control signal GAS1, and the drain is connected to the output end of the output module 103.
  • the pre-charging module 105 is coupled to the first node Q(n) and electrically connected to the n+2th GOA.
  • the first node Q(n+2) of the unit is used for the first node Q (n+2) of the n+2th GOA unit when the embedded touch display panel enters the signal and stops the touch scanning phase. )
  • the first node control signal is precharged.
  • the pre-charging module 105 includes: a first thin film transistor T1 and a second thin film transistor T2;
  • the gate and the source of the first thin film transistor T1 are both connected to the first node Q(n), and the first thin film transistor T1
  • the drain is connected to the source of the second thin film transistor T2, and the drain of the second thin film transistor T2 is connected to the first node Q(n+2) of the n+2th GOA unit, and the second thin film transistor T2
  • the gate is connected to the first control signal GAS1.
  • the nth stage GOA unit further includes: a reset module 106; and a reset module 106.
  • the thirteenth thin film transistor T13, the thirteenth thin film transistor T13 has a source and a drain connected to the reset signal RESET, and the drain is electrically connected to the second node P(n) .
  • the reset module 106 can be used to reset the GOA circuit when the GOA circuit operates, thereby making the GOA circuit more stable.
  • FIG. 2 is a first timing diagram of a GOA circuit according to an embodiment of the present invention
  • FIG. 3 A second timing diagram of a GOA circuit provided by an embodiment of the present invention.
  • the first control signal GAS1 It is low potential; when the embedded touch display panel enters the signal and stops the touch scanning phase, the first control signal GAS1 is high.
  • Forward scanning DC control signal U2D when GOA circuit is scanning forward For high potential, the reverse-scan DC control signal D2U is low; when the GOA circuit is reverse-scanning, the forward-scanning DC control signal U2D is low, and the reverse-scan DC control signal D2U It is high potential.
  • the scanning signal of the n-2th GOA unit is first.
  • G(n-2) is high
  • the third thin film transistor T3 is turned on, and the high potential forward scanning DC control signal U2D passes through the third thin film transistor T3 at the first node Q(n)
  • the first node control signal is output, and the high potential of the first node control signal is stored in the first capacitor C1;
  • the fifth thin film transistor T5 is turned on, and the constant voltage low potential VGL is passed through the fifth thin film transistor T5.
  • Outputting a second node control signal at the second node P(n) and storing the low potential of the second node control signal in the second capacitor C2;
  • the embedded touch display panel enters the signal and stops the touch scanning phase, the first node control signal is maintained at a high potential, and the second node control signal is maintained at a low potential, the first clock signal CK1 The output is low, at this time, the tenth thin film transistor T10 is turned on, and the low potential of the first clock signal CK1 is output to the output terminal of the output module 103 via the tenth thin film transistor T10, and the scanning signal G(n) Is low.
  • the embedded touch display panel enters the signal and stops the touch scanning phase, the nth stage.
  • the first node control signal on the first node Q(n) of the GOA unit needs to be maintained at a high potential, and at this time, the reverse scan DC control signal D2U For low potential, the high potential stored in the first node control signal will leak to the reverse DC control signal D2U and the constant voltage low potential VGL .
  • the thin film transistor is electrically unstable, if the leakage current of the thin film transistor is large, the first node controls the signal charge leakage more, and after the embedded touch display panel enters the signal and stops the touch scanning phase, the first The potential of a node control signal is low, so that the tenth thin film transistor cannot be completely turned on. T10 will cause the scan signal G(n) output from the nth stage GOA unit to have a large delay, or the waveform amplitude is lower than the constant voltage high level.
  • the G(n) anomaly causes the first node control signal on the first node Q(n+2) of the n+2th GOA unit to not be smoothly pulled up to the constant voltage high potential VGH, resulting in the n+2th stage.
  • the scan signal G(n+2) output by the GOA unit is abnormal, which causes the GOA circuit to fail.
  • the embedded touch display panel displays an abnormality.
  • the embedded touch display panel by setting a pre-charging module 105, the embedded touch display panel enters a signal and stops the touch scanning phase.
  • the first node control signal on the first node Q(n+2) of the n+2 level GOA unit is precharged, so that after the embedded touch display panel enters the signal and stops the touch scanning phase, the nth +2 level
  • the first node control signal on the GOA unit can be charged to a constant voltage high potential VGH, which reduces the risk of GOA circuit-level transmission failure and improves the stability of the GOA circuit.
  • the first control signal GAS1 When the embedded touch display panel enters the signal and stops the touch scanning phase, the first control signal GAS1 The output high potential, the first thin film transistor T1 and the second thin film transistor T2 are turned on, and the first node control signal on the first node Q(n) of the nth stage GOA unit passes through the first thin film transistor T1 And the second thin film transistor T2 precharges the first node control signal on the n+2th GOA unit, so that the n+2th GOA unit can normally output the scan signal G(n+2) It reduces the risk of GOA circuit-level transmission failure and improves the stability of the GOA circuit.
  • the first clock signal CK1 is high, and the first node Q(n) is The first node control signal is bootstrapped to a higher potential; at the same time, the second node control signal on the second node P(n) maintains a constant voltage low potential, and the scan signal G(n) of the nth stage GOA unit It is high potential.
  • the third clock signal CK3 is high, and the first node control signal on the first node Q(n) is pulled down to a constant voltage low potential.
  • VGL the second node control signal on the second node P(n) is pulled up to the constant voltage high potential VGH, and the scanning signal G(n) of the nth stage GOA unit is low.
  • FIG. 4 is another circuit diagram of a GOA circuit according to an embodiment of the present invention.
  • the GOA The circuit differs from the GOA circuit shown in FIG. 1 in that the GOA circuit further includes: a fourteenth thin film transistor T14, a fifteenth thin film transistor T15, and a sixteenth thin film transistor T16. .
  • the source of the fourteenth thin film transistor T14 is connected to the drain of the third thin film transistor T3, and the fourteenth thin film transistor T14
  • the gate is connected to the constant voltage high potential VGH, and the drain of the fourteenth thin film transistor T14 is connected to the first node Q(n).
  • the fifteenth thin film transistor T15 has a source connected to a constant voltage low potential VGL, and a fifteenth thin film transistor T15 The gate is connected to the second control signal GAS2, and the drain of the fifteenth thin film transistor T15 is connected to the second node P(n).
  • the source and the gate of the sixteenth thin film transistor T16 are connected to the second control signal GAS2, and the sixteenth thin film transistor T16 The drain is connected to the drain of the tenth thin film transistor T10.
  • the gate of the fourteenth thin film transistor is connected to a constant voltage high potential, so that the fourteenth thin film transistor clock is turned on.
  • the gates of the fifteenth thin film transistor and the sixteenth thin film transistor are both connected to the second control signal, and the second control signal is a constant voltage low potential, thereby making the fifteenth thin film transistor and the sixteenth thin film transistor Is off.
  • the circuit can also adjust the high and low potentials of the signals of the gates of the fourteenth thin film transistor, the fifteenth thin film transistor, and the sixteenth thin film transistor according to specific needs, and control the fourteenth thin film transistor, the fifteenth thin film transistor, and the tenth The state of the six thin film transistors, thereby making this The GOA circuit is more flexible to use.
  • the GOA circuit provided by the embodiment of the present invention passes the GOA at the nth level
  • the unit is provided with a pre-charging module, and when the embedded touch display panel enters the signal and stops the touch scanning phase, the first node control signal on the first node of the n+2th GOA unit is pre-charged, which is reduced.
  • the GOA circuit maintains insufficient capacity during the TP, which reduces the risk of failure of the stage transmission and makes the GOA circuit more stable.
  • the embodiment of the invention further provides an embedded touch display panel, which comprises the GOA described above
  • GOA embedded touch display panel
  • the GOA circuit provided by the present invention and the embedded touch display panel are passed through the nth level GOA
  • the unit is provided with a pre-charging module, and when the embedded touch display panel enters the signal and stops the touch scanning phase, the first node control signal on the first node of the n+2th GOA unit is pre-charged, which is reduced.
  • the GOA circuit maintains insufficient capacity during the TP, which reduces the risk of failure of the stage transmission and makes the GOA circuit more stable.

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Abstract

一种GOA电路及内嵌入触控显示面板，通过在第n级GOA单元设置预充电模块（105），当嵌入式触控显示面板进入信号中停并进行触控扫描阶段时，对第n+2级GOA单元的第一节点上的第一节点控制信号进行预充电，降低了该GOA电路在TP中停时维持能力不足，进而降低了级传失效的风险，使该GOA电路更加稳定。

Description

一种 GOA 电路及嵌入式触控显示面板 技术领域
本发明涉及液晶显示领域，具体涉及一种 GOA 电路及嵌入式触控显示面板。
背景技术
GOA( Gate Driver on Array ) 技术即阵列基板行驱动技术，是利用薄膜晶体管液晶显示器阵列制程将栅极扫描驱动电路制作在薄膜晶体管阵列基板上，以实现逐行扫描的驱动方式。
目前随着集成触控面板技术发展成熟，显示面板都会选择内嵌入触控显示面板。在内嵌入触控显示面板中，由于显示刷新的时间被分隔开，以空出时间（ TP 中停时间）做触控扫描，因此面板的 GOA 电路的工作状态不再连续，而是每扫描一定的级数，保持一段时间，继续扫描。这样，在 GOA 电路处于保持状态时，很容易出现电路维持能力不足的问题，使 GOA 电路级传失效，出现显示异常。
 技术问题
本发明实施例的目的在于提供一种 GOA 电路及内嵌入触控显示面板，能够降低该 GOA 电路在 TP 中停时维持能力不足，进而降低了级传失效的风险，使该 GOA 电路更加稳定。
技术解决方案
一种 GOA 电路，应用于嵌入式触控显示面板中，其包括：多级级联的 GOA 单元，第 n 级 GOA 单元包括：正反向扫描控制模块、节点控制模块、输出模块、输出控制模块以及预充电模块；
所述正反向扫描控制模块，用于根据正向扫描直流控制信号以及反向扫描直流控制信号，在第一节点输出第一节点控制信号以及在第二节点输出第二节点控制信号；
所述节点控制模块，耦接于所述第一节点和所述第二节点，用于将所述第一节点控制信号下拉至恒压低电位以及将所述第二节点控制信号升高至恒压高电位；
所述输出模块，耦接于所述第一节点并电性连接于第一时钟信号，用于根据所述第一节点控制信号和所述第一时钟信号，输出扫描信号；
所述输出控制模块，电性连接于所述第一控制信号，用于根据所述第一控制信号将所述扫描信号下拉至恒压低电位；其中，
所述预充电模块，耦接于所述第一节点并电性连接于第 n+2 级 GOA 单元的第一节点，用于当所述嵌入式触控显示面板进入信号中停并进行触控扫描阶段时，对第 n+2 级 GOA 单元的第一节点上的第一节点控制信号进行预充电；
所述预充电模块包括：第一薄膜晶体管和第二薄膜晶体管；
所述第一薄膜晶体管的栅极与源极均与所述第一节点连接，所述第一薄膜晶体管的漏极与所述第二薄膜晶体管的源极连接，所述第二薄膜晶体管的漏极与所述第 n+2 级 GOA 单元的第一节点连接，所述第二薄膜晶体管的栅极接入所述第一控制信号；
当所述嵌入式触控显示面板正常显示时，所述第一控制信号为低电位；当所述嵌入式触控显示面板进入信号中停并进行触控扫描阶段时，所述第一控制信号为高电位。
在本发明的 GOA 电路中，所述正反向扫描控制模块包括：第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第一电容以及第二电容；
所述第三薄膜晶体管的源极接入所述正向扫描直流控制信号，栅极接入第 n-2 级 GOA 单元的扫描信号，漏极与所述第一节点、所述第二薄膜晶体管的漏极以及所述第三薄膜晶体管的栅极连接；
所述第四薄膜晶体管的源极接入所述反向扫描直流控制信号，栅极接入第 n+2 级 GOA 单元的扫描信号；
所述第五薄膜晶体管的源极接入恒压低电位，漏极与所述第二节点连接；
所述第一电容的一端与所述第一节点连接，另一端接入恒压低电位；
所述第二电容的一端与所述第二节点连接，另一端接入恒压低电位。
在本发明的 GOA 电路中，所述节点控制模块包括：第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第九薄膜晶体管；
所述第六薄膜晶体管的源极接入第二时钟信号，栅极接入所述正向扫描直流控制信号，漏极与所述第八薄膜晶体管的栅极连接；
所述第七薄膜晶体管的源极接入第三时钟信号，栅极接入所述反向扫描直流控制信号，漏极与所述第八薄膜晶体管的栅极连接；
所述第八薄膜晶体管的源极接入恒压高电位，漏极与所述第二节点连接；
所述第九薄膜晶体管的源极接入恒压低电位，栅极与所述第二节点连接，漏极与所述第一节点连接。
在本发明的 GOA 电路中，所述输出模块包括：第十薄膜晶体管；
所述第十薄膜晶体管的源极接入所述第一时钟信号，栅极与所述第一节点连接，漏极与所述输出模块的输出端连接。
在本发明的 GOA 电路中，所述输出控制模块包括第十一薄膜晶体管以及第十二薄膜晶体管；
所述第十一薄膜晶体管的源极接入恒压低电位，栅极与所述第二节点连接，漏极与所述输出模块的输出端连接；
所述第十二薄膜晶体管的源极接入恒压低电位，栅极接入所述第一控制信号，漏极与所述输出模块的输出端连接。
在本发明的 GOA 电路中，所述第 n 级 GOA 单元还包括：复位模块；所述复位模块包括：第十三薄膜晶体管，所述第十三薄膜晶体管的源极以及漏极接入复位信号，漏极电性连接于所述第二节点。
在本发明的 GOA 电路中，所述 GOA 电路正向扫描时，所述正向扫描直流控制信号为高电位，所述反向扫描直流控制信号为低电位；所述 GOA 电路反向扫描时，所述正向扫描直流控制信号为低电位，所述反向扫描直流控制信号为高电位。
一种 GOA 电路，应用于嵌入式触控显示面板中，其包括：多级级联的 GOA 单元，第 n 级 GOA 单元包括：正反向扫描控制模块、节点控制模块、输出模块、输出控制模块以及预充电模块；
所述正反向扫描控制模块，用于根据正向扫描直流控制信号以及反向扫描直流控制信号，在第一节点输出第一节点控制信号以及在第二节点输出第二节点控制信号；
所述节点控制模块，耦接于所述第一节点和所述第二节点，用于将所述第一节点控制信号下拉至恒压低电位以及将所述第二节点控制信号升高至恒压高电位；
所述输出模块，耦接于所述第一节点并电性连接于第一时钟信号，用于根据所述第一节点控制信号和所述第一时钟信号，输出扫描信号；
所述输出控制模块，电性连接于所述第一控制信号，用于根据所述第一控制信号将所述扫描信号下拉至恒压低电位；其中，
所述预充电模块，耦接于所述第一节点并电性连接于第 n+2 级 GOA 单元的第一节点，用于当所述嵌入式触控显示面板进入信号中停并进行触控扫描阶段时，对第 n+2 级 GOA 单元的第一节点上的第一节点控制信号进行预充电。
在本发明的 GOA 电路中，所述预充电模块包括：第一薄膜晶体管和第二薄膜晶体管；
所述第一薄膜晶体管的栅极与源极均与所述第一节点连接，所述第一薄膜晶体管的漏极与所述第二薄膜晶体管的源极连接，所述第二薄膜晶体管的漏极与所述第 n+2 级 GOA 单元的第一节点连接，所述第二薄膜晶体管的栅极接入所述第一控制信号。
在本发明的 GOA 电路中，所述正反向扫描控制模块包括：第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第一电容以及第二电容；
所述第三薄膜晶体管的源极接入所述正向扫描直流控制信号，栅极接入第 n-2 级 GOA 单元的扫描信号，漏极与所述第一节点、所述第二薄膜晶体管的漏极以及所述第三薄膜晶体管的栅极连接；
所述第四薄膜晶体管的源极接入所述反向扫描直流控制信号，栅极接入第 n+2 级 GOA 单元的扫描信号；
所述第五薄膜晶体管的源极接入恒压低电位，漏极与所述第二节点连接；
所述第一电容的一端与所述第一节点连接，另一端接入恒压低电位；
所述第二电容的一端与所述第二节点连接，另一端接入恒压低电位。
在本发明的 GOA 电路中，所述节点控制模块包括：第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第九薄膜晶体管；
所述第六薄膜晶体管的源极接入第二时钟信号，栅极接入所述正向扫描直流控制信号，漏极与所述第八薄膜晶体管的栅极连接；
所述第七薄膜晶体管的源极接入第三时钟信号，栅极接入所述反向扫描直流控制信号，漏极与所述第八薄膜晶体管的栅极连接；
所述第八薄膜晶体管的源极接入恒压高电位，漏极与所述第二节点连接；
所述第九薄膜晶体管的源极接入恒压低电位，栅极与所述第二节点连接，漏极与所述第一节点连接。
在本发明的 GOA 电路中，所述输出模块包括：第十薄膜晶体管；
所述第十薄膜晶体管的源极接入所述第一时钟信号，栅极与所述第一节点连接，漏极与所述输出模块的输出端连接。
在本发明的 GOA 电路中，所述输出控制模块包括第十一薄膜晶体管以及第十二薄膜晶体管；
所述第十一薄膜晶体管的源极接入恒压低电位，栅极与所述第二节点连接，漏极与所述输出模块的输出端连接；
所述第十二薄膜晶体管的源极接入恒压低电位，栅极接入所述第一控制信号，漏极与所述输出模块的输出端连接。
在本发明的 GOA 电路中，所述第 n 级 GOA 单元还包括：复位模块；所述复位模块包括：第十三薄膜晶体管，所述第十三薄膜晶体管的源极以及漏极接入复位信号，漏极电性连接于所述第二节点。
在本发明的 GOA 电路中，当所述嵌入式触控显示面板正常显示时，所述第一控制信号为低电位；当所述嵌入式触控显示面板进入信号中停并进行触控扫描阶段时，所述第一控制信号为高电位。
在本发明的 GOA 电路中，所述 GOA 电路正向扫描时，所述正向扫描直流控制信号为高电位，所述反向扫描直流控制信号为低电位；所述 GOA 电路反向扫描时，所述正向扫描直流控制信号为低电位，所述反向扫描直流控制信号为高电位。
一种嵌入式触控显示面板， 其包括 GOA 电路，所述 GOA 电路，应用于嵌入式触控显示面板中，其包括：多级级联的 GOA 单元，第 n 级 GOA 单元包括：正反向扫描控制模块、节点控制模块、输出模块、输出控制模块以及预充电模块；
所述正反向扫描控制模块，用于根据正向扫描直流控制信号以及反向扫描直流控制信号，在第一节点输出第一节点控制信号以及在第二节点输出第二节点控制信号；
所述节点控制模块，耦接于所述第一节点和所述第二节点，用于将所述第一节点控制信号下拉至恒压低电位以及将所述第二节点控制信号升高至恒压高电位；
所述输出模块，耦接于所述第一节点并电性连接于第一时钟信号，用于根据所述第一节点控制信号和所述第一时钟信号，输出扫描信号；
所述输出控制模块，电性连接于所述第一控制信号，用于根据所述第一控制信号将所述扫描信号下拉至恒压低电位；其中，
所述预充电模块，耦接于所述第一节点并电性连接于第 n+2 级 GOA 单元的第一节点，用于当所述嵌入式触控显示面板进入信号中停并进行触控扫描阶段时，对第 n+2 级 GOA 单元的第一节点上的第一节点控制信号进行预充电。
在本发明的嵌入式触控显示面板中，所述预充电模块包括：第一薄膜晶体管和第二薄膜晶体管；
所述第一薄膜晶体管的栅极与源极均与所述第一节点连接，所述第一薄膜晶体管的漏极与所述第二薄膜晶体管的源极连接，所述第二薄膜晶体管的漏极与所述第 n+2 级 GOA 单元的第一节点连接，所述第二薄膜晶体管的栅极接入所述第一控制信号。
在本发明的嵌入式触控显示面板中，当所述嵌入式触控显示面板正常显示时，所述第一控制信号为低电位；当所述嵌入式触控显示面板进入信号中停并进行触控扫描阶段时，所述第一控制信号为高电位。
在本发明的嵌入式触控显示面板中，所述 GOA 电路正向扫描时，所述正向扫描直流控制信号为高电位，所述反向扫描直流控制信号为低电位；所述 GOA 电路反向扫描时，所述正向扫描直流控制信号为低电位，所述反向扫描直流控制信号为高电位。
 有益效果
本发明所述提供的 GOA 电路及内嵌入触控显示面板，通过在第 n 级 GOA 单元设置预充电模块，当嵌入式触控显示面板进入信号中停并进行触控扫描阶段时，对第 n+2 级 GOA 单元的第一节点上的第一节点控制信号进行预充电，降低了该 GOA 电路在 TP 中停时维持能力不足，进而降低了级传失效的风险，使该 GOA 电路更加稳定。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图 1 为本发明实施例提供的 GOA 电路的电路图。
图 2 为本发明实施例提供的 GOA 电路的第一时序图。
图 3 为本发明实施例提供的 GOA 电路的第二时序图。
图 4 为本发明实施例提供的 GOA 电路的另一电路图。
 本发明的最佳实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图 1 ，图 1 为本发明实施例提供的 GOA 电路的电路图。如图 1 所示，本发明实施例提供一种 GOA 电路，包括，多级级联的 GOA 单元，第 n 级 GOA 单元包括：正反向扫描控制模块 101 、节点控制模块 102 、输出模块 103 、输出控制模块 104 以及预充电模块 105 。需要说明的是，这里所说的第 n 级 GOA 单元为除第一级 GOA 单元、第二级 GOA 单元、倒数第二级 GOA 单元、及最后一级 GOA 单元外的 GOA 单元。
其中，该正反向扫描控制模块 101 ，用于根据正向扫描直流控制信号 U2D 以及反向扫描直流控制信号 D2U ，在第一节点 Q(n) 输出第一节点控制信号以及在第二节点 P(n) 输出第二节点控制信号。
具体的，该正反向扫描控制模块 101 包括：第三薄膜晶体管 T3 、第四薄膜晶体管 T4 、第五薄膜晶体管 T5 、第一电容 C1 以及第二电容 C2 。第三薄膜晶体管 T3 的源极接入正向扫描直流控制信号 U2D ，栅极接入第 n-2 级 GOA 单元的扫描信号 G(n-2) ，漏极与第一节点 Q(n) 、第四薄膜晶体管 T4 的漏极以及第五薄膜晶体管 T5 的栅极连接；第四薄膜晶体管 T4 的源极接入反向扫描直流控制信号 D2U ，栅极接入第 n+2 级 GOA 单元的扫描信号 G(n+2) ；第五薄膜晶体管 T5 的源极接入恒压低电位 VGL ，漏极与第二节点 P(n) 连接；第一电容 C1 的一端与第一节点 Q(n) 连接，另一端接入恒压低电位 VGL ；第二电容 C2 的一端与第二节点 P(n) 连接，另一端接入恒压低电位 VGL 。
其中，该节点控制模块 102 ，耦接于第一节点 Q(n) 和第二节点 P(n) ，用于将第一节点控制信号下拉至恒压低电位 VGL 以及将第二节点控制信号升高至恒压高电位 VGH 。
具体的，该节点控制模块 102 包括：第六薄膜晶体管 T6 、第七薄膜晶体管 T7 、第八薄膜晶体管 T8 以及第九薄膜晶体管 T9 。第六薄膜晶体管 T6 的源极接入第二时钟信号 CK2 ，栅极接入正向扫描直流控制信号 U2D ，漏极与第八薄膜晶体管 T8 的栅极连接；第七薄膜晶体管 T7 的源极接入第三时钟信号 CK3 ，栅极接入反向扫描直流控制信号 D2U ，漏极与第八薄膜晶体管 T8 的栅极连接；第八薄膜晶体管 T8 的源极接入恒压高电位 VGH ，漏极与第二节点 P(n) 连接；第九薄膜晶体管 T9 的源极接入恒压低电位 VGL ，栅极与第二节点连接，漏极与第一节点 Q(n) 连接。
其中，该输出模块 103 ，耦接于第一节点 Q(n) 并电性连接于第一时钟信号 CK1 ，用于根据第一节点控制信号和第一时钟信号 CK1 ，输出扫描信号 G(n) 。
具体的，该输出模块 103 包括：第十薄膜晶体管 T10 ；第十薄膜晶体管 T10 的源极接入第一时钟信号 CK1 ，栅极与第一节点 Q(n) 连接，漏极与输出模块 103 的输出端连接。
其中，该输出控制模块 104 ，电性连接于第一控制信号 GAS1 ，用于根据第一控制信号 GAS1 将扫描信号 G(n) 下拉至恒压低电位 VGL 。
具体的，该输出控制模块 104 包括：第十一薄膜晶体管 T11 以及第十二薄膜晶体管 T12 ；第十一薄膜晶体管 T11 的源极接入恒压低电位 VGL ，栅极与第二节点 P(n) 连接，漏极与输出模块 103 的输出端连接；第十二薄膜晶体管 T12 的源极接入恒压低电位 VGL ，栅极接入第一控制信号 GAS1 ，漏极与输出模块 103 的输出端连接。
其中，该预充电模块 105 ，耦接于第一节点 Q(n) 并电性连接于第 n+2 级 GOA 单元的第一节点 Q(n+2) ，用于当嵌入式触控显示面板进入信号中停并进行触控扫描阶段时，对第 n+2 级 GOA 单元的第一节点 Q(n+2) 上的第一节点控制信号进行预充电。
具体的，该预充电模块 105 包括：第一薄膜晶体管 T1 和第二薄膜晶体管 T2 ；
第一薄膜晶体管 T1 的栅极与源极均与第一节点 Q(n) 连接，第一薄膜晶体管 T1 的漏极与第二薄膜晶体管 T2 的源极连接，第二薄膜晶体管 T2 的漏极与第 n+2 级 GOA 单元的第一节点 Q(n+2) 连接，第二薄膜晶体管 T2 的栅极接入第一控制信号 GAS1 。
进一步的，第 n 级 GOA 单元还包括：复位模块 106 ；复位模块 106 包括：第十三薄膜晶体管 T13 ，第十三薄膜晶体管 T13 的源极以及漏极接入复位信号 RESET ，漏极电性连接于第二节点 P(n) 。需要说明的是，该复位模块 106 可用于在该 GOA 电路工作时，对 GOA 电路进行复位，从而使得该 GOA 电路更加稳定。
下面将结合图 2 、图 3 ，以本发明实施例提供的 GOA 电路进行正向扫描为例，说明本发明实施例提供的 GOA 电路的具体工作过程。其中，图 2 为本发明实施例提供的 GOA 电路的第一时序图；图 3 为本发明实施例提供的 GOA 电路的第二时序图。
如图 2 、图 3 所示，需要说明的是，当嵌入式触控显示面板正常显示时，第一控制信号 GAS1 为低电位；当嵌入式触控显示面板进入信号中停并进行触控扫描阶段时，第一控制信号 GAS1 为高电位。 GOA 电路正向扫描时，正向扫描直流控制信号 U2D 为高电位，反向扫描直流控制信号 D2U 为低电位； GOA 电路反向扫描时，正向扫描直流控制信号 U2D 为低电位，反向扫描直流控制信号 D2U 为高电位。
结合图 2 、图 3 所示，该 GOA 电路工作时，首先，第 n-2 级 GOA 单元的扫描信号 G(n-2) 为高电位，第三薄膜晶体管 T3 打开，高电位的正向扫描直流控制信号 U2D 经第三薄膜晶体管 T3 在第一节点 Q(n) 输出第一节点控制信号，并将第一节点控制信号的高电位存储在第一电容 C1 中；与此同时，第五薄膜晶体管 T5 打开，恒压低电位 VGL 经第五薄膜晶体管 T5 在第二节点 P(n) 输出第二节点控制信号，并将第二节点控制信号的低电位存储在第二电容 C2 中；
随后，该嵌入式触控显示面板进入信号中停并进行触控扫描阶段，第一节点控制信号维持在高电位，第二节点控制信号维持在低电位，第一时钟信号 CK1 输出低电位，此时，第十薄膜晶体管 T10 打开，第一时钟信号 CK1 的低电位经第十薄膜晶体管 T10 输出至输出模块 103 的输出端，扫描信号 G(n) 为低电位。
需要说明的是，如图 2 所示，在该嵌入式触控显示面板进入信号中停并进行触控扫描阶段，第 n 级 GOA 单元的第一节点 Q(n) 上的第一节点控制信号需维持在高电位，而此时，反向扫描直流控制信号 D2U 为低电位，第一节点控制信号存储的高电位会漏电至反向直流控制信号 D2U 和恒压低电位 VGL 。另外，由于薄膜晶体管电性不稳定，若薄膜晶体管漏电流较大时，第一节点控制信号电荷漏电较多，在该嵌入式触控显示面板进入信号中停并进行触控扫描阶段后，第一节点控制信号的电位较低，从而不能完全开启第十薄膜晶体管 T10 ，会导致第 n 级 GOA 单元输出的扫描信号 G(n) 延迟较大，或者波形幅值低于恒压高电位。进一步的，若第 n 级 GOA 单元输出的扫描信号 G(n) 异常，会使得第 n+2 级 GOA 单元的第一节点 Q(n+2) 上的第一节点控制信号不能顺利拉高至恒压高电位 VGH ，从而导致第 n+2 级 GOA 单元输出的扫描信号 G(n+2) 异常，进而导致 GOA 电路失效，该嵌入式触控显示面板显示异常。
本发明实施例通过设置一预充电模块 105 ，在该嵌入式触控显示面板进入信号中停并进行触控扫描阶段，对第 n+2 级 GOA 单元的第一节点 Q(n+2) 上的第一节点控制信号进行预充电，使得在该嵌入式触控显示面板进入信号中停并进行触控扫描阶段后，第 n+2 级 GOA 单元上的第一节点控制信号能充电至恒压高电位 VGH ，降低了 GOA 电路级传失效的风险，提高了 GOA 电路的稳定性。
具体的，如图 3 所示，当该嵌入式触控显示面板进入信号中停并进行触控扫描阶段，第一控制信号 GAS1 输出高电位，第一薄膜晶体管 T1 和第二薄膜晶体管 T2 打开，第 n 级 GOA 单元的第一节点 Q(n) 上的第一节点控制信号经第一薄膜晶体管 T1 和第二薄膜晶体管 T2 对第 n+2 级 GOA 单元上的第一节点控制信号进行预充电，进而使得第 n+2 级 GOA 单元能正常输出扫描信号 G(n+2) ，降低了 GOA 电路级传失效的风险，提高了 GOA 电路的稳定性。
接着，在该嵌入式触控显示面板完成一次触控扫描后，第一时钟信号 CK1 为高电位，将第一节点 Q(n) 上的第一节点控制信号自举到更高电位；与此同时，第二节点 P(n) 上的第二节点控制信号维持恒压低电位，第 n 级 GOA 单元的扫描信号 G(n) 为高电位。
最后，第三时钟信号 CK3 为高电位，将第一节点 Q(n) 上的第一节点控制信号拉低至恒压低电位 VGL ，第二节点 P(n) 上的第二节点控制信号拉高至恒压高电位 VGH ，第 n 级 GOA 单元的扫描信号 G(n) 为低电位。
请参阅图 4 ，图 4 为本发明实施例提供的 GOA 电路的另一电路图。如图 4 所示，该 GOA 电路与图 1 所示的 GOA 电路的区别在于，该 GOA 电路还包括：第十四薄膜晶体管 T14 、第十五薄膜晶体管 T15 以及第十六薄膜晶体管 T16 。
其中，第十四薄膜晶体管 T14 的源极与第三薄膜晶体管 T3 的漏极连接，第十四薄膜晶体管 T14 的栅极接入恒压高电位 VGH ，第十四薄膜晶体管 T14 的漏极与第一节点连接 Q(n) 。
第十五薄膜晶体管 T15 的源极接入恒压低电位 VGL ，第十五薄膜晶体管 T15 的栅极接入第二控制信号 GAS2 ，第十五薄膜晶体管 T15 的漏极与第二节点 P(n) 连接。
第十六薄膜晶体管 T16 的源极和栅极均接入第二控制信号 GAS2 ，第十六薄膜晶体管 T16 的漏极与第十薄膜晶体管 T10 的漏极连接。
值得注意的是，本发明的 GOA 电路工作时，第十四薄膜晶体管的栅极接入恒压高电位，从而使得第十四薄膜晶体管时钟处于打开状态。
本发明的 GOA 电路工作时，第十五薄膜晶体管和第十六薄膜晶体管的栅极均接入第二控制信号，且第二控制信号为恒压低电位，从而使得第十五薄膜晶体管和第十六薄膜晶体管处于关闭状态。
另外，本发明的 GOA 电路还可以根据具体需要调整第十四薄膜晶体管、第十五薄膜晶体管以及第十六薄膜晶体管的栅极接入的信号的高低电位，控制第十四薄膜晶体管、第十五薄膜晶体管以及第十六薄膜晶体管的状态，从而使得该 GOA 电路使用更加灵活。
本发明实施例提供的 GOA 电路，通过在第 n 级 GOA 单元设置预充电模块，当嵌入式触控显示面板进入信号中停并进行触控扫描阶段时，对第 n+2 级 GOA 单元的第一节点上的第一节点控制信号进行预充电，降低了该 GOA 电路在 TP 中停时维持能力不足，进而降低了级传失效的风险，使该 GOA 电路更加稳定。
本发明实施例还提供一种嵌入式触控显示面板，其包括以上所述的 GOA 电路，具体可参照以上所述，在此不做赘述。
本发明所述提供的 GOA 电路及内嵌入触控显示面板，通过在第 n 级 GOA 单元设置预充电模块，当嵌入式触控显示面板进入信号中停并进行触控扫描阶段时，对第 n+2 级 GOA 单元的第一节点上的第一节点控制信号进行预充电，降低了该 GOA 电路在 TP 中停时维持能力不足，进而降低了级传失效的风险，使该 GOA 电路更加稳定。
以上对本发明实施例提供的液晶显示组件进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明。同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (20)

  1. 一种 GOA 电路，应用于嵌入式触控显示面板中，其包括：多级级联的 GOA 单元，第 n 级 GOA 单元包括：正反向扫描控制模块、节点控制模块、输出模块、输出控制模块以及预充电模块；
    所述正反向扫描控制模块，用于根据正向扫描直流控制信号以及反向扫描直流控制信号，在第一节点输出第一节点控制信号以及在第二节点输出第二节点控制信号；
    所述节点控制模块，耦接于所述第一节点和所述第二节点，用于将所述第一节点控制信号下拉至恒压低电位以及将所述第二节点控制信号升高至恒压高电位；
    所述输出模块，耦接于所述第一节点并电性连接于第一时钟信号，用于根据所述第一节点控制信号和所述第一时钟信号，输出扫描信号；
    所述输出控制模块，电性连接于所述第一控制信号，用于根据所述第一控制信号将所述扫描信号下拉至恒压低电位；其中，
    所述预充电模块，耦接于所述第一节点并电性连接于第 n+2 级 GOA 单元的第一节点，用于当所述嵌入式触控显示面板进入信号中停并进行触控扫描阶段时，对第 n+2 级 GOA 单元的第一节点上的第一节点控制信号进行预充电；
    所述预充电模块包括：第一薄膜晶体管和第二薄膜晶体管；
    所述第一薄膜晶体管的栅极与源极均与所述第一节点连接，所述第一薄膜晶体管的漏极与所述第二薄膜晶体管的源极连接，所述第二薄膜晶体管的漏极与所述第 n+2 级 GOA 单元的第一节点连接，所述第二薄膜晶体管的栅极接入所述第一控制信号；
    当所述嵌入式触控显示面板正常显示时，所述第一控制信号为低电位；当所述嵌入式触控显示面板进入信号中停并进行触控扫描阶段时，所述第一控制信号为高电位。
  2. 根据权利要求 1 所述的 GOA 电路，其中，所述正反向扫描控制模块包括：第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第一电容以及第二电容；
    所述第三薄膜晶体管的源极接入所述正向扫描直流控制信号，栅极接入第 n-2 级 GOA 单元的扫描信号，漏极与所述第一节点、所述第二薄膜晶体管的漏极以及所述第三薄膜晶体管的栅极连接；
    所述第四薄膜晶体管的源极接入所述反向扫描直流控制信号，栅极接入第 n+2 级 GOA 单元的扫描信号；
    所述第五薄膜晶体管的源极接入恒压低电位，漏极与所述第二节点连接；
    所述第一电容的一端与所述第一节点连接，另一端接入恒压低电位；
    所述第二电容的一端与所述第二节点连接，另一端接入恒压低电位。
  3. 根据权利要求 1 所述的 GOA 电路，其中，所述节点控制模块包括：第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第九薄膜晶体管；
    所述第六薄膜晶体管的源极接入第二时钟信号，栅极接入所述正向扫描直流控制信号，漏极与所述第八薄膜晶体管的栅极连接；
    所述第七薄膜晶体管的源极接入第三时钟信号，栅极接入所述反向扫描直流控制信号，漏极与所述第八薄膜晶体管的栅极连接；
    所述第八薄膜晶体管的源极接入恒压高电位，漏极与所述第二节点连接；
    所述第九薄膜晶体管的源极接入恒压低电位，栅极与所述第二节点连接，漏极与所述第一节点连接。
  4. 根据权利要求 1 所述的 GOA 电路，其中，所述输出模块包括：第十薄膜晶体管；
    所述第十薄膜晶体管的源极接入所述第一时钟信号，栅极与所述第一节点连接，漏极与所述输出模块的输出端连接。
  5. 根据权利要求 1 所述的 GOA 电路，其中，所述输出控制模块包括第十一薄膜晶体管以及第十二薄膜晶体管；
    所述第十一薄膜晶体管的源极接入恒压低电位，栅极与所述第二节点连接，漏极与所述输出模块的输出端连接；
    所述第十二薄膜晶体管的源极接入恒压低电位，栅极接入所述第一控制信号，漏极与所述输出模块的输出端连接。
  6. 根据权利要求 1 所述的 GOA 电路，其中，所述第 n 级 GOA 单元还包括：复位模块；所述复位模块包括：第十三薄膜晶体管，所述第十三薄膜晶体管的源极以及漏极接入复位信号，漏极电性连接于所述第二节点。
  7. 根据权利要求 1 所述的 GOA 电路，其中，所述 GOA 电路正向扫描时，所述正向扫描直流控制信号为高电位，所述反向扫描直流控制信号为低电位；所述 GOA 电路反向扫描时，所述正向扫描直流控制信号为低电位，所述反向扫描直流控制信号为高电位。
  8. 一种 GOA 电路，应用于嵌入式触控显示面板中，其包括：多级级联的 GOA 单元，第 n 级 GOA 单元包括：正反向扫描控制模块、节点控制模块、输出模块、输出控制模块以及预充电模块；
    所述正反向扫描控制模块，用于根据正向扫描直流控制信号以及反向扫描直流控制信号，在第一节点输出第一节点控制信号以及在第二节点输出第二节点控制信号；
    所述节点控制模块，耦接于所述第一节点和所述第二节点，用于将所述第一节点控制信号下拉至恒压低电位以及将所述第二节点控制信号升高至恒压高电位；
    所述输出模块，耦接于所述第一节点并电性连接于第一时钟信号，用于根据所述第一节点控制信号和所述第一时钟信号，输出扫描信号；
    所述输出控制模块，电性连接于所述第一控制信号，用于根据所述第一控制信号将所述扫描信号下拉至恒压低电位；其中，
    所述预充电模块，耦接于所述第一节点并电性连接于第 n+2 级 GOA 单元的第一节点，用于当所述嵌入式触控显示面板进入信号中停并进行触控扫描阶段时，对第 n+2 级 GOA 单元的第一节点上的第一节点控制信号进行预充电。
  9. 根据权利要求 8 所述的 GOA 电路，其中，所述预充电模块包括：第一薄膜晶体管和第二薄膜晶体管；
    所述第一薄膜晶体管的栅极与源极均与所述第一节点连接，所述第一薄膜晶体管的漏极与所述第二薄膜晶体管的源极连接，所述第二薄膜晶体管的漏极与所述第 n+2 级 GOA 单元的第一节点连接，所述第二薄膜晶体管的栅极接入所述第一控制信号。
  10. 根据权利要求 8 所述的 GOA 电路，其中，所述正反向扫描控制模块包括：第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第一电容以及第二电容；
    所述第三薄膜晶体管的源极接入所述正向扫描直流控制信号，栅极接入第 n-2 级 GOA 单元的扫描信号，漏极与所述第一节点、所述第二薄膜晶体管的漏极以及所述第三薄膜晶体管的栅极连接；
    所述第四薄膜晶体管的源极接入所述反向扫描直流控制信号，栅极接入第 n+2 级 GOA 单元的扫描信号；
    所述第五薄膜晶体管的源极接入恒压低电位，漏极与所述第二节点连接；
    所述第一电容的一端与所述第一节点连接，另一端接入恒压低电位；
    所述第二电容的一端与所述第二节点连接，另一端接入恒压低电位。
  11. 根据权利要求 8 所述的 GOA 电路，其中，所述节点控制模块包括：第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第九薄膜晶体管；
    所述第六薄膜晶体管的源极接入第二时钟信号，栅极接入所述正向扫描直流控制信号，漏极与所述第八薄膜晶体管的栅极连接；
    所述第七薄膜晶体管的源极接入第三时钟信号，栅极接入所述反向扫描直流控制信号，漏极与所述第八薄膜晶体管的栅极连接；
    所述第八薄膜晶体管的源极接入恒压高电位，漏极与所述第二节点连接；
    所述第九薄膜晶体管的源极接入恒压低电位，栅极与所述第二节点连接，漏极与所述第一节点连接。
  12. 根据权利要求 8 所述的 GOA 电路，其中，所述输出模块包括：第十薄膜晶体管；
    所述第十薄膜晶体管的源极接入所述第一时钟信号，栅极与所述第一节点连接，漏极与所述输出模块的输出端连接。
  13. 根据权利要求 8 所述的 GOA 电路，其中，所述输出控制模块包括第十一薄膜晶体管以及第十二薄膜晶体管；
    所述第十一薄膜晶体管的源极接入恒压低电位，栅极与所述第二节点连接，漏极与所述输出模块的输出端连接；
    所述第十二薄膜晶体管的源极接入恒压低电位，栅极接入所述第一控制信号，漏极与所述输出模块的输出端连接。
  14. 根据权利要求 8 所述的 GOA 电路，其中，所述第 n 级 GOA 单元还包括：复位模块；所述复位模块包括：第十三薄膜晶体管，所述第十三薄膜晶体管的源极以及漏极接入复位信号，漏极电性连接于所述第二节点。
  15. 根据权利要求 8 所述的 GOA 电路，其中，当所述嵌入式触控显示面板正常显示时，所述第一控制信号为低电位；当所述嵌入式触控显示面板进入信号中停并进行触控扫描阶段时，所述第一控制信号为高电位。
  16. 根据权利要求 8 所述的 GOA 电路，其中，所述 GOA 电路正向扫描时，所述正向扫描直流控制信号为高电位，所述反向扫描直流控制信号为低电位；所述 GOA 电路反向扫描时，所述正向扫描直流控制信号为低电位，所述反向扫描直流控制信号为高电位。
  17. 一种嵌入式触控显示面板，其包括 GOA 电路，所述 GOA 电路，应用于嵌入式触控显示面板中，其包括：多级级联的 GOA 单元，第 n 级 GOA 单元包括：正反向扫描控制模块、节点控制模块、输出模块、输出控制模块以及预充电模块；
    所述正反向扫描控制模块，用于根据正向扫描直流控制信号以及反向扫描直流控制信号，在第一节点输出第一节点控制信号以及在第二节点输出第二节点控制信号；
    所述节点控制模块，耦接于所述第一节点和所述第二节点，用于将所述第一节点控制信号下拉至恒压低电位以及将所述第二节点控制信号升高至恒压高电位；
    所述输出模块，耦接于所述第一节点并电性连接于第一时钟信号，用于根据所述第一节点控制信号和所述第一时钟信号，输出扫描信号；
    所述输出控制模块，电性连接于所述第一控制信号，用于根据所述第一控制信号将所述扫描信号下拉至恒压低电位；其中，
    所述预充电模块，耦接于所述第一节点并电性连接于第 n+2 级 GOA 单元的第一节点，用于当所述嵌入式触控显示面板进入信号中停并进行触控扫描阶段时，对第 n+2 级 GOA 单元的第一节点上的第一节点控制信号进行预充电。
  18. 根据权利要求 17 所述的嵌入式触控显示面板，其中，所述预充电模块包括：第一薄膜晶体管和第二薄膜晶体管；
    所述第一薄膜晶体管的栅极与源极均与所述第一节点连接，所述第一薄膜晶体管的漏极与所述第二薄膜晶体管的源极连接，所述第二薄膜晶体管的漏极与所述第 n+2 级 GOA 单元的第一节点连接，所述第二薄膜晶体管的栅极接入所述第一控制信号。
  19. 根据权利要求 17 所述的嵌入式触控显示面板，其中，当所述嵌入式触控显示面板正常显示时，所述第一控制信号为低电位；当所述嵌入式触控显示面板进入信号中停并进行触控扫描阶段时，所述第一控制信号为高电位。
  20. 根据权利要求 17 所述的嵌入式触控显示面板，其中，所述 GOA 电路正向扫描时，所述正向扫描直流控制信号为高电位，所述反向扫描直流控制信号为低电位；所述 GOA 电路反向扫描时，所述正向扫描直流控制信号为低电位，所述反向扫描直流控制信号为高电位。
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