WO2018205333A1 - 一种液晶显示面板及装置 - Google Patents

一种液晶显示面板及装置 Download PDF

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Publication number
WO2018205333A1
WO2018205333A1 PCT/CN2017/087792 CN2017087792W WO2018205333A1 WO 2018205333 A1 WO2018205333 A1 WO 2018205333A1 CN 2017087792 W CN2017087792 W CN 2017087792W WO 2018205333 A1 WO2018205333 A1 WO 2018205333A1
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Prior art keywords
pixels
pixel group
column
scan line
liquid crystal
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PCT/CN2017/087792
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English (en)
French (fr)
Inventor
郝思坤
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深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US15/578,019 priority Critical patent/US20180322842A1/en
Publication of WO2018205333A1 publication Critical patent/WO2018205333A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a liquid crystal display panel and device.
  • the liquid crystal display panel is currently the most widely used flat panel display and is used in various electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptop screens.
  • PDAs personal digital assistants
  • digital cameras digital cameras
  • computer screens computer screens or laptop screens.
  • G1-G12 represents a scan line
  • D1-D3 represents a data line
  • the number of scan lines is twice the horizontal resolution
  • each row of pixels is driven by two scan lines
  • data The number of lines is twice the vertical resolution
  • each data line drives the left and right columns of pixels.
  • Data1 represents a waveform of an actual input voltage of D1
  • Data2 represents a waveform of an actual input voltage of D2
  • Gate1 represents the waveform of the input scan signal of the first scan line G1
  • Gate2 represents the waveform of the scan signal input by the second scan line G2
  • Gate3 represents the waveform of the scan signal input by the third scan line G3, and
  • Gate4 represents the fourth scan line G4. Enter the waveform of the scan signal.
  • FIG. 3 is a schematic view showing a charging rate of a pixel in the liquid crystal display panel shown in FIG. 1, wherein L indicates a low charging rate and H indicates a high charging rate. It can be seen that the charging rate of the corresponding left pixel is low after the polarity of each data line is inverted, and the charging rate of the corresponding right pixel is high. That is to say, all pixels with low charging rate are in the same column and all pixels with high charging rate are also in the same column, so that bright and dark lines in the vertical direction are easily generated, which affects the display effect.
  • An object of the present invention is to provide a liquid crystal display panel and device capable of improving display performance.
  • the present invention provides a liquid crystal display panel comprising: a plurality of scan lines, a plurality of data lines, and a plurality of pixels, each row of pixels correspondingly disposed with a first scan line and a second scan line, each of two columns A pixel is correspondingly set to a data line;
  • the liquid crystal display panel further includes N pixel groups, each pixel group includes at least one row of pixels, and the pixels in the 2k+1th column of the nth pixel group are connected to the corresponding first scan line; the nth pixel group The pixel located in the 2kth column is connected to the corresponding second scan line;
  • the pixels in the 2k+1th column of the n+1th pixel group are connected to the corresponding second scan line; the pixels in the 2kth column of the n+1th pixel group are connected to the corresponding first scan line, wherein 0 ⁇ n ⁇ N, N ⁇ 2, k ⁇ 0;
  • the opening time of the first scanning line corresponding to each row of pixels is earlier than the opening time of the second scanning line corresponding to the row of pixels, and the charging efficiency of the pixel corresponding to the first scanning line is lower than that of the second scanning line.
  • the charging efficiency of the pixels; the charging efficiency of the pixels in the nth pixel group in each column of pixels is different from the charging efficiency of the pixels in the n+1th pixel group in the column.
  • the polarity of the data voltages input to the adjacent two data lines at the same time is the same.
  • the polarity of the data voltages input to the adjacent two data lines at the same time is different.
  • the pixel group includes two rows of pixels, and the pixels in the 2k+1th column of the nth pixel group are connected to the corresponding first scan line; the second pixel group is located at the 2kth The pixels of the column are connected to the corresponding second scan line;
  • the pixels located in the 2k+1th column of the n+1th pixel group are connected to the corresponding second scan line; and the pixels located in the 2kth column of the n+1th pixel group are connected to the corresponding first scan line.
  • the pixel group includes two rows of pixels adjacent to each other.
  • the present invention provides a liquid crystal display panel, including:
  • each row of pixels is correspondingly disposed with a first scan line and a second scan line, and each of the two columns of pixels is correspondingly provided with one data line;
  • the liquid crystal display panel further includes N pixel groups, each pixel group includes at least one row of pixels, and the pixels in the 2k+1th column of the nth pixel group are connected to the corresponding first scan line; the nth pixel group The pixel located in the 2kth column is connected to the corresponding second scan line;
  • the pixels in the 2k+1th column of the n+1th pixel group are connected to the corresponding second scan line; the pixels in the 2kth column of the n+1th pixel group are connected to the corresponding first scan line, wherein 0 ⁇ n ⁇ N, N ⁇ 2, k ⁇ 0.
  • the polarity of the data voltages input to the adjacent two data lines at the same time is the same.
  • the polarity of the data voltages input to the adjacent two data lines at the same time is different.
  • the charging efficiency of the pixel located in the nth pixel group in each column of pixels is different from the charging efficiency of the pixel in the n+1th pixel group in the column.
  • the opening time of the first scanning line corresponding to each row of pixels is earlier than the opening time of the second scanning line corresponding to the row of pixels, and the charging efficiency of the pixel corresponding to the first scanning line Lower than the charging efficiency of the pixel corresponding to the second scan line.
  • the pixel group includes two rows of pixels, and the pixels in the 2k+1th column of the nth pixel group are connected to the corresponding first scan line; the second pixel group is located at the 2kth The pixels of the column are connected to the corresponding second scan line;
  • the pixels located in the 2k+1th column of the n+1th pixel group are connected to the corresponding second scan line; and the pixels located in the 2kth column of the n+1th pixel group are connected to the corresponding first scan line.
  • the pixel group includes two rows of pixels adjacent to each other.
  • the invention also provides a liquid crystal display device comprising:
  • a liquid crystal display panel comprising:
  • each row of pixels is correspondingly disposed with a first scan line and a second scan line, and each of the two columns of pixels is correspondingly provided with one data line;
  • the liquid crystal display panel further includes N pixel groups, each pixel group includes at least one row of pixels, and the pixels in the 2k+1th column of the nth pixel group are connected to the corresponding first scan line; the nth pixel group The pixel located in the 2kth column is connected to the corresponding second scan line;
  • the pixels in the 2k+1th column of the n+1th pixel group are connected to the corresponding second scan line; the pixels in the 2kth column of the n+1th pixel group are connected to the corresponding first scan line, wherein 0 ⁇ n ⁇ N, N ⁇ 2, k ⁇ 0.
  • the polarities of the data voltages input to the adjacent two data lines at the same time are the same.
  • the polarities of the data voltages input to the adjacent two data lines at the same time are different.
  • the charging efficiency of the pixel located in the nth pixel group in each column of pixels is different from the charging efficiency of the pixel in the n+1th pixel group in the column.
  • the opening time of the first scanning line corresponding to each row of pixels is earlier than the opening time of the second scanning line corresponding to the row of pixels, and the charging efficiency of the pixel corresponding to the first scanning line Lower than the charging efficiency of the pixel corresponding to the second scan line.
  • the pixel group includes two rows of pixels, and the pixels of the nth pixel group located in the 2k+1th column are connected to the corresponding first scan line; the nth pixel group is located at the 2kth The pixels of the column are connected to the corresponding second scan line;
  • the pixels located in the 2k+1th column of the n+1th pixel group are connected to the corresponding second scan line; and the pixels located in the 2kth column of the n+1th pixel group are connected to the corresponding first scan line.
  • the pixel group includes two rows of pixels adjacent to each other.
  • each pixel group includes at least one row of pixels, and pixels in the same column of two adjacent pixel groups are connected to scan lines having different driving times, thereby making the same
  • the charging efficiency of the column pixels is different, avoiding the occurrence of bright and dark lines in the vertical direction, and improving the display effect.
  • 1 is a drive architecture diagram of a conventional liquid crystal display panel
  • FIG. 2 is a timing chart of driving of the liquid crystal display panel of FIG. 1;
  • FIG. 3 is a schematic view showing a charging rate of a pixel of the liquid crystal display panel of FIG. 1;
  • FIG. 4 is a drive architecture diagram of a first liquid crystal display panel of the present invention.
  • Figure 5 is a timing chart of driving of the liquid crystal display panel of Figure 4.
  • FIG. 6 is a schematic diagram of a charging rate of a pixel of the liquid crystal display panel of FIG. 4;
  • FIG. 7 is a drive architecture diagram of a second liquid crystal display panel of the present invention.
  • Figure 8 is a timing chart of driving of the liquid crystal display panel of Figure 7;
  • FIG. 9 is a schematic diagram of a charging rate of a pixel of the liquid crystal display panel of FIG. 7;
  • FIG. 10 is a drive architecture diagram of a third liquid crystal display panel of the present invention.
  • Figure 11 is a timing chart of driving of the liquid crystal display panel of Figure 10.
  • FIG. 12 is a schematic diagram of a charging rate of a pixel of the liquid crystal display panel of FIG. 10;
  • FIG. 13 is a diagram showing a driving structure of a fourth liquid crystal display panel of the present invention.
  • Figure 14 is a timing chart of driving of the liquid crystal display panel of Figure 13;
  • FIG. 15 is a schematic view showing a charging rate of a pixel of the liquid crystal display panel of FIG.
  • FIG. 4 is a diagram showing the driving structure of the first liquid crystal display panel of the present invention.
  • the liquid crystal display panel of this embodiment includes a plurality of scanning lines G1-G16, a plurality of data lines D1-D3, and a plurality of pixels 101.
  • Each row of pixels is correspondingly provided with two scanning lines, that is, a first scanning line and a second scanning line.
  • the pixels of the first row are corresponding to the scanning lines G1-G2.
  • Each of the two columns of pixels is correspondingly provided with one data line; wherein each adjacent two columns of pixels is correspondingly provided with one data line.
  • the data line D1 is connected to the first column pixel and the second column pixel
  • the data line D2 is connected to the third column pixel and the fourth column pixel
  • the data line D3 is connected to the fifth column pixel and the sixth column pixel.
  • the liquid crystal display panel further includes four pixel groups 11-14.
  • Each pixel group includes 2 rows of pixels. The two rows of pixels are adjacent. In other embodiments, the two rows of pixels may not be adjacent.
  • Pixels of the nth pixel group located in the odd column (2k+1) are connected to the corresponding first scan line; pixels of the nth pixel group located in the even column (2k) are connected to the corresponding second scan line; nth Pixels of the +1 pixel group located in the odd column are connected with the corresponding second scan line; pixels of the n+1th pixel group located in the even column are connected with the corresponding first scan line, where n is greater than 0 and less than N, N Greater than 2.
  • the first pixel group 11 includes a first row of pixels and a second row of pixels
  • the second pixel group 12 includes a third row of pixels and a fourth row of pixels.
  • the pixels in the odd column in the first pixel group 11 are connected to the corresponding first scanning lines G1 and G3, and the first pixel group 11 is located in the even column.
  • the pixels are connected to the corresponding second scan lines G2, G4.
  • the first row of pixels in the odd column in the first pixel group 11 is connected to the corresponding first scanning line G1; the pixels in the first row in the even column are connected to the corresponding second scanning line G2.
  • the pixels in the second row of the odd column are connected to the corresponding first scanning line G3, and the pixels in the second row in the even column are connected to the corresponding second scanning line G4.
  • the pixels in the odd column in the second pixel group 12 are connected to the corresponding second scanning lines G6 and G8, and the pixels in the even column in the second pixel group 12 are connected to the corresponding first scanning lines G5 and G7.
  • the third row of pixels in the odd column in the second pixel group 12 is connected to the corresponding second scanning line G6; the third row of pixels in the even column is connected to the corresponding first scanning line G5.
  • the fourth row of pixels in the odd column in the second pixel group 12 is connected to the corresponding second scanning line G8, and the pixel in the fourth row in the even column is connected to the corresponding first scanning line G7.
  • the remaining pixel groups are similar.
  • the pixels in the odd column of the first pixel group are connected to the corresponding second scan line, and the pixels in the even column of the first pixel group are connected to the corresponding first scan line.
  • the pixels in the odd column in the second pixel group are connected to the corresponding first scan lines, and the pixels in the even column in the second pixel group are connected to the corresponding second scan lines.
  • the data voltages of the inputs of the adjacent two data lines at the same time have the same polarity, so that the pixels in the same row have the same polarity.
  • the display panel may also include two, three or more pixel groups.
  • Each eight pixels in the same data line is a repeating unit, and the driving order of the pixels corresponding to the data line D1 in FIG. 4 is:
  • P11, P12, P21, P22, P32, P31, P42, P41, 11, 12, 21, 22, 32, 31, 42, 41 represent the position of the pixel in the matrix, wherein the first bit represents the row in which the pixel is located, The two bits represent the column in which the pixel is located. Taking P11 as an example, it represents the pixels of the first row and the first column.
  • Data1 represents a waveform of an actual input voltage of the data line D1
  • Data2 represents a waveform of an actual input voltage of the data line D2
  • Gate1 represents a waveform of an input scan signal of the first scanning line G1.
  • Gate2 indicates the waveform of the scan signal input to the second scan line G2
  • Gate3 indicates the waveform of the scan signal input to the third scan line G3
  • Gate4 indicates the waveform of the scan signal input to the fourth scan line G4.
  • the opening time of the first scan line corresponding to each row of pixels is earlier than the on time of the second scan line corresponding to the row of pixels.
  • the on time of the first scan line G1 of the first row of pixels is greater than the on time of the second scan line G2 of the first row of pixels.
  • FIG. 6 is a schematic diagram showing the charging rate of the pixel of the liquid crystal display shown in FIG. 4, where L indicates a low charging rate and H indicates a high charging rate. It can be seen from the figure that after the polarity of the data line is reversed, the corresponding first driving pixel has a low charging rate, and the corresponding post-driving pixel charging rate is high. That is, the charging efficiency of the pixel corresponding to the corresponding first scan line of each row of pixels is lower than the charging efficiency of the pixel corresponding to the second scan line corresponding to the row of pixels.
  • the pixels with low charging rate are not located in the same column, wherein the pixels in the nth pixel group and the n+1th pixel group in the column in each column of pixels
  • the charging efficiency of the pixels is different.
  • the charging efficiency of the pixels of the first pixel group in the first column of pixels is different from the charging efficiency of the pixels in the second pixel group in the first column. That is, the pixels with high charging rate and the pixels with low charging rate are arranged in a cross arrangement, and bright and dark lines in the vertical direction are not generated, which improves the display effect of the display.
  • FIG. 7 is a diagram showing the driving structure of a second liquid crystal display panel of the present invention.
  • the liquid crystal display panel in this embodiment also includes four pixel groups 21-24.
  • the difference between the driving structures of the liquid crystal display panels shown in FIG. 7 and FIG. 4 is that the polarities of the input data voltages of the adjacent two data lines at the same time are different, so that the polarities of the pixels in the same row follow the data lines.
  • the polarities are alternately arranged. For example, the polarity of the pixel connected to the first data line D1 in the first row of pixels is negative, and the polarity of the pixel connected to the second data line D2 in the first row of pixels is positive, first The polarity of the pixel connected to the third data line D3 among the row pixels is negative. Therefore, in the liquid crystal display shown in FIG. 7, not only the H having a high charging rate but also the L having a low charging rate are cross-aligned, and the positive polarity and the negative polarity are also arranged in a crosswise manner.
  • Data1 represents a waveform of an actual input voltage of the data line D1; and Data2 represents a waveform of an actual input voltage of the data line D2; Gate1 represents the waveform of the input scan signal of the first scan line G1; Gate2 represents the waveform of the scan signal input by the second scan line G2; Gate3 represents the waveform of the scan signal input by the third scan line G3, and Gate4 represents the fourth scan line G4. Enter the waveform of the scan signal.
  • the opening time of the first scan line corresponding to each row of pixels is earlier than the on time of the second scan line corresponding to the row of pixels.
  • the on time of the first scan line G1 of the first row of pixels is greater than the on time of the second scan line G2 of the first row of pixels.
  • Fig. 9 is a view showing the charging rate of the liquid crystal display pixel shown in Fig. 7, wherein L indicates a low charging rate and H indicates a high charging rate. It can be seen from the figure that the polarity of the data line is reversed, and the corresponding first driving pixel has a low charging rate, and the corresponding post-driving charging rate is high, that is, the charging efficiency of the pixel corresponding to the first scanning line is lower than that of the pixel. The charging efficiency of the pixel corresponding to the second scan line.
  • all the pixels with low charging rate are not located in the same column, wherein the pixels in the nth pixel group and the n+1th pixel group in the column in each column of pixels
  • the charging efficiency of the pixels is different.
  • the pixels of the first pixel group in the first column of pixels are different from the charging efficiency of the pixels in the second pixel group in the first column. That is, the H with high charging rate and the L cross arrangement with low charging rate do not produce bright and dark lines in the vertical direction, which improves the display effect of the display.
  • FIG. 10 is a diagram showing the driving structure of a third liquid crystal display panel of the present invention.
  • the liquid crystal display panel of this embodiment is different from the first embodiment in that the liquid crystal display panel includes six pixel groups 31-36.
  • Each pixel group includes 1 row of pixels. Specifically, pixels in the nth pixel group located in the odd (2k+1) column are connected to the corresponding first scan line; pixels in the nth pixel group in the even (2k) column are connected to the corresponding second scan line. a pixel located in the odd column of the n+1th pixel group is connected to the corresponding second scan line; a pixel located in the even column of the n+1th pixel group is connected to the corresponding first scan line, where n is greater than 0 and less than 0 N, N is greater than 2.
  • the first pixel group 31 includes the first row of pixels
  • the second pixel group includes 32 includes the second row of pixels.
  • the pixels in the odd column in the first pixel group 31 are connected to the corresponding first scanning line G1
  • the pixels in the even column in the first pixel group correspond to The second scan line G2
  • the pixels in the odd column in the second pixel group 32 are connected to the corresponding second scanning line G4, and the pixels in the even column are connected to the corresponding first scanning line G3.
  • the remaining pixel groups are similar.
  • Each eight pixels in the same data line is a repeating unit, and the driving order of the pixels corresponding to the data line D1 in FIG. 10:
  • P11, P12, P22, P21, P31, P32, P42, P41, 11, 12, 22, 21, 31, 32, 42, 41 represent the position of the pixel in the matrix, wherein the first bit represents the row in which the pixel is located, The two bits represent the column in which the pixel is located. Taking P11 as an example, it represents the pixels of the first row and the first column.
  • the data voltages of the inputs of the adjacent two data lines at the same time have the same polarity, so that the pixels in the same row have the same polarity.
  • Data1 represents a waveform of the actual input voltage of the data line D1
  • Data2 represents a waveform of the actual input voltage of the data line D2
  • Gate1 represents a waveform of the input scan signal of the first scanning line G1.
  • Gate2 indicates the waveform of the scan signal input to the second scan line G2
  • Gate3 indicates the waveform of the scan signal input to the third scan line G3
  • Gate4 indicates the waveform of the scan signal input to the fourth scan line G4.
  • the opening time of the first scan line corresponding to each row of pixels is earlier than the on time of the second scan line corresponding to the row of pixels.
  • the opening time of the first scanning line G1 of the first row of pixels is earlier than the opening time of the second scanning line G2 of the first row of pixels.
  • FIG. 12 is a schematic diagram showing the charging rate of the liquid crystal display pixel shown in FIG. 10, where L indicates a low charging rate and H indicates a high charging rate. It can be seen from the figure that after the polarity of the data line is reversed, the corresponding first driving pixel has a low charging rate, and the corresponding post-driving pixel charging rate is high.
  • the liquid crystal display driving architecture shown in FIG. 10 all the pixels with low charging rate are not located in the same column, that is, the charging efficiency of the pixels corresponding to the first scanning line is lower than the charging of the pixels corresponding to the second scanning line. effectiveness.
  • the pixel in the nth pixel group of each column of pixels is different from the pixel in the n+1th pixel group in the column, for example, the pixel in the first pixel group in the first column of pixels and the first pixel group
  • the pixels in the second pixel group in one column have different charging efficiencies. That is to say, two pixels with high charging rate and pixels with low charging rate in the same column are arranged in a cross arrangement, and no bright and dark lines in the vertical direction are generated, which improves the display effect of the display.
  • FIG. 13 is a diagram showing a driving structure of a fourth liquid crystal display panel of the present invention.
  • the liquid crystal display panel of this embodiment includes six pixel groups 41-46.
  • the difference between the driving structure of the liquid crystal display of FIG. 13 and FIG. 10 is that the polarities of the input data voltages of the adjacent two data lines at the same time are different, so that the polarities of the pixels in the same row are alternately arranged with the polarity of the data lines.
  • the polarity of the pixel connected to the first data line D1 in the first row of pixels is negative
  • the polarity of the pixel connected to the second data line D2 in the first row of pixels is positive
  • the pixels in the first row are
  • the polarity of the pixel connected to the third data line D3 is negative. Therefore, in the liquid crystal display shown in FIG. 13, not only the pixel having a high charging rate but also the pixel having a low charging rate are arranged in a crosswise manner, and the positive polarity and the negative polarity are also alternately arranged.
  • Data1 represents the waveform of the actual input voltage of the data line D1
  • Data2 represents the waveform of the actual input voltage of the data line D2
  • Gate1 represents the waveform of the input scanning signal of the first scanning line G1.
  • Gate2 indicates the waveform of the scan signal input to the second scan line G2
  • Gate3 indicates the waveform of the scan signal input to the third scan line G3
  • Gate4 indicates the waveform of the scan signal input to the fourth scan line G4.
  • the opening time of the first scan line corresponding to each row of pixels is earlier than the on time of the second scan line corresponding to the row of pixels.
  • the opening time of the first scanning line G1 of the first row of pixels is earlier than the opening time of the second scanning line G2 of the first row of pixels.
  • Fig. 15 is a view showing the charging rate of the liquid crystal display pixel shown in Fig. 13, wherein L indicates a low charging rate and H indicates a high charging rate. It can be seen from the figure that the charging rate of the corresponding first-driven pixel is low after the polarity of the data line is inverted, and the corresponding post-driving pixel has a high charging rate. That is, the charging efficiency of the pixel corresponding to the first scan line is lower than the charging efficiency of the pixel corresponding to the second scan line.
  • L indicates a low charging rate
  • H indicates a high charging rate.
  • all the pixels with low charging rate are not located in the same column, wherein the pixels in the nth pixel group and the n+1th pixel group in the column in each column of pixels
  • the charging efficiency of the pixels is different, that is, the charging efficiency of the pixels of the adjacent two pixel groups of each column is different.
  • the pixels of the first pixel group in the first column of pixels are different from the charging efficiency of the pixels in the second pixel group in the first column. That is to say, two pixels with high charging rate and pixels with low charging rate in the same column are arranged in a cross arrangement, and no bright and dark lines in the vertical direction are generated, which improves the display effect of the display.
  • each pixel group includes at least one row of pixels, and pixels in the same column of two adjacent pixel groups are connected to scan lines having different driving times, thereby making the same
  • the charging efficiency of the column pixels is different, avoiding the occurrence of bright and dark lines in the vertical direction, and improving the display effect.

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Abstract

一种液晶显示面板及装置，该面板包括：第n个像素组中位于第2k+1列的像素与对应的第一扫描线连接；第n个像素组中位于第2k列的像素与对应的第二扫描线连接；第n+1个像素组中位于第2k+1列的像素与对应的第二扫描线连接；第n+1个像素组中位于第2k列的像素与对应的第一扫描线连接。

Description

一种液晶显示面板及装置 技术领域
本发明涉及显示器技术领域，特别是涉及一种液晶显示面板及装置。
 背景技术
液晶显示面板是目前使用最广泛的一种平板显示器，被应用在各种电子设备如移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕中。
图1为现有液晶显示面板的驱动架构图，G1-G12表示扫描线，D1-D3表示数据线，扫描线的数量为水平解析度的2倍，每行像素由两条扫描线驱动，数据线的数量为垂直解析度的2倍，每一条数据线驱动左右两列像素。
图2是图1所示的液晶显示面板的驱动时序图，Data1表示D1实际输入电压的波形；Data2表示D2实际输入电压的波形； Gate1表示第一条扫描线G1输入扫描信号的波形；Gate2表示第二条扫描线G2输入扫描信号的波形；Gate3表示第三条扫描线G3输入扫描信号的波形，Gate4表示第四条扫描线G4输入扫描信号的波形。
图3为图1所示的液晶显示面板中像素的充电率的示意图，L表示充电率低，H表示充电率高。可以看出，每条数据线的极性反转后对应的左侧像素的充电率低，对应的右侧像素的充电率高。也即使得所有充电率低的像素位于同一列以及所有充电率高的像素也位于同一列，从而容易产生垂直方向的亮暗线，影响显示效果。
因此，有必要提供一种液晶显示面板及装置，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种液晶显示面板及装置，能够提高显示效果。
 技术解决方案
为解决上述技术问题，本发明提供一种液晶显示面板，其包括：多条扫描线、多条数据线以及多个像素，每行像素对应设置第一扫描线和第二扫描线，每两列像素对应设置一条数据线；
所述液晶显示面板还包括N个像素组，每个像素组包括至少1行像素，第n个像素组中位于第2k+1列的像素与对应的第一扫描线连接；第n个像素组中位于第2k列的像素与对应的第二扫描线连接；
第n+1个像素组中位于第2k+1列的像素与对应的第二扫描线连接；第n+1个像素组中位于第2k列的像素与对应的第一扫描线连接，其中0＜n＜N，N≥2，k≥0；
每一行像素对应的所述第一扫描线的开启时间早于该行像素对应的第二扫描线的开启时间，所述第一扫描线对应的像素的充电效率低于所述第二扫描线对应的像素的充电效率；每一列像素中位于第n个像素组的像素的充电效率与该列中位于第n+1个像素组中的像素的充电效率不同。
在本发明的液晶显示面板中，同一时刻相邻两条数据线输入的数据电压的极性相同。
在本发明的液晶显示面板中，同一时刻相邻两条数据线输入的数据电压的极性不同。
在本发明的液晶显示面板中，所述像素组包括2行像素，第n个像素组中位于第2k+1列的像素与对应的第一扫描线连接；第n个像素组中位于第2k列的像素与对应的第二扫描线连接；
第n+1个像素组中位于第2k+1列的像素与对应的第二扫描线连接；第n+1个像素组中位于第2k列的像素与对应的第一扫描线连接。
在本发明的液晶显示面板中，所述像素组包括2行彼此相邻的像素。
为解决上述技术问题，本发明提供一种液晶显示面板，其包括：
多条扫描线、多条数据线以及多个像素，每行像素对应设置第一扫描线和第二扫描线，每两列像素对应设置一条数据线；
所述液晶显示面板还包括N个像素组，每个像素组包括至少1行像素，第n个像素组中位于第2k+1列的像素与对应的第一扫描线连接；第n个像素组中位于第2k列的像素与对应的第二扫描线连接；
第n+1个像素组中位于第2k+1列的像素与对应的第二扫描线连接；第n+1个像素组中位于第2k列的像素与对应的第一扫描线连接，其中0＜n＜N，N≥2，k≥0。
在本发明的液晶显示面板中，同一时刻相邻两条数据线输入的数据电压的极性相同。
在本发明的液晶显示面板中，同一时刻相邻两条数据线输入的数据电压的极性不同。
在本发明的液晶显示面板中，每一列像素中位于第n个像素组的像素的充电效率与该列中位于第n+1个像素组中的像素的充电效率不同。
在本发明的液晶显示面板中，每一行像素对应的所述第一扫描线的开启时间早于该行像素对应的第二扫描线的开启时间，所述第一扫描线对应的像素的充电效率低于所述第二扫描线对应的像素的充电效率。
在本发明的液晶显示面板中，所述像素组包括2行像素，第n个像素组中位于第2k+1列的像素与对应的第一扫描线连接；第n个像素组中位于第2k列的像素与对应的第二扫描线连接；
第n+1个像素组中位于第2k+1列的像素与对应的第二扫描线连接；第n+1个像素组中位于第2k列的像素与对应的第一扫描线连接。
在本发明的液晶显示面板中，所述像素组包括2行彼此相邻的像素。
本发明还提供一种液晶显示装置，其包括：
背光模块，以及
液晶显示面板，其包括：
多条扫描线、多条数据线以及多个像素，每行像素对应设置第一扫描线和第二扫描线，每两列像素对应设置一条数据线；
所述液晶显示面板还包括N个像素组，每个像素组包括至少1行像素，第n个像素组中位于第2k+1列的像素与对应的第一扫描线连接；第n个像素组中位于第2k列的像素与对应的第二扫描线连接；
第n+1个像素组中位于第2k+1列的像素与对应的第二扫描线连接；第n+1个像素组中位于第2k列的像素与对应的第一扫描线连接，其中0＜n＜N，N≥2，k≥0。
在本发明的液晶显示装置中，同一时刻相邻两条数据线输入的数据电压的极性相同。
在本发明的液晶显示装置中，同一时刻相邻两条数据线输入的数据电压的极性不同。
在本发明的液晶显示装置中，每一列像素中位于第n个像素组的像素的充电效率与该列中位于第n+1个像素组中的像素的充电效率不同。
在本发明的液晶显示装置中，每一行像素对应的所述第一扫描线的开启时间早于该行像素对应的第二扫描线的开启时间，所述第一扫描线对应的像素的充电效率低于所述第二扫描线对应的像素的充电效率。
在本发明的液晶显示装置中，所述像素组包括2行像素，第n个像素组中位于第2k+1列的像素与对应的第一扫描线连接；第n个像素组中位于第2k列的像素与对应的第二扫描线连接；
第n+1个像素组中位于第2k+1列的像素与对应的第二扫描线连接；第n+1个像素组中位于第2k列的像素与对应的第一扫描线连接。
在本发明的液晶显示装置中，所述像素组包括2行彼此相邻的像素。
 有益效果
本发明的液晶显示面板及装置，将全部像素划分为像素组，每个像素组包括至少1行像素，相邻两个像素组中位于同一列的像素连接驱动时间不同的扫描线，从而使得同一列像素的充电效率不同，避免产生垂直方向的亮暗线，提高了显示效果。
 附图说明
图1为现有液晶显示面板的驱动架构图；
图2是图1中液晶显示面板的驱动时序图；
图3为图1中液晶显示面板的像素的充电率的示意图；
图4为本发明第一种液晶显示面板的驱动架构图；
图5是图4中液晶显示面板的驱动时序图；
图6为图4中液晶显示面板的像素的充电率的示意图；
图7为本发明第二种液晶显示面板的驱动架构图；
图8是图7中液晶显示面板的驱动时序图；
图9为图7中液晶显示面板的像素的充电率的示意图；
图10为本发明第三种液晶显示面板的驱动架构图；
图11是图10中液晶显示面板的驱动时序图；
图12为图10中液晶显示面板的像素的充电率的示意图；
图13为本发明第四种液晶显示面板的驱动架构图；
图14是图13中液晶显示面板的驱动时序图；
图15为图13中液晶显示面板的像素的充电率的示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参照图4-6，图4为本发明第一种液晶显示面板的驱动架构图。
本实施例的液晶显示面板包括：多条扫描线G1-G16、多条数据线D1-D3以及多个像素101。每行像素对应设置两条扫描线，也即第一扫描线和第二扫描线，比如第1行像素对应设置扫描线G1-G2。每两列像素对应设置一条数据线；其中每相邻的两列像素对应设置一条数据线。比如数据线D1连接第1列像素和第2列像素，数据线D2连接第3列像素和第4列像素，数据线D3连接第5列像素和第6列像素。
所述液晶显示面板还包括4个像素组11-14。每个像素组包括2行像素。其中这2行像素相邻。在其他实施方式中，这2行像素也可以不相邻。
第n个像素组中位于奇数列（2k+1）的像素与对应的第一扫描线连接；第n个像素组中位于偶数列（2k）的像素与对应的第二扫描线连接；第n+1个像素组中位于奇数列的像素与对应的第二扫描线连接；第n+1个像素组中位于偶数列的像素与对应的第一扫描线连接，其中n大于0小于N，N大于2。
比如第一个像素组11包括第1行像素和第2行像素，第2个像素组12包括第3行像素和第4行像素。以第1个像素组和第2个像素组为例，第1个像素组11中位于奇数列的像素与对应的第一扫描线G1、G3连接，第1个像素组11中位于偶数列的像素与对应的第二扫描线G2、G4连接。具体地，第1个像素组11中的位于奇数列的第1行像素与对应的第一扫描线G1连接；位于偶数列的第1行像素与对应的第二扫描线G2连接。第1个像素组11中的位于奇数列第2行的像素与对应的第一扫描线G3连接，位于偶数列的第2行像素与对应的第二扫描线G4连接。
第2个像素组12中位于奇数列的像素与对应的第二扫描线G6、G8连接；第2个像素组12中位于偶数列的像素与对应的第一扫描线G5、G7连接。具体地，第2个像素组12中的位于奇数列的第3行像素与对应的第二扫描线G6连接；位于偶数列的第3行像素与对应的第一扫描线G5连接。第2个像素组12中的位于奇数列的第4行像素与对应的第二扫描线G8连接，位于偶数列的第4行像素与对应的第一扫描线G7连接。其余像素组与此类似。
在另一实施方式中，第1个像素组中位于奇数列的像素与对应的第二扫描线连接，第1个像素组中位于偶数列的像素与对应的第一扫描线连接。第2个像素组中位于奇数列的像素与对应的第一扫描线连接，第2个像素组中位于偶数列的像素与对应的第二扫描线连接。
其中同一时刻相邻两条数据线的输入的数据电压的极性相同，使得位于同一行的像素的极性相同。
可以理解的，该显示面板也可以包括2个、3个或者4个以上的像素组。
同一数据线中每八个像素为一重复单元，图4中数据线D1对应的像素的驱动顺序为：
P11、P12、P21、P22、P32、P31、P42、P41，11、12、21、22、32、31、42、41表示像素在矩阵中的位置，其中第一位表示像素所在的行，第二位表示像素所在的列。以P11为例，代表第1行第1列的像素。
图5是图4所示的液晶显示器的驱动时序图，Data1表示数据线D1实际输入电压的波形；Data2表示数据线D2实际输入电压的波形；Gate1表示第一条扫描线G1输入扫描信号的波形；Gate2表示第二条扫描线G2输入扫描信号的波形；Gate3表示第三条扫描线G3输入扫描信号的波形，Gate4表示第四条扫描线G4输入扫描信号的波形。
每一行像素对应的所述第一扫描线的开启时间早于该行像素对应的的第二扫描线的开启时间。比如第一行像素的第一扫描线G1的开启时间大于第一行像素的第二扫描线G2的开启时间。
图6为图4所示液晶显示器像素的充电率示意图，L表示充电率低，H表示充电率高。由图可以看出，数据线极性反转后对应的先驱动的像素充电率低，对应的后驱动的像素充电率高。也即每一行像素的对应的所述第一扫描线对应的像素的充电效率低于该行像素对应的所述第二扫描线对应的像素的充电效率。
使用图4所示的液晶显示器驱动架构，使得所有充电率低的像素不位于同一列，其中每一列像素中位于第n个像素组的像素与该列中的位于第n+1个像素组中的像素的充电效率不同，比如第1列像素中第1个像素组的像素的充电效率与第1列中的位于第2个像素组中的像素的充电效率不同。也即充电率高的像素和充电率低的像素交叉排列，不会产生垂直方向的亮暗线，提高了显示器的显示效果。
请参照图7-9，图7为本发明第二种液晶显示面板的驱动架构图。
本实施例中的液晶显示面板也包括4个像素组21-24。图7与图4所示的液晶显示面板的驱动架构的区别在于，同一时刻相邻两条数据线的输入的数据电压的极性不同，使得位于同一行中像素的极性随着数据线的极性交替排列，比如第一行像素中与第一条数据线D1连接的像素的极性为负，第一行像素中与第二条数据线D2连接的像素的极性为正，第一行像素中与第三条数据线D3连接的像素的极性为负。因此图7所示的液晶显示器，不但充电率高的H和充电率低的L交叉排列，而且正极性和负极性也交叉排列。
图8是图7所示液晶显示器的驱动时序，Data1表示数据线D1实际输入电压的波形；Data2表示数据线D2实际输入电压的波形； Gate1表示第一条扫描线G1输入扫描信号的波形；Gate2表示第二条扫描线G2输入扫描信号的波形；Gate3表示第三条扫描线G3输入扫描信号的波形，Gate4表示第四条扫描线G4输入扫描信号的波形。
每一行像素对应的所述第一扫描线的开启时间早于该行像素对应的第二扫描线的开启时间。比如第一行像素的第一扫描线G1的开启时间大于第一行像素的第二扫描线G2的开启时间。
图9为图7所示的液晶显示器像素的充电率示意图，L表示充电率低，H表示充电率高。由图可以看出，数据线的极性反转后对应的先驱动的像素充电率低，对应的后驱动的充电率高，也即所述第一扫描线对应的像素的充电效率低于所述第二扫描线对应的像素的充电效率。使用图7所示的液晶显示器驱动架构，使得所有充电率低的像素不位于同一列，其中每一列像素中位于第n个像素组的像素与该列中的位于第n+1个像素组中的像素的充电效率不同，比如第1列像素中第1个像素组的像素与第1列中的位于第2个像素组中的像素的充电效率不同。也即充电率高的H和充电率低的L交叉排列，不会产生垂直方向的亮暗线，提升了显示器的显示效果。
请参照图10-12，图10为本发明第三种液晶显示面板的驱动架构图。
本实施例的液晶显示面板与第一实施例的区别在于，所述液晶显示面板包括6个像素组31-36。每个像素组包括1行像素。具体地，第n个像素组中位于奇数（2k+1）列的像素与对应的第一扫描线连接；第n个像素组中位于偶数（2k）列的像素与对应的第二扫描线连接；第n+1个像素组中位于奇数列的像素与对应的第二扫描线连接；第n+1个像素组中位于偶数列的像素与对应的第一扫描线连接，其中n大于0小于N，N大于2。
比如第一个像素组31包括第1行像素，第二个像素组包括32包括第2行像素。以第1个像素组和第2个像素组为例，第1个像素组31中位于奇数列的像素与对应的第一扫描线G1连接，第1个像素组中位于偶数列的像素与对应的第二扫描线G2连接。第2个像素组32中位于奇数列的像素与对应的第二扫描线G4连接，位于偶数列的像素与对应的第一扫描线G3连接。其余像素组与此类似。
同一数据线中每八个像素为一重复单元，图10中数据线D1对应的像素的驱动顺序：
P11、P12、P22、P21、P31、P32、P42、P41，11、12、22、21、31、32、42、41表示像素在矩阵中的位置，其中第一位表示像素所在的行，第二位表示像素所在的列。以P11为例，代表第1行第1列的像素。
其中同一时刻相邻两条数据线的输入的数据电压的极性相同，使得位于同一行的像素的极性相同。
图11是图10所示的液晶显示器的驱动时序图，Data1表示数据线D1实际输入电压的波形；Data2表示数据线D2实际输入电压的波形；Gate1表示第一条扫描线G1输入扫描信号的波形；Gate2表示第二条扫描线G2输入扫描信号的波形；Gate3表示第三条扫描线G3输入扫描信号的波形，Gate4表示第四条扫描线G4输入扫描信号的波形。
每一行像素对应的所述第一扫描线的开启时间早于该行像素对应的第二扫描线的开启时间。比如第一行像素的第一扫描线G1的开启时间早于第一行像素的第二扫描线G2的开启时间。
图12为图10所示的液晶显示器像素的充电率示意图，L表示充电率低，H表示充电率高。由图可以看出，数据线极性反转后对应的先驱动的像素充电率低，对应的后驱动的像素充电率高。使用图10所示的液晶显示器驱动架构，使得所有充电率低的像素不位于同一列，也即所述第一扫描线对应的像素的充电效率低于所述第二扫描线对应的像素的充电效率。其中每一列像素中位于第n个像素组的像素与该列中的位于第n+1个像素组中的像素的充电效率不同，比如第1列像素中位于第1个像素组的像素与第1列中位于第2个像素组中的像素的充电效率不同。也即同一列中相邻两个充电率高的像素和充电率低的像素交叉排列，不会产生垂直方向的亮暗线，提高了显示器的显示效果。
请参照图13-15，图13为本发明第四种液晶显示面板的驱动架构图。
本实施例的液晶显示面板包括6个像素组41-46。图13与图10的液晶显示器驱动架构的区别在于：同一时刻相邻两条数据线的输入的数据电压的极性不同，使得位于同一行中像素的极性随着数据线的极性交替排列，比如第一行像素中与第一条数据线D1连接的像素的极性为负，第一行像素中与第二条数据线D2连接的像素的极性为正，第一行像素中与第三条数据线D3连接的像素的极性为负。因此图13所示的液晶显示器，不但充电率高的像素和充电率低的像素交叉排列，而且正极性和负极性也交叉排列。
图14是图13所示的液晶显示器的驱动时序图，Data1表示数据线D1实际输入电压的波形；Data2表示数据线D2实际输入电压的波形；Gate1表示第一条扫描线G1输入扫描信号的波形；Gate2表示第二条扫描线G2输入扫描信号的波形；Gate3表示第三条扫描线G3输入扫描信号的波形，Gate4表示第四条扫描线G4输入扫描信号的波形。
每一行像素对应的所述第一扫描线的开启时间早于该行像素对应的第二扫描线的开启时间。比如第一行像素的第一扫描线G1的开启时间早于第一行像素的第二扫描线G2的开启时间。
图15为图13所示的液晶显示器像素的充电率示意图，L表示充电率低，H表示充电率高。由图可以看出，数据线极性反转后对应的先驱动的像素的充电率低，对应的后驱动的像素的充电率高。也即所述第一扫描线对应的像素的充电效率低于所述第二扫描线对应的像素的充电效率。使用图15所示的液晶显示器驱动架构，使得所有充电率低的像素不位于同一列，其中每一列像素中位于第n个像素组的像素与该列中的位于第n+1个像素组中的像素的充电效率不同，也即每一列相邻两个像素组的像素的充电效率不同。比如第1列像素中第1个像素组的像素与第1列中的位于第2个像素组中的像素的充电效率不同。也即同一列中相邻两个充电率高的像素和充电率低的像素交叉排列，不会产生垂直方向的亮暗线，提高了显示器的显示效果。
本发明的液晶显示面板及装置，将全部像素划分为像素组，每个像素组包括至少1行像素，相邻两个像素组中位于同一列的像素连接驱动时间不同的扫描线，从而使得同一列像素的充电效率不同，避免产生垂直方向的亮暗线，提高了显示效果。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (19)

  1. 一种液晶显示面板，其包括：多条扫描线、多条数据线以及多个像素，每行像素对应设置第一扫描线和第二扫描线，每两列像素对应设置一条数据线；
    所述液晶显示面板还包括N个像素组，每个像素组包括至少1行像素，第n个像素组中位于第2k+1列的像素与对应的第一扫描线连接；第n个像素组中位于第2k列的像素与对应的第二扫描线连接；
    第n+1个像素组中位于第2k+1列的像素与对应的第二扫描线连接；第n+1个像素组中位于第2k列的像素与对应的第一扫描线连接，其中0＜n＜N，N≥2，k≥0；
    每一行像素对应的所述第一扫描线的开启时间早于该行像素对应的第二扫描线的开启时间，所述第一扫描线对应的像素的充电效率低于所述第二扫描线对应的像素的充电效率；每一列像素中位于第n个像素组的像素的充电效率与该列中位于第n+1个像素组中的像素的充电效率不同。
  2. 根据权利要求1所述的液晶显示面板，其中同一时刻相邻两条数据线输入的数据电压的极性相同。
  3. 根据权利要求1所述的液晶显示面板，其中同一时刻相邻两条数据线输入的数据电压的极性不同。
  4. 根据权利要求1所述的液晶显示面板，其中所述像素组包括2行像素，第n个像素组中位于第2k+1列的像素与对应的第一扫描线连接；第n个像素组中位于第2k列的像素与对应的第二扫描线连接；
    第n+1个像素组中位于第2k+1列的像素与对应的第二扫描线连接；第n+1个像素组中位于第2k列的像素与对应的第一扫描线连接。
  5. 根据权利要求4所述的液晶显示面板，其中所述像素组包括2行彼此相邻的像素。
  6. 一种液晶显示面板，其包括：多条扫描线、多条数据线以及多个像素，每行像素对应设置第一扫描线和第二扫描线，每两列像素对应设置一条数据线；
    所述液晶显示面板还包括N个像素组，每个像素组包括至少1行像素，第n个像素组中位于第2k+1列的像素与对应的第一扫描线连接；第n个像素组中位于第2k列的像素与对应的第二扫描线连接；
    第n+1个像素组中位于第2k+1列的像素与对应的第二扫描线连接；第n+1个像素组中位于第2k列的像素与对应的第一扫描线连接，其中0＜n＜N，N≥2，k≥0。
  7. 根据权利要求6所述的液晶显示面板，其中同一时刻相邻两条数据线输入的数据电压的极性相同。
  8. 根据权利要求6所述的液晶显示面板，其中同一时刻相邻两条数据线输入的数据电压的极性不同。
  9. 根据权利要求6所述的液晶显示面板，其中每一列像素中位于第n个像素组的像素的充电效率与该列中位于第n+1个像素组中的像素的充电效率不同。
  10. 根据权利要求6所述的液晶显示面板，其中每一行像素对应的所述第一扫描线的开启时间早于该行像素对应的第二扫描线的开启时间，所述第一扫描线对应的像素的充电效率低于所述第二扫描线对应的像素的充电效率。
  11. 根据权利要求6所述的液晶显示面板，其中所述像素组包括2行像素，第n个像素组中位于第2k+1列的像素与对应的第一扫描线连接；第n个像素组中位于第2k列的像素与对应的第二扫描线连接；
    第n+1个像素组中位于第2k+1列的像素与对应的第二扫描线连接；第n+1个像素组中位于第2k列的像素与对应的第一扫描线连接。
  12. 根据权利要求11所述的液晶显示面板，其中所述像素组包括2行彼此相邻的像素。
  13. 一种液晶显示装置，其包括：
    背光模块，以及
    液晶显示面板，其包括：
    多条扫描线、多条数据线以及多个像素，每行像素对应设置第一扫描线和第二扫描线，每两列像素对应设置一条数据线；
    所述液晶显示面板还包括N个像素组，每个像素组包括至少1行像素，第n个像素组中位于第2k+1列的像素与对应的第一扫描线连接；第n个像素组中位于第2k列的像素与对应的第二扫描线连接；
    第n+1个像素组中位于第2k+1列的像素与对应的第二扫描线连接；第n+1个像素组中位于第2k列的像素与对应的第一扫描线连接，其中0＜n＜N，N≥2，k≥0。
  14. 根据权利要求13所述的液晶显示装置，其中同一时刻相邻两条数据线输入的数据电压的极性相同。
  15. 根据权利要求13所述的液晶显示装置，其中同一时刻相邻两条数据线输入的数据电压的极性不同。
  16. 根据权利要求13所述的液晶显示装置，其中每一列像素中位于第n个像素组的像素的充电效率与该列中位于第n+1个像素组中的像素的充电效率不同。
  17. 根据权利要求13所述的液晶显示装置，其中每一行像素对应的所述第一扫描线的开启时间早于该行像素对应的第二扫描线的开启时间，所述第一扫描线对应的像素的充电效率低于所述第二扫描线对应的像素的充电效率。
  18. 根据权利要求13所述的液晶显示装置，其中所述像素组包括2行像素，第n个像素组中位于第2k+1列的像素与对应的第一扫描线连接；第n个像素组中位于第2k列的像素与对应的第二扫描线连接；
    第n+1个像素组中位于第2k+1列的像素与对应的第二扫描线连接；第n+1个像素组中位于第2k列的像素与对应的第一扫描线连接。
  19. 根据权利要求18所述的液晶显示装置，其中所述像素组包括2行彼此相邻的像素。
PCT/CN2017/087792 2017-05-08 2017-06-09 一种液晶显示面板及装置 WO2018205333A1 (zh)

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