WO2020093494A1 - 显示面板的驱动电路及其方法，以及显示装置 - Google Patents

显示面板的驱动电路及其方法，以及显示装置 Download PDF

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Publication number
WO2020093494A1
WO2020093494A1 PCT/CN2018/118901 CN2018118901W WO2020093494A1 WO 2020093494 A1 WO2020093494 A1 WO 2020093494A1 CN 2018118901 W CN2018118901 W CN 2018118901W WO 2020093494 A1 WO2020093494 A1 WO 2020093494A1
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WIPO (PCT)
Prior art keywords
gate
voltage
angle
driving circuit
circuit
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PCT/CN2018/118901
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English (en)
French (fr)
Inventor
黄笑宇
Original Assignee
重庆先进光电显示技术研究院
重庆惠科金渝光电科技有限公司
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Application filed by 重庆先进光电显示技术研究院, 重庆惠科金渝光电科技有限公司 filed Critical 重庆先进光电显示技术研究院
Priority to US16/454,038 priority Critical patent/US20200152150A1/en
Publication of WO2020093494A1 publication Critical patent/WO2020093494A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present application relates to the technical field of liquid crystal driving, in particular to a driving circuit and method of a display panel, and a display device.
  • the dual-gate pixel drive structure is usually matched with 1 + 2 line or The line inversion method is used to drive the polarity inversion of the capacitor in the pixel array.
  • this inversion method may cause the charging efficiency of two adjacent pixels to be inconsistent due to an excessive voltage across the data voltage, resulting in a bright and dark line problem, resulting in a decrease in the picture quality of the LCD panel.
  • the main purpose of the present application is to propose a driving circuit and method of a display panel, and a display device, aiming to improve the picture quality of the display device.
  • the present application proposes a driving circuit for a display panel, the display panel having sub-pixels; wherein, the driving circuit for the display panel includes:
  • the timing controller is configured to output the first timing control signal and the second timing control signal
  • a gate driving circuit configured to receive the gate-on voltage of the driving power source and drive the corresponding odd-numbered and even-numbered sub-pixels of the dual-gate pixel driving structure to work;
  • the angle-cutting circuit is configured to, when receiving the first timing control signal, perform angle-cutting and step-down on the gate-on voltage output by the driving power supply to the gate driving circuit to control the two adjacent rows
  • the capacitor charging voltage of the sub-pixel in the previous row is the first preset voltage; when the second timing control signal is received, the gate turn-on voltage output from the driving power supply to the gate driving circuit is angled down To control the capacitor charging voltage of the sub-pixel in the next row in the two adjacent rows to be equal to the first preset voltage.
  • the angle-cutting circuit includes a first angle-cutting resistor, a second angle-cutting resistor, a first switching tube, and a second switching tube, and the first end of the first angle-cutting resistor is a part of the angle-cutting circuit
  • the input end is connected to the first end of the second angle-cutting resistor, and the second end of the first angle-cutting resistor is respectively connected to the input end of the first switch tube and the output end of the second switch tube Interconnection, the output end of the first switch is grounded, the controlled end of the first switch is the first controlled end of the first angle-cutting circuit; the second end of the second angle-cutting resistor It is connected to the input end of the second switch tube, and the controlled end of the second switch tube is the second controlled end of the angle-cutting circuit.
  • the number of the first angle-cutting resistors is plural, and the plurality of first angle-cutting resistors are arranged in parallel.
  • the first switch tube and / or the first switch tube is an N-MOS tube.
  • the first switch tube and / or the first switch tube is a transistor.
  • the first switch tube and / or the first switch tube is an IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor).
  • IGBT Insulated Gate Bipolar Transistor, insulated gate bipolar transistor
  • the present application also proposes a display device including a dual-gate pixel driving structure having a plurality of odd-numbered rows and a plurality of even-numbered rows of sub-pixels, a timing controller, and a driving power supply, wherein the display device further includes the display device as described above Gate drive circuit;
  • the gate driving circuit is configured to receive the gate-on voltage of the driving power and drive the sub-pixels of the corresponding row in the dual-gate pixel driving structure to work;
  • the angle-cutting circuit is configured to, when receiving the first timing control signal, perform angle-cutting and step-down on the gate-on voltage output from the driving power supply to the gate driving circuit to control the capacitance of the current row of sub-pixels
  • the charging voltage is a first preset voltage; when receiving the second timing control signal, the gate turn-on voltage output from the driving power supply to the gate driving circuit is angled down to control even rows
  • the capacitor charging voltage of the pixel is equal to the first preset voltage.
  • the dual-gate pixel driving structure includes a switch array; the drive circuit of the display panel further includes multiple data lines and multiple scan lines electrically connected to the gate drive circuit, and the switch array includes multiple Thin film transistors, the thin film transistors in odd columns in each row are connected to the scan lines in odd rows, and the thin film transistors in even columns in each row are electrically connected to the scan lines in even rows, adjacent to each other The odd-numbered thin film transistors and the even-numbered thin film transistors are electrically connected to the same data line.
  • the dual-gate pixel driving structure includes a switch array; the drive circuit of the display panel further includes a plurality of data lines and a plurality of scan lines electrically connected to the gate drive circuit, and the switch array includes a plurality of Thin film transistors, the thin film transistors in odd columns in each row are respectively connected to the scan lines in even rows, the thin film transistors in even columns in each row are electrically connected to the scan lines in odd rows, adjacent The odd-numbered thin film transistors and the even-numbered thin film transistors are electrically connected to the same data line.
  • the polarity inversion mode of the switch array is 1 + 2 pixel line signal inversion.
  • the polarity reversal mode of the switch array is a 2-line pixel line signal inversion.
  • the multiple scan lines include odd-numbered scan lines and even-numbered scan lines.
  • the display device further includes a source driving circuit, and the timing controller is respectively connected to the gate driving circuit, the source driving circuit, and the driving power supply.
  • the driving power supply integrates a plurality of DC-DC conversion circuits with different circuit functions, and each of the DC-DC conversion circuits outputs different voltage values.
  • the angle-cutting circuit includes a first angle-cutting resistor, a second angle-cutting resistor, a first switching tube, and a second switching tube, and the first end of the first angle-cutting resistor is a part of the angle-cutting circuit
  • the input end is connected to the first end of the second angle-cutting resistor, and the second end of the first angle-cutting resistor is respectively connected to the input end of the first switch tube and the output end of the second switch tube Interconnection, the output end of the first switch is grounded, the controlled end of the first switch is the first controlled end of the first angle-cutting circuit; the second end of the second angle-cutting resistor It is connected to the input end of the second switch tube, and the controlled end of the second switch tube is the second controlled end of the angle-cutting circuit.
  • the number of the first angle-cutting resistors is plural, and the plurality of first angle-cutting resistors are arranged in parallel.
  • the first switch tube and / or the first switch tube is an N-MOS tube.
  • the display device is a computer display screen / mobile phone / monitor / TV.
  • the present application also proposes a driving method of a display panel.
  • the display panel includes a plurality of sub-pixels.
  • the driving method of the display panel includes:
  • the received gate-on voltage is angle-cut and stepped down to control the capacitor charging voltage of the previous sub-pixel in the adjacent two rows to be the first preset voltage;
  • the received gate-on voltage is clipped and stepped down to control the capacitor charging voltage of the sub-pixel in the next row in the adjacent two rows to be equal to the first preset voltage.
  • the angle-cutting voltage reduction of the gate-on voltage output to the gate driving circuit specifically includes:
  • the gate turn-on voltage output to the gate driving circuit is divided into different levels to cut off the voltage of the gate turn-on voltage .
  • the timing controller when the timing controller outputs a control signal to the gate driving circuit, and when the driving power source outputs the gate-on voltage to the gate driving circuit to drive the gate driving circuit to work, the timing controller outputs the first timing control signal and the second The timing control signal is sent to the angle-cutting circuit to control the angle-cutting circuit to perform angle-cutting on the gate-on voltage.
  • the control adjusts the two adjacent rows
  • the conduction degree of the thin film transistor corresponding to the scan line of the previous row is greater than the conduction degree of the thin film transistor corresponding to the scan line of the next row in the adjacent two rows.
  • the angle of the slope of the row driving voltage waveform output on the scanning line of the previous two adjacent rows is smaller than the angle of the row driving voltage waveform output on the adjacent row scanning line, so as to realize the adjacent
  • the opening area of the thin-film transistor in the previous row of the two rows is larger than that of the adjacent thin-film transistors, that is, to improve the charging efficiency of the sub-pixels corresponding to the scanning line of the previous row in the two adjacent rows to compensate for the voltage switching ramp Lost time. Therefore, the charging efficiency of the sub-pixel corresponding to the scanning line of the previous row in the two adjacent rows is consistent with the charging efficiency of the sub-pixel corresponding to the scanning line of the even-numbered row.
  • FIG. 1 is a schematic diagram of functional modules of a preferred embodiment of a display panel driving circuit of this application applied to a display device;
  • FIG. 2 is a schematic diagram of a circuit structure of an embodiment of an angle-cut circuit in the gate drive circuit in FIG. 1;
  • FIG. 3 is a schematic structural diagram of an embodiment of a dual-gate pixel driving structure in a display device of the present application
  • FIG. 4 is a schematic structural diagram of another embodiment of a dual-gate pixel driving structure in a display device of the present application.
  • FIG. 5 is a schematic flowchart of an embodiment of a gate driving method of a dual-gate pixel driving structure of the present application applied to a display device.
  • first”, “second”, etc. are for descriptive purposes only, and cannot be understood as instructions or hints Its relative importance or implicitly indicates the number of technical features indicated.
  • the features defined with “first” and “second” may include at least one of the features either explicitly or implicitly.
  • the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of those skilled in the art to realize. When the combination of technical solutions contradicts or cannot be realized, it should be considered that the combination of such technical solutions does not exist , Nor within the scope of protection required by this application.
  • This application proposes a driving circuit for a display panel, which should be provided in a display device.
  • the display device may be a display device with a liquid crystal display screen such as a computer display screen, a mobile phone, a monitor, a TV, and the like.
  • the display device includes a display panel 100; a timing controller 200 configured to output a first timing control signal and a second timing control signal; a driving power supply 300 configured to output a gate-on voltage and / or a gate-off voltage, and a gate Driving circuit 400.
  • the display device further includes a source driving circuit 500, and the timing controller 200 is respectively connected to the gate driving circuit 400, the source driving circuit 500, and the driving power supply 300.
  • the timing controller 200 is configured to receive data signals and control signals output by an external circuit module And the clock signal is converted into a data signal, a control signal, and a clock signal suitable for the gate driving circuit 400 and the source driving circuit 500 to realize the image display of the liquid crystal panel.
  • the signal format input by the timing controller 200 generally includes a transistor-transistor logic signal TTL, a low voltage differential signal (LVDS), an embedded display signal (eDP) signal, and a V-by-One signal.
  • the control signal output by the timing controller 200 includes a gate control signal and a source control signal
  • the source drive signal includes a row start signal (Start Horizontal, STH), horizontal clock pulse signal (Clock Pulse Horizontal , CPH), data output signal (TP) and data polarity inversion signal (MPOL or POL).
  • the gate drive signal includes a frame start signal (Start Vertical, STV), scanning clock pulse signal (Clock Pulse Vertical, CPV) and enable signal (Output Enable, OE).
  • the driving power supply 300 integrates a plurality of DC-DC conversion circuits with different circuit functions, and each conversion circuit outputs a different voltage value.
  • the input voltage of the input terminal of the driving power supply 300 is generally 5V or 12V.
  • the output voltage includes the operating voltage DVDD provided to the timing controller 200, and the gate turn-on voltage Vgh and the turn-off voltage provided to the gate driving circuit 400.
  • the display area is composed of multiple pixels, and each pixel is composed of three sub-pixels of red, green and blue.
  • Each sub-pixel is composed of a thin film transistor and a capacitor.
  • a plurality of odd-numbered rows and a plurality of even-numbered thin film transistors and capacitors may constitute the display panel 100.
  • a plurality of thin film transistors constitute a switch array.
  • FIGS. 3 and 4 show two embodiments of the display panel 100.
  • the thin-film transistors in odd columns in each row and the scans in even rows respectively For the connection of the lines, the thin-film transistors in the even-numbered columns in each row are electrically connected to the scan lines in the odd-numbered rows, and the adjacent odd-numbered thin-film transistors and even-numbered thin-film transistors are electrically connected to the same data line.
  • the adjacent odd-numbered thin-film transistors and even-numbered thin-film transistors are electrically connected to the same data line.
  • the thin film transistors in odd columns in each row are respectively connected to the scan lines in odd rows, and the thin film transistors in even columns in each row are electrically connected to the scan lines in even rows,
  • the adjacent odd-numbered thin film transistors and even-numbered thin film transistors are electrically connected to the same data line.
  • the pixel driving structure can be divided into a 1G1D structure that only turns on one line at a time, a 2G2D structure that turns on two lines at a time, and dual
  • the gate pixel driving structure (Dual-gate), this embodiment is preferably implemented using a dual-gate pixel structure, because in the display panel 100, the row scanning line is doubled, and the data line is doubled.
  • the gate The number of integrated chips in the driving circuit 400 will be doubled, while the number of integrated chips in the source driving circuit 500 can be reduced by half, because the cost of the integrated chips in the source driving circuit 500 is much higher than the integrated chips in the gate driving chip The cost of manufacturing, so the dual-gate pixel drive structure (Dual-gate) can effectively reduce the production cost of the display device.
  • the line write time will be reduced to half of the original, and in the design of the LCD panel, the important factor to consider the pixel drive structure is to ensure that the pixels have sufficient Pixel charging rate, and the shortening of the line writing time will affect the pixel charging rate.
  • the image quality of the panel is good, and the display panel is usually equipped with 1 + 2
  • the line or 2 line inversion method is used to drive the polarity inversion of the capacitor in the pixel array.
  • the line polarity inversion method is used to drive the polarity inversion of the capacitor in the pixel array.
  • the AC drive of the liquid crystal molecules is equivalent to the potential of the other electrode of the capacitor relative to the common electrode. Changes in potential from high to low. That is, the data signal output by the source driving circuit 500 rises or falls relative to the common electrode voltage.
  • the data signal voltage crossover voltage is relatively large, and because The reason for the RC load is that the voltage switching requires climbing time.
  • the charging rate of the sub-pixels that need to undergo voltage switching is lower than the charging rate of the sub-pixels whose voltage tends to be stable, that is, the charging saturation of the former pixel is less than that of the latter
  • the degree of saturation, and the brightness of a pixel that is saturated with charge is greater than a pixel that is not fully saturated with charge.
  • the adjacent odd-numbered thin film transistors and even-numbered thin film transistors are electrically connected to the same data line, and the gates of the adjacent odd-numbered thin film transistors and even-numbered thin film transistors are respectively formed by Two adjacent scan lines are controlled.
  • the color sub-pixels located in the first row and first column and the sub-pixels located in the first row and second column are connected to the scanning line G1, and the source is connected to the data line D2, and the gates of the sub-pixels in the first row and second column are connected to the scanning line G2 and the source and data Line D2 is connected.
  • the two adjacent sub-pixels are using 2Line
  • 2-line pixel line signal inversion the polarities of the two are the same, or l + 2Line Inversion is used (1 + 2 line pixel line signal inversion)
  • l + 2Line Inversion is used (1 + 2 line pixel line signal inversion)
  • 2Line Inversion The 2-line pixel line signal inversion
  • the gate driving circuit 420 When the gate driving circuit 420 performs progressive scanning, the G1 row scanning line is turned on first, and the G2 row scanning line is turned on; after l + 2Line Inversion (1 + 2 row pixel row line signal inversion), the G2 row scanning line is turned on first, and the G3 row scanning line is turned on later), the polarity of the color subpixels in the first row and first column is reversed from positive to The negative electrode.
  • the data voltage on the data line D2 will gradually decrease from the high level to the low level, that is, the positive electrode is switched to the negative electrode and remains low.
  • the color sub-pixels in the first row and the first column are not fully charged when charging is completed.
  • the scanning line in the G1 row is turned off, and the scanning line in the G2 row is turned on, thereby charging the sub-pixels in the first row and the second column, and charging the sub-pixels in the first row and the second column.
  • the data voltage on the data line D2 is kept at a low level, which is equivalent to switching from a negative electrode to a negative electrode.
  • the data signal voltage crossover voltage is small or no crossover voltage, so the blue When the sub-pixel is fully charged, the saturation is high. In this way, the brightness of the color sub-pixels in the first row and second column will be higher than the brightness of the color sub-pixels in the first row and first column, and so on, and the problem of bright / dark lines will appear on the entire liquid crystal panel.
  • the driving circuit of the display panel includes:
  • the gate driving circuit 420 is configured to receive the gate-on voltage Vgh of the driving power supply 300 to drive the corresponding odd-numbered sum of the display panel 100,
  • the chamfering circuit 410 is configured to, when receiving the first timing control signal, perform a chamfering reduction on the gate-on voltage Vgh output from the driving power supply 300 to the gate driving circuit 420 To control the capacitor charging voltage of the odd rows of sub-pixels as the first preset voltage; when the second timing control signal is received, the gate-on voltage Vgh output from the driving power supply 300 to the gate driving circuit 420 is performed The angle is reduced to control the capacitor charging voltage of the even-numbered sub-pixels to be equal to the first preset voltage.
  • the output end of the driving power supply 300 is connected to the input ends of the gate driving circuit 420 and the cornering circuit 410, and the control end of the timing controller 200 is connected to the controlled end of the cornering circuit 410 and the gate driving circuit 420, respectively The controlled end of the connection.
  • the scan lines for odd rows are G1, G3, G5 ... G2n + 1, and the scan lines for even rows are G2, G4, G6 ... G2n + 2.
  • the gate drive circuit 420 is based on the frame start signal (Start Vertical, STV), scanning clock pulse signal (Clock Pulse Vertical, CPV) and enable signal (Output Enable, OE) control, and when the driving power supply 300 outputs the gate-on voltage Vgh, the corresponding thin film transistors in the row G1 to G2n + 2 of the switch array G1 row are turned on row by row through the scanning lines in the timing controller 200
  • the output control signal cooperates with the data driving integrated circuit to realize the input of the data signal of the opening row into the corresponding pixel, and when the driving power supply 300 outputs the off voltage, the corresponding thin film transistor in the driving switch array is turned off.
  • the gate drive circuit 420 drives the switch array to turn on row by row, all the column data signal lines transmit data signals to the sub-pixels in the row, charge the sub-pixel capacitance, and write and maintain the signal voltage of the pixel, the sub-pixel
  • the liquid crystal molecules in the region rotate at this voltage, so that the transmittance of the incident light passing through the liquid crystal molecules is changed, that is, the light valve effect on the incident light is realized.
  • the angle-cutting circuit 410 After receiving the first timing control signal output from the timing controller 200, the angle-cutting circuit 410 performs angle-cutting and step-down on the gate-on voltage Vgh; to control the capacitance of the sub-pixel in the previous row in the two adjacent rows
  • the charging voltage is a first preset voltage; when receiving the second timing control signal, the gate turn-on voltage Vgh output from the driving power supply 300 to the gate driving circuit 420 is cut down to control
  • the capacitor charging voltage of the sub-pixel in the next row in the two adjacent rows is equal to the first preset voltage.
  • the first timing control signal and the second timing control signal are both square wave signals with alternating high and low levels
  • the angle-cutting circuit 410 uses the first timing control signal and the second timing control signal
  • the square wave signal is at a high level H
  • angle cutting starts, and when the square wave signals of the first timing control signal and the second timing control signal are low level, the angle cutting is stopped.
  • the timing controller 200 when the timing controller 200 outputs a control signal to the gate driving circuit 420, and when the driving power supply 300 outputs the gate-on voltage Vgh to the gate driving circuit 420 to drive the gate driving circuit 420 to work, the timing controller 200 outputs the first A timing control signal and a second timing control signal are sent to the angle-cutting circuit 410 to control the angle-cutting circuit 410 to perform angle-cutting on the gate-on voltage Vgh.
  • the gate driving circuit 420 outputs the corresponding row scanning signal to the thin film transistor via the row scanning line to realize the turn-on of the scanning line from the first row to the last row of the scanning line row by row
  • the two adjacent rows are controlled and adjusted
  • the conduction degree of the thin film transistors corresponding to the scanning lines in the previous row in is greater than the conduction degree of the thin film transistors corresponding to the scanning lines in the next row in the adjacent two rows.
  • the angle of the slope of the row driving voltage waveform output on the scanning line of the previous two adjacent rows is smaller than the angle of the row driving voltage waveform output on the adjacent row scanning line, so as to realize the adjacent
  • the opening area of the thin-film transistor in the previous row of the two rows is larger than that of the adjacent thin-film transistors, that is, to improve the charging efficiency of the sub-pixels corresponding to the scanning line of the previous row in the two adjacent rows to compensate for the voltage switching ramp Lost time. Therefore, the charging efficiency of the sub-pixel corresponding to the scanning line of the previous row in the two adjacent rows is consistent with the charging efficiency of the sub-pixel corresponding to the scanning line of the even-numbered row.
  • the gate drive circuit 420 When the polarity is reversed, the gate drive circuit 420 outputs the corresponding line scan signal to the switch array via the line scan line, and the second line of the scan line is called It is the previous scan line (or odd line) of the two adjacent lines, the third line is called the latter line (or even line) of the two adjacent lines, and so on, until the scan to The last line of the display panel, the angle cutting process is the same as 2Line
  • the Inversion (2-line pixel line signal inversion) method is the same when the polarity is reversed, and will not be repeated here.
  • the angle-cutting circuit 410 includes a first angle-cutting resistor R1, a second angle-cutting resistor R2, a first switching tube Q1 and a second switching tube Q2, the first The first end of the angle-cutting resistor R1 is the input end of the angle-cutting circuit 410 and is connected to the first end of the second angle-cutting resistor R2.
  • the second ends of the first angle-cutting resistor R1 are respectively connected to The input end of the first switch Q1 and the output end of the second switch Q2 are interconnected, the output of the first switch Q1 is grounded, and the controlled end of the first switch Q1 is the The first controlled end of the first chamfering circuit 410; the second end of the second chamfering resistor R2 is connected to the input end of the second switching tube Q2, and the controlled end of the second switching tube Q2 is The second controlled end of the angle-cut circuit 410.
  • the first switching transistor Q1 and the first switching transistor Q1 may use MOSFET (insulated gate field effect transistor), TFT (thin film transistor), triode, IGBT (Insulated Gate Bipolar Transistor (Insulated Gate Bipolar Transistor) and other switching transistors.
  • MOSFET insulated gate field effect transistor
  • TFT thin film transistor
  • IGBT Insulated Gate Bipolar Transistor
  • the first switching transistor Q1 and the first switching transistor Q1 are preferably N-MOSFETs (N-type insulated gate field effect transistors).
  • the first chamfered resistor R1 and the second chamfered resistor R2 are both discharge resistors, and when the first switching transistor Q1 receives the high-level first timing control signal output by the timing controller 200, the first chamfered resistor R1
  • the gate-opening voltage Vgh output from the current driving power supply 300 to the gate driving circuit 420 is subjected to a first chamfering step-down.
  • the first chamfered resistor R1 is a voltage dividing resistor
  • the first chamfered resistor R1 and the gate driving circuit 420 are equivalent to a series voltage divider
  • the first resistor is adjusted by adjusting the resistance value of the first chamfered resistor R1
  • the voltage division ratio of the voltage at the end of the angle-cutting resistor R1 and the gate-on voltage Vgh output to the gate drive circuit 420, thereby adjusting the voltage value of the gate-on voltage Vgh of the gate drive circuit 420 to adjust the gate drive circuit 420
  • the second switch Q2 receives the high-level second timing control signal output from the timing controller 200 and the first switch Q1 receives the high-level first timing control signal output from the timing controller 200
  • the second The chamfering resistor R2 and the first chamfering resistor R1 are arranged in parallel to perform a second chamfering step-down on the gate-on voltage Vgh output from the current driving power supply 300 to the gate driving circuit 420.
  • the first chamfered resistor R1 and the second chamfered resistor R2 provided in parallel are voltage-dividing resistors. According to the law of parallel resistance, the resistance decreases, the total of the first chamfered resistor R1 and the second chamfered resistor R2 The resistance value decreases.
  • the discharge degree of the first chamfered resistor R1 is smaller than that when the first chamfered resistor R1 and the second chamfered resistor R2 are arranged in parallel.
  • the timing controller 200 when the gate driving circuit 420 drives the corresponding thin film transistors on the odd-numbered scan lines to turn on, the timing controller 200 outputs a high-level first timing control signal to control the first switching transistor Q1 to be turned on, so that The first chamfering resistor R1 divides and discharges the gate-on voltage Vgh currently output to the gate driving circuit 420.
  • the timing controller 200 When the gate driving circuit 420 drives the corresponding thin film transistors on each scanning line to be turned on, the timing controller 200 outputs two second timing control signals of different high levels to control the first switching transistor Q1 and the second switching transistor Q2 simultaneously Turn on, so that the first chamfering resistor R1 and the second chamfering resistor R2 are set in parallel, and the gate-on voltage Vgh currently output to the gate driving circuit 420 is divided and discharged to make the chamfering slope of the previous row Less than the slope of the next row, so that the opening area of the previous row is greater than the opening area of the G2n + 2 row, that is, to improve the charging efficiency of the previous row, to compensate for the time lost by the voltage switching ramp, so that the previous row is charged The efficiency is consistent with the charging efficiency of the following row.
  • the number of the first chamfered resistors R1 is plural, and a plurality of the first chamfered resistors R1 are arranged in parallel.
  • the number of the first chamfering resistor R1 may be one or more, and this embodiment is preferably two, and are respectively labeled as the first chamfering resistor R1A and the first chamfering
  • the resistor R1B, the first chamfered resistor R1A and the first chamfered resistor R1B are arranged in parallel.
  • the total chamfered resistance of the first chamfered resistor R1A and the first chamfered resistor R1B is R1A * R1B / (R1A + R1B).
  • the total chamfered resistance of the first chamfered resistor R1A, the first chamfered resistor R1B, and the second chamfered resistor R2 is (R1A * R1B * R2 / ( R1A * R1B + R1A * R2 + R1B * R2).
  • the embodiments of the display device of the present application include all technical solutions of all the embodiments of the drive circuit of the display panel described above, and the achieved technology The effect is also the same, so I won't repeat them here.
  • This application also proposes a driving method for a display panel.
  • the method includes:
  • Step S1 when the first timing control signal is received, the received gate turn-on voltage is angle-cut and stepped down to control the capacitor charging voltage of the previous sub-pixel in the adjacent two rows to be the first preset voltage;
  • Step S2 When the second timing control signal is received, the received gate turn-on voltage is angle-cut and stepped down to control the capacitor charging voltage of the next row of sub-pixels in the two adjacent rows to be equal to the first preset voltage.
  • step S2 may be performed first, and those skilled in the art may set according to the angle-cut circuit and the type of polarity inversion used, so that when charging the pixel capacitance, the adjacent The charging rates of the two rows of pixel capacitors are the same, and there is no limit here.
  • the angle-cutting voltage reduction of the gate-on voltage output to the gate driving circuit specifically includes:
  • the gate turn-on voltage output to the gate driving circuit is divided into different levels to cut off the voltage of the gate turn-on voltage .
  • the first timing control signal and the second timing control signal are both square wave signals with alternating high and low levels, and the square wave signals of the first timing control signal and the second timing control signal are high Angle cutting starts at the level H, and the angle cutting stops when the square wave signals of the first timing control signal and the second timing control signal are low level.
  • the timing controller when the timing controller outputs a control signal to the gate driving circuit, and when the driving power source outputs the gate-on voltage to the gate driving circuit to drive the gate driving circuit to work, the timing controller outputs the first timing control signal and the second The timing control signal is sent to the angle-cutting circuit to control the angle-cutting circuit to perform angle-cutting and step-down on the gate-on voltage, so that the gate driving circuit outputs the corresponding line scan signal to the thin film transistor via the line scan line to realize
  • the conduction degree of the thin film transistor corresponding to the scanning line of the previous row in two rows is controlled to be greater than that of the scanning line in the previous row in two rows.
  • the turn-on degree of the thin film transistors of the TFT, and then the angle of slope of the row driving voltage waveform output from the scanning line of the previous row is smaller than the angle of the row driving voltage waveform output from the scanning line of the next row adjacent to it to achieve
  • the opening area of the thin-film transistor corresponding to the previous row is larger than the opening area of the thin-film transistor adjacent to the next row, that is, to increase the previous one Charging efficiency sub-pixels corresponding to the scan lines to compensate for the loss in the voltage switching ramp time, so that the charging efficiency of the same sub-pixels corresponding to the front row scanning line sub-pixel charging efficiency even-numbered scanning line corresponds.

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Abstract

一种显示面板(100)的驱动电路，栅极驱动电路(420)在接收到第一时序控制信号时，对驱动电源(300)输出至栅极驱动电路(420)的栅极开启电压(Vgh)进行削角降压，以控制相邻两行中的前一行子像素的电容充电电压为第一预设电压；在接收到第二时序控制信号时，对驱动电源(300)输出至栅极驱动电路(420)的栅极开启电压(Vgh)进行削角降压。

Description

显示面板的驱动电路及其方法，以及显示装置
相关专利
本申请要求2018年11月09日，申请号为201811336050.1，申请名称为“显示面板的驱动电路及其方法，以及显示装置”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及液晶驱动技术领域，特别涉及一种显示面板的驱动电路及其方法，以及显示装置。
背景技术
目前，在液晶显示面板采用双栅像素驱动结构的设计中，为了保证像素充电率高，面板的画质良好，双栅像素驱动结构通常会搭配1+2 line或2 line 反转方式来驱动像素阵列中电容的极性反转。
但是，这种反转方式可能由于数据电压的跨压过大，而导致相邻的两个像素的充电效率不一致而出现亮暗线问题，导致液晶显示面板的画面品质降低。
申请内容
本申请的主要目的是提出一种显示面板的驱动电路及其方法，以及显示装置，旨在提高显示装置的画面品质。
为实现上述目的，本申请提出一种显示面板的驱动电路，所述显示面板具有子像素；其中，该显示面板的驱动电路包括：
时序控制器，设置为输出第一时序控制信号和第二时序控制信号；
驱动电源，设置为输出栅极开启电压和/或栅极关断电压；
栅极驱动电路，设置为接收所述驱动电源的栅极开启电压而驱动双栅像素驱动结构中对应的奇数行和偶数行子像素工作；
削角电路，设置为在接收到所述第一时序控制信号时，对所述驱动电源输出至所述栅极驱动电路的栅极开启电压进行削角降压，以控制相邻两行中的前一行子像素的电容充电电压为第一预设电压；在接收到所述第二时序控制信号时，对所述驱动电源输出至所述栅极驱动电路的栅极开启电压进行削角降压，以控制相邻两行中的后一行子像素的电容充电电压等于所述第一预设电压。
可选地，所述削角电路包括第一削角电阻、第二削角电阻、第一开关管及第二开关管，所述第一削角电阻的第一端为所述削角电路的输入端，并与所述第二削角电阻的第一端连接，所述第一削角电阻的第二端分别与所述第一开关管的输入端及所述第二开关管的输出端互连，所述第一开关管的输出端接地，所述第一开关管的受控端为所述第一削角电路的第一受控端；所述第二削角电阻的第二端与所述第二开关管的输入端连接，所述第二开关管的受控端为所述削角电路的第二受控端。
可选地，所述第一削角电阻的数量为多个，多个所述第一削角电阻并联设置。
可选地，所述第一开关管和/或所述第一开关管为N-MOS管。
可选地，所述第一开关管和/或所述第一开关管为三极管。
可选地，所述第一开关管和/或所述第一开关管为IGBT（Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管）。
本申请还提出一种显示装置，包括具有多个奇数行和多个偶数行子像素的双栅像素驱动结构、时序控制器及驱动电源，其中，所述显示装置还包括如上所述的显示装置的栅极驱动电路；
栅极驱动电路，设置为接收所述驱动电源的栅极开启电压而驱动双栅像素驱动结构中对应行的子像素工作；
削角电路，设置为在接收到所述第一时序控制信号时，对所述驱动电源输出至所述栅极驱动电路的栅极开启电压进行削角降压，以控制当前行子像素的电容充电电压为第一预设电压；在接收到所述第二时序控制信号时，对所述驱动电源输出至所述栅极驱动电路的栅极开启电压进行削角降压，以控制偶数行子像素的电容充电电压等于所述第一预设电压。
可选地，所述双栅像素驱动结构包括开关阵列；所述显示面板的驱动电路还包括多条数据线及与所述栅极驱动电路电连接的多条扫描线，所述开关阵列包括多个薄膜晶体管，各行中奇数列的所述薄膜晶体管分别与奇数行的所述扫描线的连接，各行中偶数列的所述薄膜晶体管分别与偶数行的所述扫描线的电连接连接，相邻的奇数列薄膜晶体管和偶数列薄膜晶体管与同一条所述数据线电连接。
可选地，所述双栅像素驱动结构包括开关阵列；所述显示面板的驱动电路还包括条数据线及与所述栅极驱动电路电连接的多条扫描线，所述开关阵列包括多个薄膜晶体管，各行中奇数列的所述薄膜晶体管分别与偶数行的所述扫描线的连接，各行中偶数列的所述薄膜晶体管分别与奇数行的所述扫描线的电连接连接，相邻的奇数列薄膜晶体管和偶数列薄膜晶体管与同一条所述数据线电连接。
可选地，所述开关阵列的极性反转方式为1+2行画素行线信号反转。
可选地，所述开关阵列的极性反转方式为2行画素行线信号反转。
可选地，多条所述扫描线包括奇数行扫描线和偶数行扫描线。
可选地，显示装置还包括源极驱动电路，所述时序控制器分别与所述栅极驱动电路、所述源极驱动电路以及所述驱动电源连接。
可选地，所述驱动电源集成有多个不同电路功能的直流-直流转换电路，每个所述直流-直流转换电路输出不同的电压值。
可选地，所述削角电路包括第一削角电阻、第二削角电阻、第一开关管及第二开关管，所述第一削角电阻的第一端为所述削角电路的输入端，并与所述第二削角电阻的第一端连接，所述第一削角电阻的第二端分别与所述第一开关管的输入端及所述第二开关管的输出端互连，所述第一开关管的输出端接地，所述第一开关管的受控端为所述第一削角电路的第一受控端；所述第二削角电阻的第二端与所述第二开关管的输入端连接，所述第二开关管的受控端为所述削角电路的第二受控端。
可选地，所述第一削角电阻的数量为多个，多个所述第一削角电阻并联设置。
可选地，所述第一开关管和/或所述第一开关管为N-MOS管。
可选地，所述显示装置为电脑显示屏/手机/监控器/电视。
本申请还提出一种显示面板的驱动方法，所述显示面板包括多个子像素，所述显示面板的驱动方法包括：
接收到第一时序控制信号时，对接收的栅极开启电压进行削角降压，以控制相邻两行中的前一行子像素的电容充电电压为第一预设电压；
接收到第二时序控制信号时，对接收的栅极开启电压进行削角降压，以控制相邻两行中的后一行子像素的电容充电电压等于所述第一预设电压。
可选地，所述对输出至栅极驱动电路的栅极开启电压进行削角降压具体包括：
根据接收的所述第一时序控制信号或者所述第二时序控制信号，对输出至栅极驱动电路的栅极开启电压进行不同等级分压，以对所述栅极开启电压进行削角降压。
本申请在时序控制器输出控制信号至栅极驱动电路，并在驱动电源输出栅极开启电压至栅极驱动电路驱动栅极驱动电路工作时，时序控制器分别输出第一时序控制信号和第二时序控制信号至削角电路，以控制削角电路对该栅极开启电压进行削角降压。从而在栅极驱动电路经行扫描线输出对应的行扫描信号至薄膜晶体管以实现从扫描线的第一行扫描线至最后一行扫描线逐行依次开启的过程中，控制调节相邻两行中的前一行扫描线对应的薄膜晶体管的导通程度大于相邻两行中的后一行扫描线对应的薄膜晶体管的导通程度。进而使得各相邻两行中的前一行的扫描线上输出的行驱动电压波形的削角斜率小于与之相邻的行扫描线上输出的行驱动电压波形的削角斜率，以实现相邻两行中的前一行薄膜晶体管的开启面积大于与之相邻的薄膜晶体管的开启面积，即提高相邻两行中的前一行扫描线对应的子像素的充电效率，来补偿因电压切换爬坡损失掉的时间。从而使相邻两行中的前一行扫描线对应的子像素的充电效率与偶数行扫描线对应的子像素的充电效率一致。如此设置，有利于数据信号的电压从正极性切换至负极性，或者从负极性切换至正极性时，保证每一子像素的充电效果相同，且亮度一致。本申请解决了数据信号电压在极性反转时，由于跨压比较大，导致共用一数据线的两相邻子像素之间的充电饱和程度存在差异而出现低灰阶亮暗线的问题，本申请提高了显示装置的画面品质。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请显示面板的驱动电路应用于显示装置一优选实施例的功能模块示意图；
图2为图1中栅极驱动电路中削角电路一实施例的电路结构示意图；
图3为本申请显示装置中双栅像素驱动结构一实施例的结构示意图；
图4为本申请显示装置中双栅像素驱动结构另一实施例的结构示意图；
图5为本申请双栅像素驱动结构的栅极驱动方法应用于显示装置一实施例的流程示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，若本申请实施例中有涉及方向性指示（诸如上、下、左、右、前、后……），则该方向性指示仅用于解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本申请实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请提出一种显示面板的驱动电路，应设置为显示装置中。
本实施例中，该显示装置可以是电脑显示屏、手机、监控器、电视等具有液晶显示屏的显示装置。显示装置包括显示面板100；时序控制器200，设置为输出第一时序控制信号和第二时序控制信号；驱动电源300，设置为输出栅极开启电压和/或栅极关断电压，以及栅极驱动电路400。
显示装置还包括源极驱动电路500，时序控制器200分别与栅极驱动电路400、源极驱动电路500以及驱动电源300连接，时序控制器200设置为接收外部电路模块输出的数据信号、控制信号以及时钟信号，并转换成适合于栅极驱动电路400、源极驱动电路500的数据信号、控制信号以及时钟信号，实现液晶面板的图像显示。时序控制器200输入的信号格式一般由晶体管-晶体管逻辑信号TTL，低压差分信号（LVDS）、嵌入式显示信号（eDP）信号和V-by-One信号等格式。时序控制器200输出的控制信号包括栅极控制信号和源极控制信号，源极驱动信号包括行起始信号（Start Horizontal ，STH）、行时钟脉冲信号（Clock Pulse Horizontal ，CPH）、数据输出信号（TP）和数据极性翻转信号（MPOL或POL）。栅极驱动信号包括帧起始信号（Start Vertical，STV）、扫描时钟脉冲信号（Clock Pulse Vertical，CPV）及使能信号（Output Enable，OE）。
驱动电源300集成了多个不同电路功能的直流-直流转换电路，每个转换电路输出不同的电压值。驱动电源300的输入端输入的电压一般为5V或12V，输出的电压包括给时序控制器200提供的工作电压DVDD，以及给栅极驱动电路400提供的栅极开启电压Vgh和关断电压。
显示区由多个像素组成，每个像素又由红绿蓝三个子像素组成。每个子像素由一个薄膜晶体管和电容组成。多个奇数行和多个偶数行的薄膜晶体管和电容可以构成显示面板100。其中，多个薄膜晶体管构成了开关阵列。
参照图3和图4，图3和图4示出了显示面板100的两个实施例，显示面板100中，如图3，各行中奇数列的所述薄膜晶体管分别与偶数行的所述扫描线的连接，各行中偶数列的所述薄膜晶体管分别与奇数行的所述扫描线的电连接连接，相邻的奇数列薄膜晶体管和偶数列薄膜晶体管与同一条所述数据线电连接。或者，如图4，各行中奇数列的所述薄膜晶体管分别与奇数行的所述扫描线的连接，各行中偶数列的所述薄膜晶体管分别与偶数行的所述扫描线的电连接连接，相邻的奇数列薄膜晶体管和偶数列薄膜晶体管与同一条所述数据线电连接。
需要说明的是，根据某一时刻，行开启的数量以及对应的像素信号的输入，像素驱动结构可以分为某一时刻只开启一行的1G1D结构、某时刻同时开两行的2G2D结构，以及双栅像素驱动结构（Dual-gate），本实施例优选为采用双栅像素结构来实现，由于显示面板100中，行扫描线增加了一倍，同时数据线减少了一倍，相应的，栅极驱动电路400中的集成芯片数量会增加一倍，而源极驱动电路500中集成芯片的数量可以减少一半，由于源极驱动电路500中集成芯片的造价成本远高于栅极驱动芯片中集成芯片的造价成本，因此采用双栅像素驱动结构（Dual-gate）可以有效的降低显示装置的生产成本。
相较于1G1D结构，双栅像素驱动结构（Dual-gate）中，行写入时间会下降为原来的一半，而在液晶显示面板的设计中，考量像素驱动结构的重要因素即确保像素具备充足的像素充电率，而行写入时间的缩短会影响到像素充电率降低，为了保证像素充电率高，面板的画质良好，显示面板通常会搭配1+2 line或2 line反转方式来驱动像素阵列中电容的极性反转。
由于显示面板100在采用2 line或者1+2 line极性反转方式来驱动像素阵列中的电容极性反转时，在公共电极电位保持不变的情况下，实现液晶分子的交流驱动就相当于电容的另外一个电极的电位相对于公共电极电位时高时低的变化。也即源极驱动电路500输出的数据信号相对公共电极电压升高或者降低。而在数据信号电压相对公共电极电压升高由负极性的电压切换为正极性的电压，或者降低来实现由正极性电压切换为负极性的过程中，数据信号电压的跨压比较大，且因为RC负载的原因，电压切换需要爬坡时间。因此在充电时间一定的情况下，需要经历电压切换即爬坡时间的子像素的充电率要低于电压趋于平稳的子像素的充电率，也即前者的像素充电饱和程度要小于后者的饱和程度，而充电饱和的像素的亮度要大于充电不完全饱和的像素。例如在本实施例显示面板100中，相邻的奇数列薄膜晶体管和偶数列薄膜晶体管与同一条所述数据线电连接，且相邻的奇数列薄膜晶体管和偶数列薄膜晶体管的栅极分别由相邻的两条扫描线控制。例如位于第一行第一列的色子像素和位于第一行第二列的子像素。位于第一行第一列的子像素的栅极与扫描线G1连接，源极与数据线D2连接，位于第一行第二列的子像素的栅极与扫描线G2连接，源极与数据线D2连接。该相邻的两个子像素在采用2Line Inversion (2行画素行线信号反转）方式进行极性反转时，两者的极性是一致的，或者采用l+2Line Inversion (1+2行画素行线信号反转)方式进行极性反转时，扫描线的第一行为单独极性，其余扫描行中相邻的两个子像素的极性相同。本实施例以2Line Inversion (2行画素行线信号反转）方式为例进行说明。栅极驱动电路420在进行逐行扫描时，G1行扫描线先打开，G2行扫描线后打开；在l+2Line Inversion (1+2行画素行线信号反转)方式中，则是G2行扫描线先打开，G3行扫描线后打开），第一行第一列的色子像素的极性从正极反转为负极，在第一行第一列的色子像素充电过程中，数据线D2上的数据电压会由高电平逐渐降低为低电平，也即由正极切换为负极并保持低电平，此时数据信号的电压跨压较大，在第一行第一列的色子像素充电完成时，并未充电饱和。在第一行第一列的色子像素完成充电后，G1行扫描线关断，G2行扫描线打开，从而给第一行第二列的子像素充电，而给第一行第二列的子像素充电的过程中，数据线D2上的数据电压是保持为低电平的，相当于有负极切换为负极，此时，数据信号的电压跨压较小或者没有跨压，因此在蓝色子像素充电完成时，饱和程度较高。这样，将导致第一行第二列的色子像素的亮度要高于第一行第一列的色子像素的亮度，以此类推，在整个液晶面板上将出现亮/暗线的问题。
为了解决上述问题，参照图1及图2，在本申请一实施例中，该显示面板的驱动电路包括：
栅极驱动电路420，设置为接收所述驱动电源300的栅极开启电压Vgh而驱动显示面板100中对应的奇数行和，
削角电路410，所述削角电路410，设置为在接收到第一时序控制信号时，对所述驱动电源300输出至所述栅极驱动电路420的栅极开启电压Vgh进行削角降压，以控制奇数行子像素的电容充电电压为第一预设电压；在接收到第二时序控制信号时，对所述驱动电源300输出至所述栅极驱动电路420的栅极开启电压Vgh进行削角降压，以控制偶数行子像素的电容充电电压等于所述第一预设电压。
本实施例中，驱动电源300的输出端与栅极驱动电路420和削角电路410的输入端连接，时序控制器200的控制端分别与削角电路410的受控端和栅极驱动电路420的受控端连接。奇数行扫描线为G1、G3、G5…G2n+1，偶数行扫描线为G2、G4、G6…G2n+2。栅极驱动电路420基于时序控制器200输出的帧起始信号（Start Vertical，STV）、扫描时钟脉冲信号（Clock Pulse Vertical，CPV）及使能信号（Output Enable，OE）的控制，并在驱动电源300输出栅极开启电压Vgh时，通过各行扫描线，驱动开关阵列G1行中至G2n+2行的对应的薄膜晶体管逐行开启，在时序控制器200输出的控制信号的作用下与数据驱动集成电路配合，实现开启行的数据信号输入到相应的像素中，以及在驱动电源300输出关断电压时，驱动开关阵列中对应的薄膜晶体管关断。在栅极驱动电路420驱动开关阵列逐行一次开启时，所有的列数据信号线传输数据信号到该行子像素中，给子像素电容充电，实现该像素的信号电压写入并保持，子像素区的液晶分子在该电压下旋转，使通过液晶分子的入射光的透过率发生改变，即实现对入射光的光阀作用。
削角电路410在接收到所述时序控制器200输出的所述第一时序控制信号对所述栅极开启电压Vgh进行削角降压；以控制相邻两行中的前一行子像素的电容充电电压为第一预设电压；在接收到所述第二时序控制信号时，对所述驱动电源300输出至所述栅极驱动电路420的栅极开启电压Vgh进行削角降压，以控制相邻两行中的后一行子像素的电容充电电压等于所述第一预设电压。其中，所述第一时序控制信号和所述第二时序控制信号均为高低电平交替变化的方波信号，并且削角电路410在所述第一时序控制信号和所述第二时序控制信号的方波信号为高电平H时开始削角，在所述第一时序控制信号和所述第二时序控制信号的方波信号为低电平时停止削角。
本申请在时序控制器200输出控制信号至栅极驱动电路420，并在驱动电源300输出栅极开启电压Vgh至栅极驱动电路420驱动栅极驱动电路420工作时，时序控制器200分别输出第一时序控制信号和第二时序控制信号至削角电路410，以控制削角电路410对该栅极开启电压Vgh进行削角降压。从而在栅极驱动电路420经行扫描线输出对应的行扫描信号至薄膜晶体管以实现从扫描线的第一行扫描线至最后一行扫描线逐行依次开启的过程中，控制调节相邻两行中的前一行扫描线对应的薄膜晶体管的导通程度大于相邻两行中的后一行扫描线对应的薄膜晶体管的导通程度。进而使得各相邻两行中的前一行的扫描线上输出的行驱动电压波形的削角斜率小于与之相邻的行扫描线上输出的行驱动电压波形的削角斜率，以实现相邻两行中的前一行薄膜晶体管的开启面积大于与之相邻的薄膜晶体管的开启面积，即提高相邻两行中的前一行扫描线对应的子像素的充电效率，来补偿因电压切换爬坡损失掉的时间。从而使相邻两行中的前一行扫描线对应的子像素的充电效率与偶数行扫描线对应的子像素的充电效率一致。如此设置，有利于数据信号的电压从正极性切换至负极性，或者从负极性切换至正极性时，保证每一子像素的充电效果相同，且亮度一致。本申请解决了数据信号电压在极性反转时，由于跨压比较大，导致共用一数据线的两相邻子像素之间的充电饱和程度存在差异而出现低灰阶亮暗线的问题，本申请提高了显示装置的画面品质。
可以理解的是，在l+2Line Inversion (1+2行画素行线信号反转)方式进行极性反转时，栅极驱动电路420经行扫描线输出对应的行扫描信号至开关阵列进行扫描时，扫描线的第二行称之为相邻两行中的前一行扫描线（或者称之为奇数行），第三行称之为相邻两行中的后一行（或者称之为偶数行），以此类推，直至扫描至显示面板的最后一行，其削角过程与2Line Inversion (2行画素行线信号反转)方式进行极性反转时相同，此处不再赘述。
参照图1及图2，在一优选实施例中，所述削角电路410包括第一削角电阻R1、第二削角电阻R2、第一开关管Q1及第二开关管Q2，所述第一削角电阻R1的第一端为所述削角电路410的输入端，并与所述第二削角电阻R2的第一端连接，所述第一削角电阻R1的第二端分别与所述第一开关管Q1的输入端及所述第二开关管Q2的输出端互连，所述第一开关管Q1的输出端接地，所述第一开关管Q1的受控端为所述第一削角电路410的第一受控端；所述第二削角电阻R2的第二端与所述第二开关管Q2的输入端连接，所述第二开关管Q2的受控端为所述削角电路410的第二受控端。
本实施例中，第一开关管Q1和所述第一开关管Q1可以采用MOSFET（绝缘栅场效应管）、TFT（薄膜晶体管）、三极管、IGBT（Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管）等开关管来实现，本实施例中第一开关管Q1和所述第一开关管Q1优选为N-MOSFET（N型绝缘栅场效应管）。第一削角电阻R1和第二削角电阻R2均为放电电阻，并且当第一开关管Q1接收到时序控制器200输出的高电平的第一时序控制信号时，第一削角电阻R1对当前驱动电源300输出至栅极驱动电路420的栅极开启电压Vgh进行第一削角降压。可以理解的是，第一削角电阻R1为分压电阻，第一削角电阻R1与栅极驱动电路420相当于串联分压，通过调节第一削角电阻R1的电阻阻值来调节第一削角电阻R1端电压与输出至栅极驱动电路420的栅极开启电压Vgh的分压比，从而调节栅极驱动电路420的栅极开启电压Vgh的电压值，以实现调节栅极驱动电路420对应开启行的薄膜晶体管充电效率。
当第二开关管Q2接收到时序控制器200输出的高电平的第二时序控制信号且第一开关管Q1接收到时序控制器200输出的高电平的第一时序控制信号时，第二削角电阻R2和第一削角电阻R1并联设置，以对当前驱动电源300输出至栅极驱动电路420的栅极开启电压Vgh进行第二削角降压。此时并联设置的第一削角电阻R1和第二削角电阻R2为分压电阻，根据电阻并联，阻值减小的定律，第一削角电阻R1和第二削角电阻R2的总的电阻值减小。根据串联分压原理，第一削角电阻R1和第二削角电阻R2的总电阻值越小，其所分得的电压也就越大，此时输出至栅极驱动电路420的栅极开启电压Vgh的电压值就越小，从而实现调节栅极驱动电路420对应开启行的薄膜晶体管充电效率。综上所述，第一削角电阻R1的放电程度小于第一削角电阻R1与第二削角电阻R2并联设置时的放电程度。因此本实施例可以在栅极驱动电路420驱动奇数行扫描线上对应的薄膜晶体管开启时，通过时序控制器200输出高电平的第一时序控制信号控制第一开关管Q1导通，从而使第一削角电阻R1对当前输出至栅极驱动电路420的栅极开启电压Vgh进行分压放电。在栅极驱动电路420驱动各扫描线上对应的薄膜晶体管开启时，通过时序控制器200输出两个不同高电平的第二时序控制信号分别控制第一开关管Q1和第二开关管Q2同时导通，从而使第一削角电阻R1和第二削角电阻R2并联设置，并对当前输出至栅极驱动电路420的栅极开启电压Vgh进行分压放电，以使前一行的削角斜率小于后一行的削角斜率，进而实现前一行的开启面积大于G2n+2行的开启面积，即提高前一行的充电效率，来补偿因电压切换爬坡损失掉的时间，从而使前一行的充电效率与后一行的充电效率一致。最终使得在2line 反转的方式中G1、G3、G5…G2n+1等前一行扫描线上对应的子像素和G2、G4、G6…G2n+2等后一行扫描线上对应的子像素的充电效率相同，（在1+2line 反转的方式中，则是G2、G4、G6…G2n等前一行扫描线上对应的子像素和G3、G5…G2n+1后一行扫描线上对应的子像素充电效率相同）。从而实现显示装置整个显示面板上各子像素的亮度一致，以解决子像素之间由于充电饱和程度不同而出现亮/暗线的问题。
参照图1及图2，上述实施例中，所述第一削角电阻R1的数量为多个，多个所述第一削角电阻R1并联设置。
本实施例中，可以理解的是，第一削角电阻R1的数量可以是一个也可以是多个，本实施例优选为两个，且分别标记为第一削角电阻R1A和第一削角电阻R1B，第一削角电阻R1A和第一削角电阻R1B并联设置。第一开关管Q1导通时，第一削角电阻R1A和第一削角电阻R1B的总削角电阻为R1A*R1B/（R1A+R1B）。第一开关管Q1和第二开关管Q2同时导通时，第一削角电阻R1A、第一削角电阻R1B以及第二削角电阻R2的总削角电阻为（R1A*R1B*R2/（R1A*R1B+R1A*R2+R1B*R2）。如此设置，使得在不同行扫描线对应的薄膜晶体管开启时，控制对应的行扫描线上的栅极开启电压Vgh削角斜率不同，有利于提高各行扫描线对应的子像素亮度一致性。
可以理解的是，由于在本申请显示装置中使用了上述显示面板的驱动电路，因此，本申请显示装置的实施例包括上述显示面板的驱动电路全部实施例的全部技术方案，且所达到的技术效果也完全相同，在此不再赘述。
本申请还提出一种显示面板的驱动方法，参照图5，该方法包括：
步骤S1、接收到第一时序控制信号时，对接收的栅极开启电压进行削角降压，以控制相邻两行中的前一行子像素的电容充电电压为第一预设电压；
步骤S2、接收到第二时序控制信号时，对接收的栅极开启电压进行削角降压，以控制相邻两行中的后一行子像素的电容充电电压等于所述第一预设电压。
可以理解的是，在执行步骤S1之前，可以先执行步骤S2，本领域技术人员可以根据削角电路以及采用的极性反转类型进行设置，以实现在对像素电容进行充电时，相邻的两行像素电容的充电率一致，此处不做限制。
其中，所述对输出至栅极驱动电路的栅极开启电压进行削角降压具体包括：
根据接收的所述第一时序控制信号或者所述第二时序控制信号，对输出至栅极驱动电路的栅极开启电压进行不同等级分压，以对所述栅极开启电压进行削角降压。
所述第一时序控制信号和所述第二时序控制信号均为高低电平交替变化的方波信号，并且在所述第一时序控制信号和所述第二时序控制信号的方波信号为高电平H时开始削角，在所述第一时序控制信号和所述第二时序控制信号的方波信号为低电平时停止削角。
本申请在时序控制器输出控制信号至栅极驱动电路，并在驱动电源输出栅极开启电压至栅极驱动电路驱动栅极驱动电路工作时，时序控制器分别输出第一时序控制信号和第二时序控制信号至削角电路，以控制削角电路对该栅极开启电压进行削角降压，从而在栅极驱动电路经行扫描线输出对应的行扫描信号至薄膜晶体管以实现从扫描线的第一行扫描线至最后一行为的偶数行扫描线逐行依次开启的过程中，控制调节两行中的前一行扫描线对应的薄膜晶体管的导通程度大于两行中的前一行扫描线对应的薄膜晶体管的导通程度，进而使得前一行的扫描线上输出的行驱动电压波形的削角斜率小于与之相邻的后一行扫描线上输出的行驱动电压波形的削角斜率，以实现前一行对应的薄膜晶体管的开启面积大于与之相邻的后一行薄膜晶体管的开启面积，即提高前一行扫描线对应的子像素的充电效率，来补偿因电压切换爬坡损失掉的时间，从而使前一行扫描线对应的子像素的充电效率与偶数行扫描线对应的子像素的充电效率一致。如此设置，有利于数据信号的电压从正极性切换至负极性，或者从负极性切换至正极性时，保证每一子像素的充电效果相同，且亮度一致。本申请解决了数据信号电压在极性反转时，由于跨压比较大，导致共用一数据线的两相邻子像素之间的充电饱和程度存在差异而出现低灰阶亮暗线的问题，本申请提高了显示装置的画面品质。
以上所述仅为本申请的优选实施例，并非因此限制本申请的专利范围，凡是在本申请的申请构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (19)

  1. 一种显示面板的驱动电路，所述显示面板具有多个子像素；其中，该显示面板的驱动电路包括：
    时序控制器，设置为输出第一时序控制信号和第二时序控制信号；
    驱动电源，设置为输出栅极开启电压和/或栅极关断电压；
    栅极驱动电路，设置为接收所述驱动电源的栅极开启电压而驱动对应行子像素；
    削角电路，设置为在接收到所述第一时序控制信号时，对所述驱动电源输出至所述栅极驱动电路的栅极开启电压进行削角降压，以控制相邻两行中的前一行子像素的电容充电电压为第一预设电压；在接收到所述第二时序控制信号时，对所述驱动电源输出至所述栅极驱动电路的栅极开启电压进行削角降压，以控制相邻两行中的后一行子像素的电容充电电压等于所述第一预设电压。
  2. 如权利要求1所述的显示面板的驱动电路，其中，所述削角电路包括第一削角电阻、第二削角电阻、第一开关管及第二开关管，所述第一削角电阻的第一端为所述削角电路的输入端，并与所述第二削角电阻的第一端连接，所述第一削角电阻的第二端分别与所述第一开关管的输入端及所述第二开关管的输出端互连，所述第一开关管的输出端接地，所述第一开关管的受控端为所述第一削角电路的第一受控端；所述第二削角电阻的第二端与所述第二开关管的输入端连接，所述第二开关管的受控端为所述削角电路的第二受控端。
  3. 如权利要求2所述的显示面板的驱动电路，其中，所述第一削角电阻的数量为多个，多个所述第一削角电阻并联设置。
  4. 如权利要求2所述的显示面板的驱动电路，其中，所述第一开关管和/或所述第一开关管为N-MOS管。
  5. 如权利要求2所述的显示面板的驱动电路，其中，所述第一开关管和/或所述第一开关管为三极管。
  6. 如权利要求2所述的显示面板的驱动电路，其中，所述第一开关管和/或所述第一开关管为IGBT（Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管）。
  7. 一种显示装置，包括具有多个子像素的显示面板、时序控制器及驱动电源，所述时序控制器，设置为输出第一时序控制信号和第二时序控制信号；其中，所述显示装置还包括显示面板的驱动电路；所述显示面板的驱动电路包括：
    栅极驱动电路，设置为接收所述驱动电源的栅极开启电压而驱动双栅像素驱动结构中对应行的子像素工作；
    削角电路，设置为在接收到所述第一时序控制信号时，对所述驱动电源输出至所述栅极驱动电路的栅极开启电压进行削角降压，以控制当前行子像素的电容充电电压为第一预设电压；在接收到所述第二时序控制信号时，对所述驱动电源输出至所述栅极驱动电路的栅极开启电压进行削角降压，以控制偶数行子像素的电容充电电压等于所述第一预设电压。
  8. 如权利要求7所述的显示装置，其中，所述双栅像素驱动结构包括开关阵列；所述显示面板的驱动电路还包括多条数据线及与所述栅极驱动电路电连接的多条扫描线，所述开关阵列包括多个薄膜晶体管，各行中奇数列的所述薄膜晶体管分别与奇数行的所述扫描线的连接，各行中偶数列的所述薄膜晶体管分别与偶数行的所述扫描线的电连接连接，相邻的奇数列薄膜晶体管和偶数列薄膜晶体管与同一条所述数据线电连接。
  9. 如权利要求7所述的显示装置，其中，所述双栅像素驱动结构包括开关阵列；所述显示面板的驱动电路还包括多条数据线及与所述栅极驱动电路电连接的多条扫描线，所述开关阵列包括多个薄膜晶体管，各行中奇数列的所述薄膜晶体管分别与偶数行的所述扫描线的连接，各行中偶数列的所述薄膜晶体管分别与奇数行的所述扫描线的电连接连接，相邻的奇数列薄膜晶体管和偶数列薄膜晶体管与同一条所述数据线电连接。
  10. 如权利要求7所述的显示装置，其中，所述开关阵列的极性反转方式为1+2行画素行线信号反转。
  11. 如权利要求7所述的显示装置，其中，所述开关阵列的极性反转方式为2行画素行线信号反转。
  12. 如权利要求7所述的显示装置，其中，所述削角电路包括第一削角电阻、第二削角电阻、第一开关管及第二开关管，所述第一削角电阻的第一端为所述削角电路的输入端，并与所述第二削角电阻的第一端连接，所述第一削角电阻的第二端分别与所述第一开关管的输入端及所述第二开关管的输出端互连，所述第一开关管的输出端接地，所述第一开关管的受控端为所述第一削角电路的第一受控端；所述第二削角电阻的第二端与所述第二开关管的输入端连接，所述第二开关管的受控端为所述削角电路的第二受控端。
  13. 如权利要求12所述的显示装置，其中，所述第一削角电阻的数量为多个，多个所述第一削角电阻并联设置。
  14. 如权利要求7所述的显示面板的驱动电路，其中，所述第一开关管和/或所述第一开关管为N-MOS管。
  15. 如权利要求7所述的显示装置，其中，多条所述扫描线包括奇数行扫描线和偶数行扫描线。
  16. 如权利要求7所述的显示装置，其中，显示装置还包括源极驱动电路，所述时序控制器分别与所述栅极驱动电路、所述源极驱动电路以及所述驱动电源连接。
  17. 如权利要求7所述的显示装置，其中，所述驱动电源集成有多个不同电路功能的直流-直流转换电路，每个所述直流-直流转换电路输出不同的电压值。
  18. 一种显示面板的驱动方法，所述显示面板包括多个子像素，其中，所述显示面板的栅极驱动方法包括：
    接收到第一时序控制信号时，对接收的栅极开启电压进行削角降压，以控制相邻两行中的前一行子像素的电容充电电压为第一预设电压；
    接收到第二时序控制信号时，对接收的栅极开启电压进行削角降压，以控制相邻两行中的后一行子像素的电容充电电压等于所述第一预设电压。
  19. 如权利要求18所述的显示面板的驱动方法，其中，所述对输出至栅极驱动电路的栅极开启电压进行削角降压具体包括：
    根据接收的所述第一时序控制信号或者所述第二时序控制信号，对输出至栅极驱动电路的栅极开启电压进行不同等级分压，以对所述栅极开启电压进行削角降压。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109584840B (zh) * 2019-01-30 2020-12-29 惠科股份有限公司 显示面板的驱动方法及装置
CN110767191A (zh) * 2019-10-24 2020-02-07 深圳市华星光电半导体显示技术有限公司 一种液晶显示面板的像素驱动电路结构
CN111243484A (zh) * 2020-02-25 2020-06-05 福建华佳彩有限公司 一种消除直纹的双栅极面板的驱动方法
CN112068341A (zh) * 2020-09-17 2020-12-11 南京中电熊猫液晶显示科技有限公司 一种液晶显示面板及其改善横纹不良的方法
CN113299249A (zh) * 2021-05-27 2021-08-24 惠科股份有限公司 一种液晶显示装置及其驱动方法
CN114495800B (zh) * 2022-03-07 2023-12-26 北京京东方显示技术有限公司 显示面板的驱动方法及显示装置
CN117079615B (zh) * 2023-10-12 2024-01-09 惠科股份有限公司 显示面板和显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100315322A1 (en) * 2009-06-15 2010-12-16 Hsiao-Chung Cheng Liquid crystal display and driving method thereof
CN102129845A (zh) * 2010-01-14 2011-07-20 群康科技(深圳)有限公司 液晶面板驱动电路和液晶显示装置
CN103247280A (zh) * 2013-05-14 2013-08-14 深圳市华星光电技术有限公司 削角电路及其控制方法
CN104317086A (zh) * 2014-11-14 2015-01-28 深圳市华星光电技术有限公司 一种用于驱动液晶显示面板的方法
CN106128398A (zh) * 2016-08-31 2016-11-16 深圳市华星光电技术有限公司 栅极电压驱动装置、方法、驱动电路以及液晶显示面板

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101315749B (zh) * 2008-06-26 2010-06-16 上海广电光电子有限公司 液晶显示器的驱动方法
CN102360542B (zh) * 2011-09-28 2013-03-13 青岛海信电器股份有限公司 液晶显示器的控制方法和装置及液晶显示器和电视机
CN104575410B (zh) * 2013-10-18 2018-12-28 联咏科技股份有限公司 省电方法及其相关液晶显示器
CN105070243B (zh) * 2015-09-15 2017-10-31 重庆京东方光电科技有限公司 栅极开启电压补偿电路、显示面板、驱动方法及显示装置
CN106558288B (zh) * 2015-09-25 2019-08-09 天钰科技股份有限公司 栅极驱动电路、显示装置与门极脉冲调变方法
CN105206248B (zh) * 2015-11-09 2019-07-05 重庆京东方光电科技有限公司 显示驱动电路、显示装置和显示驱动方法
CN107402486B (zh) * 2017-08-31 2020-06-30 京东方科技集团股份有限公司 阵列基板及其驱动方法、显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100315322A1 (en) * 2009-06-15 2010-12-16 Hsiao-Chung Cheng Liquid crystal display and driving method thereof
CN102129845A (zh) * 2010-01-14 2011-07-20 群康科技(深圳)有限公司 液晶面板驱动电路和液晶显示装置
CN103247280A (zh) * 2013-05-14 2013-08-14 深圳市华星光电技术有限公司 削角电路及其控制方法
CN104317086A (zh) * 2014-11-14 2015-01-28 深圳市华星光电技术有限公司 一种用于驱动液晶显示面板的方法
CN106128398A (zh) * 2016-08-31 2016-11-16 深圳市华星光电技术有限公司 栅极电压驱动装置、方法、驱动电路以及液晶显示面板

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