WO2021238643A1 - 电压供给电路、显示驱动电路、显示装置和显示驱动方法 - Google Patents

电压供给电路、显示驱动电路、显示装置和显示驱动方法 Download PDF

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Publication number
WO2021238643A1
WO2021238643A1 PCT/CN2021/093003 CN2021093003W WO2021238643A1 WO 2021238643 A1 WO2021238643 A1 WO 2021238643A1 CN 2021093003 W CN2021093003 W CN 2021093003W WO 2021238643 A1 WO2021238643 A1 WO 2021238643A1
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Prior art keywords
coupled
terminal
voltage
signal
diode
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PCT/CN2021/093003
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English (en)
French (fr)
Inventor
梁云云
周留刚
戴珂
何浏
孙建伟
汪俊
李清
权宇
Original Assignee
京东方科技集团股份有限公司
合肥京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/778,125 priority Critical patent/US11847991B2/en
Publication of WO2021238643A1 publication Critical patent/WO2021238643A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display, and in particular to a voltage supply circuit, a display driving circuit, a display device, and a display driving method.
  • the column inversion or frame inversion is generally used for driving; in order to prevent the long-term single polarity change law from causing a large accumulation of bias in the pixel unit After image is caused by voltage, the polarity change rule is generally adjusted periodically, that is, the polarity reversal is adjusted.
  • one inversion adjustment period includes an even number of frames, and the polarity of the signal of the same pixel unit in adjacent frames in each inversion adjustment period is opposite (for example, using column inversion or frame inversion).
  • the adjacent inversion adjustment period any pixel unit in the last frame of the previous inversion adjustment period and the signal pole of the pixel unit in the first frame of the subsequent inversion adjustment period The same sex.
  • one inversion adjustment period will cause the pixel unit to accumulate a positive bias voltage
  • the other inversion adjustment period will cause the pixel unit to accumulate a negative bias voltage, which is a positive bias.
  • the set voltage and the negative bias voltage can cancel each other out.
  • the pixel The liquid crystal molecules in the cell keep deflecting in the same direction, and in the first frame of the subsequent inversion adjustment period, the deflection angle of the liquid crystal molecules is larger, which is represented by the brightness of the pixel unit in the first frame of the subsequent inversion adjustment period Bigger.
  • the deflection angle of the liquid crystal molecules is larger, which is represented by the brightness of the pixel unit in the first frame of the subsequent inversion adjustment period Bigger.
  • embodiments of the present disclosure provide a voltage supply circuit, including: a power management integrated circuit, a transmission branch, a step-down branch, a signal output terminal of the power management integrated circuit, and a signal of the transmission branch
  • the input end and the signal input end of the step-down branch are coupled to a first node, and the signal output end of the transmission branch and the signal output end of the step-down branch are coupled to a second node;
  • the power management integrated circuit is configured to provide an initial voltage to the first node
  • the transmission branch is coupled to the control signal terminal, has an on state and an off state, and is configured to respond to the control of the control signal provided by the control signal terminal. Switching between, and writing the initial voltage at the first node to the second node when in the on state;
  • the step-down branch is configured to perform step-down processing on the initial voltage at the first node to obtain a step-down voltage, and to reduce the step-down voltage when the transmission branch is in the disconnected state Write to the second node.
  • the voltage supply circuit further includes: a state control circuit, the signal output terminal of the state control circuit is coupled to the control signal terminal;
  • the state control circuit is configured to provide a first control signal for a preset duration to the control signal terminal every preset period, and provide a second control signal to the control signal terminal after the preset duration ends;
  • the transmission branch is switched to the off state in response to the control of the first control signal, and the transmission branch is switched to the on state in response to the control of the second control signal.
  • the state control circuit includes a timer, a digital-to-analog conversion circuit, and a switch controller.
  • the timer is coupled to a signal input terminal of the digital-to-analog conversion circuit.
  • the signal output terminal is coupled to the signal input terminal of the switch controller, and the signal output terminal of the switch controller is coupled to the control signal terminal;
  • the timer is configured to start timing at the beginning of each preset period, send the timing result to the digital-to-analog conversion circuit as a digital signal, and reset the timing result at the end of each preset period ;
  • the digital-to-analog conversion circuit is configured to perform digital-to-analog conversion processing on the received digital signal based on a preset digital-to-analog conversion rule to obtain a corresponding analog signal, and send the analog signal to the switch controller;
  • the switch controller is configured to output the first control signal or the second control signal that matches the analog signal in response to the control of the analog signal.
  • the switch controller includes: a first resistor, a second resistor, and a first transistor;
  • a first end of the first resistor is coupled to the first node, and a second end of the first resistor is coupled to the first end of the second resistor;
  • the first end of the second resistor is coupled to the signal output end of the switch controller, and the second end of the second resistor is coupled to the first pole of the first transistor;
  • the control electrode of the first transistor is coupled to the signal input terminal of the switch controller, and the second electrode of the first transistor is coupled to the first power terminal.
  • the transmission branch includes: a second transistor and a first diode
  • the control electrode of the second transistor is coupled to the control signal terminal, the first electrode of the second transistor is coupled to the first node, and the second electrode of the second transistor is coupled to the first node.
  • the first end of the pole tube is coupled, and the second end of the first diode is coupled to the second node.
  • the step-down branch includes: a low-dropout linear regulator and a second diode;
  • the signal input end of the low dropout linear regulator is coupled to the signal input end of the step-down branch, and the signal output end of the low dropout linear regulator is connected to the first end of the second diode Coupling
  • the second end of the second diode is coupled to the signal output end of the step-down branch.
  • the low-dropout linear regulator includes: a low-dropout linear regulator chip and a peripheral circuit
  • the peripheral circuit includes: a first sliding rheostat, a third resistor, a third diode, and a second Pole tube and first capacitor;
  • the control terminal of the first sliding rheostat is coupled to the second power terminal, the first terminal of the first sliding rheostat is coupled to the output voltage adjustment terminal of the low dropout linear regulator chip, the first sliding rheostat The second end of the floating connection;
  • the first end of the third resistor is coupled to the output voltage adjustment end of the low dropout linear regulator chip, and the second end of the third resistor is coupled to the signal output end of the low dropout linear regulator chip ;
  • the first end of the third diode is coupled to the output voltage adjustment end of the low dropout linear regulator chip, and the second end of the third diode is connected to the signal of the low dropout linear regulator chip The output terminal is coupled;
  • the first end of the fourth diode is coupled to the signal output end of the low dropout linear regulator chip, and the first end of the fourth diode is connected to the signal of the low dropout linear regulator chip.
  • the input terminal is coupled;
  • the first terminal of the first capacitor is coupled to the signal output terminal of the low dropout linear regulator chip, and the second terminal of the first capacitor is coupled to the second power terminal.
  • the step-down branch includes: a third transistor, a second sliding varistor, a third sliding varistor, and a second diode;
  • the control electrode of the third transistor is coupled to the control terminal of the second sliding varistor and the first terminal of the third sliding varistor, and the first electrode of the third transistor is connected to the signal of the step-down branch
  • the input terminal is coupled, and the second electrode of the third transistor is coupled to the first terminal of the second diode;
  • the second end of the second diode is coupled to the signal output end of the step-down branch
  • the first end of the second sliding rheostat is coupled to the signal input end of the step-down branch, and the second end of the second sliding rheostat is floating;
  • the control end of the third sliding rheostat is coupled to the second power source, and the second end of the third sliding rheostat is floating;
  • the second end of the second diode is coupled to the signal output end of the step-down branch.
  • the step-down branch includes: a fourth resistor, a fifth resistor, a Zener tube, a fourth sliding rheostat, a second capacitor, and a second diode;
  • the first end of the fourth resistor is coupled to the input end of the step-down branch, and the second end of the fourth resistor is coupled to the first end of the second diode;
  • the first end of the fifth resistor is coupled to the first end of the second diode, and the second end of the fifth resistor is coupled to the first end of the fourth sliding varistor;
  • the control terminal of the fourth sliding rheostat is coupled to the second power terminal, the first terminal of the fourth sliding rheostat is coupled to the reference signal supply terminal of the voltage regulator tube, and the second terminal of the fourth sliding rheostat is coupled to the reference signal supply terminal of the voltage regulator tube.
  • the first pole of the voltage regulator tube is coupled to the second power supply terminal, and the second pole of the voltage regulator tube is coupled to the first terminal of the second diode;
  • the first end of the second capacitor is coupled to the second pole of the Zener tube, and the second end of the second capacitor is coupled to the reference signal supply end of the Zener tube;
  • the second end of the second diode is coupled to the signal output end of the step-down branch.
  • the voltage supply circuit further includes: a level conversion circuit, a signal input end of the level conversion circuit is coupled to the second node, and the level conversion circuit is configured to The signal at the two nodes undergoes level conversion processing.
  • embodiments of the present disclosure also provide a display driving circuit, including: a gate driving circuit and the voltage supply circuit provided in the above first aspect, the signal output terminal of the voltage supply circuit and the gate driving circuit The working voltage input terminal configured by the circuit is coupled.
  • an embodiment of the present disclosure also provides a display device, including: the display driving circuit provided in the above-mentioned second aspect.
  • embodiments of the present disclosure also provide a display driving method based on the display driving circuit provided in the second aspect, and the display driving method includes:
  • the voltage supply circuit provides the first operating voltage to the operating voltage input terminal configured by the gate driving circuit;
  • the voltage supply circuit provides a second operating voltage to the operating voltage input terminal configured by the gate driving circuit, the first operating voltage Less than the second working voltage.
  • Figure 1 is a schematic diagram of the polarity of the charging voltage and the deflection angle of the liquid crystal when a pixel unit in a display device in the related art reverses its polarity;
  • FIG. 2 is a schematic structural diagram of a display device provided by an embodiment of the disclosure.
  • FIG. 3 is a flowchart of a display driving method provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of the polarity of the charging voltage and the deflection angle of the liquid crystal when a pixel unit in the display device in the embodiment of the disclosure performs polarity inversion;
  • FIG. 5 is a schematic diagram of a circuit structure of a voltage supply circuit provided by an embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of another circuit structure of a voltage supply circuit provided by an embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of a circuit structure of a switch controller and a transmission branch in an embodiment of the disclosure.
  • FIG. 8 is a schematic diagram of a circuit structure of a step-down branch in an embodiment of the disclosure.
  • FIG. 9 is a schematic diagram of another circuit structure of the step-down branch in the embodiment of the disclosure.
  • FIG. 10 is a schematic diagram of another circuit structure of the step-down branch in the embodiment of the disclosure.
  • Each transistor involved in the embodiments of the present disclosure may be independently selected from one of polysilicon thin film transistors, amorphous silicon thin film transistors, oxide thin film transistors, and organic thin film transistors.
  • the “control electrode” referred to in the present disclosure specifically refers to the gate of the transistor, the “first electrode” specifically refers to the source of the transistor, and correspondingly, the “second pole” specifically refers to the drain of the transistor.
  • the “first pole” and the "second pole” can be interchanged.
  • transistors can be divided into N-type transistors and P-type transistors, and each transistor in the present disclosure can be independently selected from N-type transistors or P-type transistors.
  • Figure 1 is a schematic diagram of the polarity of the charging voltage and the deflection angle of liquid crystal when a pixel unit in a display device in the related art reverses its polarity. Under the screen, the last 4 frames of the previous reversal adjustment period (N frame to N+3 frame in the figure) and the first 4 frames of the next reversal adjustment period (N+4 frame to N+7 frame in the figure) Condition.
  • the charging voltages loaded by the pixel unit are -V0, +V0, -V0, +V0, and the extremes of the charging voltage The sex presents negative (-), positive (+), negative (-), and positive (+); in the first four frames of the next inversion adjustment cycle (that is, frames N+4 to N+7 in the figure), the pixel
  • the charging voltage loaded by the unit is +V0, -V0, +V0, -V0, and the polarity of the charging voltage is positive (+), negative (-), positive (+), and negative (-).
  • the polarity of the charging voltage applied by the pixel unit in the first frame of the subsequent inversion adjustment cycle is the same as that of the last frame of the previous inversion adjustment cycle (ie N+4 frame in the figure). +3 frame) the polarity of the applied charging voltage is the same.
  • the deflection angle of the liquid crystal molecules corresponding to the pixel unit in the N+4 frame is greater than the deflection angle in the N+3 frame (also known as the "overdrive effect"), that is, the pixel unit is in The luminous brightness in the N+4 frame will be greater than the luminous brightness in the N+3 frame.
  • the technical solution of the present disclosure provides a voltage supply circuit, a display driving circuit, a display device, and a display driving method.
  • FIG. 2 is a schematic structural diagram of a display device provided by an embodiment of the disclosure.
  • the display device includes: a liquid crystal display panel and a display driving circuit, wherein the display driving circuit includes: a voltage supply circuit 1 and a gate driving circuit 2 .
  • the gate driver circuit 2 is formed on the array substrate of the liquid crystal display panel (Gate driver On Array, GOA) by an Array process, and the signal output terminal of the voltage supply circuit 1 and the gate driver circuit 2 are configured The working voltage input terminal is coupled.
  • the voltage supply circuit 1 can provide a working voltage to the working voltage input terminal of the gate driving circuit 2, and the working voltage input terminal transmits the received working voltage to the various shifts in the gate driving circuit 2.
  • Register Shift Register
  • the switching transistor M in the pixel unit electrically coupled to the gate line Gate will be in a conducting state, and the data voltage in the data line Data The (charging voltage) is written into the corresponding pixel unit through the switch transistor M in the on state, so as to realize the driving of the pixel unit.
  • the "effective level” is relative to the type of the switching transistor M; if the switching transistor M is an N-type transistor, the “effective level” refers to a high level; if the switching transistor M is a P-type transistor, the “effective level” refers to the low level.
  • an exemplary description is made by taking the switching transistor M as an N-type transistor and the effective level as a high level as an example.
  • FIG. 3 is a flowchart of a display driving method provided by an embodiment of the disclosure. As shown in FIG. 3, the display driving method includes:
  • Step S1 In the first frame of the reversal adjustment period, the voltage supply circuit provides the first operating voltage to the operating voltage input terminal configured by the gate drive circuit, the gate drive circuit outputs the first scan signal, and the first scan signal is at The voltage in the active level state is the first working voltage; and
  • Step S2 In frames other than the first frame in the inversion adjustment period, the voltage supply circuit provides the second operating voltage to the operating voltage input terminal configured by the gate drive circuit, and the gate drive circuit outputs the second scan signal , The voltage when the second scan signal is in the effective level state is the second working voltage, and the first working voltage is smaller than the second working voltage.
  • FIG. 4 is a schematic diagram of the polarity of the charging voltage and the deflection angle of the liquid crystal when a pixel unit in the display device in the embodiment of the disclosure is inverted.
  • the embodiment of the present disclosure is schematically drawn in FIG.
  • a pixel unit is in the last 4 frames of the previous inversion adjustment period (N frame to N+3 in the figure) and in the first 4 frames of the next inversion adjustment period (N+4 frame to N+ in the figure) 7 frames).
  • the charging voltage applied by the pixel unit in the first frame of the next inversion adjustment period (ie frame N+4 in the figure) is the same as the charging voltage applied in the last frame of the previous inversion adjustment period (ie frame N+3 in the figure)
  • the charging voltages loaded in) are the same, which are all +V0.
  • the first working voltage is denoted as V1
  • the second working voltage is denoted as V2, and V1 ⁇ V2.
  • the data voltage in the gate line Gate coupled to the switch transistor M in the pixel unit is V2
  • the voltage of the data line Data coupled to the switch transistor M in the pixel unit is +V0
  • the gate-source voltage of the switch transistor M is V2-V0.
  • the voltage in the gate line Gate to which the switching transistor M in the pixel unit is coupled is V1
  • the switching transistor M in the pixel unit is coupled to the voltage V1.
  • the data voltage of the connected data line Data is +V0
  • the gate-source voltage of the switching transistor M is V1-V0, V1-V0 ⁇ V2-V0.
  • the degree of conduction of the switching transistor M determines the degree of conduction of the switching transistor M (the greater the gate-source voltage, the greater the degree of conduction of the switching transistor M), so the degree of conduction of the switching transistor M in the N+4 frame is less than that in the N+4 frame. +3 the degree of continuity in the frame. Therefore, the voltage actually applied to the pixel electrode pix of the pixel unit in the N+4 frame is less than the voltage actually applied in the N+3 frame, and the liquid crystal electric field formed by the pixel unit in the N+4 frame is smaller than that in the N+4 frame. +3 The electric field of the liquid crystal formed in the frame. As the electric field of the liquid crystal is reduced, the deflection angle of the liquid crystal molecules can be reduced, so that the overdrive effect caused by the non-polarity reversal can be compensated.
  • the amount of compensation is determined by the voltage difference between V2 and V1.
  • the sizes of V2 and V1 can be set according to pre-experiments to ensure that the pixel unit loads the same in the first frame of the next inversion adjustment period and the last frame of the previous inversion adjustment period. At the data voltage, the same display brightness can be presented.
  • the voltage supply circuit 1 can only provide the gate drive circuit 2 with a fixed operating voltage, which cannot meet the requirement of providing the "first operating voltage” and the “second operating voltage” at different times in the embodiments of the present disclosure. Therefore, the embodiment of the present disclosure also provides a voltage supply circuit 1 for this purpose.
  • FIG. 5 is a schematic diagram of a circuit structure of a voltage supply circuit provided by an embodiment of the disclosure.
  • the voltage supply circuit 1 can be used to implement the steps in the above display driving method.
  • the voltage supply circuit 1 includes: power management The integrated circuit 3, the transmission branch 4 and the step-down branch 5, the signal output end of the power management integrated circuit 3, the signal input end of the transmission branch 4 and the signal input end of the step-down branch 5 are coupled to the first node N1 , The signal output end of the transmission branch 4 and the signal output end of the step-down branch 5 are coupled to the second node N2.
  • the power management integrated circuit 3 (Power Management Integrated Circuit, PMIC for short) is configured to provide an initial voltage to the first node N1.
  • the transmission branch 4 is coupled to the control signal terminal, has an on state and an off state, and is configured to respond to the control of the control signal provided by the control signal terminal, switch between the on state and the off state, and when it is in the on state In the state, the initial voltage at the first node N1 is written to the second node N2.
  • the step-down branch 5 is configured to perform step-down processing on the initial voltage at the first node N1 to obtain the step-down voltage, and write the step-down voltage to the second node N2 when the transmission branch 4 is in the disconnected state ;
  • the voltage after step-down is less than the initial voltage.
  • the voltage difference between the initial voltage and the voltage after the step-down can be controlled by configuring the step-down branch in advance (for example, when the product is debugged).
  • the initial voltage may be the second operating voltage
  • the reduced voltage may be the first operating voltage. That is, the gate driving circuit 2 can be provided with different operating voltages through the transmission branch 4 and the step-down branch 5, respectively.
  • the voltage supply circuit 1 shown in FIG. 6 not only includes the power management integrated circuit 3 and the transmission branch shown in FIG.
  • the circuit 4 and the step-down branch 5 further include: a state control circuit 6.
  • the signal output terminal of the state control circuit 6 is coupled to the control signal terminal, and the state control circuit 6 is configured to provide a continuous preset to the control signal terminal every preset period. Set the first control signal of the duration, and provide the second control signal to the control signal terminal after the preset duration is over.
  • the transmission branch 4 switches to the off state in response to the control of the first control signal, and switches to the on state in response to the control of the second control signal.
  • the time when the transmission branch 4 is in the on state and the off state can be automatically controlled.
  • the duration of the aforementioned preset period is configured as the duration of a reversal adjustment period (for example, 28s), and the preset duration is configured as the first frame time of the reversal adjustment period, so that the voltage supply circuit 1 can be reversed.
  • the gate drive circuit 2 is automatically provided with the first operating voltage in the first frame of the adjustment period, and the gate drive circuit 2 is automatically provided with the second operating voltage in the other frames.
  • the state control circuit 6 includes a timer 7, a digital-to-analog conversion circuit 8, and a switch controller 9.
  • the timer 7 is coupled to the signal input end of the digital-to-analog conversion circuit 8, and the signal of the digital-to-analog conversion circuit 8 is
  • the output terminal is coupled to the signal input terminal of the switch controller 9, and the signal output terminal of the switch controller 9 is coupled to the control signal terminal.
  • the timer 7 is configured to start timing at the beginning of each preset period, send the timing result to the digital-to-analog conversion circuit 8 as a digital signal, and reset the timing result at the end of each preset period .
  • the timer 7 may include: a clock control circuit (Timer Control Integrated Circuit) and a counter.
  • the clock control circuit can be used to generate clock pulses, and the counter can be used to count the clock pulses generated by the clock control circuit to achieve timing. Purpose.
  • the digital-to-analog conversion circuit 8 is configured to perform digital-to-analog conversion processing on the received digital signal based on a preset digital-to-analog conversion rule to obtain a corresponding analog signal, and to send the analog signal to the switch controller 9.
  • the switch controller 9 is configured to output a first control signal or a second control signal matching the analog signal in response to the control of the analog signal.
  • the clock control circuit can be controlled to output a clock pulse every 1/60s.
  • the clock control circuit can be controlled to synchronously output the first clock pulse, and the counter counts as 1.
  • the clock control circuit synchronously outputs the second For each clock pulse, the counter counts as 2, ..., and so on.
  • the counter counts as 1680, and the counting result reaches the reset threshold, and the counter is reset.
  • the counter restarts counting.
  • the digital-to-analog conversion circuit 8 is configured to output an analog signal "1" when the counting result is 1, and to output an analog signal "0" when the counting result is not 1 (exemplarily, "1" represents a high-level signal, and "0" Represents a low-level signal).
  • the switch controller 9 is configured to output a first control signal to control the transmission branch 4 to be in a disconnected state when the analog signal "1" is received, and to output a second control signal to control the transmission branch when the analog signal "0" is received.
  • Road 4 is in a conducting state.
  • FIG. 7 is a schematic diagram of a circuit structure of the switch controller and the transmission branch in the embodiment of the disclosure.
  • the switch controller 9 includes: a first resistor R1, a second resistor R2, and a first transistor T1;
  • the first end of a resistor R1 is coupled to the first node N1, the second end of the first resistor R1 is coupled to the first end of the second resistor R2; the first end of the second resistor R2 is connected to the signal of the switch controller 9
  • the output terminal is coupled, the second terminal of the second resistor R2 is coupled to the first pole of the first transistor T1; the control pole of the first transistor T1 is coupled to the signal input terminal of the switch controller 9, and the second terminal of the first transistor T1
  • the two poles are coupled with the first power terminal.
  • the transmission branch 4 includes: a second transistor T2 and a first diode D1; the control electrode of the second transistor T2 is coupled to the control signal terminal, and the first electrode of the second transistor T2 is connected to the first node N1 is coupled, the second electrode of the second transistor T2 is coupled to the first end of the first diode D1, and the second end of the first diode D1 is coupled to the second node N2.
  • the first terminal and the second terminal of the diode refer to the anode terminal and the cathode terminal of the diode, respectively.
  • the power management integrated circuit 3 provides the initial voltage VGH as an example for description.
  • the digital-to-analog conversion circuit 8 When the digital-to-analog conversion circuit 8 outputs a high-level signal "1", the first transistor T1 is turned off, the control electrode of the second transistor T2 is in a floating state, and the voltage VGH can be fully written to the control of the second transistor T2 (Ie, the switch controller 9 provides the first control signal to the transmission branch 4), the gate-source voltage of the second transistor T2 is approximately 0, and the second transistor T2 is off, that is, the transmission branch 4 is in the off state.
  • the first transistor T1 When the digital-to-analog conversion circuit 8 outputs a high-level signal "0", the first transistor T1 is turned on, a current is formed on the first resistor R1 and the second resistor R2, and the first resistor R1 and the second resistor R2 realize voltage division.
  • the voltage applied to the control electrode of the second transistor T2 (determined by the ratio of the resistance of the first resistor R1 to the second resistor R2) is less than VGH.
  • the gate-source voltage of the second transistor T2 is less than 0, and the second transistor T2 is turned on, that is, the transmission branch 4 is in the on state.
  • FIG. 8 is a schematic diagram of a circuit structure of the step-down branch in an embodiment of the disclosure.
  • the step-down branch 5 includes: a low-dropout linear regulator and a second diode D2; the signal input end of the low dropout linear regulator is coupled to the signal input end of the step-down branch 5, and the signal output end of the low dropout linear regulator is coupled to the first end of the second diode D2; The second end of the two diodes D2 is coupled to the signal output end of the step-down branch 5.
  • the low-dropout linear regulator includes: a low-dropout linear regulator chip LDO and a peripheral circuit.
  • the peripheral circuit includes: a first sliding rheostat RP1, a third resistor R3, a third diode D3, and a fourth diode.
  • the control terminal of the first sliding rheostat RP1 is coupled to the second power terminal, the first terminal of the first sliding rheostat RP1 is coupled to the output voltage adjustment terminal of the low dropout linear regulator chip LDO, and the second terminal of the first sliding rheostat RP1 Floating; the first end of the third resistor R3 is coupled to the output voltage adjustment end of the low dropout linear regulator chip LDO, and the second end of the third resistor R3 is coupled to the signal output end of the low dropout linear regulator chip LDO; The first end of the third diode D3 is coupled to the output voltage adjustment end of the low dropout linear regulator chip LDO, and the second end of the third diode D3 is coupled to the signal output end of the low dropout linear regulator chip LDO ; The first end of the fourth diode D4 is coupled to the signal output end of the low dropout linear regulator chip LDO, and the second end of the fourth diode D4 is coupled to the signal input end of the low dropout linear regulator chip LDO
  • the step-down principle of the step-down circuit shown in Figure 8 is as follows: the first node N1 provides input voltage to the signal input terminal of the low-dropout linear regulator chip LDO, so that the low-dropout linear regulator chip LDO can work, and the low-dropout linear regulator is stable. There is a set reference voltage Vref 0 between the signal output terminal and the output voltage adjustment terminal of the piezoelectric chip LDO (the voltage difference between the signal output terminal of the LDO and the output voltage adjustment terminal is equal to the reference voltage Vref 0 , and Vref 0 is linearly stabilized by the low dropout voltage.
  • Vref 0 is set at 1V to 2V, for example, it can be 1.25V).
  • the effective resistance of the first sliding varistor RP1 in the access circuit is RP1', and the resistance of the third resistor R3 is R3', since the effective resistance of the first sliding rheostat RP1 in the access circuit is connected in series with the third resistor R3, The voltage difference between the two ends of the three resistors R3 is Vref 0. Based on the principle of series voltage division, the voltage at the signal output terminal of the LDO can be calculated as Vref 0 *(RP1'+R3')/R3'.
  • the output voltage of the signal output terminal of the low dropout linear regulator chip LDO can be adjusted, that is, the low dropout linear regulator can be adjusted.
  • the size of the voltage drop (that is, the voltage difference between the signal output terminal and the signal input terminal) is adjusted.
  • the low dropout linear voltage regulator chip LDO is a conventional device in the field, and its internal structure and working principle will not be described in detail here.
  • the third diode D3 and the fourth diode D4 are used to ensure unidirectional conduction of the circuit, and the first capacitor C1 is used to reduce noise and filter the signal output from the signal output end of the low dropout linear regulator chip LDO.
  • FIG. 9 is a schematic diagram of another circuit structure of the step-down branch in the embodiment of the disclosure.
  • the step-down branch 5 includes: a third transistor T3, a second sliding varistor RP2, The third sliding varistor RP3 and the second diode D2.
  • the control terminal of the third transistor T3 is coupled to the control terminal of the second sliding varistor RP2 and the first terminal of the third sliding varistor RP3, and the first terminal of the third transistor T3 is coupled to
  • the signal input end of the step-down branch 5 is coupled, the second pole of the third transistor T3 is coupled to the first end of the second diode D2; the second end of the second diode D2 is coupled to the step-down branch 5
  • the signal output end of the second sliding rheostat RP2 is coupled to the signal input end of the step-down branch 5, and the second end of the second sliding rheostat RP2 is floating; the control end of the third sliding rheostat RP3 is connected to The second power terminal is coupled, and the second terminal of the third sliding varistor RP3 is floating.
  • the step-down principle of the step-down circuit shown in Figure 9 is as follows: if the voltage at the first node N1 is VN1, the effective resistance of the second sliding varistor RP2 is connected to the circuit is RP2', and the third sliding varistor RP3 is connected to the circuit The effective resistance size in is RP3'.
  • the second sliding varistor RP2 and the third sliding varistor RP3 divide the voltage in series, and the voltage written to the control electrode of the third transistor T3 is: VN1*RP3'/(RP2'+RP3').
  • the voltage written to the control electrode of the third transistor T3 can be adjusted, that is, the control of the conduction degree of the third transistor T3 is realized, so that the voltage VGH can be passed through the third transistor.
  • the voltage drop ⁇ V T3 generated by T3 is controlled (that is, the output step-down voltage is controlled).
  • the voltage output at the second pole of the third transistor T3 is VN1- ⁇ V T3 . It can be seen that by adjusting the voltage drop ⁇ V T3 , the voltage written by the step-down branch 5 to the second node N2 can be controlled.
  • FIG. 10 is a schematic diagram of another circuit structure of the step-down branch in the embodiments of the disclosure.
  • the step-down branch 5 includes a fourth resistor R4, a fifth resistor R5, and a stabilizer.
  • the first end of the fourth resistor R4 is coupled to the input end of the step-down branch 5, the second end of the fourth resistor R4 is coupled to the first end of the second diode D2; the first end of the fifth resistor R5 Coupled to the first end of the second diode D2, the second end of the fifth resistor R5 is coupled to the first end of the fourth sliding varistor RP4; the control end of the fourth sliding varistor RP4 is coupled to the second power supply end ,
  • the first terminal of the fourth sliding varistor RP4 is coupled to the reference signal supply terminal of the Zener tube ZD, the second terminal of the fourth sliding varistor RP4 is floating; the first terminal of the Zener tube ZD is coupled to the second power terminal ,
  • the second pole of the zener tube ZD is coupled to the first terminal of the second diode D2; the first terminal of the second capacitor C2 is coupled to the second pole of the zener tube ZD, and the second terminal of the second capacitor C2
  • the terminal is coupled to the
  • the first pole and the second pole of the Zener tube ZD refer to the anode and the cathode of the Zener tube ZD, respectively.
  • the step-down principle of the step-down circuit shown in Figure 9 is as follows: the reference signal supply terminal of the Zener tube ZD can provide a preset reference voltage, which is recorded as Vref 1 , and the effective resistance of the fourth sliding rheostat RP4 connected to the circuit is RP4 ', the resistance of the fifth resistor is R5'. At this time, the magnitude of the current flowing through the fourth sliding varistor RP4 is Vref 1 /RP4'.
  • the magnitude of the current flowing through the fifth resistor R5 is equal to the magnitude of the current flowing through the fourth sliding varistor RP4, the magnitude of the current flowing through the fifth resistor R5
  • the voltage difference is Vref 1 *R5'/RP4'
  • the first terminal voltage of the fifth resistor is Vref 1 *R5'/RP4'+Vref 1 at this time .
  • the fifth resistor R5 can be The voltage at one end is controlled, that is, the voltage written to the first end of the second diode D2 is controlled to realize the control of the output step-down voltage.
  • the fourth resistor R4 is used as a load
  • the second capacitor C2 is used to maintain the stability of the voltage at the second terminal of the fifth resistor R5.
  • the step-down branch 5 further includes a third capacitor C3, the first end of the third capacitor C3 is connected to the first end of the second diode D2, the second end of the third capacitor C3 is grounded, and the second end of the third capacitor C3 is grounded.
  • the three-capacitor C3 is used for noise reduction filtering before output.
  • the voltage supply circuit 1 further includes: a level conversion circuit 10, the signal input end of the level conversion circuit 10 is coupled to the second node N2, and the level conversion circuit 10 is configured to The signal at the second node N2 undergoes level conversion processing and is output to the gate driving circuit 2 to determine the voltage level of the scan signal.
  • the signal at the second node N2 can be converted into a clock signal by the level conversion circuit 10, and the clock signal is used as a scanning signal.
  • the embodiments of the present disclosure also provide a display driving circuit, the display driving circuit includes: a gate driving circuit and a voltage supply circuit, wherein the voltage supply circuit can adopt the voltage supply circuit provided by the above-mentioned embodiments, and the specific content will not be omitted here. Go into details.
  • the embodiments of the present disclosure also provide a display device, which includes the display driving circuit provided in the above-mentioned embodiments.
  • the display device provided by the embodiment of the present disclosure may be any product or component with display function such as electronic paper, liquid crystal display panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc.

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Abstract

本公开提供了一种电压供给电路，包括: 电源管理集成电路、传输支路、降压支路，电源管理集成电路的信号输出端、传输支路的信号输入端和降压支路的信号输入端耦接于第一节点，传输支路的信号输出端、降压支路的信号输出端耦接于第二节点; 电源管理集成电路配置为向第一节点提供初始电压; 传输支路与控制信号端耦接，具有导通状态和断开状态，配置为响应于控制信号端提供的控制信号的控制，在导通状态和断开状态之间进行切换，并在处于导通状态时将第一节点处的初始电压写入至第二节点; 降压支路配置为将第一节点处的初始电压进行降压处理以得到降压电压，并在传输支路处于断开状态时将降压电压写入至第二节点。

Description

电压供给电路、显示驱动电路、显示装置和显示驱动方法
相关申请的交叉引用
本申请要求于2020年5月29日提交的中国专利申请NO.202010477402.6的优先权，该中国专利申请的内容通过引用的方式整体合并于此。
技术领域
本公开涉及显示领域，特别涉及电压供给电路、显示驱动电路、显示装置和显示驱动方法。
背景技术
为防止液晶显示装置中的液晶分子出现极化的问题，一般会采用列反转或者帧反转的方式进行驱动；为防止长时间的单一极性变化规律导致像素单元中累积较大的偏置电压而造成残像，一般会周期性地对极性变化规律进行调整，即对极性反转进行调整。
在进行极性反转调整过程中，一个反转调整周期包括偶数个帧，每个反转调整周期中的同一像素单元在相邻帧的信号的极性相反(例如，采用列反转或者帧反转的驱动方式)，而在相邻的反转调整周期中，前一反转调整周期的最后一帧的任意像素单元与后一反转调整周期的第一帧的该像素单元的信号极性相同。在相邻的两个反转调整周期中，一个反转调整周期会使得像素单元中累积正向偏置电压，另一反转调整周期会使得像素单元中累积负向偏置电压，正向偏置电压和负向偏置电压可以相互抵消。
然而，由于前一反转调整周期的最后一帧的任意像素单元与后一反转调整周期的第一帧的该像素单元的信号极性相同(即，未进行极性反转)，该像素单元内的液晶分子保持向同一方向偏转，且在后一反转调整周期的第一帧，液晶分子的偏转角度更大，表现为该像素 单元在后一反转调整周期的第一帧的亮度更大。对于整个显示画面而言，静态画面下前后帧的亮度存在差异，造成画面短暂闪烁，影响画质。
公开内容
第一方面，本公开实施例提供了一种电压供给电路，包括：电源管理集成电路、传输支路、降压支路，所述电源管理集成电路的信号输出端、所述传输支路的信号输入端和所述降压支路的信号输入端耦接于第一节点，所述传输支路的信号输出端、所述降压支路的信号输出端耦接于第二节点；
所述电源管理集成电路配置为向所述第一节点提供初始电压；
所述传输支路与控制信号端耦接，具有导通状态和断开状态，配置为响应于所述控制信号端提供的控制信号的控制，在所述导通状态和所述断开状态之间进行切换，并在处于所述导通状态时将所述第一节点处的所述初始电压写入至所述第二节点；
所述降压支路配置为将所述第一节点处的所述初始电压进行降压处理以得到降压电压，并在所述传输支路处于所述断开状态时将所述降压电压写入至所述第二节点。
在一些实施例中，所述电压供给电路还包括：状态控制电路，所述状态控制电路的信号输出端与所述控制信号端耦接；
所述状态控制电路配置为每隔预设周期向所述控制信号端提供持续预设时长的第一控制信号，并在所述预设时长结束后向所述控制信号端提供第二控制信号；
所述传输支路响应于所述第一控制信号的控制切换至断开状态，所述传输支路响应于所述第二控制信号的控制切换至导通状态。
在一些实施例中，所述状态控制电路包括：计时器、数模转换电路和开关控制器，所述计时器与所述数模转换电路的信号输入端耦接，所述数模转换电路的信号输出端与所述开关控制器的信号输入端耦接，所述开关控制器的信号输出端与所述控制信号端耦接；
所述计时器配置为在每个预设周期开始时进行计时，并将计时 结果以数字信号发送给所述数模转换电路，以及在每个所述预设周期结束时对计时结果进行重置；
所述数模转换电路配置为基于预设数模转换规则对接收到的数字信号进行数模转换处理，以得到对应的模拟信号，并将所述模拟信号发送给所述开关控制器；
所述开关控制器配置为响应于所述模拟信号的控制，输出与所述模拟信号相匹配的所述第一控制信号或所述第二控制信号。
在一些实施例中，所述开关控制器包括：第一电阻、第二电阻和第一晶体管；
所述第一电阻的第一端与所述第一节点耦接，所述第一电阻的第二端与所述第二电阻的第一端耦接；
所述第二电阻的第一端与所述开关控制器的信号输出端耦接，所述第二电阻的第二端与所述第一晶体管的第一极耦接；
所述第一晶体管的控制极与所述开关控制器的信号输入端耦接，所述第一晶体管的第二极与所述第一电源端耦接。
在一些实施例中，所述传输支路包括：第二晶体管和第一二极管；
所述第二晶体管的控制极与所述控制信号端耦接，所述第二晶体管的第一极与所述第一节点耦接，所述第二晶体管的第二极与所述第一二极管的第一端耦接，所述第一二极管的第二端与所述第二节点耦接。
在一些实施例中，所述降压支路包括：低压差线性稳压器和第二二极管；
所述低压差线性稳压器的信号输入端与所述降压支路的信号输入端耦接，所述低压差线性稳压器的信号输出端与所述第二二极管的第一端耦接；
所述第二二极管的第二端与所述降压支路的信号输出端耦接。
在一些实施例中，所述低压差线性稳压器包括：低压差线性稳压芯片和外围电路，所述外围电路包括：第一滑动变阻器、第三电阻、第三二极管、第四二极管和第一电容；
所述第一滑动变阻器的控制端与第二电源端耦接，所述第一滑动变阻器的第一端与所述低压差线性稳压芯片的输出电压调整端耦接，所述第一滑动变阻器的第二端浮接；
所述第三电阻的第一端与所述低压差线性稳压芯片的输出电压调整端耦接，所述第三电阻的第二端与所述低压差线性稳压芯片的信号输出端耦接；
所述第三二极管的第一端与所述低压差线性稳压芯片的输出电压调整端耦接，所述第三二极管的第二端与所述低压差线性稳压芯片的信号输出端耦接；
所述第四二极管的第一端与所述低压差线性稳压芯片的信号输出端端耦接，所述第四二极管的第一端与所述低压差线性稳压芯片的信号输入端端耦接；
所述第一电容的第一端与所述低压差线性稳压芯片的信号输出端耦接，所述第一电容的第二端与所述第二电源端耦接。
在一些实施例中，所述降压支路包括：第三晶体管、第二滑动变阻器、第三滑动变阻器和第二二极管；
所述第三晶体管的控制极与所述第二滑动变阻器的控制端、所述第三滑动变阻器的第一端耦接，所述第三晶体管的第一极与所述降压支路的信号输入端耦接，所述第三晶体管的第二极与所述第二二极管的第一端耦接；
所述第二二极管的第二端与所述降压支路的信号输出端耦接；
所述第二滑动变阻器的第一端与所述降压支路的信号输入端耦接，所述第二滑动变阻器的第二端浮接；
所述第三滑动变阻器的控制端与第二电源端耦接，所述第三滑动变阻器的第二端浮接；
所述第二二极管的第二端与所述降压支路的信号输出端耦接。
在一些实施例中，所述降压支路包括：第四电阻、第五电阻、稳压管、第四滑动变阻器、第二电容和第二二极管；
所述第四电阻的第一端与所述降压支路的输入端耦接，所述第四电阻的第二端与所述第二二极管的第一端耦接；
所述第五电阻的第一端与所述第二二极管的第一端耦接，所述第五电阻的第二端与所述第四滑动变阻器的第一端耦接；
所述第四滑动变阻器的控制端与第二电源端耦接，所述第四滑动变阻器的第一端与所述稳压管的参考信号供给端耦接，所述第四滑动变阻器的第二端浮接；
所述稳压管的第一极与所述第二电源端耦接，所述稳压管的第二极与所述第二二极管的第一端耦接；
所述第二电容的第一端与所述稳压管的第二极耦接，所述第二电容的第二端与所述稳压管的参考信号供给端耦接；
所述第二二极管的第二端与所述降压支路的信号输出端耦接。
在一些实施例中，所述电压供给电路还包括：电平转换电路，所述电平转换电路的信号输入端与所述第二节点耦接，所述电平转换电路配置为将所述第二节点处的信号进行电平转换处理。
第二方面，本公开实施例还提供了一种显示驱动电路，包括：栅极驱动电路和如上述第一方面提供的电压供给电路，所述电压供给电路的信号输出端与所述栅极驱动电路所配置的工作电压输入端耦接。
第三方面，本公开实施例还提供了一种显示装置，包括：如上述第二方面提供的显示驱动电路。
第四方面，本公开实施例还提供了一种显示驱动方法，所述显示驱动方法基于第二方面提供的显示驱动电路，所述显示驱动方法包括：
在反转调整周期内的第一帧，所述电压供给电路向所述栅极驱动电路所配置的工作电压输入端提供第一工作电压；
在所述反转调整周期内的除第一帧之外的其他帧，所述电压供给电路向所述栅极驱动电路所配置的工作电压输入端提供第二工作电压，所述第一工作电压小于所述第二工作电压。
附图说明
图1为相关技术中显示装置内的一个像素单元进行极性反转时 充电电压的极性与液晶偏转角度的示意图；
图2为本公开实施例提供的显示装置的结构示意图；
图3为本公开实施例提供的显示驱动方法的流程图；
图4为本公开实施例中显示装置内的一个像素单元进行极性反转时充电电压的极性与液晶偏转角度的示意图；
图5为本公开实施例提供的电压供给电路的一种电路结构示意图；
图6为本公开实施例提供的电压供给电路的另一种电路结构示意图；
图7为本公开实施例中开关控制器与传输支路的一种电路结构示意图；
图8为本公开实施例中降压支路的一种电路结构示意图；
图9为本公开实施例中降压支路的另一种电路结构示意图；以及
图10为本公开实施例中降压支路的又一种电路结构示意图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的电压供给电路、显示驱动电路、显示装置和显示驱动方法进行详细描述。
在本公开实施例中所涉及的各个晶体管可分别独立选自多晶硅薄膜晶体管、非晶硅薄膜晶体管、氧化物薄膜晶体管以及有机薄膜晶体管中的一种。在本公开中涉及到的“控制极”具体是指晶体管的栅极，“第一极”具体是指晶体管的源极，相应的，“第二极”具体是指晶体管的漏极。当然，本领域的技术人员应该知晓的是，该“第一极”与“第二极”可进行互换。
另外，晶体管可以划分为N型晶体管和P型晶体管，本公开中的各晶体管可分别独立选自N型晶体管或P型晶体管。
图1为相关技术中显示装置内的一个像素单元进行极性反转时充电电压的极性与液晶偏转角度的示意图，如图1所示，图1中示意 性画出了一个像素单元在静态画面下在前一反转调整周期的后4帧(图中N帧至N+3帧)与在后一反转调整周期的前4帧(图中N+4帧至N+7帧)的情况。
在前一反转调整周期的后四帧(即图中N帧至N+3帧)，该像素单元所加载的充电电压分别为-V0、+V0、-V0、+V0，充电电压的极性呈现负(-)、正(+)、负(-)、正(+)；在后一反转调整周期的前四帧(即图中N+4帧至N+7帧)，该像素单元所加载的充电电压分别为+V0、-V0、+V0、-V0，充电电压的极性呈现正(+)、负(-)、正(+)、负(-)。
该像素单元在后一反转调整周期的第一帧(即图中N+4帧)中所加载的充电电压的极性，与在前一反转调整周期的最后一帧(即图中N+3帧)中所加载的充电电压的极性相同。对于同一充电电压+V0，该像素单元所对应的液晶分子在N+4帧中的偏转角度大于在N+3帧中的偏转角度(又称为“过驱动效应”)，即该像素单元在N+4帧中的发光亮度会大于N+3帧中的发光亮度。
为解决相关技术中存在的上述问题，本公开的技术方案提供了一种电压供给电路、一种显示驱动电路、一种显示装置和一种显示驱动方法。
图2为本公开实施例提供的显示装置的结构示意图，如图2所示，该显示装置包括：液晶显示面板和显示驱动电路，其中显示驱动电路包括：电压供给电路1和栅极驱动电路2。在一些实施例中，栅极驱动电路2以Array工艺形成于液晶显示面板的阵列基板上(Gate driver On Array，简称GOA)，电压供给电路1的信号输出端与栅极驱动电路2所配置的工作电压输入端耦接。
在显示驱动过程中，电压供给电路1可向栅极驱动电路2的工作电压输入端提供工作电压，该工作电压输入端将接收到的工作电压传递给栅极驱动电路2内的各级移位寄存器(Shift Register)，以使得栅极驱动电路2内的各级移位寄存器能够依次输出扫描信号，且该扫描信号处于有效电平状态时的电压大小等于工作电压输入端所提供的工作电压。
在显示面板中的栅线Gate加载扫描信号且扫描信号处于有效电平状态时，与该栅线Gate电耦接的像素单元内的开关晶体管M会处于导通状态，数据线Data中的数据电压(充电电压)通过处于导通状态的开关晶体管M写入至对应的像素单元内，以实现对像素单元的驱动。
需要说明的是，本公开中，“有效电平”是相对于开关晶体管M的类型而言的；若开关晶体管M为N型晶体管，则“有效电平”是指高电平；若开关晶体管M为P型晶体管，则“有效电平”是指低电平。在本公开实施例中，以开关晶体管M为N型晶体管、有效电平为高电平为例，进行示例性描述。
图3为本公开实施例提供的显示驱动方法的流程图，如图3所示，该显示驱动方法包括：
步骤S1、在反转调整周期内的第一帧，电压供给电路向栅极驱动电路所配置的工作电压输入端提供第一工作电压，栅极驱动电路输出第一扫描信号，第一扫描信号处于有效电平状态时的电压为第一工作电压；以及
步骤S2、在反转调整周期内的除第一帧之外的其他帧，电压供给电路向栅极驱动电路所配置的工作电压输入端提供第二工作电压，栅极驱动电路输出第二扫描信号，第二扫描信号处于有效电平状态时的电压为第二工作电压，第一工作电压小于第二工作电压。
在实际应用中，上述步骤S1和步骤S2交替进行。
图4为本公开实施例中显示装置内的一个像素单元进行极性反转时充电电压的极性与液晶偏转角度的示意图，如图4所示，图4中示意性画出了本公开实施例中的一个像素单元在前一反转调整周期的后4帧(图中N帧至N+3帧)与在后一反转调整周期的前4帧(图中N+4帧至N+7帧)的情况。
该像素单元在后一反转调整周期的第一帧(即图中N+4帧)中所加载的充电电压，与在前一反转调整周期的最后一帧(即图中N+3帧)中所加载的充电电压相同，均为+V0。
为方便描述，将第一工作电压记为V1，第二工作电压记为V2， V1＜V2。
在本公开实施例中，在前一反转调整周期的最后一帧(图中N+3帧)中，该像素单元内开关晶体管M所耦接的栅线Gate中的数据电压为V2，该像素单元内开关晶体管M所耦接的数据线Data的电压为+V0，开关晶体管M的栅源电压为V2-V0。
在后一反转调整周期的第一帧(图中N+4帧)中，该像素单元内开关晶体管M所耦接的栅线Gate中的电压为V1，该像素单元内开关晶体管M所耦接的数据线Data的数据电压为+V0，开关晶体管M的栅源电压为V1-V0，V1-V0＜V2-V0。
由于栅源电压的大小决定了开关晶体管M的导通程度(栅源电压越大，开关晶体管M的导通程度越大)，因此开关晶体管M在N+4帧中的导通程度小于在N+3帧中的导通程度。因此，该像素单元的像素电极pix在N+4帧中实际所加载的电压小于在N+3帧中实际所加载的电压，该像素单元在N+4帧中所形成的液晶电场小于在N+3帧中所形成的液晶电场。由于液晶电场减小，可使得液晶分子的偏转角度减小，从而能够对因未进行极性反转而导致的过驱动效应进行补偿。
补偿量由V2与V1之间的电压差决定。在实际应用中，可根据预先实验对来V2和V1的大小进行设定，以保证像素单元在后一反转调整周期的第一帧与前一反转调整周期的最后一帧在加载相同的数据电压时，能够呈现出相同的显示亮度。
基于上述内容可见，本公开的技术方案可有效解决在进行极性反转调整过程中因过驱动效应而导致的闪烁问题。
在相关技术中，电压供给电路1仅能向栅极驱动电路2提供固定大小的工作电压，无法满足本公开实施例中在不同时刻分别提供“第一工作电压”和“第二工作电压”的需求，为此本公开实施例还提供了一种电压供给电路1。
图5为本公开实施例提供的电压供给电路的一种电路结构示意图，如图5所示，该电压供给电路1可用于实现上述显示驱动方法中的步骤，该电压供给电路1包括：电源管理集成电路3、传输支路4和降压支路5，电源管理集成电路3的信号输出端、传输支路4的信 号输入端和降压支路5的信号输入端耦接于第一节点N1，传输支路4的信号输出端、降压支路5的信号输出端耦接于第二节点N2。
电源管理集成电路3(Power Management Integrated Circuit，简称PMIC)配置为向第一节点N1提供初始电压。
传输支路4与控制信号端耦接，具有导通状态和断开状态，配置为响应于控制信号端提供的控制信号的控制，在导通状态和断开状态进行切换，并在处于导通状态时将第一节点N1处的初始电压写入至第二节点N2。
降压支路5配置为将第一节点N1处的初始电压进行降压处理以得到降压后电压，并在传输支路4处于断开状态时将降压后电压写入至第二节点N2；降压后电压小于初始电压。
在实际应用中，可通过预先(例如产品出厂调试时)对降压支路进行配置来控制初始电压与降压后电压的电压差。
在一些实施例中，初始电压可以为第二工作电压，降压后电压可以为第一工作电压。即，可以通过传输支路4和降压支路5分别向栅极驱动电路2提供不同的工作电压。
图6为本公开实施例提供的电压供给电路的另一种电路结构示意图，如图6所示，图6所示电压供给电路1不但包括图5中所示的电源管理集成电路3、传输支路4和降压支路5，还包括：状态控制电路6，状态控制电路6的信号输出端与控制信号端耦接，状态控制电路6配置为每隔预设周期向控制信号端提供持续预设时长的第一控制信号，并在预设时长结束后向控制信号端提供第二控制信号。
传输支路4响应于第一控制信号的控制切换至断开状态，响应于第二控制信号的控制切换至导通状态。
在本公开实施例中，通过配置状态控制电路6，可对传输支路4处于导通状态和断开状态的时间进行自动控制。
在实际应用中，将上述预设周期的时长配置为一个反转调整周期(例如28s)的时长，预设时长配置为反转调整周期的第一帧时间，从而可实现电压供给电路1在反转调整周期的第一帧内自动向栅极驱动电路2提供第一工作电压，在其他帧内自动向栅极驱动电路2 提供第二工作电压。
在一些实施例中，状态控制电路6包括：计时器7、数模转换电路8和开关控制器9，计时器7与数模转换电路8的信号输入端耦接，数模转换电路8的信号输出端与开关控制器9的信号输入端耦接，开关控制器9的信号输出端与控制信号端耦接。
示例性的，计时器7配置为在每个预设周期开始时进行计时，并将计时结果以数字信号发送给数模转换电路8，以及在每个预设周期结束时对计时结果进行重置。作为一个示例，计时器7可包括：时钟控制电路(Timer Control Integrated Circuit)和计数器，时钟控制电路可用于产生时钟脉冲，计数器可用于对时钟控制电路所产生的时钟脉冲进行计数，从而达到计时的目的。
数模转换电路8配置为基于预设数模转换规则对接收到的数字信号进行数模转换处理，以得到对应的模拟信号，并将模拟信号发送给开关控制器9。
开关控制器9配置为响应于模拟信号的控制，输出与模拟信号相匹配的第一控制信号或第二控制信号。
为便于理解，下面将结合具体示例进行详细描述。假定一个反转调整周期的时长为28s，显示装置的工作频率为60HZ，一个反转调整周期包括28×60＝1680帧，一帧时间为1/60s，计数器配置的重置阈值为1680。此时，可控制时钟控制电路每隔时间1/60s输出一个时钟脉冲。
在一个反转调整周期开始第一帧时，可控制时钟控制电路同步输出第一个时钟脉冲，计数器记数为1；在第一帧结束，第二帧开始时，时钟控制电路同步输出第二个时钟脉冲，计数器记数为2，……，依次类推，在第1679帧结束，第1680帧开始时，计数器记数为1680，计数结果到达重置阈值，计数器进行重置。在下一个反转调整周期开始时，计数器重新开始计数。
数模转换电路8配置为在计数结果为1时输出模拟信号“1”，在计数结果为非1时输出模拟信号“0”(示例性地，“1”表示高电平信号，“0”表示低电平信号)。开关控制器9配置为在接收到模 拟信号“1”时输出第一控制信号以控制传输支路4处于断开状态，以及在接收到模拟信号“0”时输出第二控制信号以控制传输支路4处于导通状态。
图7为本公开实施例中开关控制器与传输支路的一种电路结构示意图，如图7所示，开关控制器9包括：第一电阻R1、第二电阻R2和第一晶体管T1；第一电阻R1的第一端与第一节点N1耦接，第一电阻R1的第二端与第二电阻R2的第一端耦接；第二电阻R2的第一端与开关控制器9的信号输出端耦接，第二电阻R2的第二端与第一晶体管T1的第一极耦接；第一晶体管T1的控制极与开关控制器9的信号输入端耦接，第一晶体管T1的第二极与第一电源端耦接。
在一些实施例中，传输支路4包括：第二晶体管T2和第一二极管D1；第二晶体管T2的控制极与控制信号端耦接，第二晶体管T2的第一极与第一节点N1耦接，第二晶体管T2的第二极与第一二极管D1的第一端耦接，第一二极管D1的第二端与第二节点N2耦接。
在本公开实施例中，二极管的第一端和第二端分别是指二级管的阳极端和阴极端。
以第一晶体管T1和第二晶体管T2均为P型晶体管、第一电源端接地、电源管理集成电路3提供初始电压VGH为例进行示例性描述。
当数模转换电路8输出高电平信号“1”时，第一晶体管T1截止，第二晶体管T2的控制极处于浮接(floating)状态，电压VGH可全部写入至第二晶体管T2的控制极(即，开关控制器9向传输支路4提供第一控制信号)，第二晶体管T2的栅源电压近似为0，第二晶体管T2截止，即传输支路4处于截止状态。
当数模转换电路8输出高电平信号“0”时，第一晶体管T1导通，第一电阻R1和第二电阻R2上形成有电流，第一电阻R1和第二电阻R2实现分压，第二晶体管T2的控制极上所加载的电压(由第一电阻R1与第二电阻R2的电阻之比决定)小于VGH。第二晶体管T2的栅源电压小于0，第二晶体管T2导通，即传输支路4处于导通状态。
图8为本公开实施例中降压支路的一种电路结构示意图，如图8 所示，在一些实施例中，降压支路5包括：低压差线性稳压器和第二二极管D2；低压差线性稳压器的信号输入端与降压支路5的信号输入端耦接，低压差线性稳压器的信号输出端与第二二极管D2的第一端耦接；第二二极管D2的第二端与降压支路5的信号输出端耦接。
在一些实施例中，低压差线性稳压器包括：低压差线性稳压芯片LDO和外围电路，外围电路包括：第一滑动变阻器RP1、第三电阻R3、第三二极管D3、第四二极管D4和第一电容C1。
第一滑动变阻器RP1的控制端与第二电源端耦接，第一滑动变阻器RP1的第一端与低压差线性稳压芯片LDO的输出电压调整端耦接，第一滑动变阻器RP1的第二端浮接；第三电阻R3的第一端与低压差线性稳压芯片LDO的输出电压调整端耦接，第三电阻R3的第二端与低压差线性稳压芯片LDO的信号输出端耦接；第三二极管D3的第一端与低压差线性稳压芯片LDO的输出电压调整端耦接，第三二极管D3的第二端与低压差线性稳压芯片LDO的信号输出端耦接；第四二极管D4的第一端与低压差线性稳压芯片LDO的信号输出端端耦接，第四二极管D4的第二端与低压差线性稳压芯片LDO的信号输入端端耦接；第一电容C1的第一端与低压差线性稳压芯片LDO的信号输出端耦接，第一电容C1的第二端与第二电源端耦接。在本公开实施例中，第二电源端接地。
图8所示降压电路的降压原理如下：第一节点N1向低压差线性稳压芯片LDO的信号输入端提供输入电压，以使得低压差线性稳压芯片LDO能够进行工作，低压差线性稳压芯片LDO的信号输出端与输出电压调整端之间具有设定基准电压Vref 0(LDO的信号输出端与输出电压调整端之间的电压差等于基准电压Vref 0，Vref 0由低压差线性稳压芯片自身结构决定，一般而言Vref 0设定在1V至2V，例如可以为1.25V)。若第一滑动变阻器RP1接入电路中的有效电阻大小为RP1’,第三电阻R3的电阻大小为R3’，由于第一滑动变阻器RP1接入电路中的有效电阻与第三电阻R3串联，第三电阻R3两端的电压差为Vref 0，基于串联分压原理，可计算出LDO的信号输出端的电压为Vref 0*(RP1’+R3’)/R3’。由此可见，通过调节第一滑动变阻器RP1接 入电路中的有效电阻大小RP1’，可对低压差线性稳压芯片LDO的信号输出端所输出电压进行调整，即对低压差线性稳压器的压降(即，信号输出端与信号输入端的电压之差)大小进行调整。需要说明的是，低压差线性稳压芯片LDO属于本领域的常规器件，其内部结构和工作原理，此处不进行详细描述。第三二极管D3和第四二极管D4用于保证电路单向导通，第一电容C1用于对低压差线性稳压芯片LDO的信号输出端输出的信号进行降噪滤波。
图9为本公开实施例中降压支路的另一种电路结构示意图，如图9所示，在一些实施例中，降压支路5包括：第三晶体管T3、第二滑动变阻器RP2、第三滑动变阻器RP3和第二二极管D2。
以第三晶体管T3为P型晶体管为例，第三晶体管T3的控制极与第二滑动变阻器RP2的控制端、第三滑动变阻器RP3的第一端耦接，第三晶体管T3的第一极与降压支路5的信号输入端耦接，第三晶体管T3的第二极与第二二极管D2的第一端耦接；第二二极管D2的第二端与降压支路5的信号输出端耦接；第二滑动变阻器RP2的第一端与降压支路5的信号输入端耦接，第二滑动变阻器RP2的第二端浮接；第三滑动变阻器RP3的控制端与第二电源端耦接，第三滑动变阻器RP3的第二端浮接。
图9所示降压电路的降压原理如下：若第一节点N1处的电压大小为VN1，第二滑动变阻器RP2接入电路中的有效电阻大小为RP2’，第三滑动变阻器RP3接入电路中的有效电阻大小为RP3’。第二滑动变阻器RP2与第三滑动变阻器RP3串联分压，写入至第三晶体管T3的控制极的电压大小为：VN1*RP3’/(RP2’+RP3’)。通过调整RP2’与RP3’的大小，可对写入至第三晶体管T3的控制极的电压进行调整，即实现对第三晶体管T3的导通程度的控制，从而能够对电压VGH通过第三晶体管T3所产生的压降△V T3的大小进行控制(即对输出的降压电压进行控制)，此时第三晶体管T3的第二极处输出的电压大小为VN1-△V T3。由此可见，通过调节压降△V T3，可对降压支路5写入至第二节点N2处的电压进行控制。
图10为本公开实施例中降压支路的又一种电路结构示意图，如 图10所示，在一些实施例中，降压支路5包括：第四电阻R4、第五电阻R5、稳压管ZD、第四滑动变阻器RP4、第二电容C2和第二二极管D2。
第四电阻R4的第一端与降压支路5的输入端耦接，第四电阻R4的第二端与第二二极管D2的第一端耦接；第五电阻R5的第一端与第二二极管D2的第一端耦接，第五电阻R5的第二端与第四滑动变阻器RP4的第一端耦接；第四滑动变阻器RP4的控制端与第二电源端耦接，第四滑动变阻器RP4的第一端与稳压管ZD的参考信号供给端耦接，第四滑动变阻器RP4的第二端浮接；稳压管ZD的第一极与第二电源端耦接，稳压管ZD的第二极与第二二极管D2的第一端耦接；第二电容C2的第一端与稳压管ZD的第二极耦接，第二电容C2的第二端与稳压管ZD的参考信号供给端耦接；第二二极管D2的第二端与降压支路5的信号输出端耦接。
稳压管ZD的第一极和第二极分别是指稳压管ZD的阳极和阴极。
图9所示降压电路的降压原理如下：稳压管ZD的参考信号供给端可提供预先设定的参考电压，记为Vref 1，第四滑动变阻器RP4接入电路的有效电阻大小为RP4’，第五电阻的电阻大小为R5’。此时，流过第四滑动变阻器RP4的电流大小为Vref 1/RP4’，由于流过第五电阻R5的电流大小等于流过第四滑动变阻器RP4的电流大小，因此第五电阻R5的两端的电压差为Vref 1*R5’/RP4’,此时第五电阻的第一端电压为Vref 1*R5’/RP4’+Vref 1，通过调节RP4’的大小，可对第五电阻R5的第一端的电压进行控制，即对写入至第二二极管D2的第一端的电压进行控制，实现对输出的降压电压进行控制。第四电阻R4用作负载，第二电容C2用于维持第五电阻R5的第二端电压的稳定。
在一些实施例中，降压支路5还包括第三电容C3，第三电容C3的第一端与第二二极管D2的第一端连接，第三电容C3的第二端接地，第三电容C3用于进行输出前的降噪滤波。
需要说明的是，上述图8至图10所示降压支路5的具体电路结构仅为本公开实施例中的示例实施方案，其不会对本公开的技术方案 产生限制。在本公开技术方案中，还可以采用其他具有降压功能的电路结构，此处不再一一举例描述。
在一些实施例中，如图6所示，电压供给电路1还包括：电平转换电路10，电平转换电路10的信号输入端与第二节点N2耦接，电平转换电路10配置为将第二节点N2处的信号进行电平转换处理，并输出到栅极驱动电路2，决定扫描信号的电压大小。例如，第二节点N2处的信号可以通过电平转换电路10转化为时钟信号，该时钟信号被作为扫描信号。
本公开实施例还提供了一种显示驱动电路，该显示驱动电路包括：栅极驱动电路和电压供给电路，其中该电压供给电路可采用上述实施例提供的电压供给电路，具体内容此处不再赘述。
本公开实施例还提供了一种显示装置，该显示装置包括上述实施例提供的显示驱动电路。
本公开实施例提供的显示装置可以为电子纸、液晶显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等具有显示功能的任何产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为落入本公开的保护范围。

Claims (13)

  1. 一种电压供给电路，包括：电源管理集成电路、传输支路、降压支路，所述电源管理集成电路的信号输出端、所述传输支路的信号输入端和所述降压支路的信号输入端耦接于第一节点，所述传输支路的信号输出端、所述降压支路的信号输出端耦接于第二节点；
    所述电源管理集成电路配置为向所述第一节点提供初始电压；
    所述传输支路与控制信号端耦接，具有导通状态和断开状态，配置为响应于所述控制信号端提供的控制信号的控制，在所述导通状态和所述断开状态之间进行切换，并在处于所述导通状态时将所述第一节点处的所述初始电压写入至所述第二节点；
    所述降压支路配置为将所述第一节点处的所述初始电压进行降压处理以得到降压电压，并在所述传输支路处于所述断开状态时将所述降压电压写入至所述第二节点。
  2. 根据权利要求1所述的电压供给电路，还包括：状态控制电路，所述状态控制电路的信号输出端与所述控制信号端耦接；
    所述状态控制电路配置为每隔预设周期向所述控制信号端提供持续预设时长的第一控制信号，并在所述预设时长结束后向所述控制信号端提供第二控制信号；
    所述传输支路响应于所述第一控制信号的控制切换至断开状态，响应于所述第二控制信号的控制切换至导通状态。
  3. 根据权利要求2所述的电压供给电路，其中，所述状态控制电路包括：计时器、数模转换电路和开关控制器，所述计时器与所述数模转换电路的信号输入端耦接，所述数模转换电路的信号输出端与所述开关控制器的信号输入端耦接，所述开关控制器的信号输出端与所述控制信号端耦接；
    所述计时器配置为在每个预设周期开始时进行计时，并将计时结果以数字信号发送给所述数模转换电路，以及在每个所述预设周期 结束时对计时结果进行重置；
    所述数模转换电路配置为基于预设数模转换规则对接收到的数字信号进行数模转换处理，以得到对应的模拟信号，并将所述模拟信号发送给所述开关控制器；
    所述开关控制器配置为响应于所述模拟信号的控制，输出与所述模拟信号相匹配的所述第一控制信号或所述第二控制信号。
  4. 根据权利要求3所述的电压供给电路，其中，所述开关控制器包括：第一电阻、第二电阻和第一晶体管；
    所述第一电阻的第一端与所述第一节点耦接，所述第一电阻的第二端与所述第二电阻的第一端耦接；
    所述第二电阻的第一端与所述开关控制器的信号输出端耦接，所述第二电阻的第二端与所述第一晶体管的第一极耦接；
    所述第一晶体管的控制极与所述开关控制器的信号输入端耦接，所述第一晶体管的第二极与所述第一电源端耦接。
  5. 根据权利要求1所述的电压供给电路，其中，所述传输支路包括：第二晶体管和第一二极管；
    所述第二晶体管的控制极与所述控制信号端耦接，所述第二晶体管的第一极与所述第一节点耦接，所述第二晶体管的第二极与所述第一二极管的第一端耦接，所述第一二极管的第二端与所述第二节点耦接。
  6. 根据权利要求1所述的电压供给电路，其中，所述降压支路包括：低压差线性稳压器和第二二极管；
    所述低压差线性稳压器的信号输入端与所述降压支路的信号输入端耦接，所述低压差线性稳压器的信号输出端与所述第二二极管的第一端耦接；
    所述第二二极管的第二端与所述降压支路的信号输出端耦接。
  7. 根据权利要求6所述的电压供给电路，其中，所述低压差线性稳压器包括：低压差线性稳压芯片和外围电路，所述外围电路包括：第一滑动变阻器、第三电阻、第三二极管、第四二极管和第一电容；
    所述第一滑动变阻器的控制端与第二电源端耦接，所述第一滑动变阻器的第一端与所述低压差线性稳压芯片的输出电压调整端耦接，所述第一滑动变阻器的第二端浮接；
    所述第三电阻的第一端与所述低压差线性稳压芯片的输出电压调整端耦接，所述第三电阻的第二端与所述低压差线性稳压芯片的信号输出端耦接；
    所述第三二极管的第一端与所述低压差线性稳压芯片的输出电压调整端耦接，所述第三二极管的第二端与所述低压差线性稳压芯片的信号输出端耦接；
    所述第四二极管的第一端与所述低压差线性稳压芯片的信号输出端端耦接，所述第四二极管的第一端与所述低压差线性稳压芯片的信号输入端端耦接；
    所述第一电容的第一端与所述低压差线性稳压芯片的信号输出端耦接，所述第一电容的第二端与所述第二电源端耦接。
  8. 根据权利要求1所述的电压供给电路，其中，所述降压支路包括：第三晶体管、第二滑动变阻器、第三滑动变阻器和第二二极管；
    所述第三晶体管的控制极与所述第二滑动变阻器的控制端、所述第三滑动变阻器的第一端耦接，所述第三晶体管的第一极与所述降压支路的信号输入端耦接，所述第三晶体管的第二极与所述第二二极管的第一端耦接；
    所述第二二极管的第二端与所述降压支路的信号输出端耦接；
    所述第二滑动变阻器的第一端与所述降压支路的信号输入端耦接，所述第二滑动变阻器的第二端浮接；
    所述第三滑动变阻器的控制端与第二电源端耦接，所述第三滑动变阻器的第二端浮接；
    所述第二二极管的第二端与所述降压支路的信号输出端耦接。
  9. 根据权利要求1所述的电压供给电路，其中，所述降压支路包括：第四电阻、第五电阻、稳压管、第四滑动变阻器、第二电容和第二二极管；
    所述第四电阻的第一端与所述降压支路的输入端耦接，所述第四电阻的第二端与所述第二二极管的第一端耦接；
    所述第五电阻的第一端与所述第二二极管的第一端耦接，所述第五电阻的第二端与所述第四滑动变阻器的第一端耦接；
    所述第四滑动变阻器的控制端与第二电源端耦接，所述第四滑动变阻器的第一端与所述稳压管的参考信号供给端耦接，所述第四滑动变阻器的第二端浮接；
    所述稳压管的第一极与所述第二电源端耦接，所述稳压管的第二极与所述第二二极管的第一端耦接；
    所述第二电容的第一端与所述稳压管的第二极耦接，所述第二电容的第二端与所述稳压管的参考信号供给端耦接；
    所述第二二极管的第二端与所述降压支路的信号输出端耦接。
  10. 根据权利要求1至9中任一项所述的电压供给电路，还包括：电平转换电路，所述电平转换电路的信号输入端与所述第二节点耦接，所述电平转换电路配置为将所述第二节点处的信号进行电平转换处理。
  11. 一种显示驱动电路，包括：栅极驱动电路和如上述权利要求1至10中任一项所述的电压供给电路，所述电压供给电路的信号输出端与所述栅极驱动电路所配置的工作电压输入端耦接。
  12. 一种显示装置，包括：如上述权利要求11所述的显示驱动电路。
  13. 一种显示驱动方法，所述显示驱动方法基于权利要求11所 述的显示驱动电路，所述显示驱动方法包括：
    在反转调整周期内的第一帧，所述电压供给电路向所述栅极驱动电路所配置的工作电压输入端提供第一工作电压；
    在所述反转调整周期内的除第一帧之外的其他帧，所述电压供给电路向所述栅极驱动电路所配置的工作电压输入端提供第二工作电压，所述第一工作电压小于所述第二工作电压。
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