WO2017128645A1 - 像素电路及其驱动方法、显示面板和显示装置 - Google Patents

像素电路及其驱动方法、显示面板和显示装置 Download PDF

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Publication number
WO2017128645A1
WO2017128645A1 PCT/CN2016/090396 CN2016090396W WO2017128645A1 WO 2017128645 A1 WO2017128645 A1 WO 2017128645A1 CN 2016090396 W CN2016090396 W CN 2016090396W WO 2017128645 A1 WO2017128645 A1 WO 2017128645A1
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Prior art keywords
liquid crystal
control signal
crystal capacitor
pole
transistor
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PCT/CN2016/090396
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English (en)
French (fr)
Inventor
王俊伟
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/519,957 priority Critical patent/US10043468B2/en
Publication of WO2017128645A1 publication Critical patent/WO2017128645A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel circuit and a driving method thereof, a display panel, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the array substrate of the liquid crystal display device includes: a plurality of intersecting gate lines and a plurality of data lines; and a plurality of pixel units arranged in a matrix form by the intersection of the gate lines and the data lines.
  • the driving signal of a certain frequency can generally be used to scan the gate line from top to bottom progressively, so that the pixel unit is gate-by-row.
  • the data line can charge the gated pixel unit to control the deflection of the liquid crystal molecules at different angles to achieve picture display.
  • a normal screen display In the process of displaying a screen on a liquid crystal display device, there are generally two states: a normal screen display and a static screen display.
  • the liquid crystal display device During normal screen display, the liquid crystal display device refreshes frame by frame to update the display content of the screen.
  • the static screen display process the liquid crystal display device is also refreshed frame by frame, but the display content of the screen does not change.
  • the charging frequency of the scanning signal in the gate line of the prior art liquid crystal display device is the same as the charging frequency of the scanning signal in the gate line when displaying the dynamic picture, that is, maintaining a higher frequency.
  • the charging frequency, and the higher the charging frequency of the gate line makes the overall power consumption of the liquid crystal display device larger. Therefore, the overall efficiency of the liquid crystal display device in the prior art when displaying a still picture is large.
  • the invention provides a pixel circuit and a driving method thereof, a display panel and a display device, which are used for solving the problem that the overall efficiency of the liquid crystal display device in the prior art when displaying a static picture is large, and the pixel can be effectively reduced. Power consumption of circuits and display panels.
  • the present invention provides a pixel circuit including: a data writing unit, a liquid crystal capacitor, a power supply unit, and a control signal output unit; the data writing unit and the gate line, the data line, and the liquid crystal capacitor The first end is connected, the second end of the liquid crystal capacitor is connected to a common voltage line, the control signal output unit is connected to the data line and the power supply unit, and the power supply unit and the first end of the liquid crystal capacitor Connected to the second end; the data write unit is configured to write the data voltage in the data line to the first of the liquid crystal capacitor under the control of the gate scan signal in the gate line during the normal display phase
  • the control signal output unit is configured to collect a data voltage provided by the data line to the pixel circuit during a normal display phase, and generate a corresponding charging control signal according to the collected data voltage, and display the static Sending the charging control signal to the power supply unit at a stage; the power supply unit is configured to charge the liquid crystal capacitor according to the charging control signal, To the voltage difference between the first
  • the power supply unit includes a first switch control module and a charging power source, and the charging control signal includes a first control signal; the first switch control module and the control signal output unit, and the liquid crystal capacitor One end, a second end, and the first pole and the second pole of the charging power source are connected; the first switch control module is configured to, under the control of the first control signal, the first pole of the charging power source Connected to the first end of the liquid crystal capacitor, and the second end of the charging power source is connected to the second end of the liquid crystal capacitor for positive charging of the liquid crystal capacitor by the charging power source until A voltage difference between the first end and the second end of the liquid crystal capacitor is Vdata-Vcom; and a fixed voltage difference is between the first pole and the second pole of the charging power source.
  • the first switch control module includes a first transistor and a second transistor; a control electrode of the first transistor is connected to the control signal output unit, and a first pole of the first transistor and the charging power source a first pole connected to the second pole of the first transistor Connected to the first end of the liquid crystal capacitor; the control electrode of the second transistor is connected to the control signal output unit, and the first pole of the second transistor is connected to the second pole of the charging power source, A second pole of the second transistor is coupled to the second end of the liquid crystal capacitor.
  • the power supply unit further includes a second switch control module
  • the charging control signal further includes a second control signal
  • the second switch control module and the control signal output unit the first of the liquid crystal capacitors The first end and the second end are connected to the first pole and the second pole of the charging power source
  • the second switch control module is configured to, under the control of the second control signal, the first pole of the charging power source
  • the second end of the liquid crystal capacitor is turned on, and the second pole of the charging power source is connected to the first end of the liquid crystal capacitor, so that the charging power source reversely charges the liquid crystal capacitor until the The voltage difference between the first end and the second end of the liquid crystal capacitor is Vcom-Vdata.
  • the second switch control module includes a third transistor and a fourth transistor; a control electrode of the third transistor is connected to the control signal output unit, and a first pole of the third transistor is charged with the a first pole of the power supply, a second pole of the third transistor being coupled to the second end of the liquid crystal capacitor; a control pole of the fourth transistor being coupled to the control signal output unit, the fourth transistor The first pole is connected to the second pole of the charging power source, and the second pole of the fourth transistor is connected to the first end of the liquid crystal capacitor.
  • control signal output unit is specifically configured to alternately output the first control signal to the first switch control module and output a second control signal to the second switch control module.
  • the power supply unit further includes a filter capacitor, the first end of the filter capacitor is connected to the first pole of the charging power source, and the second end of the filter capacitor is connected to the second pole of the charging power source .
  • the charging power source is a photovoltaic cell.
  • the data writing unit includes a fifth transistor; a control electrode of the fifth transistor is connected to the gate line, a first pole of the fifth transistor is connected to a data line, and the fifth transistor is The second pole is connected to the first end of the liquid crystal capacitor.
  • the data writing unit further includes a storage capacitor; a first end of the storage capacitor is connected to the first end of the liquid crystal capacitor, and a second end of the storage capacitor and a second end of the liquid crystal capacitor End connection.
  • the pixel circuit further includes a switch unit, the switch unit is disposed between the power supply unit and the first end of the liquid crystal capacitor, or is disposed at the power supply unit and the second of the liquid crystal capacitor
  • the switch unit is configured to control on and off between the power supply unit and the liquid crystal capacitor.
  • the switching unit includes a sixth transistor; a control electrode of the sixth transistor is connected to a switch control signal line, a first pole of the sixth transistor is connected to the power supply unit; when the switch unit is set When the power supply unit is between the first end of the liquid crystal capacitor, the second pole of the sixth transistor is connected to the first end of the liquid crystal capacitor; and when the switch unit is disposed in the power supply unit When the second end of the liquid crystal capacitor is between, the second pole of the sixth transistor is connected to the second end of the liquid crystal capacitor.
  • control signal output unit includes a data acquisition module and a signal output module; the data acquisition module is connected to the data line and the signal output module, and the signal output module is connected to the power supply unit;
  • the data acquisition module is configured to collect the data voltage provided by the data line to the pixel circuit;
  • the signal output module is configured to query a charging control signal corresponding to the data voltage according to a pre-stored relationship correspondence table.
  • each transistor in the pixel circuit is an N-type transistor.
  • the present invention provides a display panel including the above pixel circuit.
  • the display panel is a reflective display panel.
  • the present invention provides a display device including the above display panel.
  • the present invention provides a driving method of the above pixel circuit, wherein the driving method of the pixel circuit includes: in a normal display stage, the data writing unit is under the control of a gate scanning signal in a gate line, Writing a data voltage in the data line to a first end of the liquid crystal capacitor, wherein a common voltage signal is loaded with a common voltage signal to write a common voltage to a second end of the liquid crystal capacitor, the control signal output unit Collecting a data voltage supplied to the pixel circuit by the data line, and generating a corresponding charging control signal according to the collected data voltage; in the static display stage, the gate line stops outputting the gate scan signal, and the common voltage line stops loading the common a voltage signal, the power supply unit according to the charging control The signal charges the liquid crystal capacitor until a voltage difference between the first end and the second end of the liquid crystal capacitor is Vdata-Vcom, wherein Vdata is the data voltage and Vcom is the common voltage.
  • the charging control signal includes a first control signal and a second control signal
  • the control signal output unit Outputting a second control signal to the second switch control module, the second switch control module, under the control of the second control signal, the first pole of the charging power source and the second end of the liquid crystal capacitor
  • the second pole of the charging power source is connected to the first end of the liquid crystal capacitor, so that the charging power source reversely charges the liquid crystal capacitor until the first end of the liquid crystal capacitor
  • the voltage difference between the two ends is Vcom-Vdata
  • the control signal output unit outputs a first control signal to the first switch control module, and the first switch control module is under the control of the first control signal, a first pole of the charging power source is connected to the first end of the liquid crystal capacitor, and a second pole of the charging power source is connected to a second end of the liquid crystal capacitor, so that the charging power source is liquid
  • the control signal output unit outputs a first control signal to the first switch control module
  • the first switch control module is under the control of the first control signal
  • the present invention provides a pixel circuit and a driving method thereof, a display panel including the pixel circuit, and a display device including the same, wherein the pixel circuit includes: a data writing unit, a liquid crystal capacitor, a power supply unit, and a control signal output unit
  • the data writing unit is configured to write the data voltage in the data line to the first end of the liquid crystal capacitor under the control of the gate scan signal in the gate line during the normal display phase
  • the control signal output unit is used for normal display Collecting the data voltage supplied to the pixel circuit by the data line, generating a corresponding charging control signal according to the collected data voltage, and transmitting the charging control signal to the power supply unit during the static display phase
  • the power supply unit is configured to receive the charging control signal according to the charging control signal
  • the liquid crystal capacitor is charged until the voltage difference between the first end and the second end of the liquid crystal capacitor is Vdata-Vcom.
  • the technical scheme of the present invention charges a liquid crystal capacitor in a static display stage by providing a power supply unit and a control signal output unit in a pixel circuit, at this time in the gate line There is no need to load a scan signal, which can effectively reduce the overall power consumption of the display panel.
  • FIG. 1 is a schematic diagram showing the circuit structure of a pixel circuit according to a first embodiment of the present invention.
  • FIG. 2 is a timing chart showing the operation of the pixel circuit shown in FIG. 1.
  • FIG. 3 is a schematic diagram of a circuit structure of a pixel circuit according to a second embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a circuit of a pixel circuit according to a third embodiment of the present invention.
  • FIG. 5 is a timing chart showing the operation of the pixel circuit shown in FIG.
  • FIG. 6 is a flowchart of a driving method of a pixel circuit according to a sixth embodiment of the present invention.
  • FIG. 7 is a flowchart of a driving method of a pixel circuit according to a seventh embodiment of the present invention.
  • FIG. 1 is a schematic diagram showing the circuit structure of a pixel circuit according to a first embodiment of the present invention.
  • the pixel circuit includes a data writing unit 1, a liquid crystal capacitor Clc, a power supply unit 3, and a control signal output unit 2.
  • the data writing unit 1 is connected to the first terminal Q of the gate line GATE, the data line DATA and the liquid crystal capacitor Clc for controlling the gate scanning signal in the gate line GATE during the normal display phase.
  • the data voltage in the data line DATA is written to the first terminal Q of the liquid crystal capacitor Clc.
  • the second end P of the liquid crystal capacitor Clc is connected to the common voltage line VCOM for generating a corresponding electric field when a voltage is applied to both ends thereof to control the deflection of the liquid crystal molecules at a corresponding angle.
  • the control signal output unit 2 is connected to the data line DATA and the power supply unit 3 for collecting the data voltage supplied from the data line DATA to the pixel circuit during the normal display phase, and generating a corresponding charging control signal according to the collected data voltage, and The charging control signal is sent to the power supply unit 3 during the static display phase.
  • the power supply unit 3 is connected to the first end Q and the second end P of the liquid crystal capacitor Clc for charging the liquid crystal capacitor Clc according to the charging control signal, so that the first end Q and the second end P of the liquid crystal capacitor Clc are The voltage difference is Vdata-Vcom.
  • Vdata is the voltage level of the data voltage
  • Vcom is the voltage level of the common voltage output by the common voltage line VCOM.
  • FIG. 2 is a timing chart showing the operation of the pixel circuit shown in FIG. 1.
  • the pixel circuit includes two working phases: a normal display phase and a static display phase.
  • the normal display phase specifically includes: a data writing process P1 and a normal display process P2.
  • the gate line GATE outputs a gate scan signal and the gate scan signal is at a high level
  • the data writing unit 1 writes the data voltage in the data line DATA under the control of the gate scan signal.
  • the common voltage line VCOM is loaded with a common voltage, and the common voltage is written to the second end P of the liquid crystal capacitor Clc.
  • the pixel circuit displays the corresponding gray scale, and the gray scale displayed by the pixel circuit is updated (the display panel screen is updated for the entire display panel).
  • the gate scan signal is at a low level, and the liquid crystal capacitor Clc continues to maintain the pixel circuit for display, but the voltage difference Vclc between the two ends of the liquid crystal capacitor Clc continues to decrease due to leakage current, that is, the liquid crystal capacitor Clc produces a pressure drop.
  • the duration of the normal display process P2 is designed to be a fixed duration, and it is required that the human eye does not recognize the gray scale of the pixel circuit display due to the voltage drop of the liquid crystal capacitor Clc within the fixed duration.
  • the change that occurs that is, the grayscale change caused by the pressure drop does not exceed the minimum identifiability of the human eye for brightness.
  • This fixed length can be set according to actual experience.
  • the fixed duration can be set to
  • the voltage drop generated by the liquid crystal capacitor Clc is different for different data voltages.
  • the voltage drop generated by the corresponding liquid crystal capacitor Clc in the normal display process P2 when the data voltage of each gray scale is loaded on the first terminal Q of the liquid crystal capacitor Clc can be obtained by an experiment in advance, and can be established. The one-to-one correspondence between the data voltage and the voltage drop generated by the liquid crystal capacitor Clc.
  • control signal output unit 2 collects the data voltage supplied from the data line DATA to the pixel circuit, and generates a corresponding charging control signal based on the collected data voltage.
  • the power supply unit 3 is required to The amount of charge of the liquid crystal capacitor Clc for charging is also different. Accordingly, the charging control signals sent from the control signal output unit 2 to the power supply unit 3 are also different.
  • a relationship correspondence table may be stored in the control signal output unit 2, and the relationship correspondence table stores respective data voltages and charging control signals corresponding to the respective data voltages.
  • the static display phase specifically includes: a charging compensation process P3 and a static display process P4. Specifically, in the charge compensation process P3, the gate line GATE stops outputting the gate scan signal, and the common voltage line VCOM stops loading the common voltage signal to be in a floating state. At this time, the control signal output unit 2 outputs a corresponding charging control signal to the power supply unit 3, and the power supply unit 3 charges the liquid crystal capacitor Clc according to the charging control signal, so that the first end Q and the second end P of the liquid crystal capacitor Clc are between The voltage difference is restored to Vdata-Vcom.
  • the power supply unit 3 stops charging the liquid crystal capacitor Clc, and the liquid crystal capacitor Clc continues to maintain the pixel circuit for display, but the voltage difference Vclc between the two ends of the liquid crystal capacitor Clc continues to drop again due to leakage current. That is, the liquid crystal capacitor Clc generates a voltage drop.
  • the static display process is the same as the duration of the normal display process P2, the voltage drop generated by the liquid crystal capacitor Clc is also the same.
  • the charging compensation process P3 and the static display process P4 are repeated, that is, the power supply unit 3 charges the liquid crystal capacitor Clc once every preset time (the time corresponding to the start of the current charging to the next charging start).
  • the pixel circuit can be statically displayed.
  • the time for the power supply unit 3 to perform a charge compensation process to the liquid crystal capacitor Clc is much less than the time of one static display process, so the preset time can be approximately equal to the time of performing the static display process P4, and is also approximately equal to The time corresponding to the process P2 is normally displayed.
  • the preset time can be set to
  • the pixel circuit provided by the present invention does not need to perform scanning (charging) in the static display stage, so that the overall power consumption of the display panel can be effectively reduced.
  • the data writing unit 1 includes a fifth transistor T5, the control electrode of the fifth transistor T5 is connected to the gate line GATE, the first electrode of the fifth transistor T5 is connected to the data line DATA, and the second electrode of the fifth transistor T5 is connected. It is connected to the first terminal Q of the liquid crystal capacitor Clc.
  • the fifth transistor T5 as an N-type transistor as an example, when the gate scan signal is a high level signal, the fifth transistor T5 is turned on, and the data signal is written to the first terminal Q of the liquid crystal capacitor Clc through the fifth transistor T5.
  • the data writing unit 1 further includes a storage capacitor Cst.
  • the first end of the storage capacitor Cst is connected to the first end Q of the liquid crystal capacitor Clc, and the second end of the storage capacitor Cst and the second end P of the liquid crystal capacitor Clc. connection.
  • the power supply unit 3 charges the liquid crystal capacitor Clc at a time interval. It can be effectively increased, and the number of charging times per unit time is reduced, thereby effectively reducing the power consumption of the pixel circuit in the static display stage, and the overall power consumption of the display panel is also correspondingly reduced.
  • control signal output unit 2 includes a data acquisition module 201 and a signal output module 202.
  • the data acquisition module 201 is connected to the data line DATA and the signal output module 202.
  • the signal output module 202 is connected to the power supply unit 3.
  • the data acquisition module 201 is configured to collect the data voltage supplied by the data line DATA to the pixel circuit.
  • the signal output module 202 is configured to query a charging control signal corresponding to the data voltage according to the pre-stored relationship correspondence table.
  • the pixel circuit further includes a switch unit 4 disposed between the power supply unit 3 and the first end Q of the liquid crystal capacitor Clc or between the power supply unit 3 and the second end P of the liquid crystal capacitor Clc. .
  • the switching unit 4 is used to control the on and off between the power supply unit 3 and the liquid crystal capacitor Clc. When the switching unit 4 is turned on, the power supply unit 3 can charge the liquid crystal capacitor Clc. Otherwise, the power supply unit 3 cannot charge the liquid crystal capacitor Clc.
  • the switching unit 4 includes a sixth transistor T6, the control electrode of the sixth transistor T6 is connected to the switch control signal line SCAN, and the first pole of the sixth transistor T6 is connected to the power supply unit 3.
  • the second pole of the sixth transistor T6 is connected to the first terminal Q of the liquid crystal capacitor Clc.
  • the switching unit 4 is disposed between the power supply unit 3 and the second end P of the liquid crystal capacitor Clc
  • the second pole of the sixth transistor T6 is connected to the second end P of the liquid crystal capacitor Clc.
  • control signal output unit 2 is often integrated in the chip of the display panel (located in the peripheral area of the display panel), and the power supply unit 3 is directly disposed in the pixel unit, in which case a corresponding signal needs to be set on the display panel.
  • the lead conductor transmits the charging control signal outputted by the control signal output unit 2 to each of the power supply units 3. At this time, an independent signal lead CONTROL is required for each pixel circuit, thereby increasing the amount of wiring on the display panel. .
  • the technical solution of the present invention can make one signal lead CONTROL correspond to a plurality of pixel circuits (for example, pixel circuits in the same column on the display panel) by providing the switching unit 4 in the pixel circuit.
  • the switching unit 4 in the target pixel circuit is turned on, and the switching unit 4 in the other pixel circuits is turned off, and the target pixel circuit is at this time.
  • the power supply unit 3 can perform charging process on the liquid crystal capacitor Clc through the switching unit 4 according to the charging control signal.
  • FIG. 3 is a schematic diagram of a circuit structure of a pixel circuit according to a second embodiment of the present invention.
  • the pixel circuit shown in FIG. 3 is a specific scheme based on the pixel circuit shown in FIG. 1.
  • the power supply unit 3 includes a first switch control module 301 and a charging power source 303, and the charging control signal includes a first control signal.
  • First switch control mode The block 301 is connected to the control signal output unit 2, the first terminal Q of the liquid crystal capacitor Clc, the second terminal P, and the first pole M and the second pole N of the charging power source 303.
  • the first switch control module 301 is configured to turn on the first pole M of the charging power source 303 and the first end Q of the liquid crystal capacitor Clc under the control of the first control signal, and connect the second pole N of the charging power source 303 with the liquid crystal capacitor
  • the second end P of the Clc is turned on for the charging power source 303 to positively charge the liquid crystal capacitor Clc until the voltage difference between the first terminal Q and the second terminal P of the liquid crystal capacitor Clc is Vdata-Vcom.
  • the first switch control module 301 includes a first transistor T1 and a second transistor T2.
  • the control electrode of the first transistor T1 is connected to the control signal output unit 2, the first pole of the first transistor T1 is connected to the first pole M of the charging power source 303, and the second pole of the first transistor T1 and the first end of the liquid crystal capacitor Clc Q connection.
  • the control electrode of the second transistor T2 is connected to the control signal output unit 2, the first pole of the second transistor T2 is connected to the second pole N of the charging power source 303, and the second pole of the second transistor T2 is connected to the second end of the liquid crystal capacitor Clc. P connection.
  • the first transistor T1, the second transistor T2, and the sixth transistor T6 are all N-type transistors, the first pole M of the charging power source 303 is a positive electrode, and the second pole N of the charging power source 303 is a negative electrode.
  • the charging control signal is at a high level, and both the first transistor T1 and the second transistor T2 are in an on state.
  • the switch control signal in the switch control line is also at a high level.
  • the first pole M of the charging power source 303 is connected to the first terminal Q of the liquid crystal capacitor Clc
  • the second pole N of the charging power source 303 is connected to the second terminal P of the liquid crystal capacitor Clc, that is, the charging power source 303 and the liquid crystal capacitor Clc
  • the liquid crystal capacitor Clc can be regarded as a path between the load in the circuit, and the charging power source 303 positively charges the liquid crystal capacitor Clc so that the voltage difference Vclc between the first end Q and the second end P of the liquid crystal capacitor Clc
  • the voltage difference between the first terminal Q and the second terminal P of the liquid crystal capacitor Clc is Vdata-Vcom.
  • the time during which the charging power source 303 positively charges the liquid crystal capacitor Clc can be controlled by adjusting the duty ratio of the charging control signal.
  • the charging control signal is at a high level, that is, the time corresponding to the forward charging. .
  • the power supply unit 3 further includes a filter capacitor Cwf.
  • the first end of the filter capacitor Cwf is connected to the first pole M of the charging power source 303, and the second end of the filter capacitor Cwf is connected to the second pole N of the charging power source 303.
  • the charging power source 303 is a photovoltaic cell.
  • the pixel circuit provided in this embodiment is a pixel circuit in the reflective display panel, and the photocell can be charged by external light, so that the photocell maintains the display panel for static screen display, thereby reducing the overall power consumption of the display panel.
  • FIG. 4 is a schematic diagram showing the circuit structure of a pixel circuit according to a third embodiment of the present invention.
  • the power supply is provided in the pixel circuit shown in FIG.
  • the unit 3 includes not only the first switch control module 301 and the charging power source 303 but also the second switch control module 302. Further, the charging control signal includes: a first control signal and a second control signal.
  • the second switch control module 302 is connected to the first end Q and the second end P of the control signal output unit 2, the liquid crystal capacitor Clc, and the first pole M and the second pole N of the charging power source 303.
  • the second switch control module 302 is configured to turn on the first pole M of the charging power source 303 and the second end P of the liquid crystal capacitor Clc under the control of the second control signal, and connect the second pole N of the charging power source 303 with the liquid crystal capacitor
  • the first terminal Q of the Clc is turned on for the charging power source 303 to reversely charge the liquid crystal capacitor Clc until the voltage difference Vclc between the first terminal Q and the second terminal P of the liquid crystal capacitor Clc is Vcom-Vdata.
  • the second switch control module 302 includes a third transistor T3 and a fourth transistor T4.
  • the control electrode of the third transistor T3 is connected to the control signal output unit 2, the first pole of the third transistor T3 is connected to the first pole M of the charging power source 303, and the second pole of the third transistor T3 is connected to the second end of the liquid crystal capacitor Clc. P connection.
  • the control electrode of the fourth transistor T4 is connected to the control signal output unit 2, and the first pole of the fourth transistor T4 is charged and charged.
  • the second pole N of the source 303 is connected, and the second pole of the fourth transistor T4 is connected to the first terminal Q of the liquid crystal capacitor Clc.
  • control signal output unit 2 is specifically configured to alternately output the first control signal to the first switch control module 301 and output the second control signal to the second switch control module 302.
  • the working process of the pixel circuit provided by this embodiment will be described in detail below with reference to the accompanying drawings. It is assumed that the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 in FIG. 4 are all N-type transistors, and the first pole M of the charging power source 303 is a positive electrode. The second pole N of the charging power source 303 is a negative pole.
  • the control signal output unit 2 outputs a first control signal to the gates of the first transistor T1 and the second transistor T2 through the first control signal line CONTROL_1, and to the third transistor T3 and the fourth transistor T4 through the second control signal line CONTROL_2.
  • the control pole outputs a second control signal.
  • FIG. 5 is a timing chart showing the operation of the pixel circuit shown in FIG. As shown in FIG. 5, the pixel circuit includes three working phases: a normal display phase, a first polarity static display phase, and a second polarity static display phase.
  • the normal display phase specifically includes a data writing process P1 and a normal display process P2, wherein the duration of the data writing process P1 is much smaller than the duration of the normal display process P2.
  • the gate line GATE outputs a gate scan signal at a high level, and at this time, the fifth transistor T5 is turned on, and the data voltage in the data line DATA is written to the liquid crystal through the fifth transistor T5.
  • the common voltage line VCOM is loaded with a common voltage, and the common voltage is written to the second end P of the liquid crystal capacitor Clc.
  • the pixel circuit displays the corresponding gray level, and the gray level displayed by the pixel circuit is updated.
  • the gate scan signal in the gate line GATE is at a low level, and the fifth transistor T5 is turned off.
  • the liquid crystal capacitor Clc continues to maintain the pixel circuit for display, but the voltage difference Vclc between the two ends of the liquid crystal capacitor Clc continues to decrease due to leakage current, that is, the liquid crystal capacitor Clc generates a voltage drop.
  • the duration of the normal display process P2 is a preset fixed time, for example At the end of the normal display process P2, the voltage difference Vclc between the two ends of the liquid crystal capacitor Clc drops to V1' (which can be obtained by experiment in advance).
  • the first control signal line CONTROL_1, the second control signal line CONTROL_2, and the switch control signal line SCAN are all in a floating state, that is, maintained at a low level.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are all in an off state.
  • the first polarity static display phase specifically includes a first polarity charge compensation process P5 and a first polarity static display process P6.
  • the gate line GATE and the common voltage line VCOM are both in a floating state, and the fifth transistor T5 is maintained in an off state.
  • the first control signal line CONTROL_1 is still in the floating state, and the first transistor T1 and the second transistor T2 maintain the off state.
  • the control signal output unit 2 outputs the second control signal through the second control signal line CONTROL_2, and the second control signal is at a high level, and the third transistor T3 and the fourth transistor T4 are in an on state.
  • the switch control signal line SCAN is loaded with a switch control signal (which is a scan signal), and the switch control signal is at a high level, and the sixth transistor T6 is in an on state.
  • the first pole M of the charging power source 303 is connected to the second terminal P of the liquid crystal capacitor Clc, and the second pole N of the charging power source 303
  • the liquid crystal molecules corresponding to the pixel circuit realize polarity inversion, but the gray scale displayed by the pixel circuit remains unchanged.
  • liquid crystal capacitor Clc is reversely charged by the charging power source 303 so that the voltage difference Vclc between the two ends of the liquid crystal capacitor Clc is decreased from V1' to V1, which can be obtained in advance by experiments, correspondingly
  • the time when the second control signal is at a high level can also be set in advance.
  • the second control signal outputted by the second control signal line CONTROL_2 is at a low level, and the third transistor T3 and the fourth transistor T4 are turned off.
  • the switch control signal in the switch control signal line SCAN is switched from a high level to a low level at a certain time.
  • the liquid crystal capacitor Clc continues to maintain the pixel circuit for display, but the voltage difference Vclc between both ends of the liquid crystal capacitor Clc continues to drop due to leakage current.
  • the duration of the first polarity static display process P6 is approximately equal to the duration of the normal display process P2. At the end of the first polarity static display process, the voltage difference Vclc between the two ends of the liquid crystal capacitor Clc drops to -V1' (which can be obtained by an experiment in advance).
  • the second polarity static display stage specifically includes: a second polarity charge compensation process P7 and a second polarity static display process P8.
  • the gate line GATE and the common voltage line VCOM are both in a floating state, and the fifth transistor T5 is maintained in an off state.
  • the second control signal line CONTROL_2 is in a floating state, and the third transistor T3 and the fourth transistor T4 are maintained in an off state.
  • the control signal output unit 2 outputs the first control signal through the first control signal line CONTROL_1, and the first control signal is at a high level, and the first transistor T1 and the second transistor T2 are in an on state.
  • the switch control signal in the switch control signal line SCAN is at a high level, and the sixth transistor T6 is in an on state.
  • the first pole M of the charging power source 303 is electrically connected to the first terminal Q of the liquid crystal capacitor Clc, and the second pole N of the charging power source 303 is The second terminal P of the liquid crystal capacitor Clc is turned on, and the charging power source 303 is positively charged to the liquid crystal capacitor Clc, so that the voltage difference Vclc between the first terminal Q and the second terminal P of the liquid crystal capacitor Clc is charged with the charging time.
  • the liquid crystal molecules corresponding to the pixel circuit again achieve polarity inversion, but the gray scale displayed by the pixel circuit remains unchanged.
  • the first control signal outputted by the first control signal line CONTROL_1 is at a low level, and the first transistor T1 and the second transistor T2 are turned off.
  • the switch control signal in the switch control signal line SCAN is switched from a high level to a low level at a certain time.
  • the liquid crystal capacitor Clc continues to maintain the pixel circuit for display, but the voltage difference Vclc between both ends of the liquid crystal capacitor Clc continues to drop due to leakage current.
  • the duration of the second polarity static display process P8 is approximately equal to the duration of the normal display process P2. At the end of the second polarity static display process, the voltage difference Vclc between the both ends of the liquid crystal capacitor Clc drops again to V1'.
  • the periods of the switch control signal, the first control signal, and the second control signal are equal and approximately equal to the duration of the normal display process P2.
  • the periods of the switch control signal, the first control signal, and the second control signal are both
  • control signal output unit 2 alternately outputs the second control signal and the first control signal to alternately perform the first polarity static display phase and the second polarity static display phase until the display screen of the display panel needs to be performed. Update.
  • the pixel circuit provided by the embodiment can realize pixel polarity inversion when performing static display, thereby effectively avoiding liquid crystal polarization.
  • the switch control signal line SCAN when the static display process is performed, although the switch control signal line SCAN needs to be repeatedly charged to provide the switch control signal, a certain power consumption is brought about, but due to the switch control signal
  • the frequency (less than or equal to 30 Hz) is less than the frequency of the prior art gate scan signal (typically 30 Hz). Therefore, the pixel circuit provided by the present invention consumes less power than the prior art.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all N-type transistors, and only In a preferred embodiment of the embodiment, the above-mentioned transistors can be simultaneously prepared by the same production process, thereby reducing the production process and shortening the production cycle. It should be known to those skilled in the art that by the type of transistor Variations and corresponding changes to the output signal of the control line to achieve the process of the various stages described above are all within the scope of the present invention.
  • the gate of the transistor specifically refers to the gate of the transistor
  • the first and second poles of the transistor refer to the source and drain of the transistor, respectively.
  • the source of the first extreme transistor is the drain of the second transistor
  • the drain of the first transistor is the source of the second transistor.
  • a fourth embodiment of the present invention provides a display panel, the display panel includes: a plurality of gate lines and a plurality of data lines arranged in a cross, the gate lines and the data lines define a plurality of pixel units, and each pixel unit corresponds to A pixel circuit is provided.
  • the pixel circuit is a pixel circuit provided by any one of the first embodiment to the third embodiment. For the corresponding content, refer to the description in the first embodiment to the third embodiment. No longer.
  • the display panel is a reflective display panel, so that when the photocell is included in the pixel circuit, the photocell in the pixel circuit can be charged by using external light, thereby reducing the power consumption of the display panel.
  • a fifth embodiment of the present invention provides a display device.
  • the display device includes the display panel provided in the fourth embodiment.
  • FIG. 6 is a flowchart of a driving method of a pixel circuit according to a sixth embodiment of the present invention.
  • the pixel circuit may be the pixel circuit provided in the first embodiment and the second embodiment.
  • the driving method of the pixel circuit includes:
  • Step S1 In the normal display stage, the data writing unit writes the data voltage in the data line to the first end of the liquid crystal capacitor under the control of the gate scan signal in the gate line, and the common voltage line is loaded with the common voltage signal. Writing a common voltage to the second end of the liquid crystal capacitor, the control signal output unit collecting the data voltage supplied to the pixel circuit by the data line, and generating a corresponding charging control signal according to the collected data voltage;
  • Step S2 In the static display phase, the gate line stops outputting the gate scan signal, the common voltage line stops loading the common voltage signal, and the power supply unit charges the liquid crystal capacitor according to the charging control signal, so that the first end and the second end of the liquid crystal capacitor The voltage difference between them is Vdata-Vcom, where Vdata is the data voltage and Vcom is the common voltage.
  • step S1 and step S2 See the corresponding description in the above first embodiment, and details are not described herein again.
  • FIG. 7 is a flowchart of a driving method of a pixel circuit according to a seventh embodiment of the present invention. As shown in FIG. 7, the pixel circuit provides a pixel circuit in the third embodiment, and the driving method of the pixel circuit includes :
  • Step S11 in the normal display stage, the data writing unit writes the data voltage in the data line to the first end of the liquid crystal capacitor under the control of the gate scan signal in the gate line, and the common voltage line is loaded with the common voltage signal.
  • the control signal output unit Writing a common voltage to the second end of the liquid crystal capacitor, the control signal output unit collecting the data voltage supplied to the pixel circuit by the data line, and generating a corresponding charging control signal according to the collected data voltage;
  • Step S12 The control signal output unit outputs a second control signal to the second switch control module, and the second switch control module turns on the first pole of the charging power source and the second end of the liquid crystal capacitor under the control of the second control signal.
  • the second pole of the charging power source is connected to the first end of the liquid crystal capacitor, so that the charging power source reversely charges the liquid crystal capacitor until the voltage difference between the first end and the second end of the liquid crystal capacitor is Vcom-Vdata;
  • Step S13 The control signal output unit outputs a first control signal to the first switch control module, and the first switch control module turns on the first pole of the charging power source and the first end of the liquid crystal capacitor under the control of the first control signal.
  • the second pole of the charging power source is connected to the second end of the liquid crystal capacitor, so that the charging power source is positively charged to the liquid crystal capacitor until the voltage difference between the first end and the second end of the liquid crystal capacitor is Vdata-Vcom;
  • step S11 for the specific processes of step S11, step S12, and step S13, refer to the corresponding description in the foregoing third embodiment, and details are not described herein again.

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Abstract

提供了一种像素电路及其驱动方法、一种显示面板和一种显示装置。该像素电路包括：数据写入单元（1）、液晶电容（Clc）、供电单元（3）和控制信号输出单元（2）；数据写入单元（1）用于在正常显示阶段时将数据线（DATA）中的数据电压写入液晶电容（Clc）的第一端（Q）；控制信号输出单元（2）用于在正常显示阶段时采集数据线（DATA）提供给像素电路的数据电压，并根据采集到的数据电压生成相应的充电控制信号，以及在静态显示阶段将充电控制信号发送至供电单元（3）；供电单元（3）用于根据充电控制信号向液晶电容（Clc）进行充电至其两端（Q、P）之间的电压差为Vdata-Vcom。在像素电路中，在静态显示阶段对液晶电容（Clc）进行充电，此时栅线（GATE）中无需加载扫描信号，从而可降低显示面板的功耗。

Description

像素电路及其驱动方法、显示面板和显示装置 技术领域
本发明涉及显示技术领域，特别涉及像素电路及其驱动方法、显示面板和显示装置。
背景技术
薄膜晶体管液晶显示(Thin Film Transistor Liquid Crystal Display，简称TFT-LCD)装置作为一种平板显示装置，因其具有体积小、功耗低、无辐射以及制作成本相对较低等特点，而越来越多地被应用于高性能显示领域当中。
液晶显示装置的阵列基板包括：交叉的多条栅线和多条数据线；以及由栅线和数据线交叉界定出呈矩阵形式排列的多个像素单元。在一帧画面显示的过程中，一般可以采用一定频率的驱动信号对栅线从上到下进行逐行扫描，使得上述像素单元逐行选通。在此情况下，数据线能够向选通的像素单元进行充电，从而控制液晶分子发生不同角度的偏转，以实现画面显示。
液晶显示装置进行画面显示的过程中，一般包含两种状态：正常画面显示和静态画面显示。在正常画面显示过程中，液晶显示装置一帧一帧地进行刷新，以更新画面的显示内容。在静态画面显示过程中，液晶显示装置同样一帧一帧地进行刷新，但是画面的显示内容没有变。
由上述内容可见，现有技术的液晶显示装置在进行静态画面显示时栅线中的扫描信号的充电频率与显示动态画面时栅线中的扫描信号的充电频率是相同的，即维持一个较高的充电频率，而栅线的充电频率越高则会使得液晶显示装置的整体功耗越大。因此，现有技术中液晶显示装置在显示静态画面时的整体功效较大。
发明内容
本发明提供一种像素电路及其驱动方法、一种显示面板和一种显示装置，用于解决现有技术中液晶显示装置在显示静态画面时的整体功效较大的问题，可有效地降低像素电路和显示面板的功耗。
为实现上述目的，本发明提供了一种像素电路，包括：数据写入单元、液晶电容、供电单元和控制信号输出单元；所述数据写入单元与栅线、数据线和所述液晶电容的第一端连接，所述液晶电容的第二端与公共电压线连接，所述控制信号输出单元与所述数据线和所述供电单元连接，所述供电单元与所述液晶电容的第一端和第二端连接；所述数据写入单元用于在正常显示阶段时，在栅线中的栅扫描信号的控制下，将所述数据线中的数据电压写入所述液晶电容的第一端；所述控制信号输出单元用于在正常显示阶段时采集所述数据线提供给所述像素电路的数据电压，并根据采集到的所述数据电压生成相应的充电控制信号，以及在静态显示阶段时将所述充电控制信号发送至所述供电单元；所述供电单元用于根据所述充电控制信号向所述液晶电容进行充电，直至所述液晶电容的第一端与第二端之间的电压差为Vdata-Vcom；其中，Vdata为所述数据电压的电压大小，Vcom为所述公共电压线输出的公共电压的电压大小。
可选地，所述供电单元包括第一开关控制模块和充电电源，所述充电控制信号包括第一控制信号；所述第一开关控制模块与所述控制信号输出单元、所述液晶电容的第一端、第二端以及所述充电电源的第一极、第二极连接；所述第一开关控制模块用于在所述第一控制信号的控制下，将所述充电电源的第一极与所述液晶电容的第一端接通，将所述充电电源的第二极与所述液晶电容的第二端接通，以供所述充电电源向所述液晶电容进行正向充电，直至所述液晶电容的第一端与第二端之间的电压差为Vdata-Vcom；所述充电电源的第一极与第二极之间具有固定电压差。
可选地，第一开关控制模块包括第一晶体管和第二晶体管；所述第一晶体管的控制极与所述控制信号输出单元连接，所述第一晶体管的第一极与所述充电电源的第一极连接，所述第一晶体管的第二极 与所述液晶电容的第一端连接；所述第二晶体管的控制极与所述控制信号输出单元连接，所述第二晶体管的第一极与所述充电电源的第二极连接，所述第二晶体管的第二极与所述液晶电容的第二端连接。
可选地，所述供电单元还包括第二开关控制模块，所述充电控制信号还包括第二控制信号；所述第二开关控制模块与所述控制信号输出单元、所述液晶电容的第一端、第二端以及所述充电电源的第一极、第二极连接；所述第二开关控制模块用于在所述第二控制信号的控制下，将所述充电电源的第一极与所述液晶电容的第二端接通，将所述充电电源的第二极与所述液晶电容的第一端接通，以供所述充电电源向所述液晶电容进行反向充电，直至所述液晶电容的第一端与第二端之间的电压差为Vcom-Vdata。
可选地，所述第二开关控制模块包括第三晶体管和第四晶体管；所述第三晶体管的控制极与所述控制信号输出单元连接，所述第三晶体管的第一极与所述充电电源的第一极连接，所述第三晶体管的第二极与所述液晶电容的第二端连接；所述第四晶体管的控制极与所述控制信号输出单元连接，所述第四晶体管的第一极与所述充电电源的第二极连接，所述第四晶体管的第二极与所述液晶电容的第一端连接。
可选地，所述控制信号输出单元具体用于交替向所述第一开关控制模块输出所述第一控制信号和向所述第二开关控制模块输出第二控制信号。
可选地，所述供电单元还包括滤波电容，所述滤波电容的第一端与所述充电电源的第一极连接，所述滤波电容的第二端与所述充电电源的第二极连接。
可选地，所述充电电源为光电池。
可选地，所述数据写入单元包括第五晶体管；所述第五晶体管的控制极与所述栅线连接，所述第五晶体管的第一极与数据线连接，所述第五晶体管的第二极与所述液晶电容的第一端连接。
可选地，所述数据写入单元还包括存储电容；所述存储电容的第一端与所述液晶电容的第一端连接，所述存储电容的第二端与所述液晶电容的第二端连接。
可选地，所述像素电路还包括开关单元，所述开关单元设置于所述供电单元与所述液晶电容的第一端之间，或设置于所述供电单元与所述液晶电容的第二端之间；所述开关单元用于控制所述供电单元与所述液晶电容之间的通断。
可选地，所述开关单元包括第六晶体管；所述第六晶体管的控制极与开关控制信号线连接，所述第六晶体管的第一极与所述供电单元连接；当所述开关单元设置于所述供电单元与所述液晶电容的第一端之间时，所述第六晶体管的第二极与所述液晶电容的第一端连接；当所述开关单元设置于所述供电单元与所述液晶电容的第二端之间时，所述第六晶体管的第二极与所述液晶电容的第二端连接。
可选地，所述控制信号输出单元包括数据采集模块和信号输出模块；所述数据采集模块与所述数据线和所述信号输出模块连接，所述信号输出模块与所述供电单元连接；所述数据采集模块用于采集所述数据线提供给所述像素电路的所述数据电压；所述信号输出模块用于根据预先存储的关系对应表查询出与所述数据电压对应的充电控制信号。
可选地，所述像素电路中的各晶体管均为N型晶体管。
为实现上述目的，本发明提供了一种显示面板，包括上述的像素电路。
可选地，所述显示面板为反射式显示面板。
为实现上述目的，本发明提供了一种显示装置，包括上述的显示面板。
为实现上述目的，本发明提供了一种上述像素电路的驱动方法，所述像素电路的驱动方法包括：在正常显示阶段，所述数据写入单元在栅线中的栅扫描信号的控制下，将所述数据线中的数据电压写入所述液晶电容的第一端，公共电压线中加载有公共电压信号以向所述液晶电容的第二端写入公共电压，所述控制信号输出单元采集所述数据线提供给所述像素电路的数据电压，并根据采集到的所述数据电压生成相应的充电控制信号；在静态显示阶段，栅线停止输出栅扫描信号，公共电压线停止加载公共电压信号，所述供电单元根据所述充电控制 信号向所述液晶电容进行充电，直至所述液晶电容的第一端与第二端之间的电压差为Vdata-Vcom，其中，Vdata为所述数据电压，Vcom为所述公共电压。
可选地，当所述供电单元包括第一开关控制模块、第二开关控制模块时，所述充电控制信号包括第一控制信号和第二控制信号；在静态显示阶段，所述控制信号输出单元向所述第二开关控制模块输出第二控制信号，所述第二开关控制模块在所述第二控制信号的控制下，将所述充电电源的第一极与所述液晶电容的第二端接通，将所述充电电源的第二极与所述液晶电容的第一端接通，从而所述充电电源向所述液晶电容进行反向充电，直至所述液晶电容的第一端与第二端之间的电压差为Vcom-Vdata；所述控制信号输出单元向所述第一开关控制模块输出第一控制信号，所述第一开关控制模块在所述第一控制信号的控制下，将所述充电电源的第一极与所述液晶电容的第一端接通，将所述充电电源的第二极与所述液晶电容的第二端接通，从而所述充电电源向所述液晶电容进行正向充电，直至所述液晶电容的第一端与第二端之间的电压差为Vdata-Vcom；交替执行所述控制信号输出单元向所述第二开关控制模块输出第二控制信号的步骤和所述控制信号输出单元向所述第一开关控制模块输出第一控制信号的步骤。
本发明提供了一种像素电路及其驱动方法、包含该像素电路的显示面板和包含该显示面板的显示装置，其中该像素电路包括：数据写入单元、液晶电容、供电单元和控制信号输出单元；数据写入单元用于在正常显示阶段时，在栅线中的栅扫描信号的控制下，将数据线中的数据电压写入液晶电容的第一端；控制信号输出单元用于在正常显示阶段时采集数据线提供给像素电路的数据电压，并根据采集到的数据电压生成相应的充电控制信号，以及在静态显示阶段时将充电控制信号发送至供电单元；供电单元用于根据充电控制信号向液晶电容进行充电，直至液晶电容的第一端与第二端之间的电压差为Vdata-Vcom。本发明技术方案通过在像素电路中设置供电单元和控制信号输出单元，以在静态显示阶段对液晶电容进行充电，此时栅线中 无需加载扫描信号，从而可有效降低显示面板的整体功耗。
附图说明
图1为本发明的第一实施例提供的一种像素电路的电路结构示意图。
图2为图1所示的像素电路的工作时序图。
图3为本发明的第二实施例提供的一种像素电路的电路结构示意图。
图4为本发明的第三实施例提供的一种像素电路的电路结构示意图。
图5为图4所示的像素电路的工作时序图。
图6为本发明的第六实施例提供的一种像素电路的驱动方法的流程图；
图7为本发明的第七实施例提供的一种像素电路的驱动方法的流程图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的像素电路及其驱动方法、显示面板和显示装置进行详细描述。
图1为本发明的第一实施例提供的一种像素电路的电路结构示意图。如图1所示，该像素电路包括：数据写入单元1、液晶电容Clc、供电单元3和控制信号输出单元2。
该实施例中，数据写入单元1与栅线GATE、数据线DATA和液晶电容Clc的第一端Q连接，用于在正常显示阶段时，在栅线GATE中的栅扫描信号的控制下，将数据线DATA中的数据电压写入液晶电容Clc的第一端Q。
液晶电容Clc的第二端P与公共电压线VCOM连接，用于在其两端加载有电压时产生相应的电场，以控制液晶分子发生相应角度的偏转。
控制信号输出单元2与数据线DATA和供电单元3连接，用于在正常显示阶段时采集数据线DATA提供给像素电路的数据电压，并根据采集到的数据电压生成相应的充电控制信号，以及在静态显示阶段时将充电控制信号发送至供电单元3。
供电单元3与液晶电容Clc的第一端Q和第二端P连接，用于根据充电控制信号向液晶电容Clc进行充电，以使得液晶电容Clc的第一端Q与第二端P之间的电压差为Vdata-Vcom。Vdata为数据电压的电压大小，Vcom为公共电压线VCOM输出的公共电压的电压大小。
为使得本领域技术人员更好地理解本发明，下面将结合附图来对本发明的技术方案进行描述。图2为图1所示的像素电路的工作时序图。如图2所示，该像素电路包括两个工作阶段：正常显示阶段和静态显示阶段。
正常显示阶段具体包括：数据写入过程P1和正常显示过程P2。具体地，在数据写入过程P1中，栅线GATE输出栅扫描信号且栅扫描信号处于高电平，数据写入单元1在栅扫描信号的控制下，将数据线DATA中的数据电压写入至液晶电容Clc的第一端Q。公共电压线VCOM中加载有公共电压，公共电压写入至液晶电容Clc的第二端P。此时，液晶电容Clc的两端之间的电压差(即，第一端Q与第二端P之间的电压差)为Vclc＝Vdata-Vcom。假定Vdata-Vcom的大小为V1，像素电路显示出相应的灰阶，像素电路显示的灰阶完成更新(对于整个显示面板而言，显示面板的画面进行更新)。在正常显示过程P2中，栅扫描信号处于低电平，液晶电容Clc继续维持该像素电路进行显示，但是液晶电容Clc的两端之间的电压差Vclc会因为漏电流而持续下降，即液晶电容Clc产生压降。
需要说明的是，在实际应用中，该正常显示过程P2的时长设计为一个固定时长，且需要满足在该固定时长内人眼不会识别出像素电路显示的灰阶因液晶电容Clc的压降而发生的变化，即压降带来的灰阶变化不超过人眼对亮度的最小可识别能力。该固定时长可根据实际经验来设置。本发明中，该固定时长可设置为
Figure PCTCN2016090396-appb-000001
此外，在正常显示过程P2中，对于不同的数据电压，液晶电容Clc产生的压降是不同的。在本发明中，可以通过提前实验以获取到液晶电容Clc的第一端Q上加载了各灰阶的数据电压时对应的液晶电容Clc在正常显示过程P2中产生的压降大小，并可以建立数据电压与液晶电容Clc产生的压降的一一对应关系。
与此同时，控制信号输出单元2采集数据线DATA提供给像素电路的数据电压，并根据采集到的数据电压生成相应的充电控制信号。
需要说明的是，对于不同的数据电压，液晶电容Clc产生的压降不同，因此在后续将液晶电容Clc的两端之间的电压差Vclc补偿至Vdata-Vcom的过程中，需要供电单元3向液晶电容Clc进行充电的充电量也不同。相应地，控制信号输出单元2发送至供电单元3的充电控制信号也是不同的。为此，可以在控制信号输出单元2中存储一个关系对应表，该关系对应表中存储有各数据电压及各数据电压对应的充电控制信号。
静态显示阶段具体包括：充电补偿过程P3和静态显示过程P4。具体地，在充电补偿过程P3中，栅线GATE停止输出栅扫描信号，公共电压线VCOM停止加载公共电压信号而处于浮接(Floating)状态。此时，控制信号输出单元2向供电单元3输出相应的充电控制信号，供电单元3根据充电控制信号向液晶电容Clc进行充电，以使得液晶电容Clc的第一端Q与第二端P之间的电压差恢复至Vdata-Vcom。在静态显示过程P4中，供电单元3停止向液晶电容Clc进行充电，液晶电容Clc继续维持该像素电路进行显示，但是液晶电容Clc的两端之间的电压差Vclc会因为漏电流而再次持续下降，即液晶电容Clc产生压降。当静态显示过程与正常显示过程P2的持续时间相同时，则液晶电容Clc所产生的压降也相同。
在后续过程中，重复上述充电补偿过程P3和静态显示过程P4，即每隔预设时间(本次充电开始至下一次充电开始所对应的时间)供电单元3会向液晶电容Clc进行一次充电，可实现像素电路进行静态显示。在实际应用中，供电单元3向液晶电容Clc进行一次充电补偿过程的时间远远小于一次静态显示过程的时间，因此上述预设时间可 近似等于进行一次静态显示过程P4的时间，同时也近似等于正常显示过程P2所对应的时间。具体地，该预设时间可设置为
Figure PCTCN2016090396-appb-000002
由上述内容可见，本发明提供的像素电路在静态显示阶段中，栅线GATE无需进行扫描(充电)，从而可有效降低显示面板的整体功耗。
可选地，数据写入单元1包括第五晶体管T5，第五晶体管T5的控制极与栅线GATE连接，第五晶体管T5的第一极与数据线DATA连接，第五晶体管T5的第二极与液晶电容Clc的第一端Q连接。以第五晶体管T5为N型晶体管为例，当栅扫描信号为高电平信号时，则第五晶体管T5导通，数据信号通过第五晶体管T5写入至液晶电容Clc的第一端Q。
进一步可选地，数据写入单元1还包括存储电容Cst，存储电容Cst的第一端与液晶电容Clc的第一端Q连接，存储电容Cst的第二端与液晶电容Clc的第二端P连接。在本发明中，通过设置存储电容Cst可有效地降低液晶电容Clc的两端之间的电压差的下降速度，此时在静态显示阶段中，供电单元3对液晶电容Clc进行充电补偿的时间间隔可有效增加，单位时间内充电次数减少，从而可有效降低像素电路在静态显示阶段的功耗，显示面板的整体功耗也相应降低。
可选地，控制信号输出单元2包括数据采集模块201和信号输出模块202。数据采集模块201与数据线DATA和信号输出模块202连接。信号输出模块202与供电单元3连接。数据采集模块201用于采集数据线DATA提供给像素电路的数据电压。信号输出模块202用于根据预先存储的关系对应表查询出与数据电压对应的充电控制信号。
可选地，该像素电路还包括开关单元4，开关单元4设置于供电单元3与液晶电容Clc的第一端Q之间，或设置于供电单元3与液晶电容Clc的第二端P之间。开关单元4用于控制供电单元3与液晶电容Clc之间的通断。当开关单元4导通时，供电单元3可向液晶电容Clc进行充电。否则，供电单元3无法对液晶电容Clc进行充电。
进一步可选地，开关单元4包括第六晶体管T6，第六晶体管T6的控制极与开关控制信号线SCAN连接，第六晶体管T6的第一极与供电单元3连接。当开关单元4设置于供电单元3与液晶电容Clc的第一端Q之间时，第六晶体管T6的第二极与液晶电容Clc的第一端Q连接。当开关单元4设置于供电单元3与液晶电容Clc的第二端P之间时，第六晶体管T6的第二极与液晶电容Clc的第二端P连接。
需要说明的是，图1中仅示例性地画出了开关单元4设置于供电单元3与液晶电容Clc的第一端Q之间的情况，对于开关单元4设置于供电单元3与液晶电容Clc的第二端P之间的情况未给出相应附图。
在实际应用中，控制信号输出单元2往往集成在显示面板的芯片(位于显示面板的周边区域)中，而供电单元3是直接设置在像素单元内，此时需要在显示面板上设置相应的信号引线CONTROL，以将控制信号输出单元2输出的充电控制信号传递至各供电单元3，此时，针对每一个像素电路均需要设置一条独立的信号引线CONTROL，从而增大了显示面板上的布线量。
为解决上述技术问题，本发明的技术方案通过在像素电路中设置开关单元4，可使得一条信号引线CONTROL对应于多个像素电路(例如：显示面板上处于同一列的像素电路)。具体地，当该信号引线CONTROL需要向某一目标像素电路传递充电控制信号时，该目标像素电路中的开关单元4导通，而其他像素电路中的开关单元4关断，此时目标像素电路中的供电单元3可根据充电控制信号通过开关单元4对液晶电容Clc执行充电的过程，此时即便其他像素电路中的供电单元3也接收到充电控制信号，但是由于对应的开关单元4处于关断状态，因此其他像素电路中的供电单元3无法执行对液晶电容Clc进行充电的过程。
图3为本发明的第二实施例提供的一种像素电路的电路结构示意图。如图3所示，图3所示的像素电路为基于图1所示的像素电路的一种具体方案。具体地，供电单元3包括第一开关控制模块301和充电电源303，充电控制信号包括第一控制信号。第一开关控制模 块301与控制信号输出单元2、液晶电容Clc的第一端Q、第二端P以及充电电源303的第一极M、第二极N连接。第一开关控制模块301用于在第一控制信号的控制下，将充电电源303的第一极M与液晶电容Clc的第一端Q导通，将充电电源303的第二极N与液晶电容Clc的第二端P导通，以供充电电源303向液晶电容Clc进行正向充电，直至液晶电容Clc的第一端Q与第二端P之间的电压差为Vdata-Vcom。充电电源303的第一极M与第二极N之间具有固定电压差，且该固定电压差大于数据电压的最大值。
进一步可选地，第一开关控制模块301包括第一晶体管T1和第二晶体管T2。第一晶体管T1的控制极与控制信号输出单元2连接，第一晶体管T1的第一极与充电电源303的第一极M连接，第一晶体管T1的第二极与液晶电容Clc的第一端Q连接。第二晶体管T2的控制极与控制信号输出单元2连接，第二晶体管T2的第一极与充电电源303的第二极N连接，第二晶体管T2的第二极与液晶电容Clc的第二端P连接。
图3所示的像素电路的工作时序可参见图2，具体工作过程可参见上述第一实施例中的内容，此处不再赘述。
下面将结合附图来对本实施例中的供电单元3对液晶电容Clc进行充电的原理进行详细说明。假定第一晶体管T1、第二晶体管T2和第六晶体管T6均为N型晶体管，充电电源303的第一极M为正极，充电电源303的第二极N为负极。
继续参见图2，在静态显示阶段的充电补偿过程中，充电控制信号处于高电平，此时第一晶体管T1和第二晶体管T2均处于导通状态。与此同时，开关控制线中的开关控制信号也处于高电平。此时，充电电源303的第一极M与液晶电容Clc的第一端Q连接，充电电源303的第二极N与液晶电容Clc的第二端P连接，即充电电源303与液晶电容Clc(液晶电容Clc在电路中可看作是负载)之间建立通路，充电电源303对液晶电容Clc进行正向充电，以使得液晶电容Clc的第一端Q与第二端P之间的电压差Vclc随着充电时间的增长而逐渐增大，直至液晶电容Clc的第一端Q与第二端P之间的电压差为 Vdata-Vcom。
需要说明的是，充电电源303对液晶电容Clc进行正向充电的时间可通过调整充电控制信号的占空比进行控制，具体地，充电控制信号处于高电平的时间即对应正向充电的时间。
可选地，供电单元3还包括滤波电容Cwf，滤波电容Cwf的第一端与充电电源303的第一极M连接，滤波电容Cwf的第二端与充电电源303的第二极N连接。通过在充电电源303的两端之间设置滤波电容Cwf，可使得充电电源303进行稳定输出，从而保证对液晶电容Clc进行充电的充电量的精准度。
可选地，充电电源303为光电池。此时，本实施例提供的像素电路为反射式显示面板中的像素电路，通过外部光线可对光电池进行充电，以供光电池维持显示面板进行静态画面显示，从而可降低显示面板的整体功耗。
图4为本发明的第三实施例提供的一种像素电路的电路结构示意图，如图4所示，与上述图3所示的像素电路相比，在图4所示的像素电路中，供电单元3不但包括第一开关控制模块301和充电电源303，还包括第二开关控制模块302。此外，充电控制信号包括：第一控制信号和第二控制信号。
具体地，第二开关控制模块302与控制信号输出单元2、液晶电容Clc的第一端Q、第二端P以及充电电源303的第一极M、第二极N连接。第二开关控制模块302用于在第二控制信号的控制下，将充电电源303的第一极M与液晶电容Clc的第二端P导通，将充电电源303的第二极N与液晶电容Clc的第一端Q导通，以供充电电源303向液晶电容Clc进行反向充电，直至液晶电容Clc的第一端Q与第二端P之间的电压差Vclc为Vcom-Vdata。
进一步可选地，第二开关控制模块302包括第三晶体管T3和第四晶体管T4。第三晶体管T3的控制极与控制信号输出单元2连接，第三晶体管T3的第一极与充电电源303的第一极M连接，第三晶体管T3的第二极与液晶电容Clc的第二端P连接。第四晶体管T4的控制极与控制信号输出单元2连接，第四晶体管T4的第一极与充电电 源303的第二极N连接，第四晶体管T4的第二极与液晶电容Clc的第一端Q连接。
此外，控制信号输出单元2具体用于交替向第一开关控制模块301输出第一控制信号、以及向第二开关控制模块302输出第二控制信号。
下面将结合附图来对本实施例提供的像素电路的工作过程进行详细描述。假定图4中的第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6均为N型晶体管，充电电源303的第一极M为正极，充电电源303的第二极N为负极。控制信号输出单元2通过第一控制信号线CONTROL_1向第一晶体管T1和第二晶体管T2的控制极输出第一控制信号，且通过第二控制信号线CONTROL_2向第三晶体管T3和第四晶体管T4的控制极输出第二控制信号。
图5为图4所示的像素电路的工作时序图。如图5所示，该像素电路包括三个工作阶段：正常显示阶段、第一极性静态显示阶段、第二极性静态显示阶段。
正常显示阶段具体包括数据写入过程P1和正常显示过程P2，其中，数据写入过程P1的持续时间远小于正常显示过程P2的持续时间。
具体地，在数据写入过程P1中，栅线GATE输出处于高电平的栅扫描信号，此时第五晶体管T5导通，将数据线DATA中的数据电压通过第五晶体管T5写入至液晶电容Clc的第一端Q。公共电压线VCOM中加载有公共电压，公共电压写入至液晶电容Clc的第二端P。此时，液晶电容Clc的两端之间的电压差Vclc＝Vdata-Vcom。假定Vdata-Vcom的大小为V1，像素电路显示出相应的灰阶，像素电路显示的灰阶完成更新。
在正常显示过程P2中，栅线GATE中的栅扫描信号处于低电平，第五晶体管T5截至。液晶电容Clc继续维持该像素电路进行显示，但是液晶电容Clc的两端之间的电压差Vclc会因为漏电流而持续下降，即液晶电容Clc产生压降。正常显示过程P2的持续时间为一个 预先设置的固定时间，例如
Figure PCTCN2016090396-appb-000003
在该正常显示过程P2结束时，液晶电容Clc的两端之间的电压差Vclc会下降至V1’(可以通过提前实验而获取到)。
需要说明的是，在整个正常显示阶段中，第一控制信号线CONTROL_1、第二控制信号线CONTROL_2和开关控制信号线SCAN均处于浮接状态，即维持低电平。相应地，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第六晶体管T6均处于截止状态。
第一极性静态显示阶段具体包括第一极性充电补偿过程P5和第一极性静态显示过程P6。
在第一极性充电补偿过程P5中，栅线GATE和公共电压线VCOM均处于浮接状态，第五晶体管T5维持截止状态。此时，第一控制信号线CONTROL_1仍处于浮接状态，第一晶体管T1和第二晶体管T2维持截止状态。控制信号输出单元2通过第二控制信号线CONTROL_2输出第二控制信号，且第二控制信号处于高电平，第三晶体管T3和第四晶体管T4处于导通状态。与此同时，开关控制信号线SCAN中加载有开关控制信号(为一个扫描信号)，且开关控制信号处于高电平，第六晶体管T6处于导通状态。
由于第三晶体管T3、第四晶体管T4和第六晶体管T6均处于导通状态，则充电电源303的第一极M与液晶电容Clc的第二端P接通，充电电源303的第二极N与液晶电容Clc的第一端Q接通，充电电源303向液晶电容Clc进行反向充电，以使得液晶电容Clc的第一端Q与第二端P之间的电压差随着充电时间的增长而逐渐减小，直至液晶电容Clc的第一端Q与第二端P之间的电压差Vclc＝Vcom-Vdata＝-V1。该像素电路对应的液晶分子实现极性反转，但像素电路显示的灰阶保持不变。
需要说明的是，利用充电电源303对液晶电容Clc进行反向充电以使得液晶电容Clc的两端之间的电压差Vclc由V1’下降至V1的时间，可以通过预先实验提前获取，相应地第二控制信号处于高电平的时间也可以提前设置。
在第一极性静态显示过程P6中，第二控制信号线CONTROL_2输出的第二控制信号处于低电平，第三晶体管T3和第四晶体管T4截止。开关控制信号线SCAN中的开关控制信号在某一时刻由高电平切换为低电平。液晶电容Clc继续维持该像素电路进行显示，但是液晶电容Clc的两端之间的电压差Vclc会因为漏电流而持续下降。第一极性静态显示过程P6的持续时间与正常显示过程P2的持续时间近似相等。在该第一极性静态显示过程结束时，液晶电容Clc的两端之间的电压差Vclc会下降至-V1’(可以通过提前实验而获取到)。
第二极性静态显示阶段具体包括：第二极性充电补偿过程P7和第二极性静态显示过程P8。
在第二极性充电补偿过程P7中，栅线GATE和公共电压线VCOM均处于浮接状态，第五晶体管T5维持截止状态。此时，第二控制信号线CONTROL_2处于浮接状态，第三晶体管T3和第四晶体管T4维持截止状态。控制信号输出单元2通过第一控制信号线CONTROL_1输出第一控制信号，且第一控制信号处于高电平，第一晶体管T1和第二晶体管T2处于导通状态。与此同时，开关控制信号线SCAN中的开关控制信号处于高电平，第六晶体管T6处于导通状态。
由于第一晶体管T1、第二晶体管T2和第六晶体管T6均处于导通状态，则充电电源303的第一极M与液晶电容Clc的第一端Q导通，充电电源303的第二极N与液晶电容Clc的第二端P导通，充电电源303向液晶电容Clc进行正向充电，以使得液晶电容Clc的第一端Q与第二端P之间的电压差Vclc随着充电时间的增长而逐渐增大，直至液晶电容Clc的第一端Q与第二端P之间的电压差Vclc＝Vdata-Vcom＝V1。该像素电路对应的液晶分子再次实现极性反转，但像素电路显示的灰阶保持不变。
需要说明的是，利用充电电源303对液晶电容Clc进行正向充电以使得液晶电容Clc的两端之间的电压差Vclc由-V1’上升至V1的时间，可以通过预先实验提前获取，即第一控制信号处于高电平的时间也可以提前设置。
在第二极性静态显示过程P8中，第一控制信号线CONTROL_1输出的第一控制信号处于低电平，第一晶体管T1和第二晶体管T2截止。开关控制信号线SCAN中的开关控制信号在某一时刻由高电平切换为低电平。液晶电容Clc继续维持该像素电路进行显示，但是液晶电容Clc的两端之间的电压差Vclc会因为漏电流而持续下降。第二极性静态显示过程P8的持续时间与正常显示过程P2的持续时间近似相等。在该第二极性静态显示过程结束时，液晶电容Clc的两端之间的电压差Vclc会再次下降至V1’。
需要说明的是，在本实施例中，开关控制信号、第一控制信号和第二控制信号的周期相等，且近似等于正常显示过程P2的持续时间。可选地，开关控制信号、第一控制信号和第二控制信号的周期均为
Figure PCTCN2016090396-appb-000004
在后续显示过程中，控制信号输出单元2交替输出第二控制信号和第一控制信号，以交替进行第一极性静态显示阶段和第二极性静态显示阶段，直至显示面板的显示画面需要进行更新。
与上述第一实施例或第二实施例提供的像素电路相比，本实施例提供的像素电路在进行静态显示时可以实现像素极性反转，从而可有效避免液晶极化。
需要说明的是，本实施例中，在进行静态显示过程时，虽然开关控制信号线SCAN中需要反复进行充电以提供开关控制信号，从而会带来一定的功耗，但是，由于开关控制信号的频率(小于或等于30HZ)小于现有技术中栅扫描信号的频率(一般为30HZ)。因此，与现有技术相比，本发明提供的像素电路的功耗更低。
需要补充说明的是，本实施例中第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6均为N型晶体管的情况，仅为本实施例中的一种优选方式，此时可采用同一生产工序同时制备出上述各晶体管，从而可减少生产工序，缩短生产周期。本领域技术人员应该知晓的是，通过对晶体管的类型进行 变化以及对控制线的输出信号进行相应变化，以实现上述各阶段的过程的技术方案，均应属于本发明保护的范围。
此外，在本发明中，晶体管的控制极具体是指晶体管的栅极，晶体管的第一极和第二极分别是指晶体管的源极和漏极。当第一极为晶体管的源极时，则第二极为晶体管的漏极；当第一极为晶体管的漏极时，则第二极为晶体管的源极。
本发明的第四实施例提供了一种显示面板，该显示面板包括：交叉设置的多条栅线和多条数据线，栅线和数据线限定出多个像素单元，每个像素单元内对应设置有像素电路，该像素电路采用上述第一实施例至第三实施例中的任一实施例提供的像素电路，相应内容可参见上述第一实施例至第三实施例中的描述，此处不再赘述。
可选地，该显示面板为反射式显示面板，以在像素电路中包括光电池时，可利用外部光线对像素电路中的光电池进行充电，从而可降低显示面板的功耗。
本发明的第五实施例提供了一种显示装置，该显示装置包括上述第四实施例提供的显示面板，相应内容可参见上述第四实施例中的描述，此处不再赘述。
图6为本发明的第六实施例提供的一种像素电路的驱动方法的流程图，如图6所示，该像素电路可为上述第一实施例、第二实施例中提供的像素电路，该像素电路的驱动方法包括：
步骤S1、在正常显示阶段，数据写入单元在栅线中的栅扫描信号的控制下，将数据线中的数据电压写入液晶电容的第一端，公共电压线中加载有公共电压信号以向液晶电容的第二端写入公共电压，控制信号输出单元采集数据线提供给像素电路的数据电压，并根据采集到的数据电压生成相应的充电控制信号；
步骤S2、在静态显示阶段，栅线停止输出栅扫描信号，公共电压线停止加载公共电压信号，供电单元根据充电控制信号向液晶电容进行充电，以使得液晶电容的第一端与第二端之间的电压差为Vdata-Vcom，其中，Vdata为数据电压，Vcom为公共电压。
需要说明的是，对于上述步骤S1和步骤S2的具体过程，可参 见上述第一实施例中的相应描述，此处不再赘述。
图7为本发明的第七实施例提供的一种像素电路的驱动方法的流程图，如图7所示，该像素电路为上述第三实施例中提供像素电路，该像素电路的驱动方法包括：
步骤S11、在正常显示阶段，数据写入单元在栅线中的栅扫描信号的控制下，将数据线中的数据电压写入液晶电容的第一端，公共电压线中加载有公共电压信号以向液晶电容的第二端写入公共电压，控制信号输出单元采集数据线提供给像素电路的数据电压，并根据采集到的数据电压生成相应的充电控制信号；
步骤S12、控制信号输出单元向第二开关控制模块输出第二控制信号，第二开关控制模块在第二控制信号的控制下，将充电电源的第一极与液晶电容的第二端接通，将充电电源的第二极与液晶电容的第一端接通，从而充电电源向液晶电容进行反向充电，直至液晶电容的第一端与第二端之间的电压差为Vcom-Vdata；
步骤S13、控制信号输出单元向第一开关控制模块输出第一控制信号，第一开关控制模块在第一控制信号的控制下，将充电电源的第一极与液晶电容的第一端接通，将充电电源的第二极与液晶电容的第二端接通，从而充电电源向液晶电容进行正向充电，直至液晶电容的第一端与第二端之间的电压差为Vdata-Vcom；
交替执行上述步骤S12和步骤S13，直至显示面板的显示画面进行更新。
需要说明的是，对于步骤S11、步骤S12和步骤S13的具体过程，可参见上述第三实施例中的相应描述，此处不再赘述。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (19)

  1. 一种像素电路，包括：数据写入单元、液晶电容、供电单元和控制信号输出单元，其中
    所述数据写入单元与栅线、数据线和所述液晶电容的第一端连接，所述液晶电容的第二端与公共电压线连接，所述控制信号输出单元与所述数据线和所述供电单元连接，所述供电单元与所述液晶电容的第一端和第二端连接；
    所述数据写入单元用于在正常显示阶段时，在栅线中的栅扫描信号的控制下，将所述数据线中的数据电压写入所述液晶电容的第一端；
    所述控制信号输出单元用于在正常显示阶段时采集所述数据线提供给所述像素电路的数据电压，并根据采集到的所述数据电压生成相应的充电控制信号，以及在静态显示阶段时将所述充电控制信号发送至所述供电单元；
    所述供电单元用于根据所述充电控制信号向所述液晶电容进行充电，直至所述液晶电容的第一端与第二端之间的电压差等于所述数据电压与所述公共电压线输出的公共电压的差。
  2. 根据权利要求1所述的像素电路，其中，所述供电单元包括第一开关控制模块和充电电源，所述充电控制信号包括第一控制信号；
    所述第一开关控制模块与所述控制信号输出单元、所述液晶电容的第一端、第二端以及所述充电电源的第一极、第二极连接；
    所述第一开关控制模块用于在所述第一控制信号的控制下，将所述充电电源的第一极与所述液晶电容的第一端接通，将所述充电电源的第二极与所述液晶电容的第二端接通，以供所述充电电源向所述液晶电容进行正向充电，直至所述液晶电容的第一端与第二端之间的电压差等于所述数据电压与所述公共电压线输出的公共电压的差；
    所述充电电源的第一极与第二极之间具有固定电压差。
  3. 根据权利要求2所述的像素电路，其中，第一开关控制模块包括第一晶体管和第二晶体管；
    所述第一晶体管的控制极与所述控制信号输出单元连接，所述第一晶体管的第一极与所述充电电源的第一极连接，所述第一晶体管的第二极与所述液晶电容的第一端连接；
    所述第二晶体管的控制极与所述控制信号输出单元连接，所述第二晶体管的第一极与所述充电电源的第二极连接，所述第二晶体管的第二极与所述液晶电容的第二端连接。
  4. 根据权利要求2所述的像素电路，其中，所述供电单元还包括第二开关控制模块，所述充电控制信号还包括第二控制信号；
    所述第二开关控制模块与所述控制信号输出单元、所述液晶电容的第一端、第二端以及所述充电电源的第一极、第二极连接；
    所述第二开关控制模块用于在所述第二控制信号的控制下，将所述充电电源的第一极与所述液晶电容的第二端接通，将所述充电电源的第二极与所述液晶电容的第一端接通，以供所述充电电源向所述液晶电容进行反向充电，直至所述液晶电容的第一端与第二端之间的电压差等于所述公共电压与所述数据电压的差。
  5. 根据权利要求4所述的像素电路，其中，所述第二开关控制模块包括第三晶体管和第四晶体管；
    所述第三晶体管的控制极与所述控制信号输出单元连接，所述第三晶体管的第一极与所述充电电源的第一极连接，所述第三晶体管的第二极与所述液晶电容的第二端连接；
    所述第四晶体管的控制极与所述控制信号输出单元连接，所述第四晶体管的第一极与所述充电电源的第二极连接，所述第四晶体管的第二极与所述液晶电容的第一端连接。
  6. 根据权利要求4所述的像素电路，其中，所述控制信号输出 单元用于交替向所述第一开关控制模块输出所述第一控制信号和向所述第二开关控制模块输出第二控制信号。
  7. 根据权利要求2所述的像素电路，其中，所述供电单元还包括滤波电容，所述滤波电容的第一端与所述充电电源的第一极连接，所述滤波电容的第二端与所述充电电源的第二极连接。
  8. 根据权利要求2所述的像素电路，其中，所述充电电源为光电池。
  9. 根据权利要求1所述的像素电路，其中，所述数据写入单元包括第五晶体管；
    所述第五晶体管的控制极与所述栅线连接，所述第五晶体管的第一极与数据线连接，所述第五晶体管的第二极与所述液晶电容的第一端连接。
  10. 根据权利要求9所述的像素电路，其中，所述数据写入单元还包括存储电容；
    所述存储电容的第一端与所述液晶电容的第一端连接，所述存储电容的第二端与所述液晶电容的第二端连接。
  11. 根据权利要求1所述的像素电路，还包括开关单元，所述开关单元设置于所述供电单元与所述液晶电容的第一端之间，或设置于所述供电单元与所述液晶电容的第二端之间；
    所述开关单元用于控制所述供电单元与所述液晶电容之间的通断。
  12. 根据权利要求11所述的像素电路，其中，所述开关单元包括第六晶体管；
    所述第六晶体管的控制极与开关控制信号线连接，所述第六晶 体管的第一极与所述供电单元连接；
    当所述开关单元设置于所述供电单元与所述液晶电容的第一端之间时，所述第六晶体管的第二极与所述液晶电容的第一端连接；
    当所述开关单元设置于所述供电单元与所述液晶电容的第二端之间时，所述第六晶体管的第二极与所述液晶电容的第二端连接。
  13. 根据权利要求1中所述的像素电路，其中，所述控制信号输出单元包括数据采集模块和信号输出模块；
    所述数据采集模块与所述数据线和所述信号输出模块连接，所述信号输出模块与所述供电单元连接；
    所述数据采集模块用于采集所述数据线提供给所述像素电路的所述数据电压；
    所述信号输出模块用于根据预先存储的关系对应表查询出与所述数据电压对应的充电控制信号。
  14. 根据权利要求1-13中任一项所述的像素电路，其中，各晶体管均为N型晶体管。
  15. 一种显示面板，包括：权利要求1-14中任一项所述的像素电路。
  16. 根据权利要求15所述的显示面板，其中，所述显示面板为反射式显示面板。
  17. 一种显示装置，包括：权利要求15或16中所述的显示面板。
  18. 一种对权利要求1所述的像素电路进行驱动的驱动方法，所述驱动方法包括：
    在正常显示阶段，所述数据写入单元在栅线中的栅扫描信号的控制下，将所述数据线中的数据电压写入所述液晶电容的第一端，公 共电压线中加载有公共电压信号以向所述液晶电容的第二端写入公共电压，所述控制信号输出单元采集所述数据线提供给所述像素电路的数据电压，并根据采集到的所述数据电压生成相应的充电控制信号；
    在静态显示阶段，栅线停止输出栅扫描信号，公共电压线停止加载公共电压信号，所述供电单元根据所述充电控制信号向所述液晶电容进行充电，直至所述液晶电容的第一端与第二端之间的电压差等于所述数据电压与所述公共电压线输出的公共电压的差。
  19. 一种对权利要求4所述的像素电路进行驱动的驱动方法，其中，在静态显示阶段，所述驱动方法包括：
    所述控制信号输出单元向所述第二开关控制模块输出第二控制信号，所述第二开关控制模块在所述第二控制信号的控制下，将所述充电电源的第一极与所述液晶电容的第二端接通，将所述充电电源的第二极与所述液晶电容的第一端接通，从而所述充电电源向所述液晶电容进行反向充电，直至所述液晶电容的第一端与第二端之间的电压差为等于所述公共电压与所述数据电压的差；
    所述控制信号输出单元向所述第一开关控制模块输出第一控制信号，所述第一开关控制模块在所述第一控制信号的控制下，将所述充电电源的第一极与所述液晶电容的第一端接通，将所述充电电源的第二极与所述液晶电容的第二端接通，从而所述充电电源向所述液晶电容进行正向充电，直至所述液晶电容的第一端与第二端之间的电压差等于所述数据电压与所述公共电压的差；
    交替执行所述控制信号输出单元向所述第二开关控制模块输出第二控制信号的步骤和所述控制信号输出单元向所述第一开关控制模块输出第一控制信号的步骤。
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