WO2019019605A1 - 一种像素电路及其驱动方法、显示基板、显示装置 - Google Patents
一种像素电路及其驱动方法、显示基板、显示装置 Download PDFInfo
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- WO2019019605A1 WO2019019605A1 PCT/CN2018/075435 CN2018075435W WO2019019605A1 WO 2019019605 A1 WO2019019605 A1 WO 2019019605A1 CN 2018075435 W CN2018075435 W CN 2018075435W WO 2019019605 A1 WO2019019605 A1 WO 2019019605A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0202—Addressing of scan or signal lines
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
- G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3681—Details of drivers for scan electrodes suitable for passive matrices only
Definitions
- the present disclosure relates to a pixel circuit and a driving method thereof, a display substrate, and a display device.
- the liquid crystal display includes a plurality of pixel units surrounded by a plurality of data lines and a plurality of gate lines.
- the plurality of pixel units are arranged in an array, wherein each of the pixel units includes a pixel circuit, and the pixel circuit specifically includes: a thin film A transistor (English: Thin Film Transistor; abbreviated: TFT) and a liquid crystal capacitor, wherein the liquid crystal capacitor is formed by a pixel electrode and a common electrode in the pixel unit.
- TFT Thin Film Transistor
- the TFT is used for charging a liquid crystal capacitor
- the liquid crystal capacitor is used for controlling deflection of liquid crystal molecules, thereby realizing image display.
- the liquid crystal capacitor in each pixel circuit is charged by one TFT, and the gates of the TFTs in the plurality of pixel circuits in the same row are connected to the same gate line, and the gate lines are used to control the on and off of the TFT, the plurality of The source of the TFT in the pixel circuit is connected to different data lines, and the drain of each TFT is connected to the pixel electrode.
- the TFT is turned on under the control of the gate line, the data signal on the data line can be written to the pixel electrode to charge the liquid crystal capacitor.
- the drain of the TFT may output a leakage current to the data line, causing the voltage of the pixel electrode to decrease, affecting the deflection of the liquid crystal molecules, thereby affecting the image display effect of the display.
- the embodiment of the present invention provides a A pixel circuit, a driving method thereof, a display substrate, and a display device.
- the technical solution is as follows:
- a pixel circuit comprising:
- a gate line a data line, a first charging sub-circuit, a second charging sub-circuit, and a display sub-circuit;
- the first charging subcircuit is configured to be controllable to output a data signal from the data line to a charging node and to store a data signal from the data line;
- the second charging subcircuit is coupled to the charging node, the gate line, and the display subcircuit, respectively, and is configured to be controllable to output a data signal from the charging node to the display subcircuit.
- the first charging sub-circuit includes: a first transistor and a storage capacitor;
- a gate of the first transistor is connected to the gate line; or the pixel circuit further includes: a control line, a gate of the first transistor is connected to the control line;
- a first pole of the first transistor is connected to the data line, and a second pole of the first transistor is connected to the charging node;
- One end of the storage capacitor is connected to the charging node, and the other end of the storage capacitor is connected to a common electrode.
- the first charging sub-circuit includes: at least two charging sub-circuits connected in series, wherein each charging sub-circuit comprises: a first transistor and a storage capacitor;
- a gate of the first transistor is connected to the gate line; or the pixel circuit further includes: a control line, a gate of the first transistor is connected to the control line;
- a second pole of the first transistor is connected to one end of the storage capacitor, and another end of the storage capacitor is connected to a common electrode;
- a first pole of the first transistor in the first charge sub-subcircuit is connected to the data line, and a second pole of the first transistor in the second charge sub-circuit is Charging node connection;
- the first charging sub-subcircuit and the second charging sub-subcircuit are charging sub-circuits at both ends of the at least two series-connected charging sub-circuits.
- the second charging sub-circuit includes: a second transistor
- a gate of the second transistor is connected to the gate line, a first pole of the second transistor is connected to the charging node, and a second pole of the second transistor is connected to the display sub-circuit.
- a gate of the first transistor is connected to a control line, and the control line and the gate line are electrically connected to each other.
- the pixel circuit comprises: a plurality of control lines, and the gates of the first transistors in each of the charging sub-subcircuits are respectively connected to different control lines.
- the display sub-circuit includes a liquid crystal capacitor, and a capacitance value of the storage capacitor in the pixel circuit is greater than a capacitance value of the liquid crystal capacitor.
- a second aspect provides a driving method of a pixel circuit, the pixel circuit comprising: a gate line, a data line, a first charging sub-circuit, a second charging sub-circuit, and a display sub-circuit, wherein the second charging sub-circuit respectively Connected to the charging node, the gate line, and the display sub-circuit, the method comprising:
- the gate line provides a first level of gate drive signal, and the second charge subcircuit outputs a data signal from the charge node to the display subcircuit.
- the display sub-circuit includes a liquid crystal capacitor
- the pixel circuit further includes: a control line
- the first charging sub-circuit includes: a first transistor and a storage capacitor, a gate of the first transistor and the a second charging sub-circuit, comprising: a second transistor, a gate of the second transistor being connected to the gate line; a second pole of the first transistor and a second transistor One pole connection
- the controlling the first charging sub-circuit to output a data signal from the data line to the charging node and storing a data signal from the data line including:
- the control line provides a first level of gate drive signal, the first transistor is turned on, and the data line charges the storage capacitor through the first transistor.
- the gate line provides a first level of gate drive signal
- the second charge subcircuit outputs a data signal from the charging node to the display subcircuit, including:
- the gate line provides a first level of gate drive signal, the second transistor is turned on, and the storage capacitor charges the liquid crystal capacitor through the second transistor.
- the display subcircuit includes a liquid crystal capacitor
- the first charging subcircuit includes: a first transistor and a storage capacitor, a gate of the first transistor is connected to the gate line
- the second charging sub The circuit includes: a second transistor, a gate of the second transistor is connected to the gate line; a second pole of the first transistor is connected to a first pole of the second transistor;
- the first transistor and the second transistor are turned on when the gate line provides a gate driving signal of a first level, and the data line passes through the first transistor and the second transistor The liquid crystal capacitor is charged.
- the method further includes:
- the control line provides a second level of gate drive signal, and the charging node is disconnected from the data line;
- the gate line provides a second level of gate drive signal, the charging node being disconnected from the liquid crystal capacitor.
- a display substrate in a third aspect, includes: a plurality of gate lines, a plurality of data lines, and a plurality of pixel units surrounded by the gate lines and the data lines, The pixel units are arranged in an array, wherein each pixel unit includes a pixel circuit, and the pixel circuit is the pixel circuit of any of the first aspects.
- the display substrate further includes: a plurality of control lines, wherein the first charging sub-circuit in the pixel circuit is connected to the control line, and is located in the same column and two adjacent pixel units, and the first pixel unit a gate line connected to the second charging sub-circuit and a control line connected to the first charging sub-circuit in the second pixel unit are electrically connected to each other, wherein the first pixel unit and the second pixel unit follow the plurality of gates
- the lines are arranged in the scanning direction of the plurality of pixel units.
- a display device comprising the display substrate of any of the third aspects.
- the pixel circuit and the driving method thereof, the display substrate, and the display device are provided with a first charging sub-circuit and a second charging sub-circuit between the data line and the display sub-circuit in the pixel circuit, and the first charging sub-circuit is
- the charging node outputs a data signal
- the second charging sub-circuit outputs the data signal from the charging node to the display sub-circuit
- the first charging sub-circuit can store the data signal, so that the charging node can maintain the high voltage
- the second charging sub-circuit The differential pressure at the end is small, and the smaller differential pressure reduces the leakage current output to the data line, effectively reducing the influence of the leakage current on the deflection of the liquid crystal molecules, and ensuring the image display effect of the display.
- 1-1 is a structural block diagram of a pixel circuit according to an embodiment of the present invention.
- 1-2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention.
- FIG. 1-3 are schematic structural diagrams of another pixel circuit according to an embodiment of the present invention.
- 2-1 is a simulation diagram of voltage holding of a voltage of a second pole of a first transistor in a frame period after the pixel circuit shown in FIG. 1-2 charges the liquid crystal capacitor;
- FIG. 2-2 is a simulation diagram of the voltage holding condition of the voltage of the second pole of the second transistor in one frame time after the pixel circuit shown in FIG. 1-2 charges the liquid crystal capacitor;
- 3-1 is a schematic structural diagram of still another pixel circuit according to an embodiment of the present invention.
- 3-2 is a schematic structural diagram of still another pixel circuit according to an embodiment of the present invention.
- FIG. 4 is a schematic diagram of a pixel circuit in the related art
- FIG. 5 is a diagram of a driving method of a pixel circuit according to an embodiment of the present invention.
- 6-1 is a schematic diagram of a waveform of a gate driving signal applied to a gate line connected to a gate of a first transistor and a gate line connected to a gate of a second transistor according to an embodiment of the present invention
- FIG. 6-2 is a schematic diagram of waveforms of a gate driving signal connected to a gate line of a first transistor and a gate driving signal of a gate line connected to a gate of a second transistor according to an embodiment of the present invention
- FIG. 6-3 is a schematic diagram showing waveforms of a gate driving signal connected to a gate of a first transistor and a gate driving signal of a gate connected to a gate of the second transistor according to an embodiment of the present invention
- FIG. 6-4 is a schematic diagram of a voltage waveform of a second pole of a first transistor and a voltage waveform of a second pole of a second transistor during charging according to an embodiment of the present invention
- FIG. 7 is a schematic structural diagram of a display substrate according to an embodiment of the present invention.
- 8-1 is a schematic diagram of a plurality of gate lines and a plurality of control lines connected to a plurality of gate driving signal output ends on a display substrate according to an embodiment of the present invention
- 8-2 is a schematic diagram of signal waveforms outputted by respective gate driving signal output ends when a plurality of gate lines and a plurality of control lines on a display substrate are connected to a plurality of gate driving signal output ends according to an embodiment of the present disclosure
- 8-3 is a schematic diagram of a plurality of gate lines and a plurality of control lines on a display substrate connected to a plurality of gate drive signal output terminals, and each gate line and each control line in the display substrate are provided in an embodiment of the present invention.
- All of the transistors used in all embodiments of the present invention may be thin film transistors, field effect transistors or other devices having the same characteristics.
- the transistors employed in the embodiments of the present invention are mainly switching transistors according to their roles in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiment of the present invention, the source is referred to as a first stage, and the drain is referred to as a second stage. According to the form in the drawing, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
- the switching transistor used in the embodiment of the present invention may be an N-type switching transistor, wherein the N-type switching transistor is turned on when the gate is at a high potential, and is turned off when the gate is at a low potential.
- the plurality of signals in various embodiments of the present invention correspond to a first level and a second level. The first level and the second level only represent two state quantities of the potential of the signal, and do not mean that the first level or the second level in the full text has a specific value.
- the display product such as the smart wear adopts a low-power operation mode: the display panel of the display product adopts a refresh rate of 1 Hz (in English: Hz) (that is, the duration of displaying one frame of image is 1 second), and the black and white display A 1-bit bit drive is used in the panel to achieve black and white display on the display panel, and the color display panel is driven by 2 bits to realize 64-color display on the display panel.
- the working mode of the pixel electrode is increased by 60 times, and the risk of leakage increases accordingly.
- a display panel whose partial structure is made of amorphous silicon (English: Amorphous silicon; a-Si)
- the pixel electrode may output a leakage current to the data line after the transistor is turned off, the voltage of the pixel electrode is reduced. Therefore, it is difficult for the voltage of the pixel electrode to remain high for a long time (for example, 1 second), so that the capacitance of the liquid crystal capacitor is reduced, thereby affecting the deflection of the liquid crystal molecules in the display panel, resulting in an image display effect of the display product. affected.
- FIG. 1-1 is a structural block diagram of the pixel circuit.
- the pixel circuit may include:
- the gate line G1 the data line D, the first charging sub-circuit 01, the second charging sub-circuit 02, and the display sub-circuit 03.
- the first charging sub-circuit 01 is configured to be controllable to output a data signal from the data line D to the charging node P and to store the data signal from the data line D.
- the second charging sub-circuit 02 is connected to the charging node P, the gate line G1 and the display sub-circuit 03, respectively, which are configured to be controllable to output a data signal from the charging node P to the display sub-circuit 03.
- the pixel circuit provided by the embodiment of the present invention has a first charging sub-circuit and a second charging sub-circuit between the display sub-circuit and the data line, and the first charging sub-circuit outputs a data signal to the charging node.
- the first charging sub-circuit can store the data signal, so that the charging node can be kept at a high voltage, and the voltage difference across the second charging sub-circuit is small.
- the smaller differential pressure reduces the leakage current output to the data line, effectively reducing the influence of leakage current on the deflection of the liquid crystal molecules, and ensuring the image display effect of the display.
- the display sub-circuit 03 may include a liquid crystal capacitor Clc, and outputting the data signal from the charging node P to the display sub-circuit 03 is a process of charging the liquid crystal capacitor Clc. And since the liquid crystal capacitor Clc is formed by the pixel electrode and the common electrode in the pixel unit, the process of charging the liquid crystal capacitor Clc is actually a process of writing an electric signal to the pixel electrode.
- the structure of the first charging sub-circuit 01 can be implemented in various ways. The following two embodiments are described as an example:
- the first charging sub-circuit 01 may include: a first transistor M1 and a storage capacitor Cst.
- the gate of the first transistor M1 may be connected to the gate line G1 (this connection is not shown in FIGS. 1-2).
- the pixel circuit may further include: a control line G2, the gate of the first transistor M1 being connected to the control line G2.
- the first electrode of the first transistor M1 is connected to the data line D
- the second electrode of the first transistor M1 is connected to the charging node P
- one end of the storage capacitor Cst is connected to the charging node P
- the other end of the storage capacitor Cst is connected to the common electrode.
- the first charging sub-circuit 01 may include: at least two charging sub-circuits 011 connected in series (the first charging sub-circuit in FIG. 1-3 includes three charging devices).
- each of the charging sub-circuits 011 may include a first transistor M1 and a storage capacitor Cst.
- the gate of the first transistor M1 may be connected to the gate line G1 (this connection is not shown in FIGS. 1-3).
- the pixel circuit may further include: a control line G2, the gate of the first transistor M1 being connected to the control line G2.
- the second pole of the first transistor M1 is connected to one end of the storage capacitor Cst through the charging node P, and the other end of the storage capacitor Cst is connected to the common electrode.
- the second pole of the first thin film transistor M1 and the charging element away from the data line D in the charging sub-circuit 011 of the data line D in each two adjacent charging sub-circuits The first electrode of the first thin film transistor M1 is connected in the sub-circuit 011. And the first pole of the first transistor M1 in the first charging sub-circuit is connected to the data line D, and the second pole of the first transistor M1 in the second charging sub-circuit is connected to the charging node P.
- the first charging sub-circuit and the second charging sub-subcircuit are charging sub-circuits at both ends of at least two charging sub-circuits connected in series.
- the second charging sub-circuit 02 may include: a second transistor M2.
- the gate of the second transistor M2 is connected to the gate line G1, the first electrode of the second transistor M2 is connected to the charging node P, and the second electrode of the second transistor M2 is connected to the liquid crystal capacitor Clc in the display sub-circuit.
- a first transistor M1 and a second transistor M2 are spaced apart between the liquid crystal capacitor Clc and the data line D.
- the second transistor M2 is second.
- the pole is kept at a high potential, and at the same time, the second pole of the first transistor M1 is also kept at a high potential, and the voltage difference between the two is small, and the smaller voltage difference forms an obstacle when the output leakage current is caused, so that the second transistor
- the leakage current outputted to the data line D when M2 is turned off is reduced, thereby reducing the magnitude of the voltage decrease on one pole (ie, the pixel electrode) of the liquid crystal capacitor Clc connected to the second charging sub-circuit 02, thereby reducing
- the magnitude of the decrease in the capacitance of the liquid crystal capacitor Clc reduces the influence on the deflection of the liquid crystal molecules.
- the principle of reducing the leakage current outputted to the data line D when the second transistor M2 is turned off please refer to the principle, here is not Let me repeat.
- FIG. 2-1 shows the voltage holding of the voltage of the second pole of the first transistor in one frame time (for example, 1 second) after the pixel circuit shown in FIG. 1-2 charges the liquid crystal capacitor Clc.
- FIG. 2-2 shows the voltage holding condition of the voltage of the second pole of the second transistor in one frame time after the pixel circuit shown in FIG. 1-2 charges the liquid crystal capacitor Clc. Simulation diagram.
- the voltage of the second pole of the first transistor is only slightly reduced in one frame time after the completion of charging, and the voltage of the second pole of the second transistor is hardly reduced.
- the voltage of the second pole of the second transistor is the voltage of the pixel electrode, that is, when the first charging sub-circuit includes only the first transistor, it can be reduced.
- the amplitude of the pixel electrode voltage is reduced, and even the voltage of the pixel electrode is not reduced, thereby ensuring the image display effect of the display.
- the circuit of the pixel circuit at this time is relatively simple, and it is easy to implement control of the circuit.
- the gate of the first transistor and the gate of the second transistor may both be connected to the gate line G1.
- the control line and the gate line may also be electrically connected to each other.
- the two are electrically connected to each other, all of the transistors in each pixel circuit are turned on for the same time, and the data lines can simultaneously start charging a plurality of transistors.
- the pixel circuit may include: a plurality of control lines, and the gates of the first transistors in each of the charging sub-circuits may be respectively connected to different control lines, and the connection diagram thereof is shown in FIG. 3-2, as shown in FIG.
- the pixel circuit includes a control line G21, a control line G22, and a control line G23.
- the gates of the first transistors M1 of the three series-connected charge sub-circuits 011 are sequentially connected to the control line G21, the control line G22, and the control. Line G23 is connected.
- the time at which the plurality of transistors in the pixel circuit are turned on is different, and the data lines can charge the at least two transistors in series in accordance with the time when the transistors are turned on.
- the second pole of the second transistor may be connected to a storage capacitor Cst, and the storage capacitor Cst is connected in parallel with the liquid crystal capacitor Clc.
- the specific connection manner refer to the dotted line frame 03 in FIG. 3-2.
- the capacitance value of the storage capacitor in the pixel circuit is greater than the capacitance value of the liquid crystal capacitor.
- the larger the difference between the capacitance value of the storage capacitor and the capacitance value of the liquid crystal capacitor the smaller the voltage difference between the second pole of the second transistor and the second pole of the first transistor, and the second transistor leaks when it is turned off.
- the current can be small enough or even no leakage current, so that the voltage of the pixel electrode is reduced to a small enough or not to be reduced. Therefore, the better the voltage holding capacity of the pixel electrode is, the more the capacitance of the liquid crystal capacitor is reduced. The smaller or even not reduced, the more the normal deflection of the liquid crystal molecules can be ensured.
- a schematic diagram of a pixel circuit includes only one transistor M.
- the gate of the transistor M is connected to a gate line G.
- the first pole of the transistor M is connected to the data line D.
- the second pole is respectively connected to the liquid crystal capacitor Clc and the storage capacitor Cst.
- the voltage difference is the potential of the signal loaded on the data line and the second of the transistor
- the voltage difference of the pole potential for example, the voltage difference can be 5V
- the second pole of the transistor can easily output a leakage current to the data line, and under the influence thereof, the pixel electrode connected to the second pole of the transistor The voltage is reduced, resulting in poor voltage holding capability of the pixel electrode, so that the deflection of the liquid crystal molecules is greatly affected.
- the pixel circuit provided by the embodiment of the present invention has a first charging sub-circuit and a second charging sub-circuit between the display sub-circuit and the data line, and the first charging sub-circuit outputs a data signal to the charging node.
- the first charging sub-circuit can store the data signal, so that the charging node can be kept at a high voltage, and the voltage difference across the second charging sub-circuit is small.
- the smaller differential pressure reduces the leakage current output to the data line, thereby effectively reducing the magnitude of the voltage drop at the end of the connection between the liquid crystal capacitor and the second charging sub-circuit, thereby reducing the capacitance reduction of the liquid crystal capacitor.
- the amplitude effectively reduces the influence of leakage current on the deflection of liquid crystal molecules, ensures the image display effect of the display, and solves the related art that the pixel electrode cannot maintain its voltage at a high potential for 1 second or even longer. The problem.
- the driving method can be applied to the pixel circuit shown in any of FIG. 1-2, FIG. 1-3, FIG. 3-1, or FIG. 3-2.
- the pixel circuit may include: a gate line G1, a data line D, a first charging sub-circuit 01, a second charging sub-circuit 02, and a display sub-circuit 03, and the second charging sub-circuit 02 and the charging node P, the gate line G1, and the display, respectively
- the sub-circuit 03 is connected.
- the driving method of the pixel circuit may include:
- Step 501 Control the first charging sub-circuit to output a data signal from the data line to the charging node and store the data signal from the data line.
- Step 502 the gate line provides a gate drive signal of a first level, and the second charge sub-circuit outputs a data signal from the charging node to the display sub-circuit.
- Step 503 The control line provides a gate driving signal of a second level, and the charging node is disconnected from the data line.
- Step 504 The gate line provides a second level of gate driving signal, and the charging node is disconnected from the liquid crystal capacitor.
- the driving method of the pixel circuit controls the first charging sub-circuit to output a data signal from the data line to the charging node and stores the data signal from the data line, and the gate line provides the first level.
- a gate driving signal the second charging sub-circuit outputs a data signal from the charging node to the display sub-circuit
- a first charging sub-circuit and a second charging sub-circuit are interposed between the display sub-circuit and the data line
- the first charging sub- The circuit outputs a data signal to the charging node
- the second charging sub-circuit outputs the data signal from the charging node to the display sub-circuit
- the first charging sub-circuit can store the data signal, so that the charging node can maintain the high voltage
- the voltage difference across the circuit is small, and the small differential voltage reduces the leakage current output to the data line, thereby effectively reducing the magnitude of the voltage drop at the end of the connection between the liquid crystal capacitor and the second charging sub
- the display sub-circuit 03 may include a liquid crystal capacitor, and outputting the data signal from the charging contact to the display sub-circuit is a process of charging the liquid crystal capacitor.
- the first charging sub-circuit 01 may include: a first transistor M1 and a storage capacitor Cst, the first transistor M1 The gate is connected to the gate line G1 or the control line G2.
- the second charging sub-circuit 02 may include a second transistor M2. The gate of the second transistor M2 is connected to the gate line G1, and the second pole of the first transistor M1 is The first pole of the second transistor M2 is connected.
- the driving method of the pixel circuit can be divided into the following three achievable modes:
- the first implementation manner is: when the gate of the first transistor M1 is connected to the control line G2, and the gate of the second transistor M2 is connected to the gate line G1, the conduction state of the first transistor M1 and the second transistor M2, and
- the process of charging the liquid crystal capacitor Clc by the first charging sub-circuit 01 and the second charging sub-circuit 02 by the data line D may include, for example, two stages:
- the first transistor M1 In the first charging phase t1, when the control line G2 provides the gate driving signal of the first level, the first transistor M1 is turned on by the gate driving signal, and the data line D is charged by the first transistor M1 for the storage capacitor Cst. .
- the second transistor M2 In the second charging phase t2, when the gate line G1 provides the gate driving signal of the first level, the second transistor M2 is turned on by the gate driving signal, and the storage capacitor Cst charges the liquid crystal capacitor Clc through the second transistor M2. .
- the times of the two charging phases may completely overlap, partially overlap, or not overlap at all.
- the control line G2 and the gate of the gate of the first transistor M1 are connected.
- the waveform diagram of the gate drive signal loaded on the gate line G1 connected to the gate of the two transistor M2 please refer to FIG. 6-1, FIG. 6-2 and FIG. 6-3, respectively.
- the durations of the two charging phases may not be equal, the time of the two phases may overlap partially or not at all.
- the time of the two charging phases may not overlap at all, and the whole charging process is described.
- the charging process may refer to the time of the two phases completely. Non-overlapping processes.
- the charging process includes a first charging phase t1 and a second charging phase t2.
- the control line G2 provides a gate driving signal of a first level (for example, 10 volts), the first transistor M1 is turned on by the gate driving signal, and the data line D passes through the first transistor.
- M1 charges the second pole of the first transistor M1, that is, charges the storage capacitor Cst, so that the voltage of the second pole of the first transistor M1 (ie, a pole connected to the storage capacitor Cst) has been charged to the first high potential. (Example: 10 volts).
- the second transistor M2 In the second charging phase t2, when the gate line G1 provides the gate driving signal of the first level, the second transistor M2 is turned on by the gate driving signal, and the second pole of the first transistor M1 (that is, The storage capacitor Cst) charges the liquid crystal capacitor Clc through the second transistor M2 (ie, charges the pixel electrode) to charge the second electrode of the second transistor M2 and the pixel electrode to the second high potential.
- control line G2 provides a gate driving signal of a second level (for example, 0 volts), at which time the first transistor M1 is turned off, charging. Node P is disconnected from data line D.
- a second level for example, 0 volts
- the gate driving signal provided by the gate line G1 jumps to the second level, the second transistor M2 is turned off, and the charging node P is disconnected from the liquid crystal capacitor Clc.
- the gate driving signal provided by the control line G2 in the first charging phase t1 and the second charging phase t2, the gate driving signal provided by the gate line G1, the signal loaded on the data line D, and the second pole of the first transistor M1 Refer to Figure 6-4 for the voltage waveform and the voltage waveform of the second electrode of the second transistor M2.
- the amplitude of the first high potential is mainly determined by the potential of the data line D
- the amplitude of the second high potential is determined by the amplitude of the first high potential, the capacitance of the storage capacitor Cst, and the capacitance of the liquid crystal capacitor Clc. decided together.
- the capacitance value of the storage capacitor Cst and the capacitance value of the liquid crystal capacitor Clc are larger, the voltage difference between the second pole of the second transistor M2 and the second pole of the first transistor M1 is smaller, and thus,
- the capacitance value of the storage capacitor Cst can be set to be much larger than the capacitance value of the liquid crystal capacitor Clc.
- the capacitance value of the liquid crystal capacitor Clc can be set to 10 times the capacitance value of the storage capacitor Cst.
- the second high potential is obtained after a certain voltage drop on the basis of the first high potential
- the potential of the pixel electrode is obtained after a certain voltage drop on the basis of the second high potential.
- the manner compensates for the voltage drop such that the second high potential is closer to the first high potential and the potential of the pixel electrode is closer to the second high potential or even equal to the first high potential.
- the second implementation manner is: when the gate of the first transistor M1 and the gate of the second transistor M2 are both connected to the gate line G1, the conduction of the first transistor M1 and the second transistor M2, and the data line D pass
- the process of charging the liquid crystal capacitor Clc by the first charging sub-circuit 01 and the second charging sub-circuit 02 can be, for example:
- the gate line G1 to which the first transistor M1 and the second transistor M2 are connected provides the gate driving signal of the first level
- the first transistor M1 and the second transistor M2 are turned on by the gate driving signal
- the data line D charges the liquid crystal capacitor Clc through the first transistor M1 and the second transistor M2.
- a third implementation manner is: when the gate of the first transistor M1 is connected to the control line G2, the gate of the second transistor M2 is connected to the gate line G1, and the control line G2 and the gate line G1 are electrically connected to each other, the first transistor The conduction state of the M1 and the second transistor M2, and the process in which the data line D charges the liquid crystal capacitor Clc through the first charging sub-circuit 01 and the second charging sub-circuit 02, for example, may be:
- the gate line G1 (or the control line G2) supplies the gate driving signal of the first level
- the first transistor M1 and the second transistor M2 are turned on by the gate driving signal, and, in the first transistor M1 and During the turn-on of the second transistor M2, the data line D charges the liquid crystal capacitor Clc through the first transistor M1 and the second transistor M2.
- the first level is a high level with respect to the second level, for example, the first level is 10 volts, and the second level is 0 volts.
- the first charging sub-circuit 01 includes at least two charging sub-circuits 011 connected in series, and at least two charging sub-circuits 011 connected in series, the gate of the first transistor M1 in each charging sub-circuit 011
- the driving method of the pixel circuit is referred to the above-mentioned driving method, which will not be described in detail in the embodiment of the present invention.
- the driving method of the pixel circuit controls the first charging sub-circuit to output a data signal from the data line to the charging node and stores the data signal from the data line, and the gate line provides the first level.
- a gate driving signal the second charging sub-circuit outputs a data signal from the charging node to the display sub-circuit
- a first charging sub-circuit and a second charging sub-circuit are interposed between the display sub-circuit and the data line
- the first charging sub- The circuit outputs a data signal to the charging node
- the second charging sub-circuit outputs the data signal from the charging node to the display sub-circuit
- the first charging sub-circuit can store the data signal, so that the charging node can maintain the high voltage
- the voltage difference across the circuit is small, and the small differential voltage reduces the leakage current output to the data line, thereby effectively reducing the magnitude of the voltage drop at the end of the connection between the liquid crystal capacitor and the second charging sub
- FIG. 7 is a schematic structural diagram of a display substrate according to an embodiment of the present invention.
- the display substrate may include: a plurality of gate lines (the plurality of gate lines in the figure are G1, G3, and G5, respectively), a plurality of data lines (the plurality of gate data lines are D1, D2, and D3, respectively), and a plurality of pixel units surrounded by the gate lines and the data lines, wherein the plurality of pixel units are arranged in an array, wherein each The pixel unit includes a pixel circuit 0 (shown by a broken line in FIG. 7), and the pixel circuit can be a pixel circuit as shown in any of FIG. 1-2, FIG. 1-3, FIG. 3-1 or FIG. .
- the display substrate may further include: a plurality of control lines (the plurality of control lines in the figure are G2, G4, and G6, respectively), and the first charging sub-circuit in the pixel circuit is connected to the plurality of control lines Control of the connection between the gate line connected to the second charging sub-circuit of the pixel circuit in the first pixel unit and the first charging sub-circuit of the pixel circuit in the second pixel unit in two pixel units adjacent to each other in the same column
- the wires may be electrically connected to each other (the connection manner is not shown in the drawing), wherein the first pixel unit and the second pixel unit are arranged in a scanning direction of the plurality of pixel cells in accordance with the plurality of gate lines.
- the gate line G1 connected to the second charging sub-circuit of the pixel circuit in the first row of pixel units is The control lines G4 to which the first charging sub-circuits of the pixel circuits in the second row of pixel units are connected may be electrically connected to each other.
- the second transistor of the pixel circuit in the first pixel unit and the first transistor of the pixel circuit in the second pixel unit can be simultaneously turned on and charged, reducing the total charging time of the liquid crystal capacitor on the display substrate.
- the second charging sub-circuit of the pixel circuit in the first pixel unit and the first charging sub-circuit of the pixel circuit in the second pixel unit may be Each is connected to the same gate line, wherein the first pixel unit and the second pixel unit are arranged in a scanning direction of the plurality of pixel units according to the plurality of gate lines.
- the second charging sub-circuit of the pixel circuit in the first pixel unit and the first charging sub-circuit of the pixel circuit in the second pixel unit are both connected to the same gate line, the second charging is performed with respect to the pixel circuit in the first pixel unit.
- the case where the gate line connected to the electronic circuit and the control line connected to the first charging sub-circuit of the pixel circuit in the second pixel unit are different gate lines increases the aperture ratio of the display substrate.
- the gate line and the second charging sub-circuit of the pixel circuit in the first pixel unit are connected
- the control line connected to the first charging sub-circuit of the pixel circuit in the two-pixel unit may be connected to the same gate driving signal output end, wherein the first pixel unit and the second pixel unit are connected to the plurality of pixel units according to the plurality of gate lines
- the scanning direction is arranged.
- Figure 8-1 shows multiple gate lines (G1, G3, and G5) and multiple control lines (G2, G4, and G6) connected to multiple gate drive signal outputs (F1, F2, F3, and F4).
- the line G4 can be connected to the same gate drive signal terminal F2.
- each gate drive signal output terminal can be as shown in Figure 8-2, that is, each gate drive signal output terminal can sequentially output the first level gate drive signal.
- the waveform of the gate driving signal loaded on each gate line in the display substrate can be as shown in Figure 8-3.
- the gate lines connected to the same gate drive signal output are the same as the gate drive signals loaded on the control line.
- the first transistor in the first charging sub-circuit of the pixel circuit in the second transistor and the second pixel unit in the second charging sub-circuit of the pixel circuit in the first pixel unit can be simultaneously charged, thereby reducing the liquid crystal capacitance on the display substrate.
- the total charging time, and without increasing the number of gate drive signal output terminals, relatively reduces the production cost of the display substrate.
- the display substrate provided by the embodiment of the present invention includes a plurality of pixel units, each of which includes a pixel circuit, and each pixel circuit has a first interval between the display sub-circuit and the data line.
- a charging sub-circuit and a second charging sub-circuit the first charging sub-circuit outputs a data signal to the charging node, and after the second charging sub-circuit outputs the data signal from the charging node to the display sub-circuit, the first charging sub-circuit can store the data signal So that the charging node can be kept at a high voltage, and the voltage difference across the second charging sub-circuit is small, and the small differential voltage causes the leakage current to the data line to be reduced, thereby effectively reducing the liquid crystal capacitance and the
- the amplitude of the voltage reduction at one end of the connection of the charging sub-circuit further reduces the amplitude of the capacitance reduction of the liquid crystal capacitor, effectively reducing the influence of the leakage current on the deflection of the liquid crystal molecules, and
- the embodiment of the invention further provides a display device, which may include the display substrate shown in FIG. 7 or 8-1.
- the display device can be any product or component having a display function such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
- a person skilled in the art may understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium.
- the storage medium mentioned may be a read only memory, a magnetic disk or an optical disk or the like.
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Abstract
Description
Claims (14)
- 一种像素电路,包括:栅线、数据线、第一充电子电路、第二充电子电路和显示子电路;所述第一充电子电路被配置为可被控制以向充电节点输出来自所述数据线的数据信号并存储来自所述数据线的数据信号;所述第二充电子电路分别与所述充电节点、所述栅线和所述显示子电路连接,其被配置为可被控制以向所述显示子电路输出来自所述充电节点的数据信号。
- 根据权利要求1所述的像素电路,其中,所述第一充电子电路包括:第一晶体管和存储电容;所述第一晶体管的栅极与所述栅线连接;或者,所述像素电路还包括:控制线,所述第一晶体管的栅极与所述控制线连接;所述第一晶体管的第一极与所述数据线连接,所述第一晶体管的第二极与所述充电节点连接;所述存储电容的一端与所述充电节点连接,所述存储电容的另一端与公共电极连接。
- 根据权利要求1所述的像素电路,其中,所述第一充电子电路包括:至少两个串联的充电子子电路,每个充电子子电路包括:第一晶体管和存储电容;所述第一晶体管的栅极与所述栅线连接;或者,所述像素电路还包括:控制线,所述第一晶体管的栅极与所述控制线连接;所述第一晶体管的第二极与所述存储电容的一端连接,所述存储电容的另一端与公共电极连接;所述多个串联的充电子子电路中,第一充电子子电路中第一晶体管的第一极与所述数据线连接,第二充电子子电路中第一晶体管的第二极与所述充电节点连接;所述第一充电子子电路和所述第二充电子子电路为所述至少两个串联的充电子子电路中两端的充电子子电路。
- 根据权利要求1所述的像素电路,其中,所述第二充电子电路,包括:第二晶体管;所述第二晶体管的栅极与所述栅线连接,所述第二晶体管的第一极与所述充电节点连接,所述第二晶体管的第二极与所述显示子电路连接。
- 根据权利要求2或3所述的像素电路,其中,所述第一晶体管的栅极与控制线连接,所述控制线与所述栅线彼此电连接。
- 根据权利要求3所述的像素电路,其中,所述像素电路包括:多条控制线,每个充电子子电路中的第一晶体管的栅极分别与不同的控制线连接。
- 根据权利要求2或3所述的像素电路,其中,所述显示子电路包括液晶电容,所述像素电路中存储电容的电容值大于所述液晶电容的电容值。
- 一种像素电路的驱动方法,其中,所述像素电路包括:栅线、数据线、第一充电子电路、第二充电子电路和显示子电路,所述第二充电子电路分别与所述充电节点、所述栅线和所述显示子电路连接,所述方法包括:控制所述第一充电子电路向所述充电节点输出来自所述数据线的数据信号并存储来自所述数据线的数据信号;所述栅线提供第一电平的栅极驱动信号,所述第二充电子电路向所述显示子电路输出来自所述充电节点的数据信号。
- 根据权利要求8所述的驱动方法,其中,所述显示子电路包括液晶电容,所述像素电路还包括:控制线;所述第一充电子电路包括:第一晶体管和存储电容,所述第一晶体管的栅极与所述控制线连接;所述第二充电子电路,包括:第二晶体管,所述第二晶体管的栅极与所述栅线连接;所述第一晶体管的第二极与所述第二晶体管的第一极连接;所述控制所述第一充电子电路向所述充电节点输出来自所述数据线的数据信号并存储来自所述数据线的数据信号,包括:所述控制线提供第一电平的栅极驱动信号,所述第一晶体管导通,所述 数据线通过所述第一晶体管为所述存储电容充电;所述栅线提供第一电平的栅极驱动信号,所述第二充电子电路向所述显示子电路输出来自所述充电节点的数据信号,包括:所述栅线提供第一电平的栅极驱动信号,所述第二晶体管导通,所述存储电容通过所述第二晶体管为所述液晶电容充电。
- 根据权利要求8所述的驱动方法,其中,所述显示子电路包括液晶电容,所述第一充电子电路包括:第一晶体管和存储电容,所述第一晶体管的栅极与所述栅线连接;所述第二充电子电路,包括:第二晶体管,所述第二晶体管的栅极与所述栅线连接;所述第一晶体管的第二极与所述第二晶体管的第一极连接;在所述栅线提供第一电平的栅极驱动信号时,所述第一晶体管和所述第二晶体管导通,所述数据线通过所述第一晶体管和所述第二晶体管为所述液晶电容充电。
- 根据权利要求9或10所述的驱动方法,其中,所述方法还包括:所述控制线提供第二电平的栅极驱动信号,所述充电节点与所述数据线断开连接;所述栅线提供第二电平的栅极驱动信号,所述充电节点与所述液晶电容断开连接。
- 一种显示基板,包括:多条栅线、多条数据线、及由所述栅线和所述数据线交叉围成的多个像素单元,所述多个像素单元呈阵列排布,其中,每个像素单元中包括一像素电路,所述像素电路为权利要求1至7任一所述的像素电路。
- 根据权利要求12所述的显示基板,其中,所述显示基板还包括:多条控制线,所述像素电路中第一充电子电路与控制线连接,位于同一列且相邻的两个像素单元中,第一像素单元中第二充电子电路所连接的栅线与第二像素单元中第一充电子电路所连接的控制线彼此电连接,其中,所述第一像素单元和所述第二像素单元按照所述多条栅线对所述多个像素单元的扫描方 向排列。
- 一种显示装置,包括:如权利要求12或13所述的显示基板。
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CN110021262B (zh) * | 2018-07-04 | 2020-12-18 | 京东方科技集团股份有限公司 | 像素电路及其驱动方法、像素单元、显示面板 |
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CN110033729B (zh) * | 2019-05-17 | 2022-10-04 | 京东方科技集团股份有限公司 | 像素电路、显示面板及驱动方法、显示装置 |
CN110738974B (zh) * | 2019-10-28 | 2022-05-20 | 京东方科技集团股份有限公司 | 液晶像素电路、其驱动方法、显示面板及显示装置 |
CN111458944A (zh) * | 2020-04-23 | 2020-07-28 | Oppo广东移动通信有限公司 | 显示装置及电子设备 |
CN114464122B (zh) * | 2022-01-21 | 2024-02-06 | 京东方科技集团股份有限公司 | 显示装置的驱动方法、goa电路的驱动方法、显示装置 |
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JP4865512B2 (ja) * | 2006-11-27 | 2012-02-01 | 株式会社 日立ディスプレイズ | 画面入力機能付き画像表示装置 |
TWI440926B (zh) * | 2010-12-31 | 2014-06-11 | Hongda Liu | 液晶顯示裝置 |
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2017
- 2017-07-26 CN CN201710618939.8A patent/CN107221300A/zh active Pending
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- 2018-02-06 US US16/301,646 patent/US11238768B2/en active Active
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US5517150A (en) * | 1991-10-01 | 1996-05-14 | Nec Corporation | Analog switch formed of thin film transistor and having reduced leakage current |
CN101614919A (zh) * | 2009-08-14 | 2009-12-30 | 上海广电光电子有限公司 | 场序液晶显示装置及其驱动方法 |
WO2011083598A1 (ja) * | 2010-01-07 | 2011-07-14 | シャープ株式会社 | 半導体装置、アクティブマトリクス基板、及び表示装置 |
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CN102800288A (zh) * | 2011-05-23 | 2012-11-28 | 刘鸿达 | 电子装置系统 |
CN106157903A (zh) * | 2014-09-23 | 2016-11-23 | 元太科技工业股份有限公司 | 显示器 |
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US20210233448A1 (en) | 2021-07-29 |
US11238768B2 (en) | 2022-02-01 |
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