WO2019019605A1 - 一种像素电路及其驱动方法、显示基板、显示装置 - Google Patents

一种像素电路及其驱动方法、显示基板、显示装置 Download PDF

Info

Publication number
WO2019019605A1
WO2019019605A1 PCT/CN2018/075435 CN2018075435W WO2019019605A1 WO 2019019605 A1 WO2019019605 A1 WO 2019019605A1 CN 2018075435 W CN2018075435 W CN 2018075435W WO 2019019605 A1 WO2019019605 A1 WO 2019019605A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
circuit
charging
gate
sub
Prior art date
Application number
PCT/CN2018/075435
Other languages
English (en)
French (fr)
Inventor
米磊
薛艳娜
包智颖
张勇
白璐
华刚
王景棚
方浩博
院凌翔
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/301,646 priority Critical patent/US11238768B2/en
Publication of WO2019019605A1 publication Critical patent/WO2019019605A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3681—Details of drivers for scan electrodes suitable for passive matrices only

Definitions

  • the present disclosure relates to a pixel circuit and a driving method thereof, a display substrate, and a display device.
  • the liquid crystal display includes a plurality of pixel units surrounded by a plurality of data lines and a plurality of gate lines.
  • the plurality of pixel units are arranged in an array, wherein each of the pixel units includes a pixel circuit, and the pixel circuit specifically includes: a thin film A transistor (English: Thin Film Transistor; abbreviated: TFT) and a liquid crystal capacitor, wherein the liquid crystal capacitor is formed by a pixel electrode and a common electrode in the pixel unit.
  • TFT Thin Film Transistor
  • the TFT is used for charging a liquid crystal capacitor
  • the liquid crystal capacitor is used for controlling deflection of liquid crystal molecules, thereby realizing image display.
  • the liquid crystal capacitor in each pixel circuit is charged by one TFT, and the gates of the TFTs in the plurality of pixel circuits in the same row are connected to the same gate line, and the gate lines are used to control the on and off of the TFT, the plurality of The source of the TFT in the pixel circuit is connected to different data lines, and the drain of each TFT is connected to the pixel electrode.
  • the TFT is turned on under the control of the gate line, the data signal on the data line can be written to the pixel electrode to charge the liquid crystal capacitor.
  • the drain of the TFT may output a leakage current to the data line, causing the voltage of the pixel electrode to decrease, affecting the deflection of the liquid crystal molecules, thereby affecting the image display effect of the display.
  • the embodiment of the present invention provides a A pixel circuit, a driving method thereof, a display substrate, and a display device.
  • the technical solution is as follows:
  • a pixel circuit comprising:
  • a gate line a data line, a first charging sub-circuit, a second charging sub-circuit, and a display sub-circuit;
  • the first charging subcircuit is configured to be controllable to output a data signal from the data line to a charging node and to store a data signal from the data line;
  • the second charging subcircuit is coupled to the charging node, the gate line, and the display subcircuit, respectively, and is configured to be controllable to output a data signal from the charging node to the display subcircuit.
  • the first charging sub-circuit includes: a first transistor and a storage capacitor;
  • a gate of the first transistor is connected to the gate line; or the pixel circuit further includes: a control line, a gate of the first transistor is connected to the control line;
  • a first pole of the first transistor is connected to the data line, and a second pole of the first transistor is connected to the charging node;
  • One end of the storage capacitor is connected to the charging node, and the other end of the storage capacitor is connected to a common electrode.
  • the first charging sub-circuit includes: at least two charging sub-circuits connected in series, wherein each charging sub-circuit comprises: a first transistor and a storage capacitor;
  • a gate of the first transistor is connected to the gate line; or the pixel circuit further includes: a control line, a gate of the first transistor is connected to the control line;
  • a second pole of the first transistor is connected to one end of the storage capacitor, and another end of the storage capacitor is connected to a common electrode;
  • a first pole of the first transistor in the first charge sub-subcircuit is connected to the data line, and a second pole of the first transistor in the second charge sub-circuit is Charging node connection;
  • the first charging sub-subcircuit and the second charging sub-subcircuit are charging sub-circuits at both ends of the at least two series-connected charging sub-circuits.
  • the second charging sub-circuit includes: a second transistor
  • a gate of the second transistor is connected to the gate line, a first pole of the second transistor is connected to the charging node, and a second pole of the second transistor is connected to the display sub-circuit.
  • a gate of the first transistor is connected to a control line, and the control line and the gate line are electrically connected to each other.
  • the pixel circuit comprises: a plurality of control lines, and the gates of the first transistors in each of the charging sub-subcircuits are respectively connected to different control lines.
  • the display sub-circuit includes a liquid crystal capacitor, and a capacitance value of the storage capacitor in the pixel circuit is greater than a capacitance value of the liquid crystal capacitor.
  • a second aspect provides a driving method of a pixel circuit, the pixel circuit comprising: a gate line, a data line, a first charging sub-circuit, a second charging sub-circuit, and a display sub-circuit, wherein the second charging sub-circuit respectively Connected to the charging node, the gate line, and the display sub-circuit, the method comprising:
  • the gate line provides a first level of gate drive signal, and the second charge subcircuit outputs a data signal from the charge node to the display subcircuit.
  • the display sub-circuit includes a liquid crystal capacitor
  • the pixel circuit further includes: a control line
  • the first charging sub-circuit includes: a first transistor and a storage capacitor, a gate of the first transistor and the a second charging sub-circuit, comprising: a second transistor, a gate of the second transistor being connected to the gate line; a second pole of the first transistor and a second transistor One pole connection
  • the controlling the first charging sub-circuit to output a data signal from the data line to the charging node and storing a data signal from the data line including:
  • the control line provides a first level of gate drive signal, the first transistor is turned on, and the data line charges the storage capacitor through the first transistor.
  • the gate line provides a first level of gate drive signal
  • the second charge subcircuit outputs a data signal from the charging node to the display subcircuit, including:
  • the gate line provides a first level of gate drive signal, the second transistor is turned on, and the storage capacitor charges the liquid crystal capacitor through the second transistor.
  • the display subcircuit includes a liquid crystal capacitor
  • the first charging subcircuit includes: a first transistor and a storage capacitor, a gate of the first transistor is connected to the gate line
  • the second charging sub The circuit includes: a second transistor, a gate of the second transistor is connected to the gate line; a second pole of the first transistor is connected to a first pole of the second transistor;
  • the first transistor and the second transistor are turned on when the gate line provides a gate driving signal of a first level, and the data line passes through the first transistor and the second transistor The liquid crystal capacitor is charged.
  • the method further includes:
  • the control line provides a second level of gate drive signal, and the charging node is disconnected from the data line;
  • the gate line provides a second level of gate drive signal, the charging node being disconnected from the liquid crystal capacitor.
  • a display substrate in a third aspect, includes: a plurality of gate lines, a plurality of data lines, and a plurality of pixel units surrounded by the gate lines and the data lines, The pixel units are arranged in an array, wherein each pixel unit includes a pixel circuit, and the pixel circuit is the pixel circuit of any of the first aspects.
  • the display substrate further includes: a plurality of control lines, wherein the first charging sub-circuit in the pixel circuit is connected to the control line, and is located in the same column and two adjacent pixel units, and the first pixel unit a gate line connected to the second charging sub-circuit and a control line connected to the first charging sub-circuit in the second pixel unit are electrically connected to each other, wherein the first pixel unit and the second pixel unit follow the plurality of gates
  • the lines are arranged in the scanning direction of the plurality of pixel units.
  • a display device comprising the display substrate of any of the third aspects.
  • the pixel circuit and the driving method thereof, the display substrate, and the display device are provided with a first charging sub-circuit and a second charging sub-circuit between the data line and the display sub-circuit in the pixel circuit, and the first charging sub-circuit is
  • the charging node outputs a data signal
  • the second charging sub-circuit outputs the data signal from the charging node to the display sub-circuit
  • the first charging sub-circuit can store the data signal, so that the charging node can maintain the high voltage
  • the second charging sub-circuit The differential pressure at the end is small, and the smaller differential pressure reduces the leakage current output to the data line, effectively reducing the influence of the leakage current on the deflection of the liquid crystal molecules, and ensuring the image display effect of the display.
  • 1-1 is a structural block diagram of a pixel circuit according to an embodiment of the present invention.
  • 1-2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 1-3 are schematic structural diagrams of another pixel circuit according to an embodiment of the present invention.
  • 2-1 is a simulation diagram of voltage holding of a voltage of a second pole of a first transistor in a frame period after the pixel circuit shown in FIG. 1-2 charges the liquid crystal capacitor;
  • FIG. 2-2 is a simulation diagram of the voltage holding condition of the voltage of the second pole of the second transistor in one frame time after the pixel circuit shown in FIG. 1-2 charges the liquid crystal capacitor;
  • 3-1 is a schematic structural diagram of still another pixel circuit according to an embodiment of the present invention.
  • 3-2 is a schematic structural diagram of still another pixel circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a pixel circuit in the related art
  • FIG. 5 is a diagram of a driving method of a pixel circuit according to an embodiment of the present invention.
  • 6-1 is a schematic diagram of a waveform of a gate driving signal applied to a gate line connected to a gate of a first transistor and a gate line connected to a gate of a second transistor according to an embodiment of the present invention
  • FIG. 6-2 is a schematic diagram of waveforms of a gate driving signal connected to a gate line of a first transistor and a gate driving signal of a gate line connected to a gate of a second transistor according to an embodiment of the present invention
  • FIG. 6-3 is a schematic diagram showing waveforms of a gate driving signal connected to a gate of a first transistor and a gate driving signal of a gate connected to a gate of the second transistor according to an embodiment of the present invention
  • FIG. 6-4 is a schematic diagram of a voltage waveform of a second pole of a first transistor and a voltage waveform of a second pole of a second transistor during charging according to an embodiment of the present invention
  • FIG. 7 is a schematic structural diagram of a display substrate according to an embodiment of the present invention.
  • 8-1 is a schematic diagram of a plurality of gate lines and a plurality of control lines connected to a plurality of gate driving signal output ends on a display substrate according to an embodiment of the present invention
  • 8-2 is a schematic diagram of signal waveforms outputted by respective gate driving signal output ends when a plurality of gate lines and a plurality of control lines on a display substrate are connected to a plurality of gate driving signal output ends according to an embodiment of the present disclosure
  • 8-3 is a schematic diagram of a plurality of gate lines and a plurality of control lines on a display substrate connected to a plurality of gate drive signal output terminals, and each gate line and each control line in the display substrate are provided in an embodiment of the present invention.
  • All of the transistors used in all embodiments of the present invention may be thin film transistors, field effect transistors or other devices having the same characteristics.
  • the transistors employed in the embodiments of the present invention are mainly switching transistors according to their roles in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiment of the present invention, the source is referred to as a first stage, and the drain is referred to as a second stage. According to the form in the drawing, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistor used in the embodiment of the present invention may be an N-type switching transistor, wherein the N-type switching transistor is turned on when the gate is at a high potential, and is turned off when the gate is at a low potential.
  • the plurality of signals in various embodiments of the present invention correspond to a first level and a second level. The first level and the second level only represent two state quantities of the potential of the signal, and do not mean that the first level or the second level in the full text has a specific value.
  • the display product such as the smart wear adopts a low-power operation mode: the display panel of the display product adopts a refresh rate of 1 Hz (in English: Hz) (that is, the duration of displaying one frame of image is 1 second), and the black and white display A 1-bit bit drive is used in the panel to achieve black and white display on the display panel, and the color display panel is driven by 2 bits to realize 64-color display on the display panel.
  • the working mode of the pixel electrode is increased by 60 times, and the risk of leakage increases accordingly.
  • a display panel whose partial structure is made of amorphous silicon (English: Amorphous silicon; a-Si)
  • the pixel electrode may output a leakage current to the data line after the transistor is turned off, the voltage of the pixel electrode is reduced. Therefore, it is difficult for the voltage of the pixel electrode to remain high for a long time (for example, 1 second), so that the capacitance of the liquid crystal capacitor is reduced, thereby affecting the deflection of the liquid crystal molecules in the display panel, resulting in an image display effect of the display product. affected.
  • FIG. 1-1 is a structural block diagram of the pixel circuit.
  • the pixel circuit may include:
  • the gate line G1 the data line D, the first charging sub-circuit 01, the second charging sub-circuit 02, and the display sub-circuit 03.
  • the first charging sub-circuit 01 is configured to be controllable to output a data signal from the data line D to the charging node P and to store the data signal from the data line D.
  • the second charging sub-circuit 02 is connected to the charging node P, the gate line G1 and the display sub-circuit 03, respectively, which are configured to be controllable to output a data signal from the charging node P to the display sub-circuit 03.
  • the pixel circuit provided by the embodiment of the present invention has a first charging sub-circuit and a second charging sub-circuit between the display sub-circuit and the data line, and the first charging sub-circuit outputs a data signal to the charging node.
  • the first charging sub-circuit can store the data signal, so that the charging node can be kept at a high voltage, and the voltage difference across the second charging sub-circuit is small.
  • the smaller differential pressure reduces the leakage current output to the data line, effectively reducing the influence of leakage current on the deflection of the liquid crystal molecules, and ensuring the image display effect of the display.
  • the display sub-circuit 03 may include a liquid crystal capacitor Clc, and outputting the data signal from the charging node P to the display sub-circuit 03 is a process of charging the liquid crystal capacitor Clc. And since the liquid crystal capacitor Clc is formed by the pixel electrode and the common electrode in the pixel unit, the process of charging the liquid crystal capacitor Clc is actually a process of writing an electric signal to the pixel electrode.
  • the structure of the first charging sub-circuit 01 can be implemented in various ways. The following two embodiments are described as an example:
  • the first charging sub-circuit 01 may include: a first transistor M1 and a storage capacitor Cst.
  • the gate of the first transistor M1 may be connected to the gate line G1 (this connection is not shown in FIGS. 1-2).
  • the pixel circuit may further include: a control line G2, the gate of the first transistor M1 being connected to the control line G2.
  • the first electrode of the first transistor M1 is connected to the data line D
  • the second electrode of the first transistor M1 is connected to the charging node P
  • one end of the storage capacitor Cst is connected to the charging node P
  • the other end of the storage capacitor Cst is connected to the common electrode.
  • the first charging sub-circuit 01 may include: at least two charging sub-circuits 011 connected in series (the first charging sub-circuit in FIG. 1-3 includes three charging devices).
  • each of the charging sub-circuits 011 may include a first transistor M1 and a storage capacitor Cst.
  • the gate of the first transistor M1 may be connected to the gate line G1 (this connection is not shown in FIGS. 1-3).
  • the pixel circuit may further include: a control line G2, the gate of the first transistor M1 being connected to the control line G2.
  • the second pole of the first transistor M1 is connected to one end of the storage capacitor Cst through the charging node P, and the other end of the storage capacitor Cst is connected to the common electrode.
  • the second pole of the first thin film transistor M1 and the charging element away from the data line D in the charging sub-circuit 011 of the data line D in each two adjacent charging sub-circuits The first electrode of the first thin film transistor M1 is connected in the sub-circuit 011. And the first pole of the first transistor M1 in the first charging sub-circuit is connected to the data line D, and the second pole of the first transistor M1 in the second charging sub-circuit is connected to the charging node P.
  • the first charging sub-circuit and the second charging sub-subcircuit are charging sub-circuits at both ends of at least two charging sub-circuits connected in series.
  • the second charging sub-circuit 02 may include: a second transistor M2.
  • the gate of the second transistor M2 is connected to the gate line G1, the first electrode of the second transistor M2 is connected to the charging node P, and the second electrode of the second transistor M2 is connected to the liquid crystal capacitor Clc in the display sub-circuit.
  • a first transistor M1 and a second transistor M2 are spaced apart between the liquid crystal capacitor Clc and the data line D.
  • the second transistor M2 is second.
  • the pole is kept at a high potential, and at the same time, the second pole of the first transistor M1 is also kept at a high potential, and the voltage difference between the two is small, and the smaller voltage difference forms an obstacle when the output leakage current is caused, so that the second transistor
  • the leakage current outputted to the data line D when M2 is turned off is reduced, thereby reducing the magnitude of the voltage decrease on one pole (ie, the pixel electrode) of the liquid crystal capacitor Clc connected to the second charging sub-circuit 02, thereby reducing
  • the magnitude of the decrease in the capacitance of the liquid crystal capacitor Clc reduces the influence on the deflection of the liquid crystal molecules.
  • the principle of reducing the leakage current outputted to the data line D when the second transistor M2 is turned off please refer to the principle, here is not Let me repeat.
  • FIG. 2-1 shows the voltage holding of the voltage of the second pole of the first transistor in one frame time (for example, 1 second) after the pixel circuit shown in FIG. 1-2 charges the liquid crystal capacitor Clc.
  • FIG. 2-2 shows the voltage holding condition of the voltage of the second pole of the second transistor in one frame time after the pixel circuit shown in FIG. 1-2 charges the liquid crystal capacitor Clc. Simulation diagram.
  • the voltage of the second pole of the first transistor is only slightly reduced in one frame time after the completion of charging, and the voltage of the second pole of the second transistor is hardly reduced.
  • the voltage of the second pole of the second transistor is the voltage of the pixel electrode, that is, when the first charging sub-circuit includes only the first transistor, it can be reduced.
  • the amplitude of the pixel electrode voltage is reduced, and even the voltage of the pixel electrode is not reduced, thereby ensuring the image display effect of the display.
  • the circuit of the pixel circuit at this time is relatively simple, and it is easy to implement control of the circuit.
  • the gate of the first transistor and the gate of the second transistor may both be connected to the gate line G1.
  • the control line and the gate line may also be electrically connected to each other.
  • the two are electrically connected to each other, all of the transistors in each pixel circuit are turned on for the same time, and the data lines can simultaneously start charging a plurality of transistors.
  • the pixel circuit may include: a plurality of control lines, and the gates of the first transistors in each of the charging sub-circuits may be respectively connected to different control lines, and the connection diagram thereof is shown in FIG. 3-2, as shown in FIG.
  • the pixel circuit includes a control line G21, a control line G22, and a control line G23.
  • the gates of the first transistors M1 of the three series-connected charge sub-circuits 011 are sequentially connected to the control line G21, the control line G22, and the control. Line G23 is connected.
  • the time at which the plurality of transistors in the pixel circuit are turned on is different, and the data lines can charge the at least two transistors in series in accordance with the time when the transistors are turned on.
  • the second pole of the second transistor may be connected to a storage capacitor Cst, and the storage capacitor Cst is connected in parallel with the liquid crystal capacitor Clc.
  • the specific connection manner refer to the dotted line frame 03 in FIG. 3-2.
  • the capacitance value of the storage capacitor in the pixel circuit is greater than the capacitance value of the liquid crystal capacitor.
  • the larger the difference between the capacitance value of the storage capacitor and the capacitance value of the liquid crystal capacitor the smaller the voltage difference between the second pole of the second transistor and the second pole of the first transistor, and the second transistor leaks when it is turned off.
  • the current can be small enough or even no leakage current, so that the voltage of the pixel electrode is reduced to a small enough or not to be reduced. Therefore, the better the voltage holding capacity of the pixel electrode is, the more the capacitance of the liquid crystal capacitor is reduced. The smaller or even not reduced, the more the normal deflection of the liquid crystal molecules can be ensured.
  • a schematic diagram of a pixel circuit includes only one transistor M.
  • the gate of the transistor M is connected to a gate line G.
  • the first pole of the transistor M is connected to the data line D.
  • the second pole is respectively connected to the liquid crystal capacitor Clc and the storage capacitor Cst.
  • the voltage difference is the potential of the signal loaded on the data line and the second of the transistor
  • the voltage difference of the pole potential for example, the voltage difference can be 5V
  • the second pole of the transistor can easily output a leakage current to the data line, and under the influence thereof, the pixel electrode connected to the second pole of the transistor The voltage is reduced, resulting in poor voltage holding capability of the pixel electrode, so that the deflection of the liquid crystal molecules is greatly affected.
  • the pixel circuit provided by the embodiment of the present invention has a first charging sub-circuit and a second charging sub-circuit between the display sub-circuit and the data line, and the first charging sub-circuit outputs a data signal to the charging node.
  • the first charging sub-circuit can store the data signal, so that the charging node can be kept at a high voltage, and the voltage difference across the second charging sub-circuit is small.
  • the smaller differential pressure reduces the leakage current output to the data line, thereby effectively reducing the magnitude of the voltage drop at the end of the connection between the liquid crystal capacitor and the second charging sub-circuit, thereby reducing the capacitance reduction of the liquid crystal capacitor.
  • the amplitude effectively reduces the influence of leakage current on the deflection of liquid crystal molecules, ensures the image display effect of the display, and solves the related art that the pixel electrode cannot maintain its voltage at a high potential for 1 second or even longer. The problem.
  • the driving method can be applied to the pixel circuit shown in any of FIG. 1-2, FIG. 1-3, FIG. 3-1, or FIG. 3-2.
  • the pixel circuit may include: a gate line G1, a data line D, a first charging sub-circuit 01, a second charging sub-circuit 02, and a display sub-circuit 03, and the second charging sub-circuit 02 and the charging node P, the gate line G1, and the display, respectively
  • the sub-circuit 03 is connected.
  • the driving method of the pixel circuit may include:
  • Step 501 Control the first charging sub-circuit to output a data signal from the data line to the charging node and store the data signal from the data line.
  • Step 502 the gate line provides a gate drive signal of a first level, and the second charge sub-circuit outputs a data signal from the charging node to the display sub-circuit.
  • Step 503 The control line provides a gate driving signal of a second level, and the charging node is disconnected from the data line.
  • Step 504 The gate line provides a second level of gate driving signal, and the charging node is disconnected from the liquid crystal capacitor.
  • the driving method of the pixel circuit controls the first charging sub-circuit to output a data signal from the data line to the charging node and stores the data signal from the data line, and the gate line provides the first level.
  • a gate driving signal the second charging sub-circuit outputs a data signal from the charging node to the display sub-circuit
  • a first charging sub-circuit and a second charging sub-circuit are interposed between the display sub-circuit and the data line
  • the first charging sub- The circuit outputs a data signal to the charging node
  • the second charging sub-circuit outputs the data signal from the charging node to the display sub-circuit
  • the first charging sub-circuit can store the data signal, so that the charging node can maintain the high voltage
  • the voltage difference across the circuit is small, and the small differential voltage reduces the leakage current output to the data line, thereby effectively reducing the magnitude of the voltage drop at the end of the connection between the liquid crystal capacitor and the second charging sub
  • the display sub-circuit 03 may include a liquid crystal capacitor, and outputting the data signal from the charging contact to the display sub-circuit is a process of charging the liquid crystal capacitor.
  • the first charging sub-circuit 01 may include: a first transistor M1 and a storage capacitor Cst, the first transistor M1 The gate is connected to the gate line G1 or the control line G2.
  • the second charging sub-circuit 02 may include a second transistor M2. The gate of the second transistor M2 is connected to the gate line G1, and the second pole of the first transistor M1 is The first pole of the second transistor M2 is connected.
  • the driving method of the pixel circuit can be divided into the following three achievable modes:
  • the first implementation manner is: when the gate of the first transistor M1 is connected to the control line G2, and the gate of the second transistor M2 is connected to the gate line G1, the conduction state of the first transistor M1 and the second transistor M2, and
  • the process of charging the liquid crystal capacitor Clc by the first charging sub-circuit 01 and the second charging sub-circuit 02 by the data line D may include, for example, two stages:
  • the first transistor M1 In the first charging phase t1, when the control line G2 provides the gate driving signal of the first level, the first transistor M1 is turned on by the gate driving signal, and the data line D is charged by the first transistor M1 for the storage capacitor Cst. .
  • the second transistor M2 In the second charging phase t2, when the gate line G1 provides the gate driving signal of the first level, the second transistor M2 is turned on by the gate driving signal, and the storage capacitor Cst charges the liquid crystal capacitor Clc through the second transistor M2. .
  • the times of the two charging phases may completely overlap, partially overlap, or not overlap at all.
  • the control line G2 and the gate of the gate of the first transistor M1 are connected.
  • the waveform diagram of the gate drive signal loaded on the gate line G1 connected to the gate of the two transistor M2 please refer to FIG. 6-1, FIG. 6-2 and FIG. 6-3, respectively.
  • the durations of the two charging phases may not be equal, the time of the two phases may overlap partially or not at all.
  • the time of the two charging phases may not overlap at all, and the whole charging process is described.
  • the charging process may refer to the time of the two phases completely. Non-overlapping processes.
  • the charging process includes a first charging phase t1 and a second charging phase t2.
  • the control line G2 provides a gate driving signal of a first level (for example, 10 volts), the first transistor M1 is turned on by the gate driving signal, and the data line D passes through the first transistor.
  • M1 charges the second pole of the first transistor M1, that is, charges the storage capacitor Cst, so that the voltage of the second pole of the first transistor M1 (ie, a pole connected to the storage capacitor Cst) has been charged to the first high potential. (Example: 10 volts).
  • the second transistor M2 In the second charging phase t2, when the gate line G1 provides the gate driving signal of the first level, the second transistor M2 is turned on by the gate driving signal, and the second pole of the first transistor M1 (that is, The storage capacitor Cst) charges the liquid crystal capacitor Clc through the second transistor M2 (ie, charges the pixel electrode) to charge the second electrode of the second transistor M2 and the pixel electrode to the second high potential.
  • control line G2 provides a gate driving signal of a second level (for example, 0 volts), at which time the first transistor M1 is turned off, charging. Node P is disconnected from data line D.
  • a second level for example, 0 volts
  • the gate driving signal provided by the gate line G1 jumps to the second level, the second transistor M2 is turned off, and the charging node P is disconnected from the liquid crystal capacitor Clc.
  • the gate driving signal provided by the control line G2 in the first charging phase t1 and the second charging phase t2, the gate driving signal provided by the gate line G1, the signal loaded on the data line D, and the second pole of the first transistor M1 Refer to Figure 6-4 for the voltage waveform and the voltage waveform of the second electrode of the second transistor M2.
  • the amplitude of the first high potential is mainly determined by the potential of the data line D
  • the amplitude of the second high potential is determined by the amplitude of the first high potential, the capacitance of the storage capacitor Cst, and the capacitance of the liquid crystal capacitor Clc. decided together.
  • the capacitance value of the storage capacitor Cst and the capacitance value of the liquid crystal capacitor Clc are larger, the voltage difference between the second pole of the second transistor M2 and the second pole of the first transistor M1 is smaller, and thus,
  • the capacitance value of the storage capacitor Cst can be set to be much larger than the capacitance value of the liquid crystal capacitor Clc.
  • the capacitance value of the liquid crystal capacitor Clc can be set to 10 times the capacitance value of the storage capacitor Cst.
  • the second high potential is obtained after a certain voltage drop on the basis of the first high potential
  • the potential of the pixel electrode is obtained after a certain voltage drop on the basis of the second high potential.
  • the manner compensates for the voltage drop such that the second high potential is closer to the first high potential and the potential of the pixel electrode is closer to the second high potential or even equal to the first high potential.
  • the second implementation manner is: when the gate of the first transistor M1 and the gate of the second transistor M2 are both connected to the gate line G1, the conduction of the first transistor M1 and the second transistor M2, and the data line D pass
  • the process of charging the liquid crystal capacitor Clc by the first charging sub-circuit 01 and the second charging sub-circuit 02 can be, for example:
  • the gate line G1 to which the first transistor M1 and the second transistor M2 are connected provides the gate driving signal of the first level
  • the first transistor M1 and the second transistor M2 are turned on by the gate driving signal
  • the data line D charges the liquid crystal capacitor Clc through the first transistor M1 and the second transistor M2.
  • a third implementation manner is: when the gate of the first transistor M1 is connected to the control line G2, the gate of the second transistor M2 is connected to the gate line G1, and the control line G2 and the gate line G1 are electrically connected to each other, the first transistor The conduction state of the M1 and the second transistor M2, and the process in which the data line D charges the liquid crystal capacitor Clc through the first charging sub-circuit 01 and the second charging sub-circuit 02, for example, may be:
  • the gate line G1 (or the control line G2) supplies the gate driving signal of the first level
  • the first transistor M1 and the second transistor M2 are turned on by the gate driving signal, and, in the first transistor M1 and During the turn-on of the second transistor M2, the data line D charges the liquid crystal capacitor Clc through the first transistor M1 and the second transistor M2.
  • the first level is a high level with respect to the second level, for example, the first level is 10 volts, and the second level is 0 volts.
  • the first charging sub-circuit 01 includes at least two charging sub-circuits 011 connected in series, and at least two charging sub-circuits 011 connected in series, the gate of the first transistor M1 in each charging sub-circuit 011
  • the driving method of the pixel circuit is referred to the above-mentioned driving method, which will not be described in detail in the embodiment of the present invention.
  • the driving method of the pixel circuit controls the first charging sub-circuit to output a data signal from the data line to the charging node and stores the data signal from the data line, and the gate line provides the first level.
  • a gate driving signal the second charging sub-circuit outputs a data signal from the charging node to the display sub-circuit
  • a first charging sub-circuit and a second charging sub-circuit are interposed between the display sub-circuit and the data line
  • the first charging sub- The circuit outputs a data signal to the charging node
  • the second charging sub-circuit outputs the data signal from the charging node to the display sub-circuit
  • the first charging sub-circuit can store the data signal, so that the charging node can maintain the high voltage
  • the voltage difference across the circuit is small, and the small differential voltage reduces the leakage current output to the data line, thereby effectively reducing the magnitude of the voltage drop at the end of the connection between the liquid crystal capacitor and the second charging sub
  • FIG. 7 is a schematic structural diagram of a display substrate according to an embodiment of the present invention.
  • the display substrate may include: a plurality of gate lines (the plurality of gate lines in the figure are G1, G3, and G5, respectively), a plurality of data lines (the plurality of gate data lines are D1, D2, and D3, respectively), and a plurality of pixel units surrounded by the gate lines and the data lines, wherein the plurality of pixel units are arranged in an array, wherein each The pixel unit includes a pixel circuit 0 (shown by a broken line in FIG. 7), and the pixel circuit can be a pixel circuit as shown in any of FIG. 1-2, FIG. 1-3, FIG. 3-1 or FIG. .
  • the display substrate may further include: a plurality of control lines (the plurality of control lines in the figure are G2, G4, and G6, respectively), and the first charging sub-circuit in the pixel circuit is connected to the plurality of control lines Control of the connection between the gate line connected to the second charging sub-circuit of the pixel circuit in the first pixel unit and the first charging sub-circuit of the pixel circuit in the second pixel unit in two pixel units adjacent to each other in the same column
  • the wires may be electrically connected to each other (the connection manner is not shown in the drawing), wherein the first pixel unit and the second pixel unit are arranged in a scanning direction of the plurality of pixel cells in accordance with the plurality of gate lines.
  • the gate line G1 connected to the second charging sub-circuit of the pixel circuit in the first row of pixel units is The control lines G4 to which the first charging sub-circuits of the pixel circuits in the second row of pixel units are connected may be electrically connected to each other.
  • the second transistor of the pixel circuit in the first pixel unit and the first transistor of the pixel circuit in the second pixel unit can be simultaneously turned on and charged, reducing the total charging time of the liquid crystal capacitor on the display substrate.
  • the second charging sub-circuit of the pixel circuit in the first pixel unit and the first charging sub-circuit of the pixel circuit in the second pixel unit may be Each is connected to the same gate line, wherein the first pixel unit and the second pixel unit are arranged in a scanning direction of the plurality of pixel units according to the plurality of gate lines.
  • the second charging sub-circuit of the pixel circuit in the first pixel unit and the first charging sub-circuit of the pixel circuit in the second pixel unit are both connected to the same gate line, the second charging is performed with respect to the pixel circuit in the first pixel unit.
  • the case where the gate line connected to the electronic circuit and the control line connected to the first charging sub-circuit of the pixel circuit in the second pixel unit are different gate lines increases the aperture ratio of the display substrate.
  • the gate line and the second charging sub-circuit of the pixel circuit in the first pixel unit are connected
  • the control line connected to the first charging sub-circuit of the pixel circuit in the two-pixel unit may be connected to the same gate driving signal output end, wherein the first pixel unit and the second pixel unit are connected to the plurality of pixel units according to the plurality of gate lines
  • the scanning direction is arranged.
  • Figure 8-1 shows multiple gate lines (G1, G3, and G5) and multiple control lines (G2, G4, and G6) connected to multiple gate drive signal outputs (F1, F2, F3, and F4).
  • the line G4 can be connected to the same gate drive signal terminal F2.
  • each gate drive signal output terminal can be as shown in Figure 8-2, that is, each gate drive signal output terminal can sequentially output the first level gate drive signal.
  • the waveform of the gate driving signal loaded on each gate line in the display substrate can be as shown in Figure 8-3.
  • the gate lines connected to the same gate drive signal output are the same as the gate drive signals loaded on the control line.
  • the first transistor in the first charging sub-circuit of the pixel circuit in the second transistor and the second pixel unit in the second charging sub-circuit of the pixel circuit in the first pixel unit can be simultaneously charged, thereby reducing the liquid crystal capacitance on the display substrate.
  • the total charging time, and without increasing the number of gate drive signal output terminals, relatively reduces the production cost of the display substrate.
  • the display substrate provided by the embodiment of the present invention includes a plurality of pixel units, each of which includes a pixel circuit, and each pixel circuit has a first interval between the display sub-circuit and the data line.
  • a charging sub-circuit and a second charging sub-circuit the first charging sub-circuit outputs a data signal to the charging node, and after the second charging sub-circuit outputs the data signal from the charging node to the display sub-circuit, the first charging sub-circuit can store the data signal So that the charging node can be kept at a high voltage, and the voltage difference across the second charging sub-circuit is small, and the small differential voltage causes the leakage current to the data line to be reduced, thereby effectively reducing the liquid crystal capacitance and the
  • the amplitude of the voltage reduction at one end of the connection of the charging sub-circuit further reduces the amplitude of the capacitance reduction of the liquid crystal capacitor, effectively reducing the influence of the leakage current on the deflection of the liquid crystal molecules, and
  • the embodiment of the invention further provides a display device, which may include the display substrate shown in FIG. 7 or 8-1.
  • the display device can be any product or component having a display function such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a person skilled in the art may understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium.
  • the storage medium mentioned may be a read only memory, a magnetic disk or an optical disk or the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Abstract

一种像素电路(0)及其驱动方法、显示基板、显示装置，属于显示领域。像素电路(0)包括：栅线(G1)、数据线(D)、第一充电子电路(01)、第二充电子电路(02)和显示子电路(03)；第一充电子电路(01)被配置为可被控制以向充电节点(P)输出来自数据线(D)的数据信号并存储来自数据线(D)的数据信号；第二充电子电路(02)分别与充电节点(P)、栅线(G1)和显示子电路(03)连接，其被配置为可被控制以向显示子电路(03)输出来自充电节点(P)的数据信号。

Description

一种像素电路及其驱动方法、显示基板、显示装置
本公开要求于2017年7月26日递交的中国专利申请第201710618939.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及一种像素电路及其驱动方法、显示基板、显示装置。
背景技术
液晶显示器包括由多条数据线和多条栅线交叉围成的多个像素单元，该多个像素单元呈阵列排布，其中每个像素单元中包括一像素电路，该像素电路具体包括：薄膜晶体管(英文：Thin Film Transistor；缩写：TFT)和液晶电容，其中液晶电容是由像素单元中的像素电极和公共电极形成的。该TFT用于为液晶电容充电，液晶电容用于控制液晶分子的偏转，进而实现图像的显示。
相关技术中，每个像素电路中的液晶电容由一个TFT充电，同一行的多个像素电路中TFT的栅极与同一条栅线连接，该栅线用于控制TFT的通断，该多个像素电路中TFT的源极与不同的数据线连接，每个TFT的漏极与像素电极连接。TFT在栅线的控制下导通时，可以将数据线上的数据信号写入像素电极，从而为液晶电容充电。
但是，在TFT关断后，TFT的漏极可能会向数据线输出漏电流，导致像素电极的电压减小，影响液晶分子的偏转，进而影响显示器的图像显示效果。
发明内容
为了解决相关技术中TFT的漏极可能会向数据线输出漏电流，导致像素电极的电压减小，影响液晶分子的偏转，进而影响显示器的图像显示效果的问题，本发明实施例提供了一种像素电路及其驱动方法、显示基板、显示装置。所述技术方案如下：
第一方面，提供了一种像素电路，所述像素电路包括：
栅线、数据线、第一充电子电路、第二充电子电路和显示子电路；
所述第一充电子电路被配置为可被控制以向充电节点输出来自所述数据线的数据信号并存储来自所述数据线的数据信号；
所述第二充电子电路分别与所述充电节点、所述栅线和所述显示子电路连接，其被配置为可被控制以向所述显示子电路输出来自所述充电节点的数据信号。
可选地，所述第一充电子电路包括：第一晶体管和存储电容；
所述第一晶体管的栅极与所述栅线连接；或者，所述像素电路还包括：控制线，所述第一晶体管的栅极与所述控制线连接；
所述第一晶体管的第一极与所述数据线连接，所述第一晶体管的第二极与所述充电节点连接；
所述存储电容的一端与所述充电节点连接，所述存储电容的另一端与公共电极连接。
可选地，所述第一充电子电路包括：至少两个串联的充电子子电路，其中，每个充电子子电路包括：第一晶体管和存储电容；
所述第一晶体管的栅极与所述栅线连接；或者，所述像素电路还包括：控制线，所述第一晶体管的栅极与所述控制线连接；
所述第一晶体管的第二极与所述存储电容的一端连接，所述存储电容的另一端与公共电极连接；
所述多个串联的充电子子电路中，第一充电子子电路中第一晶体管的第一极与所述数据线连接，第二充电子子电路中第一晶体管的第二极与所述充电节点连接；
所述第一充电子子电路和所述第二充电子子电路为所述至少两个串联的充电子子电路中两端的充电子子电路。
可选地，所述第二充电子电路，包括：第二晶体管；
所述第二晶体管的栅极与所述栅线连接，所述第二晶体管的第一极与所述充电节点连接，所述第二晶体管的第二极与所述显示子电路连接。
可选地，所述第一晶体管的栅极与控制线连接，所述控制线与所述栅线彼此电连接。
可选地，所述像素电路包括：多条控制线，每个充电子子电路中的第一晶体管的栅极分别与不同的控制线连接。
可选地，所述显示子电路包括液晶电容，所述像素电路中存储电容的电容值大于所述液晶电容的电容值。
第二方面，提供了一种像素电路的驱动方法，所述像素电路包括：栅线、数据线、第一充电子电路、第二充电子电路和显示子电路，所述第二充电子电路分别与所述充电节点、所述栅线和所述显示子电路连接，所述方法包括：
控制所述第一充电子电路向所述充电节点输出来自所述数据线的数据信号并存储来自所述数据线的数据信号；
所述栅线提供第一电平的栅极驱动信号，所述第二充电子电路向所述显示子电路输出来自所述充电节点的数据信号。
可选地，所述显示子电路包括液晶电容，所述像素电路还包括：控制线，所述第一充电子电路包括：第一晶体管和存储电容，所述第一晶体管的栅极与所述控制线连接；所述第二充电子电路，包括：第二晶体管，所述第二晶体管的栅极与所述栅线连接；所述第一晶体管的第二极与所述第二晶体管的第一极连接；
所述控制所述第一充电子电路向所述充电节点输出来自所述数据线的数据信号并存储来自所述数据线的数据信号，包括：
所述控制线提供第一电平的栅极驱动信号，所述第一晶体管导通，所述数据线通过所述第一晶体管为所述存储电容充电。
所述栅线提供第一电平的栅极驱动信号，所述第二充电子电路向所述显示子电路输出来自所述充电节点的数据信号，包括：
所述栅线提供第一电平的栅极驱动信号，所述第二晶体管导通，所述存储电容通过所述第二晶体管为所述液晶电容充电。
可选地，所述显示子电路包括液晶电容，所述第一充电子电路包括：第一晶体管和存储电容，所述第一晶体管的栅极与所述栅线连接；所述第二充电子电路，包括：第二晶体管，所述第二晶体管的栅极与所述栅线连接；所述第一晶体管的第二极与所述第二晶体管的第一极连接；
在所述栅线提供第一电平的栅极驱动信号时，所述第一晶体管和所述第二晶体管导通，所述数据线通过所述第一晶体管和所述第二晶体管为所述液晶电容充电。
可选地，所述方法还包括：
所述控制线提供第二电平的栅极驱动信号，所述充电节点与所述数据线 断开连接；
所述栅线提供第二电平的栅极驱动信号，所述充电节点与所述液晶电容断开连接。
第三方面，提供了一种显示基板，所述显示基板包括：多条栅线、多条数据线、及由所述栅线和所述数据线交叉围成的多个像素单元，所述多个像素单元呈阵列排布，其中，每个像素单元中包括一像素电路，所述像素电路为第一方面任一所述的像素电路。
可选地，所述显示基板还包括：多条控制线，所述像素电路中第一充电子电路与控制线连接，位于同一列且相邻的两个像素单元中，第一像素单元中第二充电子电路所连接的栅线与第二像素单元中第一充电子电路所连接的控制线彼此电连接，其中，所述第一像素单元和所述第二像素单元按照所述多条栅线对所述多个像素单元的扫描方向排列。
第四方面，提供了一种显示装置，包括第三方面任一所述的显示基板。
本发明实施例提供的技术方案带来的有益效果是：
本发明实施例提供的像素电路及其驱动方法、显示基板、显示装置，像素电路中数据线与显示子电路之间间隔有第一充电子电路和第二充电子电路，第一充电子电路向充电节点输出数据信号，第二充电子电路向显示子电路输出来自充电节点的数据信号后，第一充电子电路能够存储该数据信号，使得充电节点能够保持为高电压，第二充电子电路两端的压差较小，该较小的压差使得向数据线输出的漏电流减小，有效地减小了漏电流对液晶分子的偏转的影响，保证了显示器的图像显示效果。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1-1是本发明实施例提供的一种像素电路的结构框图；
图1-2是本发明实施例提供的一种像素电路的结构示意图；
图1-3是本发明实施例提供的另一种像素电路的结构示意图；
图2-1是图1-2所示的像素电路对液晶电容充电后，第一晶体管的第二 极的电压在一帧时间内的电压保持情况的仿真图；
图2-2是图1-2所示的像素电路对液晶电容充电后，第二晶体管的第二极的电压在一帧时间内的电压保持情况的仿真图；
图3-1是本发明实施例提供的又一种像素电路的结构示意图；
图3-2是本发明实施例提供的再一种像素电路的结构示意图；
图4是相关技术中的一种像素电路的示意图；
图5是本发明实施例提供的一种像素电路的驱动方法；
图6-1的本发明实施例提供的一种第一晶体管的栅极连接的控制线和第二晶体管的栅极连接的栅线上加载的栅极驱动信号的波形示意图；
图6-2的本发明实施例提供的另一种第一晶体管的栅极连接的控制线和第二晶体管的栅极连接的栅线上加载的栅极驱动信号的波形示意图；
图6-3的本发明实施例提供的又一种第一晶体管的栅极连接的控制线和第二晶体管的栅极连接的栅线上加载的栅极驱动信号的波形示意图；
图6-4的本发明实施例提供的一种充电过程中第一晶体管的第二极的电压波形和第二晶体管的第二极的电压波形示意图；
图7是本发明实施例提供的一种显示基板的结构示意图；
图8-1是本发明实施例提供的一种显示基板上多条栅线和多条控制线与多个栅极驱动信号输出端连接的示意图；
图8-2是本发明实施例提供的一种显示基板上多条栅线和多条控制线与多个栅极驱动信号输出端连接时，各个栅极驱动信号输出端输出的信号波形示意图；
图8-3是本发明实施例提供的一种显示基板上多条栅线和多条控制线与多个栅极驱动信号输出端连接时，显示基板中各条栅线和各条控制线上加载的栅极驱动信号的波形示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
本发明所有实施例中采用的晶体管均可以为薄膜晶体管、场效应管或其他特性相同的器件，根据在电路中的作用本发明的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以 其源极、漏极是可以互换的。在本发明实施例中，将其中源极称为第一级，漏极称为第二级。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本发明实施例所采用的开关晶体管可以为N型开关晶体管，其中，N型开关晶体管在栅极为高电位时导通，在栅极为低电位时截止。此外，本发明各个实施例中的多个信号都对应有第一电平和第二电平。第一电平和第二电平仅代表该信号的电位有2个状态量，不代表全文中第一电平或第二电平具有特定的数值。
相关技术中，智能穿戴等显示产品采用低功耗的工作方式：显示产品的显示面板中采用1赫兹(英文：Hz)的刷新频率(即显示一帧图像的时长为1秒)，且黑白显示面板中采用1比特位驱动，以实现显示面板上的黑白色显示，彩色显示面板使用2比特位驱动，以实现显示面板上的64色彩色显示。该工作方式相较于刷新频率为60Hz显示面板，像素电极的电压保持时间增大了60倍，其漏电风险也相应增大。这对于部分结构由非晶硅(英文：Amorphous silicon；缩写：a-Si)制造的显示面板，由于在晶体管关断后，像素电极可能会向数据线输出漏电流，使得像素电极的电压减小，因此，像素电极的电压难以在较长时间(例如：1秒)内一直保持为高电位，使得液晶电容的电容减小，进而影响显示面板中液晶分子的偏转，导致显示产品的图像显示效果受到影响。
针对上述问题，本发明实施例提供了一种像素电路，图1-1是该像素电路的结构框图，如图1-1所示，该像素电路可以包括：
栅线G1、数据线D、第一充电子电路01、第二充电子电路02和显示子电路03。
第一充电子电路01被配置为可被控制以向充电节点P输出来自数据线D的数据信号并存储来自数据线D的数据信号。
第二充电子电路02分别与充电节点P、栅线G1和显示子电路03连接，其被配置为可被控制以向显示子电路03输出来自充电节点P的数据信号。
综上所述，本发明实施例提供的像素电路，在显示子电路与数据线之间间隔有第一充电子电路和第二充电子电路，第一充电子电路向充电节点输出数据信号，第二充电子电路向显示子电路输出来自充电节点的数据信号后，第一充电子电路能够存储该数据信号，使得充电节点能够保持为高电压，第二充电子电路两端的压差较小，该较小的压差使得向数据线输出的漏电流减 小，有效地减小了漏电流对液晶分子的偏转的影响，保证了显示器的图像显示效果。
需要说明的是，该显示子电路03可以包括液晶电容Clc，向显示子电路03输出来自充电节点P的数据信号是对液晶电容Clc充电的过程。且由于该液晶电容Clc是由像素单元中的像素电极和公共电极形成的，对液晶电容Clc充电的过程实际是将电信号写入像素电极的过程。
进一步地，根据不同的应用场景，第一充电子电路01的结构可以有多种可实现方式，本发明实施例以以下两种可实现方式为例进行说明：
第一种可实现方式，如图1-2所示，第一充电子电路01可以包括：第一晶体管M1和存储电容Cst。
该第一晶体管M1的栅极可以与栅线G1连接(图1-2中未示出该连接方式)。
或者，像素电路还可以包括：控制线G2，该第一晶体管M1的栅极与控制线G2连接。
第一晶体管M1的第一极与数据线D连接，第一晶体管M1的第二极与充电节点P连接，存储电容Cst的一端与充电节点P连接，存储电容Cst的另一端与公共电极连接。
第二种可实现方式，如图1-3所示，第一充电子电路01可以包括：至少两个串联的充电子子电路011(图1-3中为第一充电子电路包括三个充电子子电路的情形)，其中，每个充电子子电路011可以包括：第一晶体管M1和存储电容Cst。
该第一晶体管M1的栅极可以与栅线G1连接(图1-3中未示出该连接方式)。
或者，像素电路还可以包括：控制线G2，该第一晶体管M1的栅极与控制线G2连接。
第一晶体管M1的第二极通过充电节点P与存储电容Cst的一端连接，存储电容Cst的另一端与公共电极连接。
多个串联的充电子子电路011中，每两个相邻的充电子子电路中靠近数据线D的充电子子电路011中第一薄膜晶体管M1的第二极与远离数据线D的充电子子电路011中第一薄膜晶体管M1的第一极连接。且第一充电子子电路中第一晶体管M1的第一极与数据线D连接，第二充电子子电路中第一 晶体管M1的第二极与充电节点P连接。该第一充电子子电路和第二充电子子电路为至少两个串联的充电子子电路中两端的充电子子电路。
可选地，参考图1-2和图1-3，第二充电子电路02可以包括：第二晶体管M2。该第二晶体管M2的栅极与栅线G1连接，第二晶体管M2的第一极与充电节点P连接，第二晶体管M2的第二极与显示子电路中的液晶电容Clc连接。
图1-2所示的像素电路中，液晶电容Clc与数据线D之间间隔有一个第一晶体管M1和一个第二晶体管M2，在完成液晶电容Clc的充电后，第二晶体管M2的第二极保持为高电位，同时，第一晶体管M1的第二极也保持为高电位，且两者的压差较小，该较小的压差形成了输出漏电流时的阻碍，使得第二晶体管M2关断时向数据线D输出的漏电流减小，因此，减小了液晶电容Clc中与第二充电子电路02连接的一极(即像素电极)上电压减小的幅度，进而减小了液晶电容Clc的电容减小的幅度，减小了对液晶分子的偏转的影响。当第一充电子电路01包括至少两个串联的充电子子电路011时，像素电路使得第二晶体管M2关断时向数据线D输出的漏电流减小的原理请参考该原理，此处不再赘述。
请参考图2-1，其示出了图1-2所示的像素电路对液晶电容Clc充电后，第一晶体管的第二极的电压在一帧时间(例如：1秒)内的电压保持情况的仿真图，请参考图2-2，其示出了图1-2所示的像素电路对液晶电容Clc充电后，第二晶体管的第二极的电压在一帧时间内的电压保持情况的仿真图。根据图2-1和图2-2可知，在充电完成后的一帧时间内第一晶体管的第二极的电压仅有小幅度的减小，第二晶体管第二极的电压几乎没有减小，由于第二晶体管第二极与像素电极连接，该第二晶体管第二极的电压即为像素电极的电压，也即是，当第一充电子电路仅包括第一晶体管时，其能够减小像素电极电压减小的幅度，甚至像素电极的电压并未减小，进而保证了显示器的图像显示效果。并且，此时的像素电路的电路较简单，易于实现对电路的控制。
可选地，如图3-1所示，在上述像素电路中，第一晶体管的栅极和第二晶体管的栅极可以均与栅线G1连接。
或者，当第一晶体管的栅极与控制线连接，且第二晶体管的栅极与栅线连接时，该控制线与该栅线也可以彼此电连接。当两者彼此电连接时，每个像素电路中的所有晶体管被导通的时间相同，数据线能够同时开始为多个晶 体管充电。
或者，像素电路可以包括：多条控制线，且每个充电子子电路中的第一晶体管的栅极可以分别与不同的控制线连接，其连接示意图请参考图3-2，如图3-2所示，像素电路包括控制线G21、控制线G22和控制线G23，该三个串联的充电子子电路011中的第一晶体管M1的栅极依次与该控制线G21、控制线G22和控制线G23连接。此时，像素电路中的多个晶体管被导通的时间不同，数据线可以按照晶体管被导通的时间分别为该至少两个串联的晶体管充电。
实际应用中，第二晶体管的第二极还可以连接有一个存储电容Cst，该存储电容Cst与液晶电容Clc并联，其具体连接方式请参考图3-2中虚线框03所示。
进一步地，像素电路中存储电容的电容值大于液晶电容的电容值。且存储电容的电容值与液晶电容的电容值的差距越大时，第二晶体管的第二极与第一晶体管的第二极之间的压差越小，第二晶体管在关断时其漏电流就能够足够小甚至不存在漏电流，进而使像素电极的电压减小的程度足够小甚至不减小，因此，像素电极上电压的保持能力越好，液晶电容的电容减小的幅度就越小甚至不减小，就越能够保证液晶分子的正常偏转。
相关技术中像素电路的示意图请参考图4，该像素电路仅包括一个晶体管M，该晶体管M的栅极与栅线G连接，该晶体管M的第一极与数据线D连接，该晶体管M的第二极分别与液晶电容Clc和存储电容Cst连接，在晶体管M关断后，由于晶体管的两极之间具有较大压差(该压差为数据线上加载的信号的电位与晶体管的第二极的电位的压差，例如：该压差可以为5V)，晶体管的第二极能够较容易地向数据线输出漏电流，在其影响下，液晶电容与晶体管的第二极连接的像素电极的电压减小，导致像素电极的电压保持能力较差，使得液晶分子的偏转受到较大影响。
相对于相关技术，本发明实施例提供的像素电路，在显示子电路与数据线之间间隔有第一充电子电路和第二充电子电路，第一充电子电路向充电节点输出数据信号，第二充电子电路向显示子电路输出来自充电节点的数据信号后，第一充电子电路能够存储该数据信号，使得充电节点能够保持为高电压，第二充电子电路两端的压差较小，该较小的压差使得向数据线输出的漏电流减小，因此，有效地减小了液晶电容与第二充电子电路连接的一端电压 减小的幅度，进而减小了液晶电容的电容减小的幅度，有效地减小了漏电流对液晶分子的偏转的影响，保证了显示器的图像显示效果，并解决了相关技术中像素电极无法将其电压在1秒甚至更长时间内保持为高电位的问题。
图5是本发明实施例提供的一种像素电路的驱动方法，该驱动方法可以应用于图1-2、图1-3、图3-1或图3-2任一所示的像素电路，该像素电路可以包括：栅线G1、数据线D、第一充电子电路01、第二充电子电路02和显示子电路03，第二充电子电路02分别与充电节点P、栅线G1和显示子电路03连接，如图5所示，该像素电路的驱动方法可以包括：
步骤501、控制第一充电子电路向充电节点输出来自数据线的数据信号并存储来自数据线的数据信号。
步骤502、栅线提供第一电平的栅极驱动信号，第二充电子电路向显示子电路输出来自充电节点的数据信号。
步骤503、控制线提供第二电平的栅极驱动信号，充电节点与数据线断开连接。
步骤504、栅线提供第二电平的栅极驱动信号，充电节点与液晶电容断开连接。
综上所述，本发明实施例提供的像素电路的驱动方法，通过控制第一充电子电路向充电节点输出来自数据线的数据信号并存储来自数据线的数据信号，栅线提供第一电平的栅极驱动信号，第二充电子电路向显示子电路输出来自充电节点的数据信号，在显示子电路与数据线之间间隔有第一充电子电路和第二充电子电路，第一充电子电路向充电节点输出数据信号，第二充电子电路向显示子电路输出来自充电节点的数据信号后，第一充电子电路能够存储该数据信号，使得充电节点能够保持为高电压，第二充电子电路两端的压差较小，该较小的压差使得向数据线输出的漏电流减小，因此，有效地减小了液晶电容与第二充电子电路连接的一端电压减小的幅度，进而减小了液晶电容的电容减小的幅度，有效地减小了漏电流对液晶分子的偏转的影响，保证了显示器的图像显示效果。
其中，显示子电路03中可以包括液晶电容，向显示子电路输出来自充电接点的数据信号就是向液晶电容充电的过程。
可选地，如图1-2、图1-3、图3-1和图3-2所示，第一充电子电路01可以包括：第一晶体管M1和存储电容Cst，该第一晶体管M1的栅极与栅线 G1或控制线G2连接，第二充电子电路02可以包括：第二晶体管M2，该第二晶体管M2的栅极与栅线G1连接，第一晶体管M1的第二极与第二晶体管M2的第一极连接。
当第一晶体管M1的栅极与栅线G1或控制线G2连接，第二晶体管M2的栅极与栅线G1连接时，第一晶体管M1和第二晶体管M2的导通情况不同，相应地，数据线D通过第一充电子电路01和第二充电子电路02为液晶电容Clc充电的过程也会不同，两种情况下像素电路的驱动方法可以分为以下三种可实现方式：
第一种可实现方式：当第一晶体管M1的栅极与控制线G2连接，第二晶体管M2的栅极与栅线G1连接时，第一晶体管M1和第二晶体管M2的导通情况，以及数据线D通过第一充电子电路01和第二充电子电路02为液晶电容Clc充电的过程，例如可以包括两个阶段：
第一充电阶段t1，当控制线G2提供第一电平的栅极驱动信号时，第一晶体管M1在栅极驱动信号的作用下导通，数据线D通过第一晶体管M1为存储电容Cst充电。
第二充电阶段t2，当栅线G1提供第一电平的栅极驱动信号时，第二晶体管M2在栅极驱动信号的作用下导通，存储电容Cst通过第二晶体管M2为液晶电容Clc充电。
可选地，当该两个充电阶段的时长相等时，该两个充电阶段的时间可以完全重叠、部分重叠或者完全不重叠，此时，第一晶体管M1的栅极连接的控制线G2和第二晶体管M2的栅极连接的栅线G1上加载的栅极驱动信号的波形图请分别参考图6-1、图6-2和图6-3。或者，当该两个充电阶段的时长也可以不相等，此时，该两个阶段的时间可以部分重叠或者完全不重叠。
本发明实施例以两个充电阶段的时间可以完全不重叠为例，对整个充电过程进行说明，当两个阶段的时间完全重叠或部分重叠时，其充电过程可相应参考两个阶段的时间完全不重叠的过程。
对图1-2所示的像素电路，当两个阶段的时间完全不重叠时，参考图6-3，其充电过程包括第一充电阶段t1和第二充电阶段t2。
在第一充电阶段t1中，控制线G2提供第一电平(例如：10伏)的栅极驱动信号，第一晶体管M1在栅极驱动信号的作用下导通，数据线D通过第一晶体管M1为第一晶体管M1的第二极充电，即为存储电容Cst充电，以 将第一晶体管M1的第二极(即与存储电容Cst相连的一极)的电压已被充至第一高电位(例如：10伏)。
在第二充电阶段t2中，栅线G1提供第一电平的栅极驱动信号时，第二晶体管M2在栅极驱动信号的作用下导通，第一晶体管M1的第二极(也即是存储电容Cst)通过第二晶体管M2为液晶电容Clc充电(即为像素电极充电)，以将第二晶体管M2的第二极以及像素电极也被充至第二高电位。
并且，从图6-3可以看出，在该第二充电阶段t2中，控制线G2提供第二电平(例如：0伏)的栅极驱动信号，此时第一晶体管M1关断，充电节点P与数据线D断开连接。
在该第二充电阶段t2之后，栅线G1提供的栅极驱动信号跳变为第二电平，第二晶体管M2关断，充电节点P与液晶电容Clc断开连接。
其中，第一充电阶段t1和第二充电阶段t2中控制线G2提供的栅极驱动信号、栅线G1提供的栅极驱动信号、数据线D上加载的信号、第一晶体管M1的第二极的电压波形和第二晶体管M2的第二极的电压波形请参考图6-4。
需要说明的是，第一高电位的幅值主要由数据线D的电位决定，第二高电位的幅值由第一高电位的幅值、存储电容Cst的电容值和液晶电容Clc的电容值共同决定。并且，当存储电容Cst的电容值与液晶电容Clc的电容值的差距越大时，第二晶体管M2的第二极与第一晶体管M1的第二极之间的压差越小，因此，在实际应用中可以设置存储电容Cst的电容值远大于液晶电容Clc的电容值，例如：可以设置存储电容Cst的电容值为10倍的液晶电容Clc的电容值。
实际应用中，第二高电位是在第一高电位基础上经过一定的电压降之后得到的，且像素电极的电位是在第二高电位的基础上经过一定的电压降之后得到的，在该前提下，为了尽量减小第二高电位与第一高电位之间的电压差，以及像素电极的电位与第二高电位之间的电压差，可以采用增大公共电极上的电压的幅值的方式补偿上述电压降，使得第二高电位更接近第一高电位，以及像素电极的电位更接近第二高电位甚至等于第一高电位。
第二种可实现方式：当第一晶体管M1的栅极和第二晶体管M2的栅极均与栅线G1连接时，第一晶体管M1和第二晶体管M2的导通情况，以及数据线D通过第一充电子电路01和第二充电子电路02为液晶电容Clc充电 的过程，例如可以为：
当第一晶体管M1和第二晶体管M2所连接的栅线G1提供第一电平的栅极驱动信号时，第一晶体管M1和第二晶体管M2在栅极驱动信号的作用下导通，并且，在第一晶体管M1和第二晶体管M2导通的过程中，数据线D通过第一晶体管M1和第二晶体管M2为液晶电容Clc充电。
第三种可实现方式：当第一晶体管M1的栅极与控制线G2连接，第二晶体管M2的栅极与栅线G1连接，且控制线G2与栅线G1彼此电连接时，第一晶体管M1和第二晶体管M2的导通情况，以及数据线D通过第一充电子电路01和第二充电子电路02为液晶电容Clc充电的过程，例如可以为：
当栅线G1(或控制线G2)提供第一电平的栅极驱动信号时，第一晶体管M1和第二晶体管M2在栅极驱动信号的作用下导通，并且，在第一晶体管M1和第二晶体管M2导通的过程中，数据线D通过第一晶体管M1和第二晶体管M2为液晶电容Clc充电。
可选地，上述第一电平相对于第二电平为高电平，例如：第一电平为10伏，第二电平为0伏。
需要说明的是，当第一充电子电路01包括至少两个串联的充电子子电路011，且至少两个串联的充电子子电路011每个充电子子电路011中的第一晶体管M1的栅极分别与不同的控制线连接时，像素电路的驱动方法请参考上述驱动方法，本发明实施例对其不再赘述。
综上所述，本发明实施例提供的像素电路的驱动方法，通过控制第一充电子电路向充电节点输出来自数据线的数据信号并存储来自数据线的数据信号，栅线提供第一电平的栅极驱动信号，第二充电子电路向显示子电路输出来自充电节点的数据信号，在显示子电路与数据线之间间隔有第一充电子电路和第二充电子电路，第一充电子电路向充电节点输出数据信号，第二充电子电路向显示子电路输出来自充电节点的数据信号后，第一充电子电路能够存储该数据信号，使得充电节点能够保持为高电压，第二充电子电路两端的压差较小，该较小的压差使得向数据线输出的漏电流减小，因此，有效地减小了液晶电容与第二充电子电路连接的一端电压减小的幅度，进而减小了液晶电容的电容减小的幅度，有效地减小了漏电流对液晶分子的偏转的影响，保证了显示器的图像显示效果，并解决了相关技术中像素电极无法将其电压在1秒甚至更长时间内保持为高电位的问题。
图7为本发明实施例提供的一种显示基板的结构示意图，如图7所示，该显示基板可以包括：多条栅线(图中的多条栅线分别为G1、G3和G5)、多条数据线(图中多条栅数据线分别为D1、D2和D3)、及由栅线和数据线交叉围成的多个像素单元，多个像素单元呈阵列排布，其中，每个像素单元中包括一像素电路0(如图7中虚线框所示)，该像素电路可以为图1-2、图1-3、图3-1或图3-2任一所示的像素电路。
在一种可实现方式中，显示基板还可以包括：多条控制线(图中的多条控制线分别为G2、G4和G6)，像素电路中第一充电子电路与该多条控制线连接，位于同一列且相邻的两个像素单元中，第一像素单元中像素电路的第二充电子电路所连接的栅线与第二像素单元中像素电路的第一充电子电路所连接的控制线可以彼此电连接(图中未示出其连接方式)，其中，第一像素单元和第二像素单元按照多条栅线对多个像素单元的扫描方向排列。
示例的，假设图7中的多条栅线按照从上至下的顺序对多个像素单元进行扫描，则第一行像素单元中像素电路的第二充电子电路所连接的栅线G1与该第二行像素单元中像素电路的第一充电子电路所连接的控制线G4可以彼此电连接。当两者电连接时，第一像素单元中像素电路的第二晶体管和第二像素单元中像素电路的第一晶体管能够同时导通并充电，减小了显示基板上液晶电容的充电总时间。
在另一种可实现方式中，位于同一列且相邻的两个像素单元中，第一像素单元中像素电路的第二充电子电路和第二像素单元中像素电路的第一充电子电路可以均与同一条栅线连接，其中，第一像素单元和第二像素单元按照多条栅线对多个像素单元的扫描方向排列。
当第一像素单元中像素电路的第二充电子电路与第二像素单元中像素电路的第一充电子电路均与同一条栅线连接时，相对于第一像素单元中像素电路的第二充电子电路所连接的栅线与第二像素单元中像素电路的第一充电子电路所连接的控制线为不同栅线的情况，增大了显示基板的开口率。
在又一种可实现方式中，如图8-1所示，位于同一列且相邻的两个像素单元中，第一像素单元中像素电路的第二充电子电路所连接的栅线和第二像素单元中像素电路的第一充电子电路所连接的控制线可以与同一个栅极驱动信号输出端连接，其中，第一像素单元和第二像素单元按照多条栅线对多个像素单元的扫描方向排列。
例如：图8-1为多条栅线(G1、G3和G5)和多条控制线(G2、G4和G6)与多个栅极驱动信号输出端(F1、F2、F3和F4)连接的示意图，如图8-1所示，第一行像素单元中像素电路的第二充电子电路所连接的栅线G1与该第二行像素单元中像素电路的第一充电子电路所连接的控制线G4可以与同一个栅极驱动信号端F2连接。
对于图8-1所示的结构，各个栅极驱动信号输出端输出的信号波形可以如图8-2所示，即各个栅极驱动信号输出端可以依次输出第一电平的栅极驱动信号；相应的，显示基板中各条栅线上加载的栅极驱动信号的波形可以如图8-3所示。从图8-3可以看出，与同一个栅极驱动信号输出端连接的栅线和控制线上加载的栅极驱动信号相同。
当第一像素单元中像素电路的第二充电子电路所连接的栅线和第二像素单元中像素电路的第一充电子电路所连接的控制线与同一个栅极驱动信号输出端连接时，能够使第一像素单元中像素电路的第二充电子电路中第二晶体管和第二像素单元中像素电路的第一充电子电路中第一晶体管同时开始充电，减小了显示基板上液晶电容的充电总时间，并且，无需增加栅极驱动信号输出端的数量，相对地降低了显示基板的生产成本。
综上所述，本发明实施例提供的显示基板，该显示基板包括多个像素单元，每个像素单元中包括一像素电路，每个像素电路在显示子电路与数据线之间间隔有第一充电子电路和第二充电子电路，第一充电子电路向充电节点输出数据信号，第二充电子电路向显示子电路输出来自充电节点的数据信号后，第一充电子电路能够存储该数据信号，使得充电节点能够保持为高电压，第二充电子电路两端的压差较小，该较小的压差使得向数据线输出的漏电流减小，因此，有效地减小了液晶电容与第二充电子电路连接的一端电压减小的幅度，进而减小了液晶电容的电容减小的幅度，有效地减小了漏电流对液晶分子的偏转的影响，保证了显示器的图像显示效果，并解决了相关技术中像素电极无法将其电压在1秒甚至更长时间内保持为高电位的问题。
本发明实施例还提供了一种显示装置，该显示装置可以包括图7或图8-1所示的显示基板。显示装置可以为：液晶面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通 过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (14)

  1. 一种像素电路，包括：
    栅线、数据线、第一充电子电路、第二充电子电路和显示子电路；
    所述第一充电子电路被配置为可被控制以向充电节点输出来自所述数据线的数据信号并存储来自所述数据线的数据信号；
    所述第二充电子电路分别与所述充电节点、所述栅线和所述显示子电路连接，其被配置为可被控制以向所述显示子电路输出来自所述充电节点的数据信号。
  2. 根据权利要求1所述的像素电路，其中，所述第一充电子电路包括：第一晶体管和存储电容；
    所述第一晶体管的栅极与所述栅线连接；或者，所述像素电路还包括：控制线，所述第一晶体管的栅极与所述控制线连接；
    所述第一晶体管的第一极与所述数据线连接，所述第一晶体管的第二极与所述充电节点连接；
    所述存储电容的一端与所述充电节点连接，所述存储电容的另一端与公共电极连接。
  3. 根据权利要求1所述的像素电路，其中，所述第一充电子电路包括：至少两个串联的充电子子电路，每个充电子子电路包括：第一晶体管和存储电容；
    所述第一晶体管的栅极与所述栅线连接；或者，所述像素电路还包括：控制线，所述第一晶体管的栅极与所述控制线连接；
    所述第一晶体管的第二极与所述存储电容的一端连接，所述存储电容的另一端与公共电极连接；
    所述多个串联的充电子子电路中，第一充电子子电路中第一晶体管的第一极与所述数据线连接，第二充电子子电路中第一晶体管的第二极与所述充电节点连接；
    所述第一充电子子电路和所述第二充电子子电路为所述至少两个串联的充电子子电路中两端的充电子子电路。
  4. 根据权利要求1所述的像素电路，其中，所述第二充电子电路，包括：第二晶体管；
    所述第二晶体管的栅极与所述栅线连接，所述第二晶体管的第一极与所述充电节点连接，所述第二晶体管的第二极与所述显示子电路连接。
  5. 根据权利要求2或3所述的像素电路，其中，所述第一晶体管的栅极与控制线连接，所述控制线与所述栅线彼此电连接。
  6. 根据权利要求3所述的像素电路，其中，所述像素电路包括：多条控制线，每个充电子子电路中的第一晶体管的栅极分别与不同的控制线连接。
  7. 根据权利要求2或3所述的像素电路，其中，所述显示子电路包括液晶电容，所述像素电路中存储电容的电容值大于所述液晶电容的电容值。
  8. 一种像素电路的驱动方法，其中，所述像素电路包括：栅线、数据线、第一充电子电路、第二充电子电路和显示子电路，所述第二充电子电路分别与所述充电节点、所述栅线和所述显示子电路连接，所述方法包括：
    控制所述第一充电子电路向所述充电节点输出来自所述数据线的数据信号并存储来自所述数据线的数据信号；
    所述栅线提供第一电平的栅极驱动信号，所述第二充电子电路向所述显示子电路输出来自所述充电节点的数据信号。
  9. 根据权利要求8所述的驱动方法，其中，所述显示子电路包括液晶电容，所述像素电路还包括：控制线；所述第一充电子电路包括：第一晶体管和存储电容，所述第一晶体管的栅极与所述控制线连接；所述第二充电子电路，包括：第二晶体管，所述第二晶体管的栅极与所述栅线连接；所述第一晶体管的第二极与所述第二晶体管的第一极连接；
    所述控制所述第一充电子电路向所述充电节点输出来自所述数据线的数据信号并存储来自所述数据线的数据信号，包括：
    所述控制线提供第一电平的栅极驱动信号，所述第一晶体管导通，所述 数据线通过所述第一晶体管为所述存储电容充电；
    所述栅线提供第一电平的栅极驱动信号，所述第二充电子电路向所述显示子电路输出来自所述充电节点的数据信号，包括：
    所述栅线提供第一电平的栅极驱动信号，所述第二晶体管导通，所述存储电容通过所述第二晶体管为所述液晶电容充电。
  10. 根据权利要求8所述的驱动方法，其中，所述显示子电路包括液晶电容，所述第一充电子电路包括：第一晶体管和存储电容，所述第一晶体管的栅极与所述栅线连接；所述第二充电子电路，包括：第二晶体管，所述第二晶体管的栅极与所述栅线连接；所述第一晶体管的第二极与所述第二晶体管的第一极连接；
    在所述栅线提供第一电平的栅极驱动信号时，所述第一晶体管和所述第二晶体管导通，所述数据线通过所述第一晶体管和所述第二晶体管为所述液晶电容充电。
  11. 根据权利要求9或10所述的驱动方法，其中，所述方法还包括：
    所述控制线提供第二电平的栅极驱动信号，所述充电节点与所述数据线断开连接；
    所述栅线提供第二电平的栅极驱动信号，所述充电节点与所述液晶电容断开连接。
  12. 一种显示基板，包括：多条栅线、多条数据线、及由所述栅线和所述数据线交叉围成的多个像素单元，所述多个像素单元呈阵列排布，其中，每个像素单元中包括一像素电路，所述像素电路为权利要求1至7任一所述的像素电路。
  13. 根据权利要求12所述的显示基板，其中，所述显示基板还包括：多条控制线，所述像素电路中第一充电子电路与控制线连接，位于同一列且相邻的两个像素单元中，第一像素单元中第二充电子电路所连接的栅线与第二像素单元中第一充电子电路所连接的控制线彼此电连接，其中，所述第一像素单元和所述第二像素单元按照所述多条栅线对所述多个像素单元的扫描方 向排列。
  14. 一种显示装置，包括：如权利要求12或13所述的显示基板。
PCT/CN2018/075435 2017-07-26 2018-02-06 一种像素电路及其驱动方法、显示基板、显示装置 WO2019019605A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/301,646 US11238768B2 (en) 2017-07-26 2018-02-06 Pixel circuit and driving method thereof, display substrate, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710618939.8A CN107221300A (zh) 2017-07-26 2017-07-26 像素电路及其驱动方法、显示基板、显示装置
CN201710618939.8 2017-07-26

Publications (1)

Publication Number Publication Date
WO2019019605A1 true WO2019019605A1 (zh) 2019-01-31

Family

ID=59953905

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/075435 WO2019019605A1 (zh) 2017-07-26 2018-02-06 一种像素电路及其驱动方法、显示基板、显示装置

Country Status (3)

Country Link
US (1) US11238768B2 (zh)
CN (1) CN107221300A (zh)
WO (1) WO2019019605A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107221300A (zh) * 2017-07-26 2017-09-29 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置
CN110021262B (zh) * 2018-07-04 2020-12-18 京东方科技集团股份有限公司 像素电路及其驱动方法、像素单元、显示面板
CN109616042B (zh) * 2019-02-14 2022-02-11 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN110033729B (zh) * 2019-05-17 2022-10-04 京东方科技集团股份有限公司 像素电路、显示面板及驱动方法、显示装置
CN110738974B (zh) * 2019-10-28 2022-05-20 京东方科技集团股份有限公司 液晶像素电路、其驱动方法、显示面板及显示装置
CN111458944A (zh) * 2020-04-23 2020-07-28 Oppo广东移动通信有限公司 显示装置及电子设备
CN114464122B (zh) * 2022-01-21 2024-02-06 京东方科技集团股份有限公司 显示装置的驱动方法、goa电路的驱动方法、显示装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5517150A (en) * 1991-10-01 1996-05-14 Nec Corporation Analog switch formed of thin film transistor and having reduced leakage current
CN101614919A (zh) * 2009-08-14 2009-12-30 上海广电光电子有限公司 场序液晶显示装置及其驱动方法
WO2011083598A1 (ja) * 2010-01-07 2011-07-14 シャープ株式会社 半導体装置、アクティブマトリクス基板、及び表示装置
CN102169668A (zh) * 2010-02-25 2011-08-31 索尼公司 像素电路、液晶装置及电子装置
CN102800288A (zh) * 2011-05-23 2012-11-28 刘鸿达 电子装置系统
CN106157903A (zh) * 2014-09-23 2016-11-23 元太科技工业股份有限公司 显示器
CN106842748A (zh) * 2017-03-28 2017-06-13 信利半导体有限公司 一种液晶显示装置的像素结构及液晶显示装置
CN107221300A (zh) * 2017-07-26 2017-09-29 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6956553B2 (en) * 2001-04-27 2005-10-18 Sanyo Electric Co., Ltd. Active matrix display device
JP4865512B2 (ja) * 2006-11-27 2012-02-01 株式会社 日立ディスプレイズ 画面入力機能付き画像表示装置
TWI440926B (zh) * 2010-12-31 2014-06-11 Hongda Liu 液晶顯示裝置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5517150A (en) * 1991-10-01 1996-05-14 Nec Corporation Analog switch formed of thin film transistor and having reduced leakage current
CN101614919A (zh) * 2009-08-14 2009-12-30 上海广电光电子有限公司 场序液晶显示装置及其驱动方法
WO2011083598A1 (ja) * 2010-01-07 2011-07-14 シャープ株式会社 半導体装置、アクティブマトリクス基板、及び表示装置
CN102169668A (zh) * 2010-02-25 2011-08-31 索尼公司 像素电路、液晶装置及电子装置
CN102800288A (zh) * 2011-05-23 2012-11-28 刘鸿达 电子装置系统
CN106157903A (zh) * 2014-09-23 2016-11-23 元太科技工业股份有限公司 显示器
CN106842748A (zh) * 2017-03-28 2017-06-13 信利半导体有限公司 一种液晶显示装置的像素结构及液晶显示装置
CN107221300A (zh) * 2017-07-26 2017-09-29 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置

Also Published As

Publication number Publication date
US11238768B2 (en) 2022-02-01
US20210233448A1 (en) 2021-07-29
CN107221300A (zh) 2017-09-29

Similar Documents

Publication Publication Date Title
US11263942B2 (en) Shift register unit and driving method thereof, gate driving circuit, and display device
WO2019019605A1 (zh) 一种像素电路及其驱动方法、显示基板、显示装置
US9659540B1 (en) GOA circuit of reducing power consumption
US9378698B2 (en) Pixel driving circuit and method, array substrate and liquid crystal display apparatus
US9990895B2 (en) Display apparatus and driving method of display panel thereof
US10199004B2 (en) Display device
CN109300445B (zh) 阵列基板行驱动电路及显示装置
JP5538765B2 (ja) 液晶表示装置
CN107578751B (zh) 数据电压存储电路、驱动方法、液晶显示面板及显示装置
CN108319049B (zh) 液晶显示器及液晶显示器驱动方法
WO2017128645A1 (zh) 像素电路及其驱动方法、显示面板和显示装置
CN108766377B (zh) 显示面板和显示装置
CN108735174B (zh) 像素驱动电路、像素驱动方法及显示装置
US10360866B2 (en) GOA circuit and liquid crystal display device
US8144098B2 (en) Dot-matrix display refresh charging/discharging control method and system
US8860646B2 (en) Liquid crystal display device
JP5329670B2 (ja) メモリ装置およびメモリ装置を備えた液晶表示装置
US20210271142A1 (en) Array substrate and method for driving the same, and display device
US10482834B2 (en) Pixel circuit, display device, display apparatus and driving method
US20120200549A1 (en) Display Device And Drive Method For Display Device
CN108630161B (zh) 电压提供电路与控制电路
JP2009086170A (ja) 電気光学装置及び電気光学装置の駆動方法並びに電子機器
KR20150028402A (ko) 인셀 터치 액정표시장치
US20120169750A1 (en) Display device and drive method for display device
CN103135270B (zh) 薄膜晶体管液晶显示器的驱动方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18839169

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18839169

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 28.05.2020)

122 Ep: pct application non-entry in european phase

Ref document number: 18839169

Country of ref document: EP

Kind code of ref document: A1