WO2016078143A1 - 一种移位寄存器单元、栅极驱动电路及显示装置 - Google Patents

一种移位寄存器单元、栅极驱动电路及显示装置 Download PDF

Info

Publication number
WO2016078143A1
WO2016078143A1 PCT/CN2014/092899 CN2014092899W WO2016078143A1 WO 2016078143 A1 WO2016078143 A1 WO 2016078143A1 CN 2014092899 W CN2014092899 W CN 2014092899W WO 2016078143 A1 WO2016078143 A1 WO 2016078143A1
Authority
WO
WIPO (PCT)
Prior art keywords
type transistor
stage
shift register
gate
register unit
Prior art date
Application number
PCT/CN2014/092899
Other languages
English (en)
French (fr)
Inventor
虞晓江
张鑫
夏军
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/426,446 priority Critical patent/US9779681B2/en
Publication of WO2016078143A1 publication Critical patent/WO2016078143A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of display driving technologies, and in particular, to a shift register unit, a gate driving circuit, and a display device.
  • flat panel displays are high-tech that has developed rapidly in recent years. Because flat panel displays have many advantages, they are becoming more widely used. The advantages are: light weight, low voltage, no X-ray radiation, no flickering, no static electricity, low power consumption; and most displays have a longer life than cathode ray tubes.
  • the positive pole of the flat panel display can be made portable. Taking a liquid crystal display as an example, a liquid crystal display usually adopts a progressive scanning method when displaying an image, and the on and off of the thin film liquid transistor of each row of sub-pixel regions is controlled by one gate line.
  • the gate drive circuit for driving the pixel set of the liquid crystal display has a complicated structure, resulting in a large frame of the liquid crystal display and high power consumption.
  • the technical problem to be solved by the present invention is to provide a shift register unit, a gate driving circuit and a display device to reduce the frame size of the liquid crystal display.
  • the present invention provides a shift register unit for providing a gate voltage for an nth-level pixel of a liquid crystal display, wherein the shift register unit includes a first P-type transistor, a second P-type transistor, and a third P Type transistor, wherein
  • a gate of the first P-type transistor receives a gate voltage of an nth-th stage pixel, a first stage of the first P-type transistor receives a first input signal, and a second stage of the first P-type transistor Connected to a gate of the third P-type transistor; wherein a gate voltage of the n-2th pixel is used to control the Turning on and off of a P-type transistor, thereby controlling switching of the first input signal to the third P-type transistor; wherein n is a natural number greater than 2;
  • a gate of the second P-type transistor receives a gate voltage of an n+2th pixel, a first stage of the second P-type transistor receives the second input signal, and a second P-type transistor Connected to the gate of the third P-type transistor; wherein a gate voltage of the n+2th pixel is used to control on and off of the second P-type transistor, thereby controlling the second input Turning on and off the third P-type transistor;
  • a first stage of the third P-type transistor is coupled to the first clock signal or a second clock signal, and a second stage of the second P-type transistor is used as a voltage output terminal of the mobile register unit for connecting to the The nth pixel is charged and discharged to the nth pixel to provide a gate voltage.
  • the shift register unit further includes a first capacitor connected between a gate of the third P-type transistor and a second stage of the third P-type transistor.
  • the shift register unit further includes a fourth P-type transistor, the gate of the fourth P-type transistor receiving the first clock signal or the second clock signal, the first stage of the fourth P-type transistor Connected to a gate of the third P-type transistor, a second stage of the fourth P-type transistor is coupled to a second end of the third P-type transistor, wherein a gate of the fourth P-type transistor The same as the clock signal received by the first stage of the third P-type transistor.
  • the shift register unit further includes a fifth P-type transistor, the first stage of the fifth P-type transistor is connected to the second stage of the third P-type transistor, and the fifth P-type transistor is The second stage is connected to a DC high voltage source, and the gate of the fifth P-type transistor receives a pull-up control signal to be in an off state when the third P-type transistor is turned on.
  • the shift register unit further includes a sixth P-type transistor, a seventh P-type transistor, an eighth P-type transistor, and a second capacitor, and a gate of the sixth P-type transistor is connected to the sixth P-type a first stage of the transistor, the first stage of the sixth P-type transistor receives a second clock signal or a first clock signal, and the second stage of the sixth P-type transistor is coupled to the first end of the second capacitor And connected to a gate of the fifth P-type transistor to output the pull-up control signal to a gate of the fifth P-type transistor, the second end of the second capacitor being connected to the fifth a second stage of the P-type transistor, a gate of the seventh P-type transistor being coupled to a second stage of the first and second P-type transistors, the first stage of the seventh P-type transistor being coupled to the a gate of the sixth P-type transistor or connecting the DC high voltage a second stage of the seventh P-type transistor connected to a second stage of the sixth P-type transistor, a gate of the eighth P-
  • the present invention also provides a gate driving circuit for providing a gate voltage for a pixel set of a liquid crystal display, wherein: the gate driving circuit includes first and second sets of shift register units, the first group shift a bit register unit disposed on one side of the set of pixels to provide a gate voltage for pixels of a base row of the set of pixels, the second set of shift register units being disposed on another side of the set of pixels, The pixels of the even rows of the pixel set provide a gate voltage, wherein each of the first and second sets of shift register cells includes a first P-type transistor, a second P-type transistor, and a first a three P-type transistor, one shift register unit corresponding to one row of pixels;
  • the gates of the first P-type transistors of each of the shift register units are connected to the corresponding shift register unit of the corresponding group.
  • a voltage output end the first stage of the first P-type transistor receives the first input signal
  • the second stage of the first P-type transistor is connected to the gate of the corresponding third P-type transistor;
  • the upper level of the corresponding group a voltage output terminal of the shift register unit is configured to control on and off of the corresponding first P-type transistor, thereby controlling switching of the first input signal to the corresponding third P-type transistor;
  • the gates of the second P-type transistors of each of the shift register units are connected to the shift register unit of the corresponding group of the next stage.
  • a voltage output terminal, a first stage of the second P-type transistor receives the second input signal, and a second stage of the second P-type transistor is coupled to a gate of the corresponding third P-type transistor; wherein, the next group of the corresponding group
  • the voltage output terminal of the stage shift register unit is configured to control on and off of the corresponding second P-type transistor, thereby controlling switching of the second input signal to the corresponding third P-type transistor;
  • a first stage of a third P-type transistor of each shift register unit is coupled to a first or second clock signal, and a second stage of the third P-type transistor is used as a voltage output of a corresponding shift register unit for connection to The pixels of the corresponding row are charged and discharged to provide the gate voltage.
  • the first group and the second group of shift register units are all disposed on a glass substrate of the liquid crystal display.
  • Each of the shift register sheets further includes a first capacitor connected between a gate of the third P-type transistor of the corresponding shift register and a second stage of the third P-type transistor.
  • each shift register unit further includes a fourth P-type transistor, the gate of the fourth P-type transistor receiving the first clock signal or the second clock signal, the first stage of the fourth P-type transistor Connected to a gate of a corresponding third P-type transistor, the second stage of the fourth P-type transistor being connected to a second end of a corresponding third P-type transistor, wherein a gate of the fourth P-type transistor The same as the clock signal received by the first stage of the corresponding third P-type transistor.
  • the present invention also provides a liquid crystal display including a pixel set and a gate driving circuit, wherein the gate driving circuit includes first and second groups of shift register units, and the first group of shift register units are disposed at One side of the set of pixels, the gate voltage is provided for the pixels of the base row of the pixel set, and the second set of shift register units are disposed on the other side of the set of pixels to be the even row of the set of pixels
  • the pixel provides a gate voltage, wherein each of the first and second sets of shift register units includes a first P-type transistor, a second P-type transistor, and a third P-type transistor, one The shift register unit corresponds to a row of pixels,
  • the gates of the first P-type transistors of each of the shift register units are connected to the corresponding shift register unit of the corresponding group.
  • a voltage output end the first stage of the first P-type transistor receives the first input signal
  • the second stage of the first P-type transistor is connected to the gate of the corresponding third P-type transistor;
  • the upper level of the corresponding group a voltage output terminal of the shift register unit is configured to control on and off of the corresponding first P-type transistor, thereby controlling switching of the first input signal to the corresponding third P-type transistor;
  • the gates of the second P-type transistors of each of the shift register units are connected to the shift register unit of the corresponding group of the next stage.
  • a voltage output terminal, a first stage of the second P-type transistor receives the second input signal, and a second stage of the second P-type transistor is coupled to a gate of the corresponding third P-type transistor; wherein, the next group of the corresponding group
  • the voltage output terminal of the stage shift register unit is configured to control on and off of the corresponding second P-type transistor, thereby controlling switching of the second input signal to the corresponding third P-type transistor;
  • a first stage of a third P-type transistor of each shift register unit is coupled to a first or second clock signal, and a second stage of the third P-type transistor is used as a voltage output of a corresponding shift register unit for connection to The pixels of the corresponding row are charged and discharged to provide the gate voltage.
  • Each of the shift register sheets further includes a first capacitor connected between a gate of the corresponding third P-type transistor and a second stage of the corresponding third P-type transistor.
  • each shift register unit further includes a fourth P-type transistor, the gate of the fourth P-type transistor receiving the first clock signal or the second clock signal, the first stage of the fourth P-type transistor Connected to a gate of a corresponding third P-type transistor, the second stage of the fourth P-type transistor being connected to a second end of a corresponding third P-type transistor, wherein a gate of the fourth P-type transistor The same as the clock signal received by the first stage of the corresponding third P-type transistor.
  • each shift register unit further includes a fifth P-type transistor
  • the first stage of the fifth P-type transistor is connected to the second stage of the corresponding third P-type transistor
  • the fifth P-type transistor is The second stage is connected to a DC high voltage source, and the gate of the fifth P-type transistor receives a pull-up control signal to be in an off state when the corresponding third P-type transistor is turned on.
  • Each of the shift register units further includes a sixth P-type transistor, a seventh P-type transistor, an eighth P-type transistor, and a second capacitor, and a gate of the sixth P-type transistor is connected to the sixth P-type a first stage of the transistor, the first stage of the sixth P-type transistor receives a second clock signal or a first clock signal, and the second stage of the sixth P-type transistor is coupled to the first end of the corresponding second capacitor And connected to the gate of the corresponding fifth P-type transistor to output the pull-up control signal to the gate of the corresponding fifth P-type transistor, the second end of the second capacitor being connected to the corresponding fifth a second stage of the P-type transistor, a gate of the seventh P-type transistor being coupled to a second stage of the respective first and second P-type transistors, the first stage of the seventh P-type transistor being coupled to a corresponding a gate of the sixth P-type transistor or connected to the DC high voltage source, the second stage of the seventh P-type transistor being connected to a second stage of
  • the liquid crystal display further includes a glass substrate, and the first group and the second group of shift register units are disposed on the glass substrate.
  • Each of the shift register sheets further includes a first capacitor connected between a gate of the third P-type transistor of the corresponding shift register and a second stage of the third P-type transistor.
  • each shift register unit further includes a fourth P-type transistor, the fourth P-type transistor
  • the gate receives the first clock signal or the second clock signal
  • the first stage of the fourth P-type transistor is connected to the gate of the corresponding third P-type transistor
  • the second of the fourth P-type transistor The stage is coupled to the second terminal of the corresponding third P-type transistor, wherein the gate of the fourth P-type transistor is identical to the clock signal received by the first stage of the corresponding third P-type transistor.
  • the shift register unit of the present invention includes a first P-type transistor, a second P-type transistor, and a third P-type transistor.
  • the gate of the first P-type transistor receives the gate voltage of the n-2th stage pixel.
  • a first stage of the first P-type transistor is coupled to the first input signal.
  • a second stage of the first P-type transistor is coupled to a gate of the third P-type transistor.
  • the gate voltage of the n-2th stage pixel is used to control the on and off of the first P-type transistor, thereby controlling the on and off of the third P-type transistor by the first input signal.
  • n is a natural number greater than 2.
  • the gate of the second P-type transistor receives the gate voltage of the n+2th pixel.
  • a first stage of the second P-type transistor receives a second input signal.
  • a second stage of the second P-type transistor is coupled to a gate of the third P-type transistor.
  • the gate voltage of the n+2th pixel is used to control the on and off of the second P-type transistor, thereby controlling the on and off of the second P-type transistor by the second input signal.
  • the first stage of the third P-type transistor receives the first clock signal or the second clock signal.
  • a second stage of the second P-type transistor is used as a voltage output end of the mobile register unit for connecting to the nth-level pixel to charge and discharge the n-th pixel, thereby The nth stage pixel provides a gate voltage.
  • the shift register unit can provide a stable gate voltage for the nth-level pixel of the liquid crystal display, and has a compact structure, can reduce the frame size of the liquid crystal display, and the shift register unit belongs to a single-level architecture. In the course of operation, there will not be a continuous high current, so the power consumption is low.
  • FIG. 1 is a circuit diagram of a shift register unit according to a first embodiment of the first aspect of the present invention
  • FIG. 2 is a circuit diagram of a shift register unit according to a second embodiment of the first aspect of the present invention.
  • FIG. 3 is a schematic diagram of an application environment of a gate driving circuit according to an embodiment of a second aspect of the present invention.
  • FIG. 4 is a scanning timing diagram of a shift register unit of the gate driving circuit of FIG. 3;
  • FIG. 5 is a schematic diagram of a liquid crystal display according to an embodiment of the third aspect of the present invention.
  • a first embodiment of the first aspect of the present invention provides a shift register unit 100.
  • the shift register unit 100 is configured to provide a gate voltage for an nth-level pixel of the liquid crystal display.
  • the shift register unit 100 includes a first P-type transistor T1, a second P-type transistor T2, a third P-type transistor T3, and a first capacitor C1.
  • the gate of the first P-type transistor T1 receives the gate voltage of the n-2th stage pixel.
  • the first stage of the first P-type transistor T1 is coupled to the first input signal D2U.
  • a second stage of the first P-type transistor T1 is coupled to a gate of the third P-type transistor T3.
  • the gate voltage of the n-2th pixel is used to control the on and off of the first P-type transistor T1, thereby controlling the on/off of the third P-type transistor T3 by the first input signal D2U.
  • n is a natural number greater than 2.
  • the gate of the second P-type transistor T2 receives the gate voltage of the n+2th stage pixel.
  • the first stage of the second P-type transistor T2 receives the second input signal U2D.
  • the second stage of the second P-type transistor T2 is coupled to the gate of the third P-type transistor T3.
  • the gate voltage of the n+2th pixel is used to control the on and off of the second P-type transistor T2, thereby controlling the on and off of the third P-type transistor T3 by the second input signal.
  • the shift register unit 100 is an nth stage shift register unit.
  • the gate of the first P-type transistor T1 of the nth stage shift register unit receives the gate voltage of the n-2th stage pixel through a voltage output terminal G connected to the n-2th stage shift register unit (n-2) is obtained.
  • the gate of the second P-type transistor T2 of the nth stage shift register unit receives the gate voltage of the n+2th stage pixel through a voltage output terminal G connected to the n+2th stage shift register unit (n-2) is obtained.
  • the first stage of the third P-type transistor T3 receives the first clock signal CK1 or the second clock signal CK2.
  • the second stage of the second P-type transistor T2 serves as the voltage of the mobile register unit 100
  • the output terminal G(n) is configured to be connected to the nth-level pixel to charge and discharge the n-th pixel to provide a gate voltage for the nth-level pixel.
  • the first input signal D2U is opposite to the potential of the second input signal U2D, that is, when the first input signal D2U is a high potential signal, the second input signal U2D is low. signal.
  • the first input signal D2U is a low potential signal
  • the second input signal U2D is a high potential signal.
  • the first P-type transistor, the second P-type transistor, and the third P-type transistor are NMOS (N-Mental-Oxide-Semiconductor, N-type metal-oxide-semiconductor) thin film transistors. Since the source and drain of the first to third P-type transistors T1-T3 used herein are symmetrical, the source and the gate are indistinguishable. Therefore, the first stage and the second stage of the first to third P-type transistors T1-T3 may be a source and a drain, respectively, and may be a drain and a source.
  • the first to third P-type transistors T1-T3 may also be FETs or other devices having the same characteristics.
  • a node between the gate of the third P-type transistor T3 and the first and second P-type transistors T1 and T2 is defined as Q(n).
  • first capacitor C1 is connected between the gate of the third P-type transistor T3 and the second stage of the third P-type transistor T3.
  • the second input signal U2D is at a high potential.
  • the first P-type transistor T1 is turned on, so that the first input signal D2U is transmitted to the gate of the third P-type transistor T3.
  • the third P-type transistor T3 is turned on, and the first clock signal CK1 or the second clock signal CK2 charges and discharges the nth-level pixel through the voltage output terminal G(n) to provide a gate. Voltage.
  • the potential of the node Q(n) is adjusted due to the bootstrap effect of the first capacitor C1 to reduce the delay of outputting the gate voltage of the voltage output terminal G(n) of the shift register unit 100, The stability of the output of the shift register unit 100 is further improved.
  • the second P-type transistor T2 When the gate voltage of the n+2th pixel is low, the second P-type transistor T2 is turned on, so that the second input signal U2D is transmitted to the gate of the third P-type transistor T3. The third P-type transistor T3 is turned off. The first clock signal CK1 or the second clock signal CK2 no longer affects the potential of the voltage output terminal G(n) of the shift register unit 100.
  • the second input signal U2D is at a low potential.
  • the second P-type transistor T2 is turned on, so that the second input signal U2D is transmitted to the gate of the third P-type transistor T3.
  • the third P-type transistor T3 is turned on, and the first clock signal CK1 or the second clock signal CK2 charges and discharges the nth-level pixel through the voltage output terminal G(n) to provide a gate. Voltage.
  • the potential of the node Q(n) is adjusted due to the bootstrap effect of the first capacitor C1 to reduce the delay of outputting the gate voltage of the voltage output terminal G(n) of the shift register unit 100, The stability of the output of the shift register unit 100 is further improved.
  • the first P-type transistor T1 When the gate voltage of the n-2th pixel is low, the first P-type transistor T1 is turned on, so that the first input signal D2U is transmitted to the gate of the third P-type transistor T3. The third P-type transistor T3 is turned off. The first clock signal CK1 or the second clock signal CK2 no longer affects the potential of the voltage output terminal G(n) of the shift register unit 100.
  • the shift register unit 100 includes a first P-type transistor T1, a second P-type transistor T2, and a third P-type transistor T3.
  • the gate of the first P-type transistor T1 receives the gate voltage of the n-2th stage pixel.
  • the first stage of the first P-type transistor T1 is coupled to the first input signal D2U.
  • a second stage of the first P-type transistor T1 is coupled to a gate of the third P-type transistor T3.
  • the gate voltage of the n-2th pixel is used to control the on and off of the first P-type transistor T1, thereby controlling the on/off of the third input transistor to the third P-type transistor T3.
  • n is a natural number greater than 2.
  • the gate of the second P-type transistor T2 receives the gate voltage of the n+2th stage pixel.
  • the first stage of the second P-type transistor T2 receives the second input signal U2D.
  • the second stage of the second P-type transistor T2 is coupled to the gate of the third P-type transistor T3.
  • the gate voltage of the n+2th pixel is used to control the on and off of the second P-type transistor T2, thereby controlling the on and off of the third P-type transistor T3 by the second input signal U2D.
  • the first stage of the third P-type transistor T3 receives the first clock signal CK1 or the second clock signal CK2.
  • a second stage of the second P-type transistor T2 is used as a voltage output terminal G(n) of the mobile register unit 100 for connecting to the nth-level pixel to charge the nth-level pixel. Discharged to provide a gate voltage for the nth level of pixels. Therefore, the shift register unit 100 can provide a stable gate voltage for the nth-level pixel of the liquid crystal display, and has a compact structure, and can reduce the side of the liquid crystal display.
  • the frame size is small, and the shift register unit 100 belongs to a single-stage architecture, and does not travel continuously with a large current during operation, so power consumption is low.
  • the shift register unit 100 further includes a fourth P-type transistor T4.
  • the gate of the fourth P-type transistor T4 receives the first clock signal CK1 or the second clock signal CK2.
  • a first stage of the fourth P-type transistor T4 is coupled to a gate of the third P-type transistor T3.
  • the second stage of the fourth P-type transistor T4 is coupled to the second end of the third P-type transistor T3.
  • the gate of the fourth P-type transistor T4 is the same as the clock signal received by the first stage of the third P-type transistor T3.
  • the fourth P-type transistor T4 is controlled by the first clock signal CK1 or the second clock signal CK2 to pull up the node Q(n) during a non-charging period, and keep Q(n) at a high potential state. Thereby, the stability of the gate voltage output of the voltage output terminal G(n) of the shift register unit 100 is maintained.
  • the shift register unit 100 further includes a sixth P-type transistor T6, a seventh P-type transistor T7, an eighth P-type transistor T8, and a second capacitor C2.
  • the gate of the sixth P-type transistor T6 is connected to the first stage of the sixth P-type transistor T6.
  • the first stage of the sixth P-type transistor T6 receives the second clock signal CK2 or the first clock signal CK1.
  • the second stage of the sixth P-type transistor T6 is connected to the first end of the second capacitor C2 and is connected to the gate of the fifth P-type transistor T5 to output the pull-up control signal to the The gate of the fifth P-type transistor T5 is described.
  • the second end of the second capacitor C2 is coupled to the second stage of the fifth P-type transistor T5.
  • the gate of the seventh P-type transistor T7 is connected to the second stage of the first and second P-type transistors T1 and T2.
  • the first stage of the seventh P-type transistor T7 is coupled to the second stage of the sixth P-type transistor T6.
  • the second stage of the seventh P-type transistor T7 is coupled to the second stage of the sixth P-type transistor T6.
  • the gate of the eighth P-type transistor T8 receives a reset signal RESET.
  • a first stage of the eighth P-type transistor T8 is coupled to a gate of the seventh P-type transistor T7.
  • the second stage of the eighth P-type transistor T8 is coupled to the second stage of the fifth P-type transistor T5.
  • the first stage of the sixth P-type transistor T6 is different from the clock signal received by the first stage of the third P-type transistor T3.
  • the first stage of the third P-type transistor receives the first clock signal CK1
  • the first stage of the sixth P-type transistor T6 receives the second clock signal CK2
  • the gate of the fourth P-type transistor T4 receives the first clock signal CK1.
  • the first stage of the third P-type transistor receives the second clock signal CK2
  • the first stage of the sixth P-type transistor T6 Receiving the first clock signal CK1
  • the gate of the fourth P-type transistor T4 receives the second clock signal CK2.
  • the sixth P-type transistor T6, the seventh P-type transistor T8, and the second capacitor C2 may constitute a pull-up control unit to output the pull-up control signal.
  • the node P(n) between the second stage of the sixth P-type transistor T6 and the second capacitor C2 outputs the pull-up control signal to the gate of the fifth P-type transistor T5.
  • the pull-up control signal output by the node P(n) is used to control the fifth P-type transistor T5 to be turned off before charging and charging at the voltage input end of the n-th pixel, and other than The other time is in an on state to maintain the voltage output terminal G(n) of the shift register unit 100 in a high potential state.
  • the gate of the eighth P-type transistor T8 receives the reset signal RESET, and when the reset signal RESET is low, the eighth P-type transistor T8 is turned on, thereby pulling up the node Q(n) to a high level. a potential such that the third P-type transistor T3 is turned off, so that the gate voltage outputted by the voltage output terminal G(n) of the shift register unit 100 is not affected by the signal, thereby improving the shift register unit. 100 output stability.
  • a second embodiment of the first aspect of the present invention provides a shift register 200.
  • the shift register 200 provided by the second embodiment is similar to the shift register 100 provided by the first embodiment, and the difference is that in the second embodiment, the seventh P-type transistor T7 One stage is connected to the DC high voltage source to keep the fifth P type transistor in an off state when the voltage output terminal G(n) of the shift register 100 discharges the nth stage pixel, The voltage output terminal G(n) of the shift register unit 100 is maintained in a low potential state.
  • the node Q(n) when the voltage output terminal G(n) of the shift register 100 discharges the nth-level pixel, the node Q(n) is at a low potential, and the seventh P-type transistor T7 is turned on.
  • the node P(n) may be pulled up when the second clock signal or the first clock signal becomes high, such that the node P(n) is at a high potential, thereby causing the fifth P-type transistor T5 It is in the cutoff state.
  • the shift register unit 200 includes a first P-type transistor T1, a second P-type transistor T2, and a third P-type transistor T3.
  • the gate of the first P-type transistor T1 receives the gate voltage of the N-2th stage pixel.
  • the first stage of the first P-type transistor T1 is coupled to the first input signal D2U.
  • a second stage of the first P-type transistor T1 is coupled to a gate of the third P-type transistor T3.
  • the gate voltage of the n-2th pixel is used to control the on and off of the first P-type transistor T1, thereby controlling the on/off of the third P-type transistor T3 by the first input signal D2U.
  • n is a natural number greater than 2.
  • the gate of the second P-type transistor T2 receives the n+2th image The gate voltage of the element.
  • the first stage of the second P-type transistor T2 receives the second input signal U2D.
  • the second stage of the second P-type transistor T2 is coupled to the gate of the third P-type transistor T3.
  • the gate voltage of the n+2th pixel is used to control the on and off of the second P-type transistor T2, thereby controlling the on and off of the third P-type transistor T3 by the second input signal U2D.
  • the first stage of the third P-type transistor T3 receives the first clock signal CK1 or the second clock signal CK2.
  • a second stage of the second P-type transistor T2 is used as a voltage output terminal G(n) of the mobile register unit 100 for connecting to the nth-level pixel to charge the nth-level pixel. Discharged to provide a gate voltage for the nth level of pixels. Therefore, the shift register unit 100 can provide a stable gate voltage for the nth-level pixel of the liquid crystal display, and has a compact structure, can reduce the frame size of the liquid crystal display, and the shift register unit 100 belongs to a single The stage architecture does not run a large current during operation, so the power consumption is low.
  • a second aspect of the present invention provides a gate driving circuit 300.
  • the gate drive circuit 300 is configured to provide a gate voltage for the pixel set 310 of the liquid crystal display.
  • the gate driving circuit 300 includes a first register unit 301 and a second group of shift register units 302.
  • the first set of shift register units 301 are disposed on one side of the set of pixels 310 to provide gate voltages for pixels of the base row in the set of pixels 310.
  • the second set of shift register units 302 are disposed on the other side of the set of pixels 310 to provide gate voltages for pixels of even rows in the set of pixels 310.
  • the shift register unit in the first and second groups of shift register units 301 and 302 may be the shift register unit 100 provided in the first embodiment of the first scheme. It is of course also possible to provide the shift register unit 200 of the second embodiment of the first scheme.
  • the structure and function of the shift register unit 100 have been described in detail in the above first embodiment, and are not described herein again.
  • the gates of the first P-type transistors T1 of each of the shift register units 100 are connected to the corresponding groups.
  • the voltage output of the stage shift register unit 100 is connected to the first and second sets of shift register units 301 and 302, except for the first row shift register unit 100.
  • the gates of the second P-type transistors T2 of each of the shift register units 100 are connected to the next of the corresponding groups.
  • the voltage output of the stage shift register unit 100 is connected to the first and second sets of shift register units 301 and 302, except for the tail row shift register unit 100.
  • the first group of shift register units 301 includes a single-stage register unit 100, such as a first-level register unit, a third-level register unit, a fifth-level register unit, and the like. Said The first stage register unit, the third stage register unit, the fifth stage register unit, and the like respectively correspond to the first level pixel, the third level pixel, the fifth level pixel, and the like.
  • the gate of the first P-type transistor T1 of the third-stage shift register unit is connected to the voltage output terminal G of the first-stage shift register unit 100 except for the first-stage shift register unit located in the first row.
  • a gate of the second P-type transistor T2 of the third-stage shift register unit is connected to a voltage output terminal G(5) of the fifth-stage shift register unit 100;
  • the gate of the first P-type transistor T1 of the bit register unit is connected to the voltage output terminal G(3) of the third-stage shift register unit 100;
  • the second P-type transistor T2 of the fifth-stage shift register unit The gate is connected to the voltage output terminal G(7) of the seventh stage shift register unit 100; and so on, it will not be described again.
  • the first group and the second group of shift register units 301 and 302 are disposed on a glass substrate of the liquid crystal display.
  • FIG. 4 the structure shown in FIG. 1 is taken as an example, wherein the first to eighth P-type transistors T1-T8 in the shift register unit 100 are all PMOS thin film transistors.
  • the operation of the shift register unit 100 will be described in detail in conjunction with the scan timing chart of the shift register unit 100.
  • the first input signal D2U is at a low potential
  • the second input signal U2D is at a high potential
  • CK1_L and CK2_L are first and second clock signals that drive the first group of shift register units 301.
  • CK1_R and CK2_R are first and second clock signals that drive the second set of shift register units 302.
  • the reset signal RESET outputs a low potential during a special period (such as when turned on), so that the potential of the node Q(n) is pulled high. At this time, the clock signal no longer affects the voltage output end of the shift register unit output.
  • the period t1 to t3 is the preparation time of the voltage output terminal G(n-2) of the n-2th stage shift register unit before charging the n-2th stage pixel; the period t3 to t4 is the n-2th stage The charging time at which the voltage output terminal G(n-2) of the shift register unit charges the n-2th stage pixel.
  • the potentials of the second clock signal CK2_L and the voltage output terminal G(n-4) of the n-4th stage shift register unit start to decrease, and the number of the n-2th stage shift register unit 100
  • a P-type transistor T1 is turned on.
  • the node Q(n-2) is pulled to a low potential.
  • the third P-type transistor T3 is turned on, and the first clock signal CK1_L is at a high potential.
  • the voltage output terminal G(n-2) of the n-2th stage shift register unit 100 is at a high potential.
  • the potential of the second clock signal CK2_L and the voltage output terminal G(n-4) of the n-4th stage shift register unit rises, and the first of the n-2th stage shift register unit 100
  • the P-type transistor T1 is turned off, and the node Q(n-2) is kept at a low potential.
  • the potential of the node P(n-2) is pulled low to a high potential to turn on the fifth P-type transistor T5 which is pulled up.
  • the voltage output terminal G(n-2) of the n-2th stage shift register unit 100 is at a high potential.
  • the first clock signal CK1_L is lowered in potential, and since the node Q(n-2) is at a low potential, the third P-type transistor T3 of the n-2th stage shift register unit 100 is turned on. Thereby, the voltage output terminal G(n-2) of the n-2th stage shift register unit 100 is pulled to a low potential.
  • the first clock signal CK1_L rises in potential, and since the node Q(n-2) is still at a low potential, the third P-type transistor T3 of the n-2th stage shift register unit 100 still leads The voltage output terminal G(n-2) of the n-2th stage shift register unit 100 is pulled to a high potential.
  • the period from t3 to t5 is the preparation time before the voltage output terminal G(n) of the nth stage shift register unit is charged to the Nth stage pixel; the period from t5 to t6 is the voltage output of the nth stage shift register unit.
  • the shift register units of each stage charge and discharge the gate scan lines of the corresponding level pixels step by step, so that the liquid crystal panel can work normally.
  • the first and second groups of shift register units 301 and 302 each include the shift register unit 100.
  • the gates of the first P-type transistors T1 of each of the other shift register units 100 are connected to the voltage output terminals of the corresponding shift register unit 100 of the corresponding group.
  • the gates of the second P-type transistors T2 of each of the shift register units 100 are connected to the voltage output terminals of the shift register unit 100 of the corresponding group of the next stage.
  • the structure of the gate driving circuit 300 is simplified, the frame size of the liquid crystal display can be reduced, and the shift register unit 100 belongs to a single-stage architecture, and does not travel continuously with a large current during operation, so power consumption Lower.
  • an embodiment of the third aspect of the present invention provides a liquid crystal display 500.
  • the liquid crystal display 500 includes a pixel set 510 and a gate driving circuit.
  • the gate driving circuit may be the gate driving circuit 300 provided by the second solution. Since the gate drive circuit 300 has The detailed description is made in the above second embodiment, and therefore no further description is made here.
  • the gate drive circuit is coupled to the set of pixels to provide a gate voltage for the set of pixels.
  • the liquid crystal display includes the first and second groups of shift register units 301 and 302.
  • the first and second sets of shift register units 301 and 302 in addition to the first row shift register unit 100, in the first and second sets of shift register units 301 and 302, except for the first line shift Outside of the register unit 100, the gates of the first P-type transistors T1 of each of the other shift register units 100 are connected to the voltage output terminals of the corresponding shift register unit 100 of the corresponding group. Except for the tail row shift register unit 100, the gates of the second P-type transistors T2 of each of the shift register units 100 are connected to the voltage output terminals of the shift register unit 100 of the corresponding group of the next stage.
  • the structure of the gate driving circuit 300 is simplified, the frame size of the liquid crystal display can be reduced, and the shift register unit 100 belongs to a single-stage architecture, and a continuous large current does not travel during operation, so the The power consumption of the liquid crystal display 500 is low.

Abstract

一种移位寄存器单元，用于为液晶显示器的第ｎ级像素提供栅极电压，其包括第一至第三Ｐ型晶体管，第一及第二Ｐ型晶体管的栅极分别接收第ｎ－２及ｎ＋２级像素的栅极电压，第一及第二Ｐ型晶体管第一级分别接收第一及第二输入信号，第一及第二Ｐ型晶体管第二级均连接至第三Ｐ型晶体管的栅极；第ｎ－２及ｎ＋２级像素的栅极电压分别用于控制第一及第二Ｐ型晶体管的通断，以分别使第一或第二输入信号通断第三Ｐ型晶体管；ｎ是大于２的自然数；第三Ｐ型晶体管的第一级连接至第一时钟信号或第二时钟信号，第二级作为电压输出端，用于连接至第ｎ级像素。本发明可以减小液晶显示器的边框尺寸。本发明还提供了一种栅极驱动电路及液晶显示器。

Description

一种移位寄存器单元、栅极驱动电路及显示装置
本发明要求2014年11月20日递交的发明名称为“一种移位寄存器单元、栅极驱动电路及显示装置”的申请号201410669167.7的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示器驱动技术领域，尤其涉及一种移位寄存器单元、栅极驱动电路及显示装置。
背景技术
目前，平板显示器是近年来发展较快的高新技术。由于平板显示器有许多优点，因此应用越来越广泛。其优点主要是：轻便、电压低、无X射线辐射、没有闪烁抖动、不产生静电、功耗低；并且大部分显示器的寿命比阴极射线管的寿命长。平板显示器的正极可做成便携式。以液晶显示器为例，液晶显示器显示图像时通常采用逐行扫面的方式，每一行子像素区域的薄膜液晶体管的导通和截止由一条栅线控制。其中，用于驱动液晶显示器的像素集的栅极驱动电路结构复杂，导致液晶显示器的边框较大，且功耗高。
发明内容
本发明所要解决的技术问题在于提供一种移位寄存器单元、栅极驱动电路及显示装置，以缩小液晶显示器的边框尺寸。
为了实现上述目的，本发明实施方式提供如下技术方案：
本发明供了一种移位寄存器单元，用于为液晶显示器的第n级像素提供栅极电压，其中，所述移位寄存器单元包括第一P型晶体管、第二P型晶体管及第三P型晶体管，其中，
所述第一P型晶体管的栅极接收第n-2级像素的栅极电压，所述第一P型晶体管的第一级接收第一输入信号，所述第一P型晶体管的第二级连接至所述第三P型晶体管的栅极；其中，所述第n-2级像素的栅极电压用于控制所述第 一P型晶体管的通断，从而控制所述第一输入信号对所述第三P型晶体管的通断；其中，n是大于2的自然数；
所述第二P型晶体管的栅极接收第n+2级像素的栅极电压，所述第二P型晶体管的第一级接收所述第二输入信号，所述第二P型晶体管的第二级连接至所述第三P型晶体管的栅极；其中，所述第n+2级像素的栅极电压用于控制所述第二P型晶体管的通断，从而控制所述第二输入信号对所述第三P型晶体管的通断；
所述第三P型晶体管的第一级连接至第一时钟信号或第二时钟信号，所述第二P型晶体管的第二级作为所述移动寄存器单元的电压输出端，用于连接至所述第n级像素，以对所述第n级像素进行充、放电，从而提供栅极电压。
其中，所述移位寄存器单还包括第一电容，所述第一电容连接在所述第三P型晶体管的栅极与所述第三P型晶体管的第二级之间。
其中，所述移位寄存器单元还包括第四P型晶体管，所述第四P型晶体管的栅极接收所述第一时钟信号或第二时钟信号，所述第四P型晶体管的第一级连接至所述第三P型晶体管的栅极，所述第四P型晶体管的第二级连接至所述第三P型晶体管的第二端，其中，所述第四P型晶体管的栅极与所述第三P型晶体管的第一级接收的时钟信号相同。
其中，所述移位寄存器单元还包括第五P型晶体管，所述第五P型晶体管的第一级连接至所述第三P型晶体管的第二级，所述第五P型晶体管的第二级连接至直流高电压源，所述第五P型晶体管的栅极接收上拉控制信号，以在所述第三P型晶体管导通时处于断开状态。
其中，所述移位寄存器单元还包括第六P型晶体管、第七P型晶体管、第八P型晶体管及第二电容，所述第六P型晶体管的栅极连接至所述第六P型晶体管的第一级，所述第六P型晶体管的第一级接收第二时钟信号或第一时钟信号，所述第六P型晶体管的第二级连接至所述第二电容的第一端，并连接至所述第五P型晶体管的栅极，以输出所述上拉控制信号至所述第五P型晶体管的栅极，所述第二电容的第二端连接至所述第五P型晶体管的第二级，所述第七P型晶体管的栅极连接至所述第一及第二P型晶体管的第二级，所述第七P型晶体管的第一级连接至所述第六P型晶体管的栅极或连接所述直流高电压 源，所述第七P型晶体管的第二级连接至所述第六P型晶体管的第二级，所述第八P型晶体管的栅极接收复位信号，所述第八P型晶体管的第一级连接至所述第七P型晶体管的栅极，所述第八P型晶体管的第二级连接至所述第五P型晶体管的第二级，其中，所述第六P型晶体管的第一级与所述第三P型晶体管的第一级接收的时钟信号不同。
本发明还提供一种栅极驱动电路，用于为液晶显示器的像素集提供栅极电压，其中：所述栅极驱动电路包括第一及第二组移位寄存器单元，所述第一组移位寄存器单元设置于所述像素集的一侧，以为所述像素集中的基数行的像素提供栅极电压，所述第二组移位寄存器单元设置于所述像素集的另一侧，以为所述像素集中的偶数行的像素提供栅极电压，其中，所述第一及第二组移位寄存器单元中的每个移位寄存器单元均包括第一P型晶体管、第二P型晶体管及第三P型晶体管，一个移位寄存器单元对应一行像素；
在第一及第二组移位寄存器单元中，除首行移位寄存器单元外，其余每个移位寄存器单元的第一P型晶体管的栅极连接至相应组的上一级移位寄存器单元的电压输出端，第一P型晶体管的第一级接收第一输入信号，第一P型晶体管的第二级连接至相应的第三P型晶体管的栅极；其中，相应组的上一级移位寄存器单元的电压输出端用于控制相应的第一P型晶体管的通断，从而控制所述第一输入信号对相应的第三P型晶体管的通断；
在第一及第二组移位寄存器单元中，除尾行移位寄存器单元外，其余每个移位寄存器单元的第二P型晶体管的栅极连接至相应组的下一级移位寄存器单元的电压输出端，第二P型晶体管的第一级接收所述第二输入信号，第二P型晶体管的第二级连接至相应的第三P型晶体管的栅极；其中，相应组的下一级移位寄存器单元的电压输出端用于控制相应的第二P型晶体管的通断，从而控制所述第二输入信号对相应的第三P型晶体管的通断；
每个移位寄存器单元的第三P型晶体管的第一级连接至第一或第二时钟信号，第三P型晶体管的第二级作为相应的移动寄存器单元的电压输出端，用于连接至相应行的像素，以对所述像素进行充、放电，从而提供栅极电压。
其中，所述第一组及第二组移位寄存器单元均设置于液晶显示器的玻璃基板上。
其中，每一移位寄存器单还包括第一电容，所述第一电容连接在相应的移位寄存器的第三P型晶体管的栅极与第三P型晶体管的第二级之间。
其中，每一移位寄存器单元还包括第四P型晶体管，所述第四P型晶体管的栅极接收所述第一时钟信号或第二时钟信号，所述第四P型晶体管的第一级连接至相应的第三P型晶体管的栅极，所述第四P型晶体管的第二级连接至相应的第三P型晶体管的第二端，其中，所述第四P型晶体管的栅极与相应的第三P型晶体管的第一级接收的时钟信号相同。
本发明还提供一种液晶显示器，包括像素集及栅极驱动电路，其中，所述栅极驱动电路包括第一及第二组移位寄存器单元，所述第一组移位寄存器单元设置于所述像素集的一侧，以为所述像素集中的基数行的像素提供栅极电压，所述第二组移位寄存器单元设置于所述像素集的另一侧，以为所述像素集中的偶数行的像素提供栅极电压，其中，所述第一及第二组移位寄存器单元中的每个移位寄存器单元均包括第一P型晶体管、第二P型晶体管及第三P型晶体管，一个移位寄存器单元对应一行像素，
在第一及第二组移位寄存器单元中，除首行移位寄存器单元外，其余每个移位寄存器单元的第一P型晶体管的栅极连接至相应组的上一级移位寄存器单元的电压输出端，第一P型晶体管的第一级接收第一输入信号，第一P型晶体管的第二级连接至相应的第三P型晶体管的栅极；其中，相应组的上一级移位寄存器单元的电压输出端用于控制相应的第一P型晶体管的通断，从而控制所述第一输入信号对相应的第三P型晶体管的通断；
在第一及第二组移位寄存器单元中，除尾行移位寄存器单元外，其余每个移位寄存器单元的第二P型晶体管的栅极连接至相应组的下一级移位寄存器单元的电压输出端，第二P型晶体管的第一级接收所述第二输入信号，第二P型晶体管的第二级连接至相应的第三P型晶体管的栅极；其中，相应组的下一级移位寄存器单元的电压输出端用于控制相应的第二P型晶体管的通断，从而控制所述第二输入信号对相应的第三P型晶体管的通断；
每个移位寄存器单元的第三P型晶体管的第一级连接至第一或第二时钟信号，第三P型晶体管的第二级作为相应的移动寄存器单元的电压输出端，用于连接至相应行的像素，以对所述像素进行充、放电，从而提供栅极电压。
其中，每个移位寄存器单还包括第一电容，所述第一电容连接在相应的第三P型晶体管的栅极与相应的第三P型晶体管的第二级之间。
其中，每个移位寄存器单元还包括第四P型晶体管，所述第四P型晶体管的栅极接收所述第一时钟信号或第二时钟信号，所述第四P型晶体管的第一级连接至相应的第三P型晶体管的栅极，所述第四P型晶体管的第二级连接至相应的第三P型晶体管的第二端，其中，所述第四P型晶体管的栅极与相应的第三P型晶体管的第一级接收的时钟信号相同。
其中，每个移位寄存器单元还包括第五P型晶体管，所述第五P型晶体管的第一级连接至相应的第三P型晶体管的第二级，所述第五P型晶体管的第二级连接至直流高电压源，所述第五P型晶体管的栅极接收上拉控制信号，以在相应的第三P型晶体管导通时处于断开状态。
其中，每个移位寄存器单元还包括第六P型晶体管、第七P型晶体管、第八P型晶体管及第二电容，所述第六P型晶体管的栅极连接至所述第六P型晶体管的第一级，所述第六P型晶体管的第一级接收第二时钟信号或第一时钟信号，所述第六P型晶体管的第二级连接至相应的第二电容的第一端，并连接至相应的第五P型晶体管的栅极，以输出所述上拉控制信号至相应的第五P型晶体管的栅极，所述第二电容的第二端连接至相应的第五P型晶体管的第二级，所述第七P型晶体管的栅极连接至相应的第一及第二P型晶体管的第二级，所述第七P型晶体管的第一级连接至相应的第六P型晶体管的栅极或连接所述直流高电压源，所述第七P型晶体管的第二级连接至相应的第六P型晶体管的第二级，所述第八P型晶体管的栅极接收复位信号，所述第八P型晶体管的第一级连接至相应的第七P型晶体管的栅极，所述第八P型晶体管的第二级连接至相应的第五P型晶体管的第二级，其中，所述第六P型晶体管的第一级与相应的第三P型晶体管的第一级接收的时钟信号不同。
其中，所述液晶显示器还包括玻璃基板，所述第一组及第二组移位寄存器单元均设置于所述玻璃基板上。
其中，每一移位寄存器单还包括第一电容，所述第一电容连接在相应的移位寄存器的第三P型晶体管的栅极与第三P型晶体管的第二级之间。
其中，每一移位寄存器单元还包括第四P型晶体管，所述第四P型晶体管 的栅极接收所述第一时钟信号或第二时钟信号，所述第四P型晶体管的第一级连接至相应的第三P型晶体管的栅极，所述第四P型晶体管的第二级连接至相应的第三P型晶体管的第二端，其中，所述第四P型晶体管的栅极与相应的第三P型晶体管的第一级接收的时钟信号相同。
本发明所述移位寄存器单元包括第一P型晶体管、第二P型晶体管、第三P型晶体管。所述第一P型晶体管的栅极接收第n-2级像素的栅极电压。所述第一P型晶体管的第一级连接至第一输入信号。所述第一P型晶体管的第二级连接至所述第三P型晶体管的栅极。其中，所述第n-2级像素的栅极电压用于控制所述第一P型晶体管的通断，从而控制所述第一输入信号对所述第三P型晶体管的通断。其中，n是大于2的自然数。所述第二P型晶体管的栅极接收第n+2级像素的栅极电压。所述第二P型晶体管的第一级接收第二输入信号。所述第二P型晶体管的第二级连接至所述第三P型晶体管的栅极。其中，所述第n+2级像素的栅极电压用于控制所述第二P型晶体管的通断，从而控制所述第二输入信号对所述第三P型晶体管的通断。所述第三P型晶体管的第一级接收第一时钟信号或第二时钟信号。所述第二P型晶体管的第二级作为所述移动寄存器单元的电压输出端，用于连接至所述第n级像素，以对所述第n级像素进行充、放电，从而为所述第n级像素提供栅极电压。因此，所述移位寄存器单元可以为液晶显示器的第n级像素提供稳定地栅极电压，且结构精简，可以减小所述液晶显示器的边框尺寸，且所述移位寄存器单元属于单级架构，在运作过程中不会出行持续的大电流，因此功耗较低。
附图说明
为了更清楚地说明本发明的技术方案，下面将对实施方式中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以如这些附图获得其他的附图。
图1是本发明第一方案的第一实施例提供的一种移位寄存器单元的电路图；
图2是本发明第一方案的第二实施例提供的一种移位寄存器单元的电路 图；
图3是本发明第二方案的实施例提供的栅极驱动电路的应用环境示意图；
图4是图3中的栅极驱动电路的移位寄存器单元的扫描时序图；
图5是本发明第三方案的实施例提供的液晶显示器的示意图。
具体实施方式
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述。
请参阅图1，本发明第一方案第一实施例提供一种移位寄存器单元100。所述移位寄存器单元100用于为液晶显示器的第n级像素提供栅极电压。所述移位寄存器单元100包括第一P型晶体管T1、第二P型晶体管T2、第三P型晶体管T3及第一电容C1。其中，所述第一P型晶体管T1的栅极接收第n-2级像素的栅极电压。所述第一P型晶体管T1的第一级连接至第一输入信号D2U。所述第一P型晶体管T1的第二级连接至所述第三P型晶体管T3的栅极。其中，所述第n-2级像素的栅极电压用于控制所述第一P型晶体管T1的通断，从而控制所述第一输入信号D2U对所述第三P型晶体管T3的通断。其中，n是大于2的自然数。
所述第二P型晶体管T2的栅极接收第n+2级像素的栅极电压。所述第二P型晶体管T2的第一级接收第二输入信号U2D。所述第二P型晶体管T2的第二级连接至所述第三P型晶体管T3的栅极。其中，所述第n+2级像素的栅极电压用于控制所述第二P型晶体管T2的通断，从而控制所述第二输入信号对所述第三P型晶体管T3的通断。
需要说明的是，所述移位寄存器单元100为第n级移位寄存器单元。所述第n级移位寄存器单元的第一P型晶体管T1的栅极接收第n-2级像素的栅极电压是通过连接至所述第n-2级移位寄存器单元的电压输出端G(n-2)得到。所述第n级移位寄存器单元的第二P型晶体管T2的栅极接收第n+2级像素的栅极电压是通过连接至所述第n+2级移位寄存器单元的电压输出端G(n-2)得到。
所述第三P型晶体管T3的第一级接收第一时钟信号CK1或第二时钟信号CK2。所述第二P型晶体管T2的第二级作为所述移动寄存器单元100的电压 输出端G(n)，用于连接至所述第n级像素，以对所述第n级像素进行充、放电，从而为所述第n级像素提供栅极电压。
在本实施例中，所述第一输入信号D2U与所述第二输入信号U2D的电位相反，即当所述第一输入信号D2U为高电位信号时，所述第二输入信号U2D为低电位信号。当所述第一输入信号D2U为低电位信号时，所述第二输入信号U2D为高电位信号。所述第一P型晶体管、所述第二P型晶体管及所述第三P型晶体管为NMOS(N-Mental-Oxide-Semiconductor，N型金属-氧化物-半导体)薄膜晶体管。由于这里采用的第一至第三P型晶体管T1-T3的源极与漏极是对称的，所以其源极及栅极是没有区别的。故，所述第一至第三P型晶体管T1-T3的第一级及第二级可以分别为源极及漏极，也可以为漏极及源极。
在其他的实施例中，所述第一至第三P型晶体管T1-T3也可以为场效应管或其他特性相同的器件。
需要说明的是，所述第三P型晶体管T3的栅极与所述第一及第二P型晶体管T1及T2之间的节点定义为Q(n)。
进一步地，所述第一电容C1连接在所述第三P型晶体管T3的栅极与所述第三P型晶体管T3的第二级之间。
当所述液晶显示器的显示屏的栅极扫描方式为由下向上时，且所述第一输入信号D2U为低电位，所述第二输入信号U2D为高电位。当第n-2级像素的栅极电压为低电位时，所述第一P型晶体管T1导通，使得所述第一输入信号D2U传输至所述第三P型晶体管T3的栅极。所述第三P型晶体管T3导通，所述第一时钟信号CK1或第二时钟信号CK2通过所述电压输出端G(n)对所述第n级像素进行充电及放电，以提供栅极电压。其中，由于所述第一电容C1自举效应来调整所述节点Q(n)的电位，以减小所述移位寄存器单元100的电压输出端G(n)输出栅极电压的延时，进而提高了所述移位寄存器单元100输出的稳定性。
当第n+2级像素的栅极电压为低电位时，所述第二P型晶体管T2导通，使得所述第二输入信号U2D传输至所述第三P型晶体管T3的栅极。所述第三P型晶体管T3截止。所述第一时钟信号CK1或第二时钟信号CK2不再影响所述移位寄存器单元100的电压输出端G(n)的电位。
同理，当所述液晶显示器的显示屏的栅极扫描方式为由上向下时，且所述第一输入信号U2D为高电位，所述第二输入信号U2D为低电位。当第n+2级像素的栅极电压为低电位时，所述第二P型晶体管T2导通，使得所述第二输入信号U2D传输至所述第三P型晶体管T3的栅极。所述第三P型晶体管T3导通，所述第一时钟信号CK1或第二时钟信号CK2通过所述电压输出端G(n)对所述第n级像素进行充电及放电，以提供栅极电压。其中，由于所述第一电容C1自举效应来调整所述节点Q(n)的电位，以减小所述移位寄存器单元100的电压输出端G(n)输出栅极电压的延时，进而提高了所述移位寄存器单元100输出的稳定性。
当第n-2级像素的栅极电压为低电位时，所述第一P型晶体管T1导通，使得所述第一输入信号D2U传输至所述第三P型晶体管T3的栅极。所述第三P型晶体管T3截止。所述第一时钟信号CK1或第二时钟信号CK2不再影响所述移位寄存器单元100的电压输出端G(n)的电位。
在本实施例中，所述移位寄存器单元100包括第一P型晶体管T1、第二P型晶体管T2、第三P型晶体管T3。所述第一P型晶体管T1的栅极接收第n-2级像素的栅极电压。所述第一P型晶体管T1的第一级连接至第一输入信号D2U。所述第一P型晶体管T1的第二级连接至所述第三P型晶体管T3的栅极。其中，所述第n-2级像素的栅极电压用于控制所述第一P型晶体管T1的通断，从而控制所述第一输入信号对所述第三P型晶体管T3的通断。其中，n是大于2的自然数。所述第二P型晶体管T2的栅极接收第n+2级像素的栅极电压。所述第二P型晶体管T2的第一级接收第二输入信号U2D。所述第二P型晶体管T2的第二级连接至所述第三P型晶体管T3的栅极。其中，所述第n+2级像素的栅极电压用于控制所述第二P型晶体管T2的通断，从而控制所述第二输入信号U2D对所述第三P型晶体管T3的通断。所述第三P型晶体管T3的第一级接收第一时钟信号CK1或第二时钟信号CK2。所述第二P型晶体管T2的第二级作为所述移动寄存器单元100的电压输出端G(n)，用于连接至所述第n级像素，以对所述第n级像素进行充、放电，从而为所述第n级像素提供栅极电压。因此，所述移位寄存器单元100可以为液晶显示器的第n级像素提供稳定地栅极电压，且结构精简，可以减小所述液晶显示器的边 框尺寸，且所述移位寄存器单元100属于单级架构，在运作过程中不会出行持续的大电流，因此功耗较低。
进一步地，所述移位寄存器单元100还包括第四P型晶体管T4。所述第四P型晶体管T4的栅极接收所述第一时钟信号CK1或第二时钟信号CK2。所述第四P型晶体管T4的第一级连接至所述第三P型晶体管T3的栅极。所述第四P型晶体管T4的第二级连接至所述第三P型晶体管T3的第二端。其中，所述第四P型晶体管T4的栅极与所述第三P型晶体管T3的第一级接收的时钟信号相同。
所述第四P型晶体管T4受到所述第一时钟信号CK1或第二时钟信号CK2的控制在非充电时段对所述节点Q(n)进行上拉，保持Q(n)处于高电位状态，从而维持所述移位寄存器单元100的电压输出端G(n)输出栅极电压的稳定性。
进一步地，所述移位寄存器单元100还包括第六P型晶体管T6、第七P型晶体管T7、第八P型晶体管T8及第二电容C2。所述第六P型晶体管T6的栅极连接至所述第六P型晶体管T6的第一级。所述第六P型晶体管T6的第一级接收第二时钟信号CK2或第一时钟信号CK1。所述第六P型晶体管T6的第二级连接至所述第二电容C2的第一端，并连接至所述第五P型晶体管T5的栅极，以输出所述上拉控制信号至所述第五P型晶体管T5的栅极。所述第二电容C2的第二端连接至所述第五P型晶体管T5的第二级。所述第七P型晶体管T7的栅极连接至所述第一及第二P型晶体管T1及T2的第二级。所述第七P型晶体管T7的第一级连接至所述第六P型晶体管T6的第二级。所述第七P型晶体管T7的第二级连接至所述第六P型晶体管T6的第二级。所述第八P型晶体管T8的栅极接收复位信号RESET。所述第八P型晶体管T8的第一级连接至所述第七P型晶体管T7的栅极。所述第八P型晶体管T8的第二级连接至所述第五P型晶体管T5的第二级。其中，所述第六P型晶体管T6的第一级与所述第三P型晶体管T3的第一级接收的时钟信号不同。
需要说明的是，当所述第三P型晶体管的第一级接收所述第一时钟信号CK1，则所述第六P型晶体管T6的第一级接收所述第二时钟信号CK2，所述第四P型晶体管T4的栅极接收所述第一时钟信号CK1。当所述第三P型晶体管的第一级接收所述第二时钟信号CK2，则所述第六P型晶体管T6的第一级 接收所述第一时钟信号CK1，所述第四P型晶体管T4的栅极接收所述第二时钟信号CK2。所述第六P型晶体管T6、所述第七P型晶体管T8及第二电容C2可以构成上拉控制单元，来输出所述上拉控制信号。所述第六P型晶体管T6的第二级与所述第二电容C2之间的节点P(n)输出所述上拉控制信号至所述第五P型晶体管T5的栅极。所述节点P(n)输出的所述上拉控制信号用于控制所述第五P型晶体管T5在所述第n级像素的电压输入端充电前及充电时截止，并在除此之外的其他时间处于导通状态，以维持所述移位寄存器单元100的电压输出端G(n)处于高电位状态。所述第八P型晶体管T8的栅极接收所述复位信号RESET，当复位信号RESET为低电位时，所述第八P型晶体管T8导通，从而将所述节点Q(n)上拉至高电位，使得第三P型晶体管T3截止，从而使得所述移位寄存器单元100的电压输出端G(n)输出的栅极电压不受所述信号的影响，进而提高了所述移位寄存器单元100输出的稳定性。
请参阅图2，本发明第一方案的第二实施例提供一种移位寄存器200。所述第二实施例提供的移位寄存器200与所述第一实施例提供的移位寄存器100相似，两者的区别在于：在第二实施例中，所述第七P型晶体管T7的第一级连接至所述直流高电压源，以在所述移位寄存器100的电压输出端G(n)对所述第n级像素放电时，保持所述第五P型晶体管处于截止状态，以维持所述移位寄存器单元100的电压输出端G(n)处于低电位状态。
具体地，当所述移位寄存器100的电压输出端G(n)对所述第n级像素放电时，所述节点Q(n)处于低电位，所述第七P型晶体管T7导通，可以在所述第二时钟信号或第一时钟信号变为高电位时上拉所述节点P(n)，使得所述节点P(n)处于高电位，从而使得所述第五P型晶体管T5处于截止状态。
在本实施例中，所述移位寄存器单元200包括第一P型晶体管T1、第二P型晶体管T2及第三P型晶体管T3。所述第一P型晶体管T1的栅极接收第N-2级像素的栅极电压。所述第一P型晶体管T1的第一级连接至第一输入信号D2U。所述第一P型晶体管T1的第二级连接至所述第三P型晶体管T3的栅极。其中，所述第n-2级像素的栅极电压用于控制所述第一P型晶体管T1的通断，从而控制所述第一输入信号D2U对所述第三P型晶体管T3的通断。其中，n是大于2的自然数。所述第二P型晶体管T2的栅极接收第n+2级像 素的栅极电压。所述第二P型晶体管T2的第一级接收第二输入信号U2D。所述第二P型晶体管T2的第二级连接至所述第三P型晶体管T3的栅极。其中，所述第n+2级像素的栅极电压用于控制所述第二P型晶体管T2的通断，从而控制所述第二输入信号U2D对所述第三P型晶体管T3的通断。所述第三P型晶体管T3的第一级接收第一时钟信号CK1或第二时钟信号CK2。所述第二P型晶体管T2的第二级作为所述移动寄存器单元100的电压输出端G(n)，用于连接至所述第n级像素，以对所述第n级像素进行充、放电，从而为所述第n级像素提供栅极电压。因此，所述移位寄存器单元100可以为液晶显示器的第n级像素提供稳定的栅极电压，且结构精简，可以减小所述液晶显示器的边框尺寸，且所述移位寄存器单元100属于单级架构，在运作过程中不会出行持续的大电流，因此功耗较低。
请参阅图3，本发明第二方案提供一种栅极驱动电路300。所述栅极驱动电路300用于为液晶显示器的像素集310提供栅极电压。所述栅极驱动电路300包括第一寄存器单元301及第二组移位寄存器单元302。所述第一组移位寄存器单元301设置于所述像素集310的一侧，以为所述像素集310中的基数行的像素提供栅极电压。所述第二组移位寄存器单元302设置于所述像素集310的另一侧，以为所述像素集310中的偶数行的像素提供栅极电压。其中，所述第一及第二组移位寄存器单元301及302中的移位寄存器单元可以为第一方案第一实施例提供的移位寄存器单元100。当然也可以为第一方案第二实施例提供的移位寄存器单元200。所述移位寄存器单元100的结构及功能已在上述第一方案中进行了详细的描述，在此不再赘述。
在第一及第二组移位寄存器单元301及302中，除首行移位寄存器单元100外，其余每个移位寄存器单元100的第一P型晶体管T1的栅极连接至相应组的上一级移位寄存器单元100的电压输出端。
在第一及第二组移位寄存器单元301及302中，除尾行移位寄存器单元100外，其余每个移位寄存器单元100的第二P型晶体管T2的栅极连接至相应组的下一级移位寄存器单元100的电压输出端。
需要说明的是，所述第一组移位寄存器单元301包括单数级寄存器单元100，如第一级寄存器单元、第三级寄存器单元、第五级寄存器单元等。所述 第一级寄存器单元、所述第三级寄存器单元、所述第五级寄存器单元等分别对应所述第一级像素、所述第三级像素、所述第五级像素等。除了位于首行的第一级移位寄存器单元外，所述第三级移位寄存器单元的第一P型晶体管T1的栅极连接至所述第一级移位寄存器单元100的电压输出端G(1)；所述第三级移位寄存器单元的第二P型晶体管T2的栅极连接至所述第五级移位寄存器单元100的电压输出端G(5)；所述第五级移位寄存器单元的第一P型晶体管T1的栅极连接至所述第三级移位寄存器单元100的电压输出端G(3)；所述第五级移位寄存器单元的第二P型晶体管T2的栅极连接至所述第七级移位寄存器单元100的电压输出端G(7)；以此类推，不再进行赘述。
具体地，所述第一组及第二组移位寄存器单元301及302设置于液晶显示器的玻璃基板上。
请参阅图4，以下以图1所示的结构为例，其中，所述移位寄存器单元100中的第一至第八P型晶体管T1-T8均是以PMOS薄膜晶体管。结合所述移位寄存器单元100的扫描时序图，对所述移位寄存器单元100的工作过程进行详细的描述。
需要说明的是，在所述扫描时序图中，所述第一输入信号D2U为低电位，所述第二输入信号U2D为高电位。CK1_L和CK2_L为驱动第一组移位寄存器单元301的第一及第二时钟信号。CK1_R和CK2_R为驱动所述第二组移位寄存器单元302的第一及第二时钟信号。所述复位信号RESET在特殊时段(如开机时)输出低电位，使得所述节点Q(n)的电位被拉高，此时，时钟信号不再影响所述移位寄存器单元输出的电压输出端G(n)的电位。其中，t1～t3时段为第n-2级移位寄存器单元的电压输出端G(n-2)在给第n-2级像素充电前的准备时间；t3～t4时段为第n-2级移位寄存器单元的电压输出端G(n-2)在给第n-2级像素充电的充电时间。具体为：
在t1时，所述第二时钟信号CK2_L和第n-4级移位寄存器单元的电压输出端G(n-4)的电位开始下降，所述第n-2级移位寄存器单元100的第一P型晶体管T1导通。所述节点Q(n-2)被拉至低电位。所述第三P型晶体管T3导通，所述第一时钟信号CK1_L为高电位。所述第n-2级移位寄存器单元100的电压输出端G(n-2)处于高电位。
在t2时，所述第二时钟信号CK2_L和第n-4级移位寄存器单元的电压输出端G(n-4)的电位上升，所述第n-2级移位寄存器单元100的第一P型晶体管T1断开，所述节点Q(n-2)保持低电位。所述节点P(n-2)的电位被拉低至高电位，使起上拉作用的第五P型晶体管T5导通。所述第n-2级移位寄存器单元100的电压输出端G(n-2)处于高电位。
在t3时，所述第一时钟信号CK1_L电位下降，由于所述节点Q(n-2)处于低电位，因此所述第n-2级移位寄存器单元100的第三P型晶体管T3导通，从而将所述第n-2级移位寄存器单元100的电压输出端G(n-2)拉至低电位。
在t4时，所述第一时钟信号CK1_L电位上升，由于所述节点Q(n-2)仍处于低电位，所述第n-2级移位寄存器单元100的第三P型晶体管T3仍导通，从而将所述第n-2级移位寄存器单元100的电压输出端G(n-2)拉至高电位。
同样道理，t3～t5时段为第n级移位寄存器单元的电压输出端G(n)在给第N级像素充电前的准备时间；t5～t6时段为第n级移位寄存器单元的电压输出端G(n)在给第n-2级像素充电的充电时间。
需要说明的是，各级移位寄存器单元逐级地给相应级像素各级栅极扫描线充电、放电，使得液晶面板可以正常工作。
在本实施例中，所述第一及第二组移位寄存器单元301及302均包括所述移位寄存器单元100。在第一及第二组移位寄存器单元301及302中，除首行移位寄存器单元100外，在所述第一组及第二组移位寄存器单元301及302中，除首行移位寄存器单元100外，其余每个移位寄存器单元100的第一P型晶体管T1的栅极连接至相应组的上一级移位寄存器单元100的电压输出端。，除尾行移位寄存器单元100外，其余每个移位寄存器单元100的第二P型晶体管T2的栅极连接至相应组的下一级移位寄存器单元100的电压输出端。且所述栅极驱动电路300结构精简，可以减小所述液晶显示器的边框尺寸，且所述移位寄存器单元100属于单级架构，在运作过程中不会出行持续的大电流，因此功耗较低。
请继续参阅图5，本发明第三方案的实施例提供一种液晶显示器500。所述液晶显示器500包括像素集510及栅极驱动电路。其中，所述栅极驱动电路可以为上述第二方案提供的栅极驱动电路300。由于所述栅极驱动电路300已 在上述第二方案中进行了详细的描述，故在此不再进行赘述。所述栅极驱动电路连接至所述像素集，以为所述像素集提供栅极电压。
在本实施例中，所述液晶显示器包括所述第一及第二组移位寄存器单元301及302。在第一及第二组移位寄存器单元301及302中，除首行移位寄存器单元100外，在所述第一组及第二组移位寄存器单元301及302中，除首行移位寄存器单元100外，其余每个移位寄存器单元100的第一P型晶体管T1的栅极连接至相应组的上一级移位寄存器单元100的电压输出端。，除尾行移位寄存器单元100外，其余每个移位寄存器单元100的第二P型晶体管T2的栅极连接至相应组的下一级移位寄存器单元100的电压输出端。且所述栅极驱动电路300结构精简，可以减小所述液晶显示器的边框尺寸，且所述移位寄存器单元100属于单级架构，在运作过程中不会出行持续的大电流，因此所述液晶显示器500的功耗较低。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (17)

  1. 一种移位寄存器单元，用于为液晶显示器的第n级像素提供栅极电压，其中，所述移位寄存器单元包括第一P型晶体管、第二P型晶体管及第三P型晶体管，其中，
    所述第一P型晶体管的栅极接收第n-2级像素的栅极电压，所述第一P型晶体管的第一级接收第一输入信号，所述第一P型晶体管的第二级连接至所述第三P型晶体管的栅极；其中，所述第n-2级像素的栅极电压用于控制所述第一P型晶体管的通断，从而控制所述第一输入信号对所述第三P型晶体管的通断；其中，n是大于2的自然数；
    所述第二P型晶体管的栅极接收第n+2级像素的栅极电压，所述第二P型晶体管的第一级接收所述第二输入信号，所述第二P型晶体管的第二级连接至所述第三P型晶体管的栅极；其中，所述第n+2级像素的栅极电压用于控制所述第二P型晶体管的通断，从而控制所述第二输入信号对所述第三P型晶体管的通断；
    所述第三P型晶体管的第一级连接至第一时钟信号或第二时钟信号，所述第二P型晶体管的第二级作为所述移动寄存器单元的电压输出端，用于连接至所述第n级像素，以对所述第n级像素进行充、放电，从而提供栅极电压。
  2. 如权利要求1所述的移位寄存器单元，其中，所述移位寄存器单还包括第一电容，所述第一电容连接在所述第三P型晶体管的栅极与所述第三P型晶体管的第二级之间。
  3. 如权利要求1所述的移位寄存器单元，其中，所述移位寄存器单元还包括第四P型晶体管，所述第四P型晶体管的栅极接收所述第一时钟信号或第二时钟信号，所述第四P型晶体管的第一级连接至所述第三P型晶体管的栅极，所述第四P型晶体管的第二级连接至所述第三P型晶体管的第二端，其中，所述第四P型晶体管的栅极与所述第三P型晶体管的第一级接收的时钟信号相同。
  4. 如权利要求3所述的移位寄存器单元，其中，所述移位寄存器单元还包括第五P型晶体管，所述第五P型晶体管的第一级连接至所述第三P型晶 体管的第二级，所述第五P型晶体管的第二级连接至直流高电压源，所述第五P型晶体管的栅极接收上拉控制信号，以在所述第三P型晶体管导通时处于断开状态。
  5. 如权利要求4所述的移位寄存器单元，其中，所述移位寄存器单元还包括第六P型晶体管、第七P型晶体管、第八P型晶体管及第二电容，所述第六P型晶体管的栅极连接至所述第六P型晶体管的第一级，所述第六P型晶体管的第一级接收第二时钟信号或第一时钟信号，所述第六P型晶体管的第二级连接至所述第二电容的第一端，并连接至所述第五P型晶体管的栅极，以输出所述上拉控制信号至所述第五P型晶体管的栅极，所述第二电容的第二端连接至所述第五P型晶体管的第二级，所述第七P型晶体管的栅极连接至所述第一及第二P型晶体管的第二级，所述第七P型晶体管的第一级连接至所述第六P型晶体管的栅极或连接所述直流高电压源，所述第七P型晶体管的第二级连接至所述第六P型晶体管的第二级，所述第八P型晶体管的栅极接收复位信号，所述第八P型晶体管的第一级连接至所述第七P型晶体管的栅极，所述第八P型晶体管的第二级连接至所述第五P型晶体管的第二级，其中，所述第六P型晶体管的第一级与所述第三P型晶体管的第一级接收的时钟信号不同。
  6. 一种栅极驱动电路，用于为液晶显示器的像素集提供栅极电压，其中：所述栅极驱动电路包括第一及第二组移位寄存器单元，所述第一组移位寄存器单元设置于所述像素集的一侧，以为所述像素集中的基数行的像素提供栅极电压，所述第二组移位寄存器单元设置于所述像素集的另一侧，以为所述像素集中的偶数行的像素提供栅极电压，其中，所述第一及第二组移位寄存器单元中的每个移位寄存器单元均包括第一P型晶体管、第二P型晶体管及第三P型晶体管，一个移位寄存器单元对应一行像素；
    在第一及第二组移位寄存器单元中，除首行移位寄存器单元外，其余每个移位寄存器单元的第一P型晶体管的栅极连接至相应组的上一级移位寄存器单元的电压输出端，第一P型晶体管的第一级接收第一输入信号，第一P型晶体管的第二级连接至相应的第三P型晶体管的栅极；其中，相应组的上一级移位寄存器单元的电压输出端用于控制相应的第一P型晶体管的通断，从而控制所述第一输入信号对相应的第三P型晶体管的通断；
    在第一及第二组移位寄存器单元中，除尾行移位寄存器单元外，其余每个移位寄存器单元的第二P型晶体管的栅极连接至相应组的下一级移位寄存器单元的电压输出端，第二P型晶体管的第一级接收所述第二输入信号，第二P型晶体管的第二级连接至相应的第三P型晶体管的栅极；其中，相应组的下一级移位寄存器单元的电压输出端用于控制相应的第二P型晶体管的通断，从而控制所述第二输入信号对相应的第三P型晶体管的通断；
    每个移位寄存器单元的第三P型晶体管的第一级连接至第一或第二时钟信号，第三P型晶体管的第二级作为相应的移动寄存器单元的电压输出端，用于连接至相应行的像素，以对所述像素进行充、放电，从而提供栅极电压。
  7. 如权利要求6所述的移位寄存器单元，其中，所述第一组及第二组移位寄存器单元均设置于液晶显示器的玻璃基板上。
  8. 如权利要求6所述的移位寄存器单元，其中，每一移位寄存器单还包括第一电容，所述第一电容连接在相应的移位寄存器的第三P型晶体管的栅极与第三P型晶体管的第二级之间。
  9. 如权利要求6所述的移位寄存器单元，其中，每一移位寄存器单元还包括第四P型晶体管，所述第四P型晶体管的栅极接收所述第一时钟信号或第二时钟信号，所述第四P型晶体管的第一级连接至相应的第三P型晶体管的栅极，所述第四P型晶体管的第二级连接至相应的第三P型晶体管的第二端，其中，所述第四P型晶体管的栅极与相应的第三P型晶体管的第一级接收的时钟信号相同。
  10. 一种液晶显示器，包括像素集及栅极驱动电路，其中，所述栅极驱动电路包括第一及第二组移位寄存器单元，所述第一组移位寄存器单元设置于所述像素集的一侧，以为所述像素集中的基数行的像素提供栅极电压，所述第二组移位寄存器单元设置于所述像素集的另一侧，以为所述像素集中的偶数行的像素提供栅极电压，其中，所述第一及第二组移位寄存器单元中的每个移位寄存器单元均包括第一P型晶体管、第二P型晶体管及第三P型晶体管，一个移位寄存器单元对应一行像素，
    在第一及第二组移位寄存器单元中，除首行移位寄存器单元外，其余每个移位寄存器单元的第一P型晶体管的栅极连接至相应组的上一级移位寄存器 单元的电压输出端，第一P型晶体管的第一级接收第一输入信号，第一P型晶体管的第二级连接至相应的第三P型晶体管的栅极；其中，相应组的上一级移位寄存器单元的电压输出端用于控制相应的第一P型晶体管的通断，从而控制所述第一输入信号对相应的第三P型晶体管的通断；
    在第一及第二组移位寄存器单元中，除尾行移位寄存器单元外，其余每个移位寄存器单元的第二P型晶体管的栅极连接至相应组的下一级移位寄存器单元的电压输出端，第二P型晶体管的第一级接收所述第二输入信号，第二P型晶体管的第二级连接至相应的第三P型晶体管的栅极；其中，相应组的下一级移位寄存器单元的电压输出端用于控制相应的第二P型晶体管的通断，从而控制所述第二输入信号对相应的第三P型晶体管的通断；
    每个移位寄存器单元的第三P型晶体管的第一级连接至第一或第二时钟信号，第三P型晶体管的第二级作为相应的移动寄存器单元的电压输出端，用于连接至相应行的像素，以对所述像素进行充、放电，从而提供栅极电压。
  11. 如权利要求10所述的液晶显示器，其中，每个移位寄存器单还包括第一电容，所述第一电容连接在相应的第三P型晶体管的栅极与相应的第三P型晶体管的第二级之间。
  12. 如权利要求10所述的液晶显示器，其中，每个移位寄存器单元还包括第四P型晶体管，所述第四P型晶体管的栅极接收所述第一时钟信号或第二时钟信号，所述第四P型晶体管的第一级连接至相应的第三P型晶体管的栅极，所述第四P型晶体管的第二级连接至相应的第三P型晶体管的第二端，其中，所述第四P型晶体管的栅极与相应的第三P型晶体管的第一级接收的时钟信号相同。
  13. 如权利要求12所述的液晶显示器，其中，每个移位寄存器单元还包括第五P型晶体管，所述第五P型晶体管的第一级连接至相应的第三P型晶体管的第二级，所述第五P型晶体管的第二级连接至直流高电压源，所述第五P型晶体管的栅极接收上拉控制信号，以在相应的第三P型晶体管导通时处于断开状态。
  14. 如权利要求13所述的液晶显示器，其中，每个移位寄存器单元还包括第六P型晶体管、第七P型晶体管、第八P型晶体管及第二电容，所述第 六P型晶体管的栅极连接至所述第六P型晶体管的第一级，所述第六P型晶体管的第一级接收第二时钟信号或第一时钟信号，所述第六P型晶体管的第二级连接至相应的第二电容的第一端，并连接至相应的第五P型晶体管的栅极，以输出所述上拉控制信号至相应的第五P型晶体管的栅极，所述第二电容的第二端连接至相应的第五P型晶体管的第二级，所述第七P型晶体管的栅极连接至相应的第一及第二P型晶体管的第二级，所述第七P型晶体管的第一级连接至相应的第六P型晶体管的栅极或连接所述直流高电压源，所述第七P型晶体管的第二级连接至相应的第六P型晶体管的第二级，所述第八P型晶体管的栅极接收复位信号，所述第八P型晶体管的第一级连接至相应的第七P型晶体管的栅极，所述第八P型晶体管的第二级连接至相应的第五P型晶体管的第二级，其中，所述第六P型晶体管的第一级与相应的第三P型晶体管的第一级接收的时钟信号不同。
  15. 如权利要求14所述的液晶显示器，其中，所述液晶显示器还包括玻璃基板，所述第一组及第二组移位寄存器单元均设置于所述玻璃基板上。
  16. 如权利要求14所述的液晶显示器，其中，每一移位寄存器单还包括第一电容，所述第一电容连接在相应的移位寄存器的第三P型晶体管的栅极与第三P型晶体管的第二级之间。
  17. 如权利要求14所述的液晶显示器，其中，每一移位寄存器单元还包括第四P型晶体管，所述第四P型晶体管的栅极接收所述第一时钟信号或第二时钟信号，所述第四P型晶体管的第一级连接至相应的第三P型晶体管的栅极，所述第四P型晶体管的第二级连接至相应的第三P型晶体管的第二端，其中，所述第四P型晶体管的栅极与相应的第三P型晶体管的第一级接收的时钟信号相同。
PCT/CN2014/092899 2014-11-20 2014-12-03 一种移位寄存器单元、栅极驱动电路及显示装置 WO2016078143A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/426,446 US9779681B2 (en) 2014-11-20 2014-12-03 Shift register unit, gate driving circuit and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410669167.7 2014-11-20
CN201410669167.7A CN104376825B (zh) 2014-11-20 2014-11-20 一种移位寄存器单元、栅极驱动电路及显示装置

Publications (1)

Publication Number Publication Date
WO2016078143A1 true WO2016078143A1 (zh) 2016-05-26

Family

ID=52555702

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/092899 WO2016078143A1 (zh) 2014-11-20 2014-12-03 一种移位寄存器单元、栅极驱动电路及显示装置

Country Status (3)

Country Link
US (1) US9779681B2 (zh)
CN (1) CN104376825B (zh)
WO (1) WO2016078143A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104851384B (zh) * 2015-05-29 2018-04-20 合肥京东方光电科技有限公司 显示面板的驱动方法及驱动模块、显示面板及显示装置
CN105118465B (zh) * 2015-09-23 2018-01-30 深圳市华星光电技术有限公司 一种goa电路及其驱动方法、液晶显示器
CN105469756B (zh) * 2015-12-07 2018-01-30 武汉华星光电技术有限公司 基于ltps半导体薄膜晶体管的goa电路
CN105405406B (zh) * 2015-12-29 2017-12-22 武汉华星光电技术有限公司 栅极驱动电路和使用栅极驱动电路的显示器
CN106875890B (zh) * 2017-04-27 2021-01-12 京东方科技集团股份有限公司 阵列基板、显示面板、显示设备及驱动方法
CN108932933B (zh) * 2017-05-27 2020-01-21 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示装置
CN112382239B (zh) * 2020-11-05 2022-07-29 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN112331142B (zh) * 2020-11-25 2022-06-17 厦门天马微电子有限公司 扫描驱动电路、显示面板和显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100007598A1 (en) * 2008-07-11 2010-01-14 Wintek Corporation Shift register
CN101894588A (zh) * 2010-01-11 2010-11-24 友达光电股份有限公司 双向移位寄存器及其驱动方法
CN103187040A (zh) * 2011-12-30 2013-07-03 海蒂斯技术有限公司 移位寄存器及利用它的栅极驱动电路
CN103236273A (zh) * 2013-04-16 2013-08-07 北京京东方光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN103426414A (zh) * 2013-07-16 2013-12-04 北京京东方光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI349906B (en) * 2006-09-01 2011-10-01 Au Optronics Corp Shift register, shift register array circuit, and display apparatus
JP5484109B2 (ja) * 2009-02-09 2014-05-07 三菱電機株式会社 電気光学装置
TWI413050B (zh) * 2009-03-17 2013-10-21 Au Optronics Corp 高可靠度閘極驅動電路
CN101847445B (zh) * 2009-03-27 2012-11-21 北京京东方光电科技有限公司 移位寄存器及其栅线驱动装置
CN102097132B (zh) * 2009-12-14 2013-11-20 群康科技(深圳)有限公司 移位寄存器及液晶面板驱动电路
US8537094B2 (en) * 2010-03-24 2013-09-17 Au Optronics Corporation Shift register with low power consumption and liquid crystal display having the same
TWI433459B (zh) * 2010-07-08 2014-04-01 Au Optronics Corp 雙向移位暫存器
KR101340197B1 (ko) * 2011-09-23 2013-12-10 하이디스 테크놀로지 주식회사 쉬프트 레지스터 및 이를 이용한 게이트 구동회로
JP2014153532A (ja) * 2013-02-08 2014-08-25 Japan Display Inc 表示装置及び駆動回路
CN104103244B (zh) * 2013-04-03 2016-06-01 瀚宇彩晶股份有限公司 液晶显示器及其双向移位暂存装置
CN103413514A (zh) * 2013-07-27 2013-11-27 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器和显示装置
TWI537912B (zh) * 2014-07-21 2016-06-11 友達光電股份有限公司 移位暫存器及使用其之平面顯示器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100007598A1 (en) * 2008-07-11 2010-01-14 Wintek Corporation Shift register
CN101894588A (zh) * 2010-01-11 2010-11-24 友达光电股份有限公司 双向移位寄存器及其驱动方法
CN103187040A (zh) * 2011-12-30 2013-07-03 海蒂斯技术有限公司 移位寄存器及利用它的栅极驱动电路
CN103236273A (zh) * 2013-04-16 2013-08-07 北京京东方光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN103426414A (zh) * 2013-07-16 2013-12-04 北京京东方光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置

Also Published As

Publication number Publication date
CN104376825B (zh) 2017-02-22
CN104376825A (zh) 2015-02-25
US20160343333A1 (en) 2016-11-24
US9779681B2 (en) 2017-10-03

Similar Documents

Publication Publication Date Title
WO2016078141A1 (zh) 一种移位寄存器单元、栅极驱动电路及显示装置
WO2016078143A1 (zh) 一种移位寄存器单元、栅极驱动电路及显示装置
CN105405406B (zh) 栅极驱动电路和使用栅极驱动电路的显示器
CN109285505B (zh) 一种移位寄存器单元、栅极驱动电路和显示装置
US9396813B2 (en) Shift register cell, shift register, gate driver and display panel
WO2017067432A1 (zh) 移位寄存器单元及其驱动方法、移位寄存器和显示装置
WO2019085578A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2018059075A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN104091572B (zh) 双下拉控制模块、移位寄存单元、栅极驱动器和显示面板
CN105390086B (zh) 栅极驱动电路和使用栅极驱动电路的显示器
WO2017113447A1 (zh) 栅极驱动电路及显示装置
US11749154B2 (en) Gate driver on array circuit and display panel
US11263940B2 (en) Shift register unit, driving method thereof, gate drive circuit and display device
WO2020147689A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN112397008B (zh) Goa电路及显示面板
US9799294B2 (en) Liquid crystal display device and GOA scanning circuit of the same
CN106920526B (zh) 移位寄存器及其驱动方法和栅极驱动电路
WO2016169389A1 (zh) 栅极驱动电路及其单元和一种显示装置
CN111199703A (zh) Goa电路及显示面板
WO2020077897A1 (zh) Goa 驱动电路及显示面板
US10255983B2 (en) Shift register, unit thereof, and display device
KR102015848B1 (ko) 액정표시장치
CN110890077A (zh) 一种goa电路及液晶显示面板
US11355044B2 (en) GOA circuit and display panel
CN211181598U (zh) 栅极驱动电路及显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14426446

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14906353

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14906353

Country of ref document: EP

Kind code of ref document: A1