WO2016169389A1 - 栅极驱动电路及其单元和一种显示装置 - Google Patents

栅极驱动电路及其单元和一种显示装置 Download PDF

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Publication number
WO2016169389A1
WO2016169389A1 PCT/CN2016/077394 CN2016077394W WO2016169389A1 WO 2016169389 A1 WO2016169389 A1 WO 2016169389A1 CN 2016077394 W CN2016077394 W CN 2016077394W WO 2016169389 A1 WO2016169389 A1 WO 2016169389A1
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Prior art keywords
transistor
pole
module
driving circuit
gate
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PCT/CN2016/077394
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English (en)
French (fr)
Inventor
张盛东
冷传利
胡治晋
廖聪维
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北京大学深圳研究生院
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Priority to US15/568,992 priority Critical patent/US10373562B2/en
Publication of WO2016169389A1 publication Critical patent/WO2016169389A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of electronic circuits, and in particular to a gate driving circuit and a unit thereof and a display device.
  • TFT Thin film transistor
  • FPD flat panel display
  • GOA Gate Driver On Array
  • the output gate scan signal is at a low level for most of the working time, a low-level-holding circuit is generally required to maintain the intermediate node and the signal output node.
  • the low level avoids the influence of the clock feedthrough effect or leakage current on the potential of the GOA intermediate node or the output node, preventing the GOA output logic from being disordered.
  • the low level sustain circuit of the GOA is prone to performance degradation due to the drift of the pull-down transistor threshold voltage.
  • the traditional design idea is to reduce the characteristic drift of the pull-down tube.
  • the main implementation methods are as follows: 1. The pull-down transistor is biased in the high-frequency pulse stress mode; 2.
  • the pull-down transistor is biased in the low-frequency pulse stress mode;
  • the pull-down transistor is biased in a low voltage DC mode.
  • Test results show that these methods can reduce the threshold voltage drift of the pull-down transistor to some extent compared to the high-voltage DC bias mode.
  • the threshold voltage drift of the pull-down transistor is still unavoidable, so the lifetime of the GOA is still short. It is urgent to study the new GOA circuit structure to further extend the life of the GOA to meet the requirements of high-performance TV panels.
  • the present application provides a gate driving circuit and a unit thereof and a display device to compensate for low The level maintains the threshold voltage of the module, extending the operating life of the circuit.
  • an embodiment provides a gate driving circuit including a cascade of at least one gate driving circuit unit, the gate driving circuit unit including:
  • a driving module configured to transmit a first clock signal to a signal output end of the gate driving circuit unit through a switching state of the control end thereof, thereby outputting a scan signal; and an input module configured to control a control end switching state of the driving module; a low level maintaining module for maintaining a signal output end of the gate driving circuit and/or a control end of the driving module at a low level when the sustaining end thereof obtains an active level; the gate driving circuit further includes at least one self The appropriate voltage generating module, the signal output end of the adaptive voltage generating module is used for connecting to the sustaining end, and the adaptive voltage generating module is configured to generate a self-compensating voltage according to the constant current source, and transmit the signal to the sustaining source through the signal output end thereof.
  • the energy terminal provides an effective level to the sustain enable terminal.
  • an embodiment provides a display device, including:
  • a two-dimensional pixel array composed of a plurality of pixels, and a plurality of data lines in a first direction connected to each pixel in the array and a plurality of gate scan lines in a second direction; a data driving circuit for providing data signals for the data lines And the gate driving circuit described above, providing a gate driving signal for the gate scan line.
  • the gate driving circuit when the threshold voltage drift occurs in the pull-down transistor in the low-level sustaining module, the sustaining end is maintained, and the signal output terminal of the adaptive voltage generating module is connected at a low level.
  • the sustaining end of the module therefore, when the threshold voltage drift occurs in the pull-down transistor, the adaptive voltage generating module generates a self-compensating voltage under the action of its constant current source, thereby making up for the increase of the threshold voltage and making the pull-down transistor overdriven.
  • the voltage is constant, maintaining good pull-down capability, which in turn extends the operating life of the gate drive circuit.
  • Embodiment 1 is a circuit structural diagram of a gate driving circuit unit disclosed in Embodiment 1;
  • FIG. 2 is a timing chart showing an operation of a gate driving circuit unit of an embodiment
  • FIG. 3 is a circuit structural diagram of a gate driving circuit unit disclosed in Embodiment 2;
  • FIG. 4a is a schematic structural diagram of a circuit of an adaptive voltage generating module disclosed in Embodiment 3;
  • FIG. 4b is a schematic structural diagram of another adaptive voltage generating module disclosed in Embodiment 3.
  • FIG. 4c is a schematic structural diagram of a third adaptive voltage generating module disclosed in Embodiment 3.
  • FIG. 5 is a circuit structural diagram of a gate driving circuit unit disclosed in Embodiment 3.
  • FIG. 6 is a schematic structural diagram of a display device disclosed in Embodiment 4.
  • the switch tube in this application is a transistor.
  • the transistor in the present application may be a bipolar transistor or a field effect transistor.
  • the gate of the transistor is the base of the bipolar transistor
  • the first pole can be the collector or emitter of the bipolar transistor
  • the corresponding second pole can be a bipolar transistor.
  • Emitter or collector when the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor
  • the first pole can be the drain or source of the field effect transistor
  • the corresponding second pole can be the field effect The source or drain of the transistor.
  • the transistor in the display is typically a field effect transistor: a thin film transistor (TFT).
  • TFT thin film transistor
  • the present application will be described in detail by taking a transistor as a field effect transistor.
  • the transistor may also be a bipolar transistor.
  • the effective level refers to the level at which the transistor can be turned on.
  • the transistor is an N-type transistor
  • the corresponding active level is a high level.
  • the high level is taken as an example, unless otherwise specified.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • FIG. 1 is a circuit structural diagram of a gate driving circuit unit disclosed in this embodiment.
  • the gate driving circuit unit includes a driving module 20, an input module 10, a low level maintaining module 30, and an adaptive voltage generating module 40. among them,
  • the driving module 20 is configured to transmit the first clock signal V A to the signal output end of the gate driving circuit unit through the switching state switching of the control terminal Q thereof, thereby outputting the scanning signal V OUT .
  • the switching state of the control terminal Q can be characterized by a high level and a low level. For example, when the high level is, the control terminal Q is in an on state, and when the level is low, the control terminal Q is in an off state; in another embodiment. In the middle, it is also possible to replace the switch state depending on the type of transistor.
  • the driving module 20 may include: a second transistor T2, a first pole of the second transistor T2 is used to input the first clock signal V A , and a control of the second transistor T2 is used to drive the control terminal Q of the module 20,
  • the second extreme gate of the second transistor T2 is a signal output terminal of the gate drive circuit unit.
  • other existing or future driving methods may also be used.
  • the input module 10 is configured to control the control terminal Q of the driving module 20 to switch the switch state.
  • the input module 10 includes: a first transistor T1, a control electrode of the first transistor T1 is coupled to the first electrode for inputting the first input signal V I1 ; and a second electrode of the first transistor T1 is coupled to the driving Control terminal Q of module 20.
  • other existing or future input methods may also be used.
  • the first input signal V I1 active level ahead of the arrival time the arrival time of the first active level of the clock signal V A for example, a first clock cycle of the clock signal V A is T, the duty ratio is 50%, the pulse width of the first input signal V I1 is T/2, and the effective level arrival time of the first input signal V I1 may be ahead of the effective level of the first clock signal V A by the time T/2.
  • the transistor is an N-type transistor, the effective level of the gate corresponding to the control electrode is a high level, and when the transistor is a P-type transistor, the effective level of the gate corresponding to the transistor is turned on. Is low.
  • an N-type transistor is taken as an example for description. Accordingly, the effective level at which the transistor is turned on is a high level.
  • the low level sustaining module 30 is configured to maintain the signal output terminal of the gate driving circuit and/or the control terminal Q of the driving module 20 at a low level when the sustaining terminal P thereof obtains an active level.
  • the low level maintenance module 30 includes: a fifth transistor T5 and a sixth transistor T6, wherein the control electrode of the fifth transistor T5 is connected to the control electrode of the sixth transistor T6, and the connection node is maintained at a low level.
  • the sustaining terminal P of the module 30; the first pole of the fifth transistor T5 is connected to the control terminal Q of the driving module 20; the second pole of the fifth transistor T5 is used to be connected to the low-level terminal V SS .
  • the first electrode of the sixth transistor T6 is connected to the signal output terminal of the gate driving circuit unit, and the second electrode of the sixth transistor T6 is used to be connected to the low level terminal V SS .
  • the low level maintenance module 30 may further include a first capacitor C1 connected between the sustain enable terminal P and the low level terminal V SS .
  • the main function of the first capacitor C1 is to The potential of the enable terminal P is maintained during the low level sustain period. In other embodiments, other existing or future maintenance modes may also be used.
  • each of the above modules only schematically illustrates the gate driving circuit unit by way of example, and each module can adopt the existing technical solutions. Therefore, some details are not described in detail in the above modules.
  • the technician can realize the connection between the modules of the gate driving circuit unit according to the existing technical solutions.
  • those skilled in the art can also appropriately add components or modules according to actual needs, in order to improve the functions of each module:
  • the gate driving circuit unit may further include a third transistor T3, and the control electrode of the third transistor T3 is used to input an initialization signal V STV ,
  • the first pole of the three transistor T3 is connected to the control terminal Q of the driving module 20, and the second pole of the third transistor T3 is used to be connected to the low level terminal Vss .
  • the third transistor T3 is turned on in response to the active level of the initialization signal V STV , thereby initializing the potential of the control terminal Q.
  • the active level of the initialization signal V STV may be a high pulse signal of, for example, T/2 pulse width, and the active level of the first input signal V I1 may be T/4 after the initialization signal V STV is active. (Of course, you can also set it according to actual needs).
  • the gate driving circuit unit may further include a fourth transistor T4 and a control of the fourth transistor T4.
  • the pole is used to input the second input signal V I2
  • the first pole of the fourth transistor T4 is connected to the control terminal Q of the driving module 20
  • the second pole of the fourth transistor T4 is used to be connected to the low-level terminal V SS .
  • the fourth transistor T4 is turned on in response to the active level of the second input signal V I2 , thereby achieving discharge of the control terminal Q.
  • the low-level maintenance module 30 may further include a seventh transistor T7, the control electrode of the seventh transistor T7 is for inputting the first input signal V I1 , the first electrode of the seventh transistor T7 is connected to the sustain enable terminal P, and the second transistor is the second transistor T7 The pole is used to connect to the low level terminal V SS .
  • a seventh transistor T7 is also turned on in response to the active level of the first input signal V I1 active level in response to the input module 10 of the first input signal V I1 will be able to maintain the potential of the terminal P Coupled to low level.
  • the effective level arrival time of the second input signal V I2 lags behind the effective level end time of the first clock signal V A .
  • the pulse width of the second input signal V I2 is T/2, and the effective level arrival time of the second input signal V I2 may lag behind the first clock signal V A active level end time T/2.
  • the gate driving circuit unit disclosed in this embodiment further includes: an adaptive voltage generating module 40, the signal output end of the adaptive voltage generating module 40 is connected to the sustaining enable terminal P, and the adaptive voltage generating module 40 is used according to the
  • the constant current source generates a self-compensation voltage V R and is transmitted through its signal output terminal to the sustain enable terminal P to provide an active level to the sustain enable terminal P.
  • an eighth transistor T8 is connected between the adaptive voltage generating module 40 and the low level maintaining module 30, and the first pole of the eighth transistor T8 is connected to the adaptive voltage generating module 40.
  • the second electrode of the eighth transistor T8 is connected to the sustain enable terminal P of the low level sustaining module 30, the control electrode of the eighth transistor T8 is used for inputting the second input signal V I2 , and the eighth transistor T8 is responsive to the first
  • the active level of the two input signals V I2 turns on the first and second poles of the eighth transistor T8, so that the self-compensating voltage V R generated by the adaptive voltage generating module 40 is transmitted through its signal output terminal to the sustain enable terminal. P.
  • the adaptive voltage generating module 40 includes: a constant current source and a ninth transistor T9, wherein the first pole of the ninth transistor T9 is connected to the gate of the ninth transistor T9; and the control of the ninth transistor T9 is extremely
  • the signal output terminal of the adaptive voltage generating module 40; the second pole of the ninth transistor T9 is used to connect to the low-level terminal V SS .
  • the constant current source is used to generate a constant current I REF , the first end of the constant current source is used to input a preset potential, and the second end of the constant current source is connected to the first pole of the ninth transistor T9 .
  • the constant current source may be a current source, preferably a current source with a controllable current magnitude.
  • the preset potential can be provided by the high level terminal.
  • the adaptive voltage generating module 40 may be shared by the plurality of gate driving circuit units; or each gate driving circuit unit may be separately An adaptive voltage generating module 40 is configured.
  • FIG. 2 is a timing diagram of the operation of the gate driving circuit unit in the embodiment.
  • the high level (high potential) of each clock signal or pulse signal is represented by V H
  • the low level (low potential) of each clock signal or pulse signal is represented by V L .
  • the working process of the gate driving circuit unit in this embodiment is divided into five stages of initialization, pre-charging, pull-up, pull-down, and low-level maintenance.
  • the gate driving circuit in this embodiment is described in detail below with reference to FIG. 1 and FIG. The working process of the unit.
  • the initialization signal V STV is at a high level, so that the third transistor T3 is turned on, and the third transistor T3 of the control terminal Q of the driving module 20 is turned on to the low level V L , thereby The initialization operation of the control terminal Q is completed.
  • the first input signal V I1 is at a high level, and the first clock signal V A is at a low level.
  • the first response to the first input transistor T1 of the high level signal V I1 is turned on, a first input signal V I1 charges the control terminal Q of the drive module 20 through the first transistor T1 is turned on, then, the control terminal of the voltage rise Q
  • the second transistor T2 is turned on.
  • the scan signal V OUT outputted from the signal output terminal of the gate driving circuit unit is at a low level.
  • the seventh transistor T7 is turned on in response to the high level of the first input signal V I1 , and the seventh transistor T7 that keeps the enable terminal P turned on is pulled down to the low level, so that the fifth transistor T5 and the sixth transistor T6 are disconnected. .
  • the voltage of the control terminal Q reaches V H - V T , where V T is the threshold voltage of the second transistor T2, and the precharge operation is completed.
  • the first clock signal V A becomes a high level, and the initialization signal V STV and the second input signal V I2 are at a low level. Since the voltage of the control terminal Q is V H -V T , the second transistor T2 is turned on, and the first clock signal V A supplies a charging current to the load through the turned-on second transistor T2, and the signal output terminal of the gate driving circuit unit outputs The scan signal V OUT gradually rises to V H .
  • the first transistor T1 is in a diode-connected state; since the initialization signal V STV and the second input signal V I2 are at a low level, then the third transistor T3 and the fourth transistor T4 remain in an off state; maintaining the enable terminal P Low level, then the fifth transistor T5 and the sixth transistor T6 are also kept off, so the control terminal Q will be in a floating state, and the control terminal Q is coupled to the high level 2V by the first clock signal V A due to the bootstrap effect. H -V T .
  • the first clock signal V A becomes a low level, and the second transistor T2 remains open, so that the scan signal V OUT outputted by the gate driving circuit unit falls to a low level due to the first clock signal With the coupling of V A , the control terminal Q drops to V H -V T .
  • the second input signal V I2 is at a high level, and the fourth transistor T4 and the eighth transistor T8 are turned on in response to the high level of the second input signal V I2 . Then, the fourth transistor T4 whose control terminal Q is turned on is pulled down to a low level; the self-compensation voltage V R is transmitted to the sustain enable terminal P through the turned-on eighth transistor T8.
  • the charge accumulation can be discharged by the pull-down transistors (ie, the fifth transistor T5 and the sixth transistor T6).
  • the threshold voltage of each transistor in the gate drive circuit will drift and affect the life of the circuit.
  • the influence of DC voltage stress on the transistor is particularly obvious.
  • the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 operate under the DC bias
  • the other transistors operate under the low frequency pulse bias, and the threshold voltage drift is small, and the working state thereof is not Significant impact.
  • the threshold voltages of the three transistors will rise, and the gate voltages of the three transistors are both
  • the voltage of the second pole for example, the source
  • the threshold voltage drift laws of the three transistors can be approximately considered to be similar.
  • the threshold voltage of the ninth transistor T9 rises, and the voltage V R formed on the control electrode of the ninth transistor T9 also follows the rise, thereby making it possible to compensate for the increase in the threshold voltage of the fifth transistor T5 and the sixth transistor T6.
  • the pull-up transistor control voltage voltage adaptive boost can effectively maintain the low level of the control terminal Q and the signal output terminal of the gate driving circuit unit.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the first electrode of the third transistor T3 is connected to the control terminal Q of the driving module 20, and the second pole thereof is connected to the low-level terminal V SS through the third
  • the transistor T3 directly discharges the control terminal Q of the driving module 20, and in this embodiment, the third transistor T3 supplies an active level to the sustaining terminal P to realize the initializing discharge of the control terminal Q, and the fourth can be saved.
  • FIG. 3 is a circuit structural diagram of a gate driving circuit unit disclosed in this embodiment.
  • the first transistor of the third transistor T3 is connected to the control electrode and is used for inputting the initialization signal V STV , and the second electrode of the third transistor T3 is connected to the sustain enable terminal P.
  • the working sequence of the gate driving circuit unit of this embodiment is the same as that of the above embodiment, and the working process is substantially the same.
  • the difference is that in the initialization phase: the initialization signal V STV is high, and then the third transistor T3 is turned on, and the initialization signal V STV is transmitted to the sustain enable terminal P through the turned-on third transistor T3.
  • the fifth transistor T5 and the sixth transistor T6 are turned on in response to the active level of the sustain terminal P, so that the control terminal Q of the driving module 20 and the signal output terminal of the gate driving circuit unit respectively pass through
  • the five transistors T5 and the sixth transistor T6 are discharged to the low level terminal V SS , and thus the potential terminals of the control terminal Q of the driving module 20 and the signal output terminal of the gate driving circuit unit are respectively initialized.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • the adaptive voltage generating module 40 outputs the self-compensating voltage V R to the circuit unit to affect the normal operation of the gate driving circuit unit, and may also be in the actual application process. Appropriate switching transistors are added to the appropriate voltage generating module 40 to control the operating state of the adaptive voltage generating module 40.
  • the adaptive voltage generating module 40 disclosed in this embodiment further includes: a tenth transistor T10 and an eleventh transistor T11. To achieve switching control of the adaptive voltage generating module 40. among them,
  • the eleventh transistor T11 is connected between the second end of the constant current source and the first end of the ninth transistor T9. Specifically, the first electrode of the eleventh transistor T11 is connected to the second end of the constant current source, and the tenth The second pole of a transistor T11 is coupled to the first pole of the ninth transistor T9.
  • the tenth transistor 10 is connected between the first pole of the ninth transistor T9 and the gate of the ninth transistor T9. Specifically, the first pole of the tenth transistor 10 is connected to a first pole of the ninth transistor T9, and a second pole of the tenth transistor 10 is connected to the gate of the ninth transistor T9; or
  • the tenth transistor 10 is connected between the first pole of the eleventh transistor T11 and the gate of the ninth transistor T9, specifically, the first pole of the tenth transistor 10. Connected to the first pole of the eleventh transistor T11, the second pole of the tenth transistor 10 is connected to the gate of the ninth transistor T9.
  • the control electrode of the eleventh transistor T11 is connected to the control electrode of the tenth transistor 10 for inputting the third input signal V I3 .
  • the eleventh transistor T11 and the tenth transistor 10 are turned on in response to the active level of the third input signal V I3 to activate the adaptive voltage generating module 40 to operate.
  • the third input signal V I3 It can also be provided by the second input signal V I2 .
  • the adaptive voltage generating module 40 may further include: a second capacitor C2 connected in parallel between the gate of the ninth transistor T9 and the second pole of the ninth transistor T9.
  • the second capacitor C2 is such that, for example, when the eleventh transistor T11 and the tenth transistor 10 are turned off, the self-compensation voltage V R generated by the adaptive voltage generating module 40 is maintained.
  • the tenth transistor 10 and the eleventh transistor T11 are turned on in response to the effective level of the third input signal V I3 .
  • the current I REF generated by the constant current source flows through the tenth transistor 10, the eleventh transistor T11 and the ninth transistor T9, and forms a self-compensation voltage V R at the control electrode (eg, the gate) of the ninth transistor T9, self-compensating
  • the voltage V R can be expressed as:
  • ⁇ , C ox , L, and W are the device mobility, the unit area gate capacitance, the channel length, and the width of the ninth transistor T9, respectively, and V TH is the threshold voltage of the ninth transistor T9, and the above equation indicates that the self-compensation
  • the potential of the voltage V R rises as the threshold voltage V TH of the ninth transistor T9 rises, thereby ensuring a low level sustaining phase and stable output.
  • the eleventh transistor T11 and the tenth transistor 10 are in an off state, and under the action of the second capacitor C2, the potential of the self-compensation voltage V R can be continuously maintained until The next active level of the third input signal V I3 comes.
  • the self-compensation voltage V R generated by the adaptive voltage generating module 40 can also be sent to the gate driving circuit units of each stage through the output buffer.
  • the threshold voltage drift of the fifth transistor T5 and the sixth transistor T6 can also be recovered.
  • the control electrode (such as the gate) of the transistor is applied with a negative voltage, the threshold voltage drift that occurs will partially recover.
  • the gate driving circuit unit further disclosed in the embodiment further includes a recovery module 50. Referring to FIG. 4c, the recovery module 50 includes a fourteenth transistor T14, and the first electrode of the fourteenth transistor T14 is connected to the adaptive voltage.
  • the signal output end of the generating module 40, the second pole of the fourteenth transistor T14 is used for inputting the reverse bias voltage V SSL , and the reverse bias voltage V SSL is lower than the potential of the low level terminal V SS , the fourteenth transistor T14
  • the control electrode is used to input the fourth input signal V I4 .
  • the fourteenth transistor T14 is configured to transmit the reverse bias voltage V SSL to the signal output end of the adaptive voltage generating module 40 under the excitation of the active level of the fourth input signal V I4 , thereby transmitting the pull-down transistor to the low level module
  • the gates of for example, the fifth transistor T5 and the sixth transistor T6).
  • the gate driving circuit continues to operate, and the fourth input signal V I4 is at an active level (eg, a high level), and at this time, the low level V SSL is transmitted to the ninth transistor through the fourteenth transistor T14.
  • the control pole of T9 is transmitted to the control poles of T5 and T6 as self-compensating voltages. Due to the reverse bias of V SSL , transistors T9, T5 and T6 will have a certain degree of threshold recovery, which can extend the use of transistors. life.
  • the constant current source should stop supplying the current I REF to the ninth transistor T9: in one embodiment, the current source can be controlled by the current magnitude.
  • the current I REF generated by the constant current source can be turned off in an existing manner; in another embodiment, the switching transistor can also be used.
  • the current I REF supplied from the disconnected constant current source is turned to the ninth transistor T9, which is realized by the tenth transistor 10 and the eleventh transistor T11 as shown in FIGS. 4a and 4b.
  • the application of the adaptive voltage generating module 40 shown in FIG. 4a is taken as an example.
  • FIG. 5 a circuit structure diagram of a gate driving circuit unit disclosed in this embodiment is shown.
  • the gate driving circuit unit employs the adaptive voltage generating module 40 shown in FIG. 4a, and the gate electrode of the tenth transistor 10 and the gate electrode of the ninth transistor T9 are used to input the second input signal V I2 .
  • the working sequence of the gate driving circuit unit of this embodiment is as shown in FIG. 2, and the working process is substantially the same as that of the above embodiment, and includes five stages of initialization, pre-charging, pull-up, pull-down, and low level maintenance, which are different.
  • the low level sustain phase the second input signal V I2 is at a high level, the fourth transistor T4 is turned on, and the potential of the control terminal Q is pulled to a low level.
  • the eleventh transistor T11 and the tenth transistor 10 are turned on in response to the high level of the second input signal V I2 , and the current I REF provided by the constant current source is maintained and enabled by the turned-on eleventh transistor T11 and the tenth transistor 10
  • the terminal P is charged, and the final potential of the enable terminal P (ie, the self-compensation voltage V R ) is related to the threshold voltage of the ninth transistor T9 as follows:
  • Maintaining the voltage of the enable terminal P causes the fifth transistor T5 and the sixth transistor T6 to be turned on, and the fifth terminal T5 and the sixth transistor T6 whose control terminal Q and the signal output terminal of the gate driving circuit unit are turned on are pulled down to a low level. Then, the charge accumulated at the two ends is released.
  • the gate driving circuit unit can be constructed by cascading a plurality of gate driving circuit units disclosed in the above embodiments, wherein the cascading mode can adopt an existing scheme.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • This embodiment also discloses a display device. As shown in Figure 6, it includes:
  • the display panel 100 includes a two-dimensional pixel composed of a plurality of two-dimensional pixels An array, and a plurality of gate scan lines in a first direction (eg, lateral) connected to each pixel and a plurality of data lines in a second direction (eg, longitudinal).
  • the same row of pixels in the pixel array are connected to the same gate scan line, and the same column of pixels in the pixel array are connected to the same data line.
  • the display panel 100 may be a liquid crystal display panel, an organic light emitting display panel, an electronic paper display panel, or the like, and the corresponding display device may be a liquid crystal display, an organic light emitting display, an electronic paper display, or the like.
  • the gate driving circuit 200 and the gate driving circuit 200 are configured by the gate driving circuit unit provided in the above embodiment.
  • the signal output end of the gate driving circuit unit in the gate driving circuit 200 is coupled to a corresponding gate scanning line in the display panel 100 for progressive scanning of the pixel array, and the gate driving circuit 200 can pass through the soldering and display panel 100 is connected or integrated in the display panel 100.
  • the gate driving circuit 200 may be disposed on one side of the display panel 100; in a preferred embodiment, a pair of gate driving circuits 200 are disposed on both sides of the display panel 100.
  • the data driving circuit 400 is configured to generate an image data signal and output it to a data line corresponding thereto in the display panel 100, and transmit the data to the corresponding pixel unit through the data line to realize image grayscale.
  • the timing generation circuit 300 is configured to generate various control signals required by the gate driving circuit 200.

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Abstract

一种栅极驱动电路，包括级联的至少一个栅极驱动电路单元，在栅极驱动电路单元的低电平维持使能端(P)连接有自适电压产生模块(40)，自适电压产生模块(40)根据其恒流源产生自补偿电压，并传输给维持使能端(P)，以向维持使能端(P)提供有效电平。由于低电平维持模块(30)中下拉晶体管发生阈值电压漂移时，会体现在维持使能端(P)，因此，自适电压产生模块(40)在其恒流源的作用下会根据阈值电压产生自补偿电压，从而能够弥补阈值电压的增加，使得下拉晶体管的过驱动电压恒定，保持良好的下拉能力，进而延长了栅极驱动电路的工作寿命。

Description

栅极驱动电路及其单元和一种显示装置 技术领域
本发明涉及电子电路领域，具体涉及到一种栅极驱动电路及其单元和一种显示装置。
背景技术
薄膜晶体管(TFT)平板显示(Flat Panel Display，FPD)技术是当今显示技术的主流，大尺寸、更高分辨率显示是TFT-FPD的重要发展方向。TFT集成的栅极驱动电路(Gate Driver On Array，GOA)是大尺寸、高分辨率TFT-FPD发展过程中产生的重要技术。相比于传统的采用外围栅极驱动IC的方式，采用GOA的TFT-FPD面板的外接引线数量极大地减少，于是引线过密对分辨率的限制被放宽。GOA技术带来的其他优势包括：减少外围IC的使用数量，使得信号传输更为稳定可靠，同时还可以减少显示模组的成本，使显示面板更轻薄，显示边框更窄、更美观。
在GOA电路中，由于其输出的栅极扫描信号在大部分的工作时间内处于低电平，所以一般需要低电平维持电路(low-level-holding circuit)来维持中间节点以及信号输出节点上的低电平，以避免时钟馈通效应或者泄露电流等对GOA的中间节点或者输出节点电位的影响，防止GOA输出逻辑紊乱。但是，GOA的低电平维持电路容易由于下拉晶体管阈值电压的漂移而发生性能退化。传统的设计思路是减少下拉管的特性漂移，实现的方式主要有：1，将下拉晶体管偏置于高频脉冲应力模式下；2，将下拉晶体管偏置于低频脉冲应力模式下；3，将下拉晶体管偏置于低压直流模式下。测试结果表明，相比于高压直流偏置模式，这些方式都能在一定程度上减少下拉晶体管的阈值电压漂移。但是，下拉晶体管的阈值电压漂移仍然不可避免，所以GOA的寿命仍然较短。亟待研究新的GOA电路结构，进一步提升地延长GOA的寿命，以满足高性能电视面板的要求。
发明内容
本申请提供一种栅极驱动电路及其单元和一种显示装置，以补偿低 电平维持模块的阈值电压，延长电路的工作寿命。
根据第一方面，一种实施例中提供一种栅极驱动电路，包括级联的至少一个栅极驱动电路单元，栅极驱动电路单元包括：
驱动模块，用于通过其控制端的开关状态切换，将第一时钟信号传送到栅极驱动电路单元的信号输出端，从而输出扫描信号；输入模块，用于控制驱动模块的控制端切换开关状态；低电平维持模块，用于在其维持使能端获得有效电平时将栅极驱动电路的信号输出端和/或驱动模块的控制端维持在低电平；栅极驱动电路还包括至少一个自适电压产生模块，自适电压产生模块的信号输出端用于连接至维持使能端，自适电压产生模块用于根据其恒流源产生自补偿电压，并通过其信号输出端传输给维持使能端，以向维持使能端提供有效电平。
根据第二方面，一种实施例中提供一种显示装置，包括：
由多个像素构成的二维像素阵列，以及与阵列中每个像素相连的第一方向的多条数据线和第二方向的多条栅极扫描线；数据驱动电路，为数据线提供数据信号；和上述栅极驱动电路，为所述栅极扫描线提供栅极驱动信号。
依据上述实施例提供的栅极驱动电路，在低电平维持模块中下拉晶体管发生阈值电压漂移时，会体现在维持使能端，由于自适电压产生模块的信号输出端连接在低电平维持模块的维持使能端，因此，当下拉晶体管发生阈值电压漂移时，自适电压产生模块在其恒流源的作用下产生自补偿电压，从而能够弥补阈值电压的增加，使得下拉晶体管的过驱动电压恒定，保持良好的下拉能力，继而延长了栅极驱动电路的工作寿命。
附图说明
图1为实施例一公开的一种栅极驱动电路单元的电路结构图；
图2为一种实施例栅极驱动电路单元的一种工作时序图；
图3为实施例二公开的一种栅极驱动电路单元的电路结构图；
图4a为实施例三公开的一种自适电压产生模块电路结构示意图；
图4b为实施例三公开的另一种自适电压产生模块电路结构示意图；
图4c为实施例三公开的第三种自适电压产生模块电路结构示意图；
图5为实施例三公开的一种栅极驱动电路单元电路结构图；
图6为实施例四公开的一种显示装置结构示意图。
具体实施方式
下面通过具体实施方式结合附图对本发明作进一步详细说明。
首先对一些术语进行说明：
本申请中的开关管为晶体管。
本申请中的晶体管可以为双极型晶体管或场效应晶体管。当晶体管为双极型晶体管时，其控制极是指双极型晶体管的基极，第一极可以为双极型晶体管的集电极或发射极，对应的第二极可以为双极型晶体管的发射极或集电极；当晶体管为场效应晶体管时，其控制极是指场效应晶体管的栅极，第一极可以为场效应晶体管的漏极或源极，对应的第二极可以为场效应晶体管的源极或漏极。显示器中的晶体管通常为一种场效应晶体管：薄膜晶体管(TFT)。下面以晶体管为场效应晶体管为例对本申请做详细的说明，在其它实施例中晶体管也可以是双极型晶体管。
有效电平是指能够导通晶体管的电平，例如当晶体管为N型晶体管时，则对应的有效电平为高电平。在本实施例中，除特别说明外，以有效电平为高电平为例进行阐述。
实施例一：
请参考图1，为本实施例公开的一种栅极驱动电路单元的电路结构图。该栅极驱动电路单元包括：驱动模块20、输入模块10、低电平维持模块30和自适电压产生模块40。其中，
驱动模块20，用于通过其控制端Q的开关状态切换，将第一时钟信号VA传送到栅极驱动电路单元的信号输出端，从而输出扫描信号VOUT。在一种实施例中，控制端Q的开关状态可以通过高低电平来表征，例如高电平时，控制端Q为开启状态，低电平时，控制端Q为关闭状态；在另一种实施例中，还可以根据晶体管的类型置换开关状态。在具体实施例中，驱动模块20可以包括：第二晶体管T2，第二晶体管T2的第一极用于输入第一时钟信号VA，第二晶体管T2的控制极为驱动模块20的控制端Q，第二晶体管T2的第二极为栅极驱动电路单元的信号输出端。在其它实施例中，也可以是其它现有的或者将来出现的驱动方式。
输入模块10，用于控制驱动模块20的控制端Q切换开关状态。在具体实施例中，输入模块10包括：第一晶体管T1，第一晶体管T1的控 制极连接至第一极，用于输入第一输入信号VI1；第一晶体管T1的第二极连接至驱动模块20的控制端Q。在其它实施例中，也可以是其它现有的或者将来出现的输入方式。在本实施例中，第一输入信号VI1的有效电平到来时间超前于第一时钟信号VA的有效电平到来时间，例如第一时钟信号VA的时钟周期为T，占空比为50％，第一输入信号VI1的脉宽为T/2，则第一输入信号VI1的有效电平到来时间可以超前于第一时钟信号VA的有效电平到来时间T/2。需要说明的是，当晶体管为N型晶体管时，其控制极对应的导通的有效电平为高电平，反之，当晶体管为P型晶体管时，其控制极对应的导通的有效电平为低电平。本实施例中，以N型晶体管为例进行说明，相应地，晶体管导通的有效电平为高电平。
低电平维持模块30，用于在其维持使能端P获得有效电平时将栅极驱动电路的信号输出端和/或驱动模块20的控制端Q维持在低电平。在具体实施例中，低电平维持模块30包括：第五晶体管T5和第六晶体管T6，其中，第五晶体管T5的控制极连接至第六晶体管T6的控制极，连接节点为低电平维持模块30的维持使能端P；第五晶体管T5的第一极连接至驱动模块20的控制端Q；第五晶体管T5的第二极用于连接至低电平端VSS。第六晶体管T6的第一极连接至栅极驱动电路单元的信号输出端，第六晶体管T6的第二极用于连接至低电平端VSS。在优选的实施例中，低电平维持模块30还可以包括第一电容C1，第一电容C1连接在维持使能端P和低电平端VSS之间，第一电容C1的主要作用是为了在低电平维持阶段保持维持使能端P的电位。在其它实施例中，也可以是其它现有的或者将来出现的维持方式。
需要说明的是，上述各个模块只是以示例的方式原理性地阐述栅极驱动电路单元，各模块均可采用现有的技术方案，因此，上述各模块中，有些细节并未详细描述，本领域技术人员依据现有的技术方案能够实现栅极驱动电路单元各模块之间的连接。此外，本领域技术人员也可以根据实际需要，为完善各模块的功能，而适当增加元器件或模块：
例如，为了初始化驱动模块20的控制端Q的电位，在一种实施例中，栅极驱动电路单元还可以包括第三晶体管T3，第三晶体管T3的控制极用于输入初始化信号VSTV，第三晶体管T3的第一极连接至驱动模块20的控制端Q，第三晶体管T3的第二极用于连接至低电平端VSS。在初始化阶段，第三晶体管T3响应初始化信号VSTV的有效电平导通， 从而初始化控制端Q的电位。在具体实施例中初始化信号VSTV的有效电平可以是例如T/2脉宽的高脉冲信号，第一输入信号VI1的有效电平可以在初始化信号VSTV有效电平结束后T/4(当然，也可以根据实际需要来设定)到来。
例如，为了在栅极驱动电路单元输出扫描信号VOUT之后，实现对初始化驱动模块20的控制端Q的电位的下拉，栅极驱动电路单元还可以包括第四晶体管T4，第四晶体管T4的控制极用于输入第二输入信号VI2，第四晶体管T4的第一极连接至驱动模块20的控制端Q，第四晶体管T4的第二极用于连接至低电平端VSS。在栅极驱动电路单元输出扫描信号VOUT之后，第四晶体管T4响应第二输入信号VI2的有效电平导通，从而实现控制端Q的放电。
例如，为了使得输入模块10在响应第一输入信号VI1时，能够更好地向控制端Q充电，防止控制端Q的电位被低电平维持模块30不期望地下拉，低电平维持模块30还可以进一步包括第七晶体管T7，第七晶体管T7的控制极用于输入第一输入信号VI1，第七晶体管T7的第一极连接至维持使能端P，第七晶体管T7的第二极用于连接至低电平端VSS。于是，在输入模块10响应第一输入信号VI1的有效电平向控制端Q充电时，第七晶体管T7也响应第一输入信号VI1的有效电平导通将维持使能端P的电位耦合到低电平。
在本实施例中，第二输入信号VI2的有效电平到来时间滞后于第一时钟信号VA的有效电平结束时间。例如，第二输入信号VI2的脉宽为T/2，则第二输入信号VI2的有效电平到来时间可以滞后于第一时钟信号VA有效电平结束时间T/2。
本实施例公开的栅极驱动电路单元还包括：自适电压产生模块40，自适电压产生模块40的信号输出端用于连接至维持使能端P，自适电压产生模块40用于根据其恒流源产生自补偿电压VR，并通过其信号输出端传输给维持使能端P，以向维持使能端P提供有效电平。
在优选的实施例中，自适电压产生模块40和低电平维持模块30之间还连接有：第八晶体管T8，第八晶体管T8的第一极用于连接至自适电压产生模块40的信号输出端，第八晶体管T8的第二极连接至低电平维持模块30的维持使能端P，第八晶体管T8的控制极用于输入第二输入信号VI2；第八晶体管T8响应第二输入信号VI2的有效电平导通第八 晶体管T8的第一极和第二极，从而使得自适电压产生模块40产生的自补偿电压VR通过其信号输出端传输给维持使能端P。
在具体实施例中，自适电压产生模块40包括：恒流源和第九晶体管T9，其中，第九晶体管T9的第一极连接至第九晶体管T9的控制极；第九晶体管T9的控制极为自适电压产生模块40的信号输出端；第九晶体管T9的第二极用于连接至低电平端VSS。恒流源用于产生恒定的电流IREF，恒流源的第一端用于输入预设电位，恒流源的第二端连接至第九晶体管T9的第一极。在具体实施例中，恒流源可以是电流源，优选的，可以是电流大小可控的电流源。在具体实施例中，预设电位可以由高电平端提供。
需要说明的是，当栅极驱动电路级联了多个栅极驱动电路单元时，自适电压产生模块40可以由多个栅极驱动电路单元共用；也可以是每个栅极驱动电路单元分别配置一个自适电压产生模块40。
请参考图2，为本实施例中栅极驱动电路单元工作时序图。为方便后续的描述，本实施例中，以VH来表征各时钟信号或者脉冲信号的高电平(高电位)，以VL来表征各时钟信号或者脉冲信号的低电平(低电位)。本实施例中栅极驱动电路单元的工作过程分为初始化、预充电、上拉、下拉、低电平维持五个阶段，下面结合图1和图2，详细介绍本实施例中栅极驱动电路单元的工作过程。
在初始化阶段(t1)，初始化信号VSTV为高电平，于是，第三晶体管T3导通，驱动模块20的控制端Q被导通的第三晶体管T3下拉至低电平VL，从而，完成控制端Q的初始化操作。
在预充电阶段(t2)，第一输入信号VI1为高电平，第一时钟信号VA为低电平。第一晶体管T1响应第一输入信号VI1的高电平导通，第一输入信号VI1通过导通的第一晶体管T1向驱动模块20的控制端Q充电，于是，控制端Q的电压上升，当控制端Q的电压高于第二晶体管T2阈值电压时，第二晶体管T2打开。此时，由于第一时钟信号VA为低电平，所以栅极驱动电路单元的信号输出端输出的扫描信号VOUT为低电平。第七晶体管T7响应第一输入信号VI1的高电平导通，维持使能端P被导通的第七晶体管T7下拉至低电平，于是，第五晶体管T5和第六晶体管T6断开。在预充电结束时刻，控制端Q的电压达到VH-VT，其中，VT为第二晶体管T2的阈值电压，完成预充电操作。
在上拉阶段(t3)，第一时钟信号VA变为高电平，初始化信号VSTV和第二输入信号VI2为低电平。由于控制端Q的电压为VH-VT，第二晶体管T2打开，第一时钟信号VA通过导通的第二晶体管T2给负载提供充电电流，栅极驱动电路单元的信号输出端输出的扫描信号VOUT逐渐上升到VH。在该阶段，第一晶体管T1处于二极管连接状态；由于初始化信号VSTV和第二输入信号VI2为低电平，于是第三晶体管T3和第四晶体管T4保持关断状态；维持使能端P为低电平，于是，第五晶体管T5和第六晶体管T6也保持关断，因此控制端Q将处于悬浮状态，由于自举效应，控制端Q被第一时钟信号VA耦合至高电平2VH-VT。
在下拉阶段(t4)，第一时钟信号VA变为低电平，第二晶体管T2保持打开，于是，栅极驱动电路单元输出的扫描信号VOUT下降至低电平，由于第一时钟信号VA的耦合作用，控制端Q下降至VH-VT。
在低电平维持阶段(t5)，第二输入信号VI2为高电平，第四晶体管T4和第八晶体管T8响应第二输入信号VI2的高电平导通。于是，控制端Q被导通的第四晶体管T4下拉至低电平；自补偿电压VR通过导通的第八晶体管T8传输到维持使能端P。维持使能端P电压上升，当维持使能端P电压超过第五晶体管T5和第六晶体管T6的阈值电压时，第五晶体管T5和第六晶体管T6响应维持使能端P的电位导通，于是，驱动模块20的控制端Q以及栅极驱动电路单元的信号输出端的电位被下拉至低电平，从而使得控制端Q以及栅极驱动电路单元的信号输出端上因时钟信号或噪声信号引起的电荷积累可以通过下拉晶体管(即第五晶体管T5和第六晶体管T6)泄放掉。
栅极驱动电路中各个晶体管在长时间栅极电压应力作用下，其阈值电压会发生漂移从而影响电路寿命，直流电压应力对晶体管的影响尤为明显。本实施例中，除了第五晶体管T5、第六晶体管T6以及第九晶体管T9工作在直流偏置之下，其他晶体管都工作在低频脉冲偏置下，阈值电压漂移较小，对其工作状态没有明显影响。由于加载在第五晶体管T5、第六晶体管T6以及第九晶体管T9控制极(例如栅极)的电位为正电压，这三个晶体管的阈值电压将会上升，这三个晶体管的控制极电压均为维持使能端P的电压，第二极(例如源极)电压均为低电平端VSS的低电平VL，因此，可以近似地认为这三个晶体管的阈值电压漂移规律相近。随着时间推移，第九晶体管T9的阈值电压上升，第九晶体管T9 控制极上形成的电压VR也会跟随上升，从而能够弥补第五晶体管T5和第六晶体管T6的阈值电压提升而导致的导通能力下降，这种下拉晶体管控制极电压自适应的提升能够有效维持控制端Q以及栅极驱动电路单元的信号输出端的低电平。通过调整恒流源产生的恒定电流IREF及第九晶体管T9、第五晶体管T5和第六晶体管T6的晶体管的尺寸，能够使维持使能端P的电压在GOA电路早期工作时是一个高于阈值电压不多的较低电压，之后随着第九晶体管T9的阈值电压提升，维持使能端P的电压才自适应提升，相对第九晶体管T9、第五晶体管T5和第六晶体管T6有一个较为恒定的低栅极-源极电压差(过驱动电压)，因此这三个晶体管的阈值电压漂移速度会比较慢，使这三个晶体管在很长时间内能够正常工作，从而延长了GOA电路的工作寿命。
实施例二：
与上述实施例不同之处在于，在上述实施例中，第三晶体管T3的第一极连接至驱动模块20的控制端Q，其第二极用于连接至低电平端VSS，通过第三晶体管T3直接对驱动模块20的控制端Q进行放电初始化，本实施例中，通过第三晶体管T3向维持使能端P提供有效电平以实现控制端Q的初始化放电，并且，可以节省第四晶体管T4。
请参考图3，为本实施例公开的一种栅极驱动电路单元的电路结构图。第三晶体管T3第一极连接至控制极，并用于输入初始化信号VSTV，第三晶体管T3的第二极连接至维持使能端P。
请参考图2，本实施例栅极驱动电路单元的工作时序同上述实施例，其工作过程大致相同，所不同的是，在初始化阶段：初始化信号VSTV为高电平，于是，第三晶体管T3导通，初始化信号VSTV通过导通的第三晶体管T3传输至维持使能端P。于是，第五晶体管T5和第六晶体管T6会响应维持使能端P的有效电平导通，从而使得驱动模块20的控制端Q和栅极驱动电路单元的信号输出端分别通过导通的第五晶体管T5和第六晶体管T6放电至低电平端VSS，于是分别完成了驱动模块20的控制端Q和栅极驱动电路单元的信号输出端电位初始化。
本实施例公开的栅极驱动电路单元中，其它工作阶段与上述实施例大致相同，在此不再赘述。
实施例三：
为了防止栅极驱动电路单元在非低电平维持阶段，自适电压产生模块40向电路单元输出自补偿电压VR而影响栅极驱动电路单元正常工作，在实际应用过程中，还可以在自适电压产生模块40中增加适当的开关晶体管，以控制自适电压产生模块40的工作状态。
请参考图4a和图4b，为本实施例公开的一种自适电压产生模块40电路结构示意图，本实施例公开的自适电压产生模块40还包括：第十晶体管T10和第十一晶体管T11，以实现对自适电压产生模块40的开关控制。其中，
第十一晶体管T11连接至恒流源的第二端和第九晶体管T9的第一极之间，具体地，第十一晶体管T11的第一极连接至恒流源的第二端，第十一晶体管T11的第二极连接至第九晶体管T9的第一极。
在一种实施例中，请参考图4a，第十晶体管10连接至第九晶体管T9的第一极和第九晶体管T9的控制极之间，具体地，第十晶体管10的第一极连接至第九晶体管T9的第一极，第十晶体管10的第二极连接至第九晶体管T9的控制极；或者，
在另一种实施例中，请参考图4b，第十晶体管10连接至第十一晶体管T11的第一极和第九晶体管T9的控制极之间，具体地，第十晶体管10的第一极连接至第十一晶体管T11的第一极，第十晶体管10的第二极连接至第九晶体管T9的控制极。
请参考图4a和图4b，第十一晶体管T11的控制极连接至第十晶体管10的控制极，用于输入第三输入信号VI3。第十一晶体管T11和第十晶体管10响应第三输入信号VI3的有效电平导通以激励自适电压产生模块40工作。在具体实施例中，由于自适电压产生模块40通常在低电平维持阶段才开始向栅极驱动电路单元传输自补偿电压VR，因此，在优选的实施例中，第三输入信号VI3也可以由第二输入信号VI2提供。
在优选的实施例中，自适电压产生模块40还可以进一步包括：第二电容C2，第二电容C2并接在第九晶体管T9的控制极和第九晶体管T9的第二极之间。第二电容C2是：例如当第十一晶体管T11和第十晶体管10关断时，实现维持自适电压产生模块40产生的自补偿电压VR。
请参考图4a和图4b，当第三输入信号VI3为有效电平(例如高电平)时，第十晶体管10和第十一晶体管T11响应第三输入信号VI3的有效电 平导通，恒流源产生的电流IREF流过第十晶体管10、第十一晶体管T11和第九晶体管T9，并在第九晶体管T9的控制极(例如栅极)形成自补偿电压VR，自补偿电压VR可以表示为：
Figure PCTCN2016077394-appb-000001
式中，μ、Cox、L以及W分别为第九晶体管T9的器件迁移率、单位面积栅电容、沟道长度及宽度，VTH为第九晶体管T9的阈值电压，上式表明，自补偿电压VR的电位会随着第九晶体管T9的阈值电压VTH升高而升高，从而保证了低电平维持阶段，输出的稳定。
当第三输入信号VI3为低电平时，第十一晶体管T11和第十晶体管10会处于截止状态，而在第二电容C2存储的作用下，可以继续维持自补偿电压VR的电位，直到下一次第三输入信号VI3的有效电平到来。
需要说明的是，在其它实施例中，自适电压产生模块40产生的自补偿电压VR也可以通过输出缓冲器送入到各级栅极驱动电路单元中。
为了在实现更长的使用寿命，在优选的实施例中，还可以对第五晶体管T5以及第六晶体管T6的阈值电压漂移进行恢复。当晶体管的控制极(例如栅极)加负电压时，其发生的阈值电压漂移就会部分恢复。根据此原理本实施例还公开的栅极驱动电路单元中还包括恢复模块50，请参考图4c，恢复模块50包括第十四晶体管T14，第十四晶体管T14的第一极连接到自适电压产生模块40的信号输出端，第十四晶体管T14的第二极用于输入反偏电压VSSL，反偏电压VSSL为比低电平端VSS电位更低的电平，第十四晶体管T14的控制极用于输入第四输入信号VI4。第十四晶体管T14用于在第四输入信号VI4的有效电平的激励下将反偏电压VSSL传输到自适电压产生模块40的信号输出端，从而传输至低电平模块的下拉晶体管(例如第五晶体管T5以及第六晶体管T6)的控制极。在面板进入待机状态时，栅极驱动电路继续工作，第四输入信号VI4为有效电平(例如高电平)，此时低电平VSSL通过第第十四晶体管T14传输到第九晶体管T9的控制极，并作为自补偿电压依次传输到T5和T6的控制极，由于VSSL的反偏作用，晶体管T9、T5和T6就会产生一定程度的阈值恢复作用，从而能够延长晶体管的使用寿命。需要说明的是，在第四输入信号VI4的有效电平到来时，恒流源应当停止向第九晶 体管T9提供电流IREF：在一种实施例中，可以通过电流大小可控的电流源来实现，譬如，当第四输入信号VI4的有效电平到来时，可采用现有的方式关断恒流源产生的电流IREF；在另一种实施例中，也可以通过开关晶体管来实现断开恒流源提供的电流IREF流向第九晶体管T9，譬如图4a和图4b所示的第十晶体管10和第十一晶体管T11来实现。
以图4a所示自适电压产生模块40应用为例，请参考图5，为本实施例公开的一种栅极驱动电路单元电路结构图。其中，输入模块10、低电平维持模块30、驱动模块20以及第三晶体管T3和第四晶体管T4的连接方式可参见实施例二的描述，与上述实施例不同之处在于，本实施例中，栅极驱动电路单元采用了图4a所示的自适电压产生模块40，第十晶体管10的控制极以及第九晶体管T9的控制极用于输入第二输入信号VI2。
本实施例栅极驱动电路单元的工作时序如图2所示，其工作过程与上述实施例大致相同，也包括了初始化、预充电、上拉、下拉、低电平维持五个阶段，所不同的是，在低电平维持阶段：第二输入信号VI2为高电平，第四晶体管T4打开，控制端Q的电位被拉到低电平。第十一晶体管T11和第十晶体管10响应第二输入信号VI2的高电平导通，恒流源提供的电流IREF通过导通的第十一晶体管T11和第十晶体管10给维持使能端P充电，维持使能端P的最终电位(即自补偿电压VR)与第九晶体管T9的阈值电压有如下关系：
Figure PCTCN2016077394-appb-000002
维持使能端P的电压使第五晶体管T5和第六晶体管T6打开，控制端Q以及栅极驱动电路单元的信号输出端被导通的第五晶体管T5和第六晶体管T6下拉至低电平，于是泄放掉了该两端积累的电荷。
级联多个上述实施例公开的栅极驱动电路单元便可构成栅极驱动电路，其中，级联方式可以采用现有的方案。
实施例四：
本实施例还公开了一种显示装置。如图6所示，包括：
显示面板100，显示面板100包括由多个二维像素构成的二维像素 阵列，以及与每个像素相连的第一方向(例如横向)的多条栅极扫描线和第二方向(例如纵向)的多条数据线。像素阵列中的同一行像素均连接到同一条栅极扫描线，而像素阵列中的同一列像素则连接到同一条数据线。显示面板100可以是液晶显示面板、有机发光显示面板、电子纸显示面板等，而对应的显示装置可以是液晶显示器、有机发光显示器、电子纸显示器等。
栅极驱动电路200，栅极驱动电路200采用上述实施例提供的栅极驱动电路单元构成。栅极驱动电路200中栅极驱动电路单元的信号输出端耦合到显示面板100中与其对应的栅极扫描线，用于对像素阵列的逐行扫描，栅极驱动电路200可以通过焊接与显示面板100相连或者集成于显示面板100内。在一种具体实施例中，栅极驱动电路200可以布置在显示面板100的一侧；在优选的实施例中，采用成对的栅极驱动电路200，布置在显示面板100的两侧。
数据驱动电路400，用于产生图像数据信号，并将其输出到显示面板100中与其对应的数据线上，通过数据线传输到对应的像素单元内以实现图像灰度。
时序产生电路300，用于产生栅极驱动电路200所需的各种控制信号。
以上应用了具体个例对本发明进行阐述，只是用于帮助理解本发明，并不用以限制本发明。对于本发明所属技术领域的技术人员，依据本发明的思想，还可以做出若干简单推演、变形或替换。

Claims (10)

  1. 一种栅极驱动电路，包括级联的至少一个栅极驱动电路单元，所述栅极驱动电路单元包括：
    驱动模块(20)，用于通过其控制端(Q)的开关状态切换，将第一时钟信号(VA)传送到栅极驱动电路单元的信号输出端，从而输出扫描信号(VOUT)；
    输入模块(10)，用于控制驱动模块(20)的控制端(Q)切换开关状态；
    低电平维持模块(30)，用于在其维持使能端(P)获得有效电平时将栅极驱动电路的信号输出端和/或驱动模块(20)的控制端(Q)维持在低电平；
    其特征在于，所述栅极驱动电路还包括至少一个自适电压产生模块(40)，自适电压产生模块(40)的信号输出端用于连接至维持使能端(P)，自适电压产生模块(40)用于根据其恒流源产生自补偿电压(VR)，并通过其信号输出端传输给维持使能端(P)，以向维持使能端(P)提供有效电平。
  2. 如权利要求1所述的栅极驱动电路，其特征在于，
    所述输入模块(10)包括：第一晶体管(T1)，第一晶体管(T1)的控制极连接至第一极，用于输入第一输入信号(VI1)；第一晶体管(T1)的第二极连接至驱动模块(20)的控制端(Q)；
    所述驱动模块(20)包括：第二晶体管(T2)，第二晶体管(T2)的第一极用于输入第一时钟信号(VA)，第二晶体管(T2)的控制极为所述驱动模块(20)的控制端(Q)，第二晶体管(T2)的第二极为所述栅极驱动电路单元的信号输出端；
    所述第一输入信号(VI1)的有效电平到来时间超前于所述第一时钟信号(VA)的有效电平到来时间。
  3. 如权利要求2所述的栅极驱动电路，其特征在于，在自适电压产生模块(40)和低电平维持模块(30)之间还连接有：第八晶体管(T8)；
    第八晶体管(T8)的第一极用于连接至自适电压产生模块(40)的信号输出端，第八晶体管(T8)的第二极连接至低电平维持模块(30)的维持使能端(P)，第八晶体管(T8)的控制极用于输入第二输入信号(VI2)；
    第八晶体管(T8)响应第二输入信号(VI2)的有效电平导通第八晶体管(T8)的第一极和第二极；
    第二输入信号(VI2)的有效电平到来时间滞后于所述第一时钟信号(VA)的有效电平结束时间。
  4. 如权利要求1所述的栅极驱动电路，其特征在于，所述低电平维持模块(30)包括：第五晶体管(T5)和第六晶体管(T6)；
    第五晶体管(T5)的控制极连接至第六晶体管(T6)的控制极，连接节点为所述低电平维持模块(30)的维持使能端(P)；第五晶体管(T5)的第一极连接至驱动模块(20)的控制端(Q)；第五晶体管(T5)的第二极用于连接至低电平端(VSS)；
    第六晶体管(T6)的第一极连接至栅极驱动电路单元的信号输出端，第六晶体管(T6)的第二极用于连接至低电平端(VSS)。
  5. 如权利要求1-4任意一项所述的栅极驱动电路，其特征在于，所述自适电压产生模块(40)包括：恒流源和第九晶体管(T9)；
    第九晶体管(T9)的第一极连接至第九晶体管(T9)的控制极；第九晶体管(T9)的控制极为自适电压产生模块(40)的信号输出端；第九晶体管(T9)的第二极用于连接至低电平端(VSS)；
    恒流源的第一端用于输入预设电位，恒流源的第二端连接至第九晶体管(T9)的第一极。
  6. 如权利要求5所述的栅极驱动电路，其特征在于，所述恒流源为电流大小可控电流源。
  7. 如权利要求6所述的栅极驱动电路，其特征在于，还包括恢复模块(50)，所述恢复模块(50)包括：第十四晶体管(T14)，第十四晶体管(T14)的第一极连接至自适电压产生模块(40)的信号输出端，第十四晶体管(T14)的第二极用于输入反偏电压(VSSL)，第十四晶体管(T14)的控制极用于输入第四输入信号(VI4)；第十四晶体管(T14)响应第四输入信号(VI4)的有效电平导通，向自适电压产生模块(40)的信号输出端提供反偏电压(VSSL)。
  8. 如权利要求5所述的栅极驱动电路，其特征在于，所述自适电压产生模块(40)还包括：第十晶体管(T10)和第十一晶体管(T11)；
    第十一晶体管(T11)连接至恒流源的第二端和第九晶体管(T9)的第一极之间；第十一晶体管(T11)的第一极连接至恒流源的第二端， 第十一晶体管(T11)的第二极连接至第九晶体管(T9)的第一极；
    第十晶体管(10)连接至第九晶体管(T9)的第一极和第九晶体管(T9)的控制极之间；第十晶体管(10)的第一极连接至第九晶体管(T9)的第一极，第十晶体管(10)的第二极连接至第九晶体管(T9)的控制极；或者，
    第十晶体管(10)连接至第十一晶体管(T11)的第一极和第九晶体管(T9)的控制极之间；第十晶体管(10)的第一极连接至第十一晶体管(T11)的第一极，第十晶体管(10)的第二极连接至第九晶体管(T9)的控制极；
    第十一晶体管(T11)的控制极连接至第十晶体管(10)的控制极，用于输入第三输入信号(VI3)；第十一晶体管(T11)和第十晶体管(10)响应第三输入信号(VI3)的有效电平导通以激励自适电压产生模块(40)工作。
  9. 如权利要求5所述的栅极驱动电路，其特征在于，所述自适电压产生模块(40)还包括：第二电容(C2)；第二电容(C2)并接在第九晶体管(T9)的控制极和第九晶体管(T9)的第二极之间。
  10. 一种显示装置，包括由多个像素构成的二维像素阵列，以及与阵列中每个像素相连的第一方向的多条数据线和第二方向的多条栅极扫描线；
    数据驱动电路，为数据线提供数据信号；
    其特征在于，还包括：
    如权利要求1-9任意一项所述的栅极驱动电路，为所述栅极扫描线提供栅极驱动信号。
PCT/CN2016/077394 2015-04-24 2016-03-25 栅极驱动电路及其单元和一种显示装置 WO2016169389A1 (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113112951A (zh) * 2021-04-29 2021-07-13 合肥维信诺科技有限公司 扫描电路和显示面板
CN114093331A (zh) * 2021-11-22 2022-02-25 武汉华星光电技术有限公司 一种goa驱动电路及显示面板

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104795013B (zh) * 2015-04-14 2017-08-29 北京大学深圳研究生院 移位寄存器及其单元和一种显示装置
CN104821146B (zh) * 2015-04-24 2017-05-24 北京大学深圳研究生院 栅极驱动电路及其单元和一种显示装置
CN109637424A (zh) * 2019-01-24 2019-04-16 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN110933335B (zh) * 2020-01-21 2020-05-12 南京迪钛飞光电科技有限公司 一种平板探测器的驱动电路以及时序驱动方法
CN114203123B (zh) * 2021-11-25 2022-12-06 北京奕斯伟计算技术股份有限公司 自反馈补偿电路及监控补偿方法、显示面板、显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090278785A1 (en) * 2008-05-12 2009-11-12 Chi Mei Optoelectronics Corporation Displays
US20100182227A1 (en) * 2009-01-16 2010-07-22 Yuan-Hsin Tsou Gate driving circuit capable of suppressing threshold voltage drift
CN104318883A (zh) * 2014-10-10 2015-01-28 北京大学深圳研究生院 移位寄存器及其单元、显示器和阈值电压补偿电路
CN104332127A (zh) * 2013-11-29 2015-02-04 北京大学深圳研究生院 一种移位寄存器单元和栅极驱动电路及其显示器
CN104332126A (zh) * 2013-11-29 2015-02-04 北京大学深圳研究生院 移位寄存器单元、栅极驱动电路和显示器
CN104821146A (zh) * 2015-04-24 2015-08-05 北京大学深圳研究生院 栅极驱动电路及其单元和一种显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100495520C (zh) * 2006-07-28 2009-06-03 胜华科技股份有限公司 位移缓存器及位移缓存单元
CN101783124B (zh) * 2010-02-08 2013-05-08 北京大学深圳研究生院 栅极驱动电路单元、栅极驱动电路及显示装置
JP5396543B2 (ja) * 2010-09-02 2014-01-22 シャープ株式会社 信号処理回路、ドライバ回路、表示装置
KR101966381B1 (ko) * 2012-09-28 2019-04-05 엘지디스플레이 주식회사 쉬프트 레지스터 및 이를 포함하는 평판표시장치
CN105096792B (zh) * 2014-05-12 2017-10-31 北京大学深圳研究生院 自适应电压源、移位寄存器及其单元和一种显示器
CN105446402B (zh) * 2014-08-04 2017-03-15 北京大学深圳研究生院 可控电压源、移位寄存器及其单元和一种显示器
KR102281814B1 (ko) * 2014-12-10 2021-07-26 엘지디스플레이 주식회사 게이트 구동회로 및 이를 포함하는 표시장치
CN104732951B (zh) * 2015-04-21 2017-03-01 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置、显示面板
CN104992661B (zh) * 2015-07-29 2017-09-19 京东方科技集团股份有限公司 移位寄存电路及其驱动方法、栅极驱动电路及显示装置
CN105469763B (zh) * 2015-12-28 2018-09-11 深圳市华星光电技术有限公司 栅极驱动单元、栅极驱动电路及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090278785A1 (en) * 2008-05-12 2009-11-12 Chi Mei Optoelectronics Corporation Displays
US20100182227A1 (en) * 2009-01-16 2010-07-22 Yuan-Hsin Tsou Gate driving circuit capable of suppressing threshold voltage drift
CN104332127A (zh) * 2013-11-29 2015-02-04 北京大学深圳研究生院 一种移位寄存器单元和栅极驱动电路及其显示器
CN104332126A (zh) * 2013-11-29 2015-02-04 北京大学深圳研究生院 移位寄存器单元、栅极驱动电路和显示器
CN104318883A (zh) * 2014-10-10 2015-01-28 北京大学深圳研究生院 移位寄存器及其单元、显示器和阈值电压补偿电路
CN104821146A (zh) * 2015-04-24 2015-08-05 北京大学深圳研究生院 栅极驱动电路及其单元和一种显示装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113112951A (zh) * 2021-04-29 2021-07-13 合肥维信诺科技有限公司 扫描电路和显示面板
CN113112951B (zh) * 2021-04-29 2023-06-20 合肥维信诺科技有限公司 扫描电路和显示面板
CN114093331A (zh) * 2021-11-22 2022-02-25 武汉华星光电技术有限公司 一种goa驱动电路及显示面板
CN114093331B (zh) * 2021-11-22 2022-10-04 武汉华星光电技术有限公司 一种goa驱动电路及显示面板

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