WO2016165546A1 - 移位寄存器及其单元和一种显示装置 - Google Patents

移位寄存器及其单元和一种显示装置 Download PDF

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Publication number
WO2016165546A1
WO2016165546A1 PCT/CN2016/077395 CN2016077395W WO2016165546A1 WO 2016165546 A1 WO2016165546 A1 WO 2016165546A1 CN 2016077395 W CN2016077395 W CN 2016077395W WO 2016165546 A1 WO2016165546 A1 WO 2016165546A1
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Prior art keywords
transistor
terminal
shift register
pole
level
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PCT/CN2016/077395
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English (en)
French (fr)
Inventor
张盛东
胡治晋
廖聪维
李文杰
李君梅
曹世杰
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北京大学深圳研究生院
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Priority to US15/566,608 priority Critical patent/US10255983B2/en
Publication of WO2016165546A1 publication Critical patent/WO2016165546A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of electronic circuits, and in particular to a voltage regulating circuit, a shift register and a unit thereof, and a display device.
  • the threshold voltage of the low level sustain transistor is generally reduced by reducing the magnitude of the voltage stress, the pulse voltage bias, and the duty ratio of the voltage reduction. Drift, extending the working life of the circuit.
  • the driver circuit needs to be in the working mode for a longer period of time, and objectively puts more stringent requirements on the life of the circuit. Therefore, how to effectively extend the working time of the circuit and improve the working life of the shift register is a problem of great research value.
  • an embodiment provides a shift register including at least one shift register unit, the shift register unit comprising: a drive module for passing through its control terminal Switching state switching, transmitting a first clock signal to a signal output end of the shift register unit, thereby outputting a scan signal; an input module for controlling a control terminal switching state of the driving module; and a low level maintaining module, including: a sustaining unit for maintaining the signal output terminal and/or the control terminal of the driving module at a low level when the first sustaining enable terminal obtains an active level; and a second maintaining unit for obtaining the effective at the second sustaining enable terminal The signal output terminal and/or the control terminal of the driving module are maintained at a low level; the shift register unit further includes: a threshold voltage sensing module, wherein the sensing end is connected to the first sustaining enable end, and the signal output end is connected to The second sustaining enable terminal is configured to control the signal output terminal to provide an active level to the second sustain enable terminal according to the threshold drift voltage sensed by the sensing input terminal
  • FIG. 6 is a schematic circuit diagram of another shift register unit according to Embodiment 2 of the present application.
  • FIG. 9 is a schematic structural diagram of a display disclosed in an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a voltage adjustment circuit disclosed in an embodiment of the present application.
  • the switch tube in this application is a transistor.
  • the transistor in the present application may be a bipolar transistor or a field effect transistor.
  • the gate of the transistor is the base of the bipolar transistor
  • the first pole can be the collector or emitter of the bipolar transistor
  • the corresponding second pole can be a bipolar transistor.
  • Emitter or collector when the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor
  • the first pole can be the drain or source of the field effect transistor
  • the corresponding second pole can be the field effect The source or drain of the transistor.
  • the transistor in the display is typically a field effect transistor: a thin film transistor (TFT).
  • TFT thin film transistor
  • the present application will be described in detail by taking a transistor as a field effect transistor.
  • the transistor may also be a bipolar transistor.
  • FIG. 1 is a circuit structural diagram of a shift register unit disclosed in this embodiment.
  • the shift register unit includes a driving module 20, an input module 10, a low level maintaining module 30, and a threshold voltage sensing module 40. among them,
  • the driving module 20 is configured to transmit the first clock signal V A to the signal output terminal OUT of the shift register unit through the switching state switching of the control terminal Q thereof, thereby outputting the scan signal.
  • the switching state of the control terminal Q can be characterized by a high level and a low level. For example, when the high level is, the control terminal Q is in an on state, and when the level is low, the control terminal Q is in an off state; in another embodiment. In the middle, it is also possible to replace the switch state depending on the type of transistor.
  • the driving module 20 may include a second transistor T2 and a first capacitor C1.
  • the second terminal of the second transistor T2 is connected to the first terminal of the first capacitor C1 to form the control terminal Q of the driving module 20, and the second terminal of the second transistor T2 is connected to the second terminal of the first capacitor C1 to form a shift register.
  • the signal output of the unit, the first pole of the second transistor T2 is used to input the first clock signal V A .
  • other existing or future driving methods may also be used.
  • the input module 10 is configured to control the control terminal Q of the driving module 20 to switch the switch state.
  • the input module 10 includes a first transistor T1, a third transistor T3, and a fourth transistor T4.
  • the control electrode of the first transistor T1 is connected to the first pulse for inputting the first pulse signal V I1 ;
  • the second electrode of the first transistor T1 is connected to the control terminal Q of the driving module 20;
  • the control of the fourth transistor T4 The gate of the pole and third transistor T3 is used to input the second pulse signal V I2 ;
  • the first pole of the fourth transistor T4 is connected to the control terminal Q of the driving module 20, and the second pole of the fourth transistor T4 is used to connect to the low The level terminal;
  • the first electrode of the third transistor T3 is connected to the signal output terminal of the shift register unit, and the second electrode of the third transistor T3 is used for connection to the low level terminal.
  • the effective level arrival time of the first pulse input signal V I1 is earlier than the first clock signal V A effective level arrival time by half a clock cycle, and the effective time of the second pulse input signal V I2 is coming It is delayed by half a clock cycle than the arrival time of the first clock signal V A active level.
  • the transistor is an N-type transistor, the effective level of the gate corresponding to the control electrode is a high level, and when the transistor is a P-type transistor, the effective level of the gate corresponding to the transistor is turned on. Is low.
  • an N-type transistor is taken as an example for description. Accordingly, the effective level at which the transistor is turned on is a high level.
  • the low level maintaining module 30 includes: the first maintaining unit 31 is configured to maintain the signal output end and/or the control end Q of the driving module 20 at a low level when the first maintaining enable terminal P1 obtains an active level;
  • the maintaining unit 32 is configured to maintain the signal output terminal and/or the control terminal Q of the driving module 20 at a low level when the second sustaining enable terminal P2 obtains an active level.
  • the second maintaining unit 32 may include a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11.
  • the control electrode of the ninth transistor T9 is connected to the second electrode of the tenth transistor T10
  • the first electrode of the ninth transistor T9 is connected to the control electrode of the tenth transistor T10
  • the second electrode of the ninth transistor T9 is used for connection to The low level terminal V SS
  • the first pole of the tenth transistor T10 is connected to the control terminal Q of the driving module 20
  • the second pole of the tenth transistor T10 is connected to the first pole of the eleventh transistor T11, and the control of the tenth transistor T10
  • the second sustain transistor P2 the control electrode of the eleventh transistor T11 is connected to the control electrode of the tenth transistor T10, and the first electrode of the eleventh transistor T11 is connected to the signal output terminal of the shift register unit, the eleventh The second pole of transistor T11 is used to connect to the low level terminal Vss .
  • each of the above modules only schematically illustrates the shift register unit by way of example, and each module can adopt the existing technical solutions. Therefore, some details are not described in detail in the above modules, which are common in the art.
  • the technician can implement the connection between the modules of the shift register unit according to the existing technical solutions.
  • the threshold voltage sensing module 40 has a sensing end connected to the first sustaining enable terminal P1 and a signal output terminal connected to the second sustaining enable terminal P2.
  • the threshold voltage sensing module 40 is configured to detect the threshold drift according to the sensing input thereof.
  • the voltage control has its signal output providing an active level to the second sustain enable P2.
  • the threshold voltage sensing module 40 since the threshold voltage sensing module 40 is connected between the first maintaining unit 31 and the second maintaining unit 32, even when the first sustaining terminal P1 corresponds to the transistor in the first maintaining unit 31 When the threshold drift voltage is too large, under the sensing of the threshold voltage sensing module 40, and controlling its signal output terminal to provide an active level to the second sustain enable terminal P2, so that the second maintaining unit 32 starts to work, thereby also achieving shifting.
  • the low level of the bit register unit is maintained.
  • the threshold voltage sensing module 40 includes a twelfth transistor T12 and a second capacitor C2.
  • the control of the twelfth transistor T12 is extremely the sensing end of the threshold voltage sensing module 40, the second electrode of the twelfth transistor T12 is used to connect to the low level terminal V SS , and the first pole of the twelfth transistor T12 is connected.
  • the first end of the second capacitor C2 forms a signal output end of the threshold voltage sensing module 40, and the second end of the second capacitor C2 is used to input the first clock signal V A .
  • each input signal preferentially satisfies the following relationship: a high level of the first pulse input signal V I1 is one half ahead of the first clock signal V A and a high level ratio of the second pulse input signal V I2
  • the first clock signal V A is delayed by half a clock cycle.
  • the high level (high potential) of each clock signal or pulse signal is represented by V H
  • the low level (low potential) of each clock signal or pulse signal is represented by V L .
  • the working process of the shift register unit in this embodiment is divided into two phases: a working phase and a low-level sustaining phase. The working process of the shift register unit in this embodiment will be described in detail below with reference to FIG. 1 and FIG.
  • the shift register unit of the current stage is in the strobing phase, and the pull-up and pull-down process of the output signal OUT of the output terminal of the shift register unit of the present stage is completed, and this stage is the working phase of the shift register unit.
  • the first clock signal V A and the second pulse signal V I2 are both low level V L , and the first pulse signal V I1 rises from a low level to a high level V H .
  • the first transistor T1 Turning on, the second transistor T2 is turned on.
  • the first pulse signal V I1 charges the control terminal Q through the turned-on first transistor T1.
  • V TH1 is the threshold voltage of the first transistor T1.
  • the signal output terminal OUT is discharged to the low level V L through the turned-on second transistor T2.
  • the time t2 is reached.
  • the second pulse signal V I2 is kept at a low level
  • the first pulse signal V I1 also falls to a low level
  • the first clock signal V A rises from a low level to a high level
  • the first The transistor T1, the third transistor T3, and the fourth transistor T4 are turned off. Therefore, the control terminal Q is in a floating state
  • the first clock signal V A charges the signal output terminal through the second transistor T2 that is turned on
  • the potential of the control terminal Q also rises rapidly as the potential of the signal output terminal rises.
  • bootstrap As the Q potential of the control terminal rises, the charging speed of the signal output terminal OUT is accelerated, so that the potential of the output signal V OUT can quickly rise to a high level V H .
  • the first clock signal V A falls from a high level to a low level, and the second pulse signal V I2 also rises from a low level to a high level.
  • the third transistor T3 and the fourth transistor T4 lead Then, the potential of the signal output terminal OUT and the drive control terminal Q is pulled down by V L .
  • the second transistor T2 is still turned on, and can serve as an auxiliary discharge path of the signal output terminal. Therefore, the output signal V OUT is fast. Pull down to low level V L .
  • the sixth transistor T6 is turned on, and the potential of the first sustaining enable terminal P1 is pulled down to a low level, which can make the seventh transistor T7 And the eighth transistor T8 is substantially in an off state, thereby ensuring that the bootstrap process of the control terminal Q and the charging process of the signal output terminal OUT are not affected.
  • the shift register unit completely transmits a high level pulse of the first clock signal V A to the signal output terminal OUT, and the operation phase of the shift register unit ends.
  • the shift register unit of this stage In the low-level sustain phase, after the potential of the signal output terminal OUT is pulled down to the low level V L , the shift register unit of this stage enters the non-strobe state.
  • the potential of the output signal V OUT at the signal output must be maintained at a low level V L to prevent the switching transistor in the display pixel connected to the signal output terminal from being erroneously turned on, resulting in an image information writing error. This process is a low level maintenance phase. .
  • the potentials of the first pulse signal V I1 and the second pulse signal V I2 are at a low level V L , and the potential of the control terminal Q is also maintained at a low level, so that the first transistor T1 and the second transistor T2 is turned off, and the potential of the signal output terminal OUT should also be kept at a low level V L .
  • the second transistor T2 is controlled (e.g., gate) of the first pole and a larger parasitic capacitance between C GD2 (e.g. the drain), when the first clock signal transitions from the low level V A V L When it changes to the high level V H , the potential of the control terminal Q also rises. This phenomenon is called the clock feedthrough effect.
  • This embodiment employs the low level sustaining module 30 to suppress the clock feedthrough effect and eliminate the noise voltage of the signal output terminal OUT.
  • the first maintaining unit 31 starts to operate, and maintains the low-level potential of the control terminal Q and the signal output terminal OUT, specifically: when the voltage of the control terminal Q drops from a high level to a low level
  • the sixth transistor T6 is turned off, and the high level provided by the high level terminal turns on the fifth transistor T5 and charges the first sustaining enable terminal P1 to a high level, so that the seventh transistor T7 and the eighth transistor T8 lead
  • the control terminal Q and the signal output terminal OUT are respectively coupled to the low-level terminal V SS , so that the noise charge on the control terminal Q and the signal output terminal OUT can be released in time to achieve the purpose of maintaining the low level.
  • the seventh transistor T7 and the eighth transistor T8 for low level maintenance are under DC stress during the entire low level sustaining phase, and the first sustaining unit 31 will be the seventh after the circuit is operated for a long time. A severe drift of the threshold voltage of transistor T7 and/or eighth transistor T8 fails, resulting in an overall circuit output error.
  • the second maintaining unit 32 and the threshold voltage sensing module 40 are added to the shift register unit disclosed in the embodiment.
  • the threshold voltage sensing module 40 can sense the threshold voltage drift of the seventh transistor T7 and the eighth transistor T8 in the first maintaining unit 31 through the first sustaining enable terminal P1, and control the second maintaining unit according to the magnitude of the induced threshold voltage drift. 32 is on. Therefore, even if a severe threshold voltage shift occurs in the seventh transistor T7 and the eighth transistor T8, the second sustain unit 32 can continue to maintain the low level of the control terminal Q and the signal output terminal OUT.
  • the control electrode of the twelfth transistor T12 is connected to the first sustain enable terminal P1, and the control terminals of the seventh transistor T7 and the eighth transistor T8 are also connected to the first sustain enable terminal P1, and the three transistors are The second pole is simultaneously connected to the low level terminal V SS . Therefore, it can be considered that the twelfth transistor T12 has approximately the same threshold voltage shift amount as the transistor T7 and the transistor T8.
  • the second sustain enable terminal P2 is due to the coupling of the second capacitor C2.
  • the potential is rapidly coupled to a high level, and the magnitude of the coupling voltage ⁇ V C2 can be expressed as:
  • C 2 is the capacitance value of the second capacitor C2
  • C P2 is the total capacitance of the first low level maintaining control terminal P2
  • V H and V L are the high level and low level voltage values of the clock, respectively.
  • the twelfth transistor T12 since the twelfth transistor T12 is in an on state, there is a current path from the second sustain enable terminal P2 to the V SS terminal, and thus the high level of the second sustain enable terminal P2 gradually decreases with time.
  • the threshold voltage VTHM of the seventh transistor T7, the eighth transistor T8, and the twelfth transistor T12 is small, so the high level of the second sustain enable terminal P2 is affected by the twelfth transistor. T12 is quickly pulled down to V L , at which time the second sustaining end P2 is not sufficient to turn the second sustain unit 32 on.
  • the threshold voltage VTHM of the seventh transistor T7, the eighth transistor T8, and the twelfth transistor T12 starts to drift.
  • the conduction capability decreases as the threshold voltage V THM increases, so when the potential of the second sustain enable terminal P2 is coupled to the high level, the high-level falling speed gradually becomes slower. .
  • FIG. 3 is a schematic diagram of the signal waveform of the second sustain enable terminal P2 changing with the drift of V THM .
  • Figure 3 shows that as VTHM increases, the signal waveform of the second sustain enable terminal P2 will gradually converge toward a square pulse, as indicated by the dashed arrow in FIG. This change causes the second sustain unit 32 to be gradually turned on, thereby achieving the effect of continuing to maintain the low level of the control terminal Q and the signal output terminal OUT.
  • the signal of the second sustain enable terminal P2 is at a high level, the tenth transistor T10 and the eleventh transistor T11 are turned on, and the potentials of the control terminal Q and the signal output terminal OUT are pulled down to a low level V L .
  • the ninth transistor T9 functions to pull down the potential of the second sustain enable terminal P2 to V L when the output signal V OUT is at a high level, thereby turning off the tenth transistor T10 and the eleventh transistor T11. Avoiding the leakage of these two transistors affects the bootstrap of the control terminal Q in the working phase of the shift register unit and the charging of the signal output terminal OUT.
  • the threshold voltage sensing module 40 controls the opening of the second maintaining unit 32 by sensing the threshold voltage drift of the transistors in the first maintaining unit 31, and can effectively maintain the levels of the control terminal Q and the signal output terminal OUT. Even when the threshold drift of the low-level sustain transistor in the first sustain unit 31 is large, the circuit can operate normally, thereby enabling the low-level sustaining module to withstand a large threshold voltage drift, which in turn can extend the operational life of the circuit. .
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the first maintaining unit 31 of the embodiment includes: a third capacitor C3, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8.
  • the first end of the third capacitor C3 is used to input the first clock signal V A , the second end of the third capacitor C3 is connected to the first pole of the sixth transistor T6, and the control pole of the sixth transistor T6 is connected to the seventh
  • the first pole of the transistor T7, the second pole of the sixth transistor T6 is for connecting to the low-level terminal V SS ;
  • the first pole of the seventh transistor T7 is connected to the control terminal Q of the driving module 20;
  • the second pole of the seventh transistor T7 is used to connect to the low-level terminal V SS ;
  • the eighth transistor T8 One pole is connected to the signal output terminal of the shift register unit, the gate of the eighth transistor T8 is connected to the gate of the seventh transistor T7, and the second pole of the eighth transistor T8 is used to be connected to the low-level terminal V SS .
  • FIG. 5 is a timing chart of the operation of the shift register unit of the embodiment.
  • the operation of the shift register unit in this embodiment is the same as that of the circuit described in the first embodiment.
  • the difference is that the signal waveform of the first sustain control terminal P1 is a pulse signal supplied from the first clock signal V A during the low-level sustain phase in which the shift register unit operates.
  • An advantage of the shift register unit in this embodiment is that the shift register unit in this embodiment does not require an additional high level terminal, thereby reducing the number of signal lines required by the circuit. Further, in the first sustaining unit 31, the seventh transistor T7 and the eighth transistor T8 are driven by the pulse stress, and therefore, the threshold voltage drift speed is slower, and the operating life of the shift register unit in the present embodiment is longer.
  • the low level maintenance module 30 may further include a plurality of cascaded maintaining units 39, each of which is configured to drive the module 20 when its sustaining end obtains an active level.
  • the signal output and/or control terminal Q is maintained at a low level.
  • Each of the maintaining units 39 includes a threshold voltage sensing module 40 connected in series, and the sensing end of the threshold voltage sensing module 40 is connected to the sustaining end of the upper level maintaining unit, and the signal output end of the threshold voltage sensing module 40 is connected to the next stage to maintain
  • the threshold voltage sensing module 40 is configured to control the signal output terminal to provide an active level to the sustain enable terminal of the first stage sustaining unit according to the threshold drift voltage sensed by the sensing input terminal.
  • the maintaining unit 39 and the threshold voltage sensing module 40 may adopt the circuit configuration of any of the above embodiments.
  • the advantage of the shift register unit in this embodiment is that each threshold voltage sensing module 40 can sense the threshold voltage drift of the upper stage maintaining unit 39, and control the opening of the next stage maintaining unit according to the sensed threshold voltage drift amount. Therefore, a plurality of maintenance units can operate continuously.
  • the present embodiment employs a multi-stage sustaining unit to maintain a low level of maintenance, which can make the operating life of the circuit longer.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • FIG. 7 is a structural diagram of a shift register disclosed in this embodiment.
  • the shift register includes: a first clock line CK 1 , a second clock line CK 2 , an enable signal line V ST , and a total common ground line V SSL , and a multi-stage cascade according to any one of the above embodiments.
  • a disclosed shift register unit includes: a first clock line CK 1 , a second clock line CK 2 , an enable signal line V ST , and a total common ground line V SSL , and a multi-stage cascade according to any one of the above embodiments.
  • the first clock line CK 1 and the second clock line CK 2 are two-phase non-overlapping clock signals for the shift register.
  • the enable signal line V ST is coupled to the first pulse signal input of the first stage shift register unit.
  • V SSL common ground terminal is coupled to the low level V SS each stage shift register unit, a low level signal V L for each stage of the shift register unit.
  • the first clock line CK 1 provides the first clock signal V A for the odd-numbered (or even-numbered) shift register unit
  • the second clock line CK 2 is provided for the even-numbered (or odd-numbered) shift register unit.
  • the first clock signal V A a signal output end of the kth stage shift register unit of the shift register is coupled to the first pulse signal input end of the k+1th stage shift register unit and the second pulse signal input end of the k-1th stage shift register unit , k is a positive integer greater than one.
  • FIG. 8 is a timing diagram of an operation of the shift register disclosed in this embodiment.
  • the signal output ends of the first to Nth stage shift register units are respectively coupled to the N gate scan lines on the panel, and the high level of the clock signals transmitted by the first clock line CK 1 and the second clock line CK 2 alternates Upon arrival, the gate drive signals V G[1] to V G[N] sequentially output high-level pulses.
  • the threshold voltage sensing module senses the threshold voltage drift of the previous sustaining unit, and controls the opening of the next sustaining unit according to the induced threshold voltage drift, thereby enabling the low level maintaining module to withstand a large threshold voltage drift.
  • the working life of the circuit can be extended.
  • the circuit is simple and the number of signal lines is small.
  • the shift register provided in this embodiment can make the low level sustain circuit work stably without adding an additional clock.
  • This embodiment also discloses a display. As shown in Figure 9, it includes:
  • the display panel 100 includes a two-dimensional pixel array composed of a plurality of two-dimensional pixels, and a plurality of gate scan lines and a second direction (for example, a vertical direction) in a first direction (for example, a lateral direction) connected to each pixel. Multiple data lines. The same row of pixels in the pixel array are connected to the same gate scan line, and the same column of pixels in the pixel array are connected to the same data line.
  • the display panel 100 may be a liquid crystal display panel, an organic light emitting display panel, an electronic paper display panel, etc., and the corresponding display device may be a liquid crystal display, an organic light emitting display, or an electronic paper. Display, etc.
  • the gate driving circuit 200, the gate scanning signal output terminal of the gate driving unit circuit in the gate driving circuit 200 is coupled to the corresponding gate scanning line in the display panel 100 for progressive scanning of the pixel array, the gate The driving circuit 200 may be connected to the display panel 100 by soldering or integrated in the display panel 100.
  • the gate driving circuit 200 employs the shift register provided in the above embodiment.
  • the gate driving circuit 200 may be disposed on one side of the display panel 100; in a preferred embodiment, a pair of gate driving circuits 200 are disposed on both sides of the display panel 100.
  • the data driving circuit 400 is configured to generate an image data signal and output it to a data line corresponding thereto in the display panel 100, and transmit the data to the corresponding pixel unit through the data line to realize image grayscale.
  • the timing generation circuit 300 is configured to generate various control signals required by the gate driving circuit 200.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • the embodiment of the present invention discloses a voltage regulating circuit for adjusting a power supply voltage outputted to a second device circuit according to threshold voltage information of the first device circuit.
  • the voltage regulating circuit includes: a coupling capacitor C X and sense transistor T X .
  • the sensing transistor T X is controlled by the sensing terminal INx of the voltage regulating circuit for sensing the threshold voltage drift of the transistor to be sensed in the first device circuit; the second pole of the sensing transistor T X is connected to the low-level terminal V SS The signal output terminal OUTx of the first extreme voltage regulating circuit of the sensing transistor T X is used to supply a supply voltage to the second device.
  • the first end of the coupling capacitor C X is used to input the clock signal V X , and the second end of the coupling capacitor C X is connected to the first pole of the sensing transistor T X .
  • the sense transistor T X adjusts its conduction level according to the sensed threshold drift voltage to adjust the supply voltage output to the second device circuit.
  • the voltage regulating circuit disclosed in this embodiment may be adapted to: when the voltage of the first device circuit is sensed to reach a certain threshold, the voltage regulating circuit can control the supply voltage to/from the second device circuit.
  • the voltage adjustment circuit can also control the magnitude of the supply voltage supplied to the second device circuit according to the magnitude of the sensed voltage.

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Abstract

提供一种移位寄存器及其单元，其中，低电平维持模块（30）包括第一维持单元（31）和第二维持单元（32），分别用于在获得有效电平时将驱动模块（20）的信号输出端和/或控制端（Q）维持在低电平。在第一维持单元（31）和第二维持单元（32）之间连接有阈值电压感应模块（40），阈值电压感应模块（40）根据感应到第一维持单元（31）的阈值漂移电压控制其信号输出端向第二维持使能端（P2）提供有效电平。从而能够提高低电平维持模块（30）所能忍受的阈值电压漂移，继而可以延长电路的工作寿命。还公开了一种显示器和一种电压调节电路。

Description

移位寄存器及其单元和一种显示装置 技术领域
本发明涉及电子电路领域，具体涉及到一种电压调节电路、移位寄存器及其单元和一种显示装置。
背景技术
近年来，集成显示驱动电路逐渐成为平板显示技术的研究热点。所谓集成显示驱动电路是指将栅极驱动电路和数据驱动电路等外围电路以薄膜晶体管(TFT)的形式与像素TFT一起制作于显示面板上，从而减少外围驱动芯片的数量及其压封程序、降低成本，此外，还能使得显示器外围更加纤薄，使显示器模组更加紧凑，机械和电学可靠性得以增强。
在显示器的驱动电路中，移位寄存器单元是栅极驱动电路非常重要的单元模块。在移位寄存器单元的设计中，通常需要一些低电平维持电路，来保证与行扫描线相连的信号输出端不会处于浮空状态，并且消除由于时钟馈通和电容耦合导致的低电平噪声。可是，在低电平维持电路中，那些用于低电平维持的晶体管通常会由于受到较长时间的电压应力而发生阈值电压漂移，这些晶体管严重的退化会导致电路在长时间工作后失效。尤其是对于基于非晶硅TFT技术设计的移位寄存器单元而言，低电平维持晶体管的阈值电压漂移将更加严重，往往成为影响电路寿命的关键。
为了得到高可靠的移位寄存器单元，现有的一些设计中，通常采用降低电压应力的大小、脉冲电压偏置、减小电压的占空比等方式来减小低电平维持晶体管的阈值电压漂移，延长电路的工作寿命。但是，在大、中尺寸面板显示应用中，驱动电路需要在更长时间下处于工作模式，客观上对电路的寿命提出了更加苛刻的要求。因此，如何有效的延长电路的工作时间，提高移位寄存器的工作寿命，是一个极具研究价值的问题。
发明内容
本申请提供一种电压调节电路、移位寄存器及其单元和一种显示装置，以实现根据前一个维持单元中阈值电压的漂移情况，将后一个维持单元开启，从而延长电路的工作时间。
根据第一方面，一种实施例中提供一种移位寄存器，包括至少一个移位寄存器单元，移位寄存器单元包括：驱动模块，用于通过其控制端 的开关状态切换，将第一时钟信号传送到移位寄存器单元的信号输出端，从而输出扫描信号；输入模块，用于控制驱动模块的控制端切换开关状态；低电平维持模块，包括：第一维持单元用于在第一维持使能端获得有效电平时将驱动模块的信号输出端和/或控制端维持在低电平；第二维持单元，用于在第二维持使能端获得有效电平时将驱动模块的信号输出端和/或控制端维持在低电平；移位寄存器单元还包括：阈值电压感应模块，其感应端连接至第一维持使能端，其信号输出端连接至第二维持使能端；阈值电压感应模块用于根据其感应输入端感应到的阈值漂移电压控制其信号输出端向第二维持使能端提供有效电平。
根据第二方面，一种实施例中提供一种显示器，包括由多个像素构成的二维像素阵列，以及与阵列中每个像素相连的第一方向的多条数据线和第二方向的多条栅极扫描线；数据驱动电路，为数据线提供数据信号；栅极驱动电路，为栅极扫描线提供栅极驱动信号；其中，栅极驱动电路采用上述移位寄存器构成。
根据第三方面，一种实施例中提供一种电压调节电路，用于根据第一设备电路的阈值电压信息调节输出给第二设备电路的供电电压，电压调节电路包括：耦合电容和感应晶体管；感应晶体管的控制极为电压调节电路的感应端，用于感应第一设备电路中待感应晶体管的阈值电压漂移；感应晶体管的第二极用于连接至低电平端；感应晶体管的第一极为电压调节电路的信号输出端，用于向第二设备提供供电电压；耦合电容的第一端用于输入时钟信号，耦合电容的第二端连接至感应晶体管的第一极；感应晶体管根据感应到的阈值漂移电压调整其导通程度，以调整输出给第二设备电路的供电电压。
依据上述实施例提供的移位寄存器，通过阈值电压感应模块感应第一维持使能端的阈值电压漂移，并依据感应的阈值电压调整输出给第二维持使能端的供电电压，从而能够提高低电平维持模块所能忍受的阈值电压漂移，继而可以延长电路的工作寿命。
依据本发明提供的电压调节电路，感应晶体管根据感应到第一设备电路的阈值漂移电压调整其导通程度，以调整输出给第二设备电路的供电电压，从而改善了第一设备电路和第二设备电路之间的协同工作模式。
附图说明
图1是本申请实施例一的一种移位寄存器单元的电路结构图；
图2是本申请实施例一的移位寄存器单元的一种工作时序图；
图3是本申请实施例一第二维持使能端P2的信号波形示意图；
图4是本申请实施例二的一种移位寄存器单元的电路结构图；
图5是本申请实施例二的移位寄存器单元的一种工作时序图；
图6是本申请实施例二的另一种移位寄存器单元的电路结构示意图；
图7是本申请实施例三的一种移位寄存器的结构图；
图8是本申请实施例三移位寄存器的一种工作时序图；
图9是本申请实施例公开的一种显示器结构示意图；
图10是本申请实施例公开的一种电压调节电路结构示意图。
具体实施方式
下面通过具体实施方式结合附图对本发明作进一步详细说明。
首先对一些术语进行说明：
本申请中的开关管为晶体管。
本申请中的晶体管可以为双极型晶体管或场效应晶体管。当晶体管为双极型晶体管时，其控制极是指双极型晶体管的基极，第一极可以为双极型晶体管的集电极或发射极，对应的第二极可以为双极型晶体管的发射极或集电极；当晶体管为场效应晶体管时，其控制极是指场效应晶体管的栅极，第一极可以为场效应晶体管的漏极或源极，对应的第二极可以为场效应晶体管的源极或漏极。显示器中的晶体管通常为一种场效应晶体管：薄膜晶体管(TFT)。下面以晶体管为场效应晶体管为例对本申请做详细的说明，在其它实施例中晶体管也可以是双极型晶体管。
实施例一：
请参考图1，为本实施例公开的一种移位寄存器单元的电路结构图。该移位寄存器单元包括：驱动模块20、输入模块10、低电平维持模块30和阈值电压感应模块40。其中，
驱动模块20，用于通过其控制端Q的开关状态切换，将第一时钟信号VA传送到移位寄存器单元的信号输出端OUT，从而输出扫描信号。在一种实施例中，控制端Q的开关状态可以通过高低电平来表征，例如高电平时，控制端Q为开启状态，低电平时，控制端Q为关闭状态；在另一种实施例中，还可以根据晶体管的类型置换开关状态。在具体实施 例中，驱动模块20可以包括：第二晶体管T2和第一电容C1。其中，第二晶体管T2的控制极连接至第一电容C1的第一端形成驱动模块20的控制端Q，第二晶体管T2的第二极连接至第一电容C1的第二端形成移位寄存器单元的信号输出端，第二晶体管T2的第一极用于输入第一时钟信号VA。在其它实施例中，也可以是其它现有的或者将来出现的驱动方式。
输入模块10，用于控制驱动模块20的控制端Q切换开关状态。在具体实施例中，输入模块10包括：第一晶体管T1、第三晶体管T3和第四晶体管T4。其中，第一晶体管T1的控制极连接至其第一极，用于输入第一脉冲信号VI1；第一晶体管T1的第二极连接至驱动模块20的控制端Q；第四晶体管T4的控制极和第三晶体管T3的控制极用于输入第二脉冲信号VI2；第四晶体管T4的第一极连接至驱动模块20的控制端Q，第四晶体管T4的第二极用于连接至低电平端；第三晶体管T3的第一极连接至移位寄存器单元的信号输出端，第三晶体管T3的第二极用于连接至低电平端。在其它实施例中，也可以是其它现有的或者将来出现的输入方式。在本实施例中，第一脉冲输入信号VI1的有效电平到来时间比第一时钟信号VA有效电平到来时间超前半个时钟周期，第二脉冲输入信号VI2的有效电平到来时间比第一时钟信号VA有效电平到来时间滞后半个时钟周期。需要说明的是，当晶体管为N型晶体管时，其控制极对应的导通的有效电平为高电平，反之，当晶体管为P型晶体管时，其控制极对应的导通的有效电平为低电平。本实施例中，以N型晶体管为例进行说明，相应地，晶体管导通的有效电平为高电平。
低电平维持模块30，包括：第一维持单元31用于在第一维持使能端P1获得有效电平时将驱动模块20的信号输出端和/或控制端Q维持在低电平；第二维持单元32，用于在第二维持使能端P2获得有效电平时将驱动模块20的信号输出端和/或控制端Q维持在低电平。
在具体实施例中，例如，第一维持单元31可以包括：第五晶体管T5、第六晶体管T6、第七晶体管T7和第八晶体管T8。其中，第五晶体管T5的控制极连接至第五晶体管T5的第一极，用于连接至高电平端，第五晶体管T5的第二极连接至第六晶体管T6的第一极；第六晶体管T6的控制极连接至第七晶体管T7的第一极，第六晶体管T6的第二极用于连接至低电平端VSS；第七晶体管T7的第一极连接至驱动模块20 的控制端Q；第七晶体管T7的控制极连接至第六晶体管T6的第一极，第七晶体管T7的控制极为第一维持使能端P1；第七晶体管T7的第二极用于连接至低电平端VSS；第八晶体管T8的第一极连接至移位寄存器单元的信号输出端，第八晶体管T8的控制极连接至第七晶体管T7的控制极，第八晶体管T8的第二极用于连接至低电平端VSS。在其它实施例中，也可以是其它现有的或者将来出现的维持方式。
在具体实施例中，例如，第二维持单元32可以包括：第九晶体管T9、第十晶体管T10和第十一晶体管T11。其中，第九晶体管T9的控制极连接至第十晶体管T10的第二极，第九晶体管T9的第一极连接至第十晶体管T10的控制极，第九晶体管T9的第二极用于连接至低电平端VSS；第十晶体管T10的第一极连接至驱动模块20的控制端Q，第十晶体管T10的第二极连接至第十一晶体管T11的第一极，第十晶体管T10的控制极为第二维持使能端P2；第十一晶体管T11的控制极连接至第十晶体管T10的控制极，第十一晶体管T11的第一极连接至移位寄存器单元的信号输出端，第十一晶体管T11的第二极用于连接至低电平端VSS。同样地，在其它实施例中，也可以是其它现有的或者将来出现的维持方式。需要说明的是，在其它实施例中，第一维持单元31和第二维持单元32也可以采用相同的电路。
需要说明的是，上述各个模块只是以示例的方式原理性地阐述移位寄存器单元，各模块均可采用现有的技术方案，因此，上述各模块中，有些细节并未详细描述，本领域普通技术人员依据现有的技术方案能够实现移位寄存器单元各模块之间的连接。
阈值电压感应模块40，其感应端连接至第一维持使能端P1，其信号输出端连接至第二维持使能端P2；阈值电压感应模块40用于根据其感应输入端感应到的阈值漂移电压控制其信号输出端向第二维持使能端P2提供有效电平。在本实施例中，由于在第一维持单元31和第二维持单元32之间连接阈值电压感应模块40，因此，即使当第一维持单元31中第一维持使能端P1所对应的晶体管的阈值漂移电压过大时，在阈值电压感应模块40的感应下，并控制其信号输出端向第二维持使能端P2提供有效电平，使得第二维持单元32开始工作，从而也能实现移位寄存器单元的低电平维持工作。
为便于本领域技术人员理解，请参考图1，在具体实施例中，阈值 电压感应模块40包括：第十二晶体管T12和第二电容C2。其中，第十二晶体管T12的控制极为所述阈值电压感应模块40的感应端，第十二晶体管T12的第二极用于连接至低电平端VSS，第十二晶体管T12的第一极连接至第二电容C2的第一端形成所述阈值电压感应模块40的信号输出端，第二电容C2的第二端用于输入第一时钟信号VA。
请参考图2，为本实施例中移位寄存器单元工作时序图。在本实施例中，各个输入信号优先满足如下关系：第一脉冲输入信号VI1的高电平比第一时钟信号VA超前半个时钟周期，第二脉冲输入信号VI2的高电平比第一时钟信号VA滞后半个时钟周期。为方便后续的描述，本实施例中，以VH来表征各时钟信号或者脉冲信号的高电平(高电位)，以VL来表征各时钟信号或者脉冲信号的低电平(低电位)本实施例中移位寄存器单元的工作过程分为两个阶段：工作阶段和低电平维持阶段，下面结合图1和图2，详细介绍本实施例中移位寄存器单元的工作过程。
在工作阶段，本级移位寄存器单元处于选通阶段，完成本级移位寄存器单元信号输出端OUT输出信号VOUT的上拉和下拉过程，该阶段为移位寄存器单元的工作阶段。
在t1时刻，第一时钟信号VA和第二脉冲信号VI2均为低电平VL，第一脉冲信号VI1由低电平上升为高电平VH，此时，第一晶体管T1导通，第二晶体管T2导通。第一脉冲信号VI1通过导通的第一晶体管T1对控制端Q充电。当控制端Q电位上升到VH-VTH1时，第一晶体管T1关断，其中，VTH1为第一晶体管T1的阈值电压。在这个过程中，信号输出端OUT通过导通的第二晶体管T2放电到低电平VL。
驱动控制端Q充电结束后，到达t2时刻。在t2时刻，第二脉冲信号VI2保持为低电平，第一脉冲信号VI1也下降为低电平，第一时钟信号VA由低电平上升为高电平，此时，第一晶体管T1、第三晶体管T3和第四晶体管T4关断。于是，控制端Q处于浮空状态，第一时钟信号VA通过导通的第二晶体管T2对信号输出端充电，控制端Q的电位也随着信号输出端电位的上升而快速上升，该现象被称为自举。随着控制端Q电位的上升，加快了信号输出端OUT的充电速度，使得输出信号VOUT的电位得以快速上升到高电平VH。
在t3时刻，第一时钟信号VA由高电平下降为低电平，第二脉冲信号VI2也由低电平上升为高电平，此时，第三晶体管T3和第四晶体管 T4导通，于是，将信号输出端OUT以及驱动控制端Q的电位下拉VL。此过程中，在控制端Q的电压下降到第二晶体管T2的阈值电压VTH2之前，第二晶体管T2仍然导通，可以作为信号输出端的一个辅助的放电通路，因此，输出信号VOUT被快速下拉至低电平VL。
需要注意的是，在控制端Q电压为高电平期间，第六晶体管T6导通，并将第一维持使能端P1的电位下拉至低电平，该低电平可以使第七晶体管T7和第八晶体管T8基本处于关断状态，从而，保证了控制端Q的自举过程与信号输出端OUT的充电过程不受影响。
至此，移位寄存器单元将第一时钟信号VA的一个高电平脉冲完全传输到了信号输出端OUT，至此，移位寄存器单元的工作阶段结束。
在低电平维持阶段，信号输出端OUT的电位下拉至低电平VL之后，本级移位寄存器单元进入非选通状态。信号输出端的输出信号VOUT的电位必须维持在低电平VL，以避免与信号输出端相连的显示器像素中的开关晶体管误导通，导致图像信息写入错误，此过程为低电平维持阶段。
在工作阶段结束后，第一脉冲信号VI1和第二脉冲信号VI2的电位为低电平VL，控制端Q的电位也维持为低电平，于是，第一晶体管T1与第二晶体管T2关断，信号输出端OUT的电位也应保持为低电平VL。但是，由于在第二晶体管T2的控制极(例如栅极)和第一极(例如漏极)之间有较大的寄生电容CGD2，当第一时钟信号VA由低电平VL跳变到高电平VH时，控制端Q的电位也会随之上升，该现象称为时钟馈通效应。当控制端Q的电位上升大于第二晶体管T2的阈值电压时，会导致第二晶体管T2开启，第一时钟信号VA通过第二晶体管T2对信号输出端被不期望地充电，导致信号输出端产生较大的噪声电压。此外，在实际的显示器中，面板上的信号线之间存在寄生电容耦合效应，也会使得移位寄存器单元的输出信号产生噪声电压。因此，在移位寄存器单元的非选通状态，必须采取一定的措施来保证输出端的输出信号VOUT为低电平VL。
本实施例采用低电平维持模块30来抑制时钟馈通效应，并且消除信号输出端OUT的噪声电压。在低电平维持阶段，首先第一维持单元31开始工作，并对控制端Q和信号输出端OUT的低电平电位进行维持，具体的：当控制端Q电压由高电平下降为低电平后，第六晶体管T6关断，高电平端提供的高电平导通第五晶体管T5并将第一维持使能端P1 充电至高电平，于是，第七晶体管T7和第八晶体管T8导通，并分别将控制端Q和信号输出端OUT耦合至低电平端VSS，从而能够将控制端Q和信号输出端OUT上的噪声电荷及时的释放，达到维持低电平的目的。需要注意的是，用于低电平维持的第七晶体管T7和第八晶体管T8在整个低电平维持阶段都处于直流应力下，在电路长时间工作后，第一维持单元31会因为第七晶体管T7和/或第八晶体管T8的阈值电压的严重漂移而失效，导致整个电路输出错误。
为解决第一维持单元31因阈值电压的严重漂移而导致的失效，本实施例公开的移位寄存器单元中，增加了第二维持单元32以及阈值电压感应模块40。阈值电压感应模块40可以通过第一维持使能端P1感应第一维持单元31中第七晶体管T7和第八晶体管T8的阈值电压漂移，并根据感应的阈值电压漂移的大小，控制第二维持单元32开启。因此，即使第七晶体管T7和第八晶体管T8发生严重的阈值电压漂移，第二维持单元32仍然能够继续对控制端Q与信号输出端OUT的低电平进行维持。
具体的，第十二晶体管T12的控制极连接第一维持使能端P1，由于第七晶体管T7和第八晶体管T8的控制极亦连接于第一维持使能端P1，并且，该三个晶体管的第二极同时连接至低电平端VSS。因此，可以认为第十二晶体管T12与晶体管T7、晶体管T8具有近似相同的阈值电压漂移量。
请参照图2，在低电平维持阶段，当第一时钟信号VA由低电平上升为高电平时(例如t4时刻)，由于第二电容C2的耦合作用，第二维持使能端P2的电位被迅速耦合至高电平，耦合电压ΔVC2的大小可以表示为：
Figure PCTCN2016077395-appb-000001
其中，C2为第二电容C2的电容值，CP2为第一低电平维持控制端P2端的总的电容大小，VH与VL分别为时钟的高电平和低电平电压值。但是由于第十二晶体管T12处于开启状态，因此存在由第二维持使能端P2至VSS端的电流通路，于是，第二维持使能端P2的高电平会随着时间逐渐下降。在移位寄存器单元的工作初期，第七晶体管T7、第八晶体管T8以及第十二晶体管T12的阈值电压VTHM较小，因此第二维持使能端P2的高电平会被第十二晶体管T12迅速地下拉至VL，此时，第二维 持使能端P2并不足以将第二维持单元32开启。
但是，随着移位寄存器单元工作时间的增加，第七晶体管T7、第八晶体管T8以及第十二晶体管T12的阈值电压VTHM开始发生漂移。对于第十二晶体管T12，随着阈值电压VTHM的增大其导通能力下降，因此在当第二维持使能端P2的电位被耦合至高电平时，高电平下降的速度会逐渐变慢。
请参照图3，为第二维持使能端P2的信号波形随VTHM的漂移而变化的示意图。图3表明，随着VTHM的增加，第二维持使能端P2的信号波形会逐渐的趋向于方形脉冲，如图3中虚线箭头所示。这种变化会使得第二维持单元32逐渐的开启，从而达到继续维持控制端Q与信号输出端OUT的低电平的作用。当第二维持使能端P2的信号处于高电平时，第十晶体管T10和第十一晶体管T11导通，并将控制端Q以及信号输出端OUT的电位下拉至低电平VL。第九晶体管T9的作用，是在当输出信号VOUT为高电平时，将第二维持使能端P2的电位下拉至VL，从而将第十晶体管T10和第十一晶体管T11关断，进而避免这两个晶体管的漏电影响到移位寄存器单元的工作阶段中控制端Q的自举，以及信号输出端OUT的充电。
由上述分析可知，阈值电压感应模块40通过感应第一维持单元31中晶体管的阈值电压漂移，控制第二维持单元32的开启，可以有效地维持控制端Q以及信号输出端OUT的电平。即使当第一维持单元31中低电平维持晶体管的阈值漂移很大时，电路仍可以正常工作，从而能够使得低电平维持模块能够忍受较大的阈值电压漂移，继而可以延长电路的工作寿命。
实施例二：
请参考图4，为本实施例公开的一种移位寄存器单元的电路结构图。与上述实施例不同的是，本实施例第一维持单元31包括：包括第三电容C3、第六晶体管T6、第七晶体管T7和第八晶体管T8。其中，第三电容C3的第一端用于输入第一时钟信号VA，第三电容C3的第二端连接至第六晶体管T6的第一极；第六晶体管T6的控制极连接至第七晶体管T7的第一极，第六晶体管T6的第二极用于连接至低电平端VSS；第七晶体管T7的第一极连接至驱动模块20的控制端Q；第七晶体管T7的控制 极连接至第六晶体管T6的第一极，第七晶体管T7的控制极为第一维持使能端P1；第七晶体管T7的第二极用于连接至低电平端VSS；第八晶体管T8的第一极连接至移位寄存器单元的信号输出端，第八晶体管T8的控制极连接至第七晶体管T7的控制极，第八晶体管T8的第二极用于连接至低电平端VSS。
请参考图5，为本实施例移位寄存器单元工作时序图。本实施例中的移位寄存器单元的工作过程与实施例一中所述电路的工作过程相同。不同的是，在移位寄存器单元工作的低电平维持阶段，第一维持控制端P1的信号波形是由第一时钟信号VA提供的脉冲信号。
本实施例中移位寄存器单元的优势在于，本实施例中的移位寄存器单元不需要额外的高电平端，从而减少了电路所需要的信号线的数目。此外，在第一维持单元31中，第七晶体管T7和第八晶体管T8受到脉冲应力的驱动，因此，阈值电压漂移速度更慢，本实施例中移位寄存器单元的工作寿命更长。
在其它实施例中，请参考图6，低电平维持模块30还可以包括多个级联的维持单元39，各维持单元39用于在其维持使能端获得有效电平时将驱动模块20的信号输出端和/或控制端Q维持在低电平。各维持单元39之间包括串联的阈值电压感应模块40，阈值电压感应模块40的感应端连接至上一级维持单元的维持使能端，阈值电压感应模块40的信号输出端连接至下一级维持单元的维持使能端；阈值电压感应模块40用于根据其感应输入端感应到的阈值漂移电压控制其信号输出端向下一级维持单元的维持使能端提供有效电平。
在本实施例中，维持单元39、阈值电压感应模块40可以采用上述任意一个实施例的电路结构。本实施例中移位寄存器单元的优势在于，各阈值电压感应模块40可以感应其上一级维持单元39的阈值电压漂移，并且根据感应到的阈值电压漂移量控制下一级维持单元的开启，因此多个维持单元可以连续进行工作。和前面的实施例所述的电路相比，本实施例采用多级维持单元来协同低电平维持，可以使电路的工作寿命更长。
实施例三：
请参考图7，为本实施例公开的一种移位寄存器的结构图。
本实施中，移位寄存器包括：包括第一时钟线CK1、第二时钟线CK2、 启动信号线VST和总的公共地线VSSL，以及多级级联的如上述任意一个实施例公开的移位寄存器单元。
第一时钟线CK1和第二时钟线CK2为移位寄存器传输两相不交叠时钟信号。启动信号线VST耦合至第1级移位寄存器单元的第一脉冲信号输入端。公共地线VSSL耦合至每一级移位寄存器单元的低电平端VSS，为每一级移位寄存器单元提供低电平信号VL。
本实施例中，第一时钟线CK1为奇数级(或偶数级)移位寄存器单元提供第一时钟信号VA，第二时钟线CK2为偶数级(或奇数级)移位寄存器单元提供第一时钟信号VA。移位寄存器的第k级移位寄存器单元的信号输出端耦合至第k+1级移位寄存器单元的第一脉冲信号输入端和第k-1级移位寄存器单元的第二脉冲信号输入端，k为大于1的正整数。
请参考图8，为本实施例公开的移位寄存器的一种工作时序图。第1到第N级移位寄存器单元的信号输出端分别耦合至面板上的N条栅极扫描线，当第一时钟线CK1和第二时钟线CK2传输的时钟信号的高电平交替到来时，栅极驱动信号VG[1]～VG[N]顺次输出高电平脉冲。
综上所述，本实施例的有益之处在于：
其一，工作寿命长；
本实施例根据阈值电压感应模块感应前一个维持单元的阈值电压漂移，并且根据感应的阈值电压漂移，控制下一个维持单元的开启，从而能够使得低电平维持模块能够忍受较大的阈值电压漂移，从而可以延长电路的工作寿命。
其二，电路简单，信号线数量少。
本实施例提供的移位寄存器不需要增加附加的时钟，便可以使得低电平维持电路稳定工作。
本实施例还公开了一种显示器。如图9所示，包括：
显示面板100，显示面板100包括由多个二维像素构成的二维像素阵列，以及与每个像素相连的第一方向(例如横向)的多条栅极扫描线和第二方向(例如纵向)的多条数据线。像素阵列中的同一行像素均连接到同一条栅极扫描线，而像素阵列中的同一列像素则连接到同一条数据线。显示面板100可以是液晶显示面板、有机发光显示面板、电子纸显示面板等，而对应的显示装置可以是液晶显示器、有机发光显示器、电子纸 显示器等。
栅极驱动电路200，栅极驱动电路200中栅极驱动单元电路的栅极扫描信号输出端耦合到显示面板100中与其对应的栅极扫描线，用于对像素阵列的逐行扫描，栅极驱动电路200可以通过焊接与显示面板100相连或者集成于显示面板100内。该栅极驱动电路200采用上述实施例提供的移位寄存器。在一种具体实施例中，栅极驱动电路200可以布置在显示面板100的一侧；在优选的实施例中，采用成对的栅极驱动电路200，布置在显示面板100的两侧。
数据驱动电路400，用于产生图像数据信号，并将其输出到显示面板100中与其对应的数据线上，通过数据线传输到对应的像素单元内以实现图像灰度。
时序产生电路300，用于产生栅极驱动电路200所需的各种控制信号。
实施例四：
本实施例公开了一种电压调节电路，该电压调节电路用于根据第一设备电路的阈值电压信息调节输出给第二设备电路的供电电压，请参考图10，该电压调节电路包括：耦合电容CX和感应晶体管TX。
其中，感应晶体管TX的控制极为电压调节电路的感应端INx，用于感应第一设备电路中待感应晶体管的阈值电压漂移；感应晶体管TX的第二极用于连接至低电平端VSS；感应晶体管TX的第一极为电压调节电路的信号输出端OUTx，用于向第二设备提供供电电压。
耦合电容CX的第一端用于输入时钟信号VX，耦合电容CX的第二端连接至感应晶体管TX的第一极。
感应晶体管TX根据感应到的阈值漂移电压调整其导通程度，以调整输出给第二设备电路的供电电压。
本实施例公开的电压调节电路可以适用于：当感应到第一设备电路电压达到某一阈值时，电压调节电路可以控制向/从第二设备电路的供电电压供给/断开。当然，根据上述实施例的描述可知，电压调节电路也可以根据感应到的电压的大小，来控制向第二设备电路提供的供电电压的大小。
以上应用了具体个例对本发明进行阐述，只是用于帮助理解本发 明，并不用以限制本发明。对于本发明所属技术领域的技术人员，依据本发明的思想，还可以做出若干简单推演、变形或替换。

Claims (10)

  1. 一种移位寄存器，包括至少一个移位寄存器单元，移位寄存器单元包括：
    驱动模块(20)，用于通过其控制端(Q)的开关状态切换，将第一时钟信号(VA)传送到移位寄存器单元的信号输出端，从而输出扫描信号；
    输入模块(10)，用于控制驱动模块(20)的控制端(Q)切换开关状态；
    低电平维持模块(30)，包括：第一维持单元(31)用于在第一维持使能端(P1)获得有效电平时将驱动模块(20)的信号输出端和/或控制端(Q)维持在低电平；第二维持单元(32)，用于在第二维持使能端(P2)获得有效电平时将驱动模块(20)的信号输出端和/或控制端(Q)维持在低电平；
    其特征在于，移位寄存器单元还包括：
    阈值电压感应模块(40)，其感应端连接至第一维持使能端(P1)，其信号输出端连接至第二维持使能端(P2)；阈值电压感应模块(40)用于根据其感应输入端感应到的阈值漂移电压控制其信号输出端向第二维持使能端(P2)提供有效电平。
  2. 如权利要求1所述的移位寄存器，其特征在于，
    所述低电平维持模块(30)包括多个级联的维持单元，各维持单元用于在其维持使能端获得有效电平时将驱动模块(20)的信号输出端和/或控制端(Q)维持在低电平；
    各维持单元之间包括串联的阈值电压感应模块(40)，阈值电压感应模块(40)的感应端连接至上一级维持单元的维持使能端，阈值电压感应模块(40)的信号输出端连接至下一级维持单元的维持使能端；阈值电压感应模块(40)用于根据其感应输入端感应到的阈值漂移电压控制其信号输出端向下一级维持单元的维持使能端提供有效电平。
  3. 如权利要求1或2所述的移位寄存器，其特征在于，所述阈值电压感应模块(40)包括：第十二晶体管(T12)和第二电容(C2)；
    第十二晶体管(T12)的控制极为所述阈值电压感应模块(40)的感应端，第十二晶体管(T12)的第二极用于连接至低电平端(VSS)，第十二晶体管(T12)的第一极连接至第二电容(C2)的第一端形成所 述阈值电压感应模块(40)的信号输出端，第二电容(C2)的第二端用于输入第一时钟信号(VA)。
  4. 如权利要求1所述的移位寄存器，其特征在于，所述第一维持单元(31)包括：第五晶体管(T5)、第六晶体管(T6)、第七晶体管(T7)和第八晶体管(T8)；
    第五晶体管(T5)的控制极连接至第五晶体管(T5)的第一极，用于连接至高电平端，第五晶体管(T5)的第二极连接至第六晶体管(T6)的第一极；
    第六晶体管(T6)的控制极连接至第七晶体管(T7)的第一极，第六晶体管(T6)的第二极用于连接至低电平端(VSS)；
    第七晶体管(T7)的第一极连接至驱动模块(20)的控制端(Q)；第七晶体管(T7)的控制极连接至第六晶体管(T6)的第一极，第七晶体管(T7)的控制极为第一维持使能端(P1)；第七晶体管(T7)的第二极用于连接至低电平端(VSS)；
    第八晶体管(T8)的第一极连接至移位寄存器单元的信号输出端，第八晶体管(T8)的控制极连接至第七晶体管(T7)的控制极，第八晶体管(T8)的第二极用于连接至低电平端(VSS)。
  5. 如权利要求1所述的移位寄存器，其特征在于，所述第一维持单元(31)包括：第三电容(C3)、第六晶体管(T6)、第七晶体管(T7)和第八晶体管(T8)；
    第三电容(C3)的第一端用于输入第一时钟信号(VA)，第三电容(C3)的第二端连接至第六晶体管(T6)的第一极；
    第六晶体管(T6)的控制极连接至第七晶体管(T7)的第一极，第六晶体管(T6)的第二极用于连接至低电平端(VSS)；
    第七晶体管(T7)的第一极连接至驱动模块(20)的控制端(Q)；第七晶体管(T7)的控制极连接至第六晶体管(T6)的第一极，第七晶体管(T7)的控制极为第一维持使能端(P1)；第七晶体管(T7)的第二极用于连接至低电平端(VSS)；
    第八晶体管(T8)的第一极连接至移位寄存器单元的信号输出端，第八晶体管(T8)的控制极连接至第七晶体管(T7)的控制极，第八晶体管(T8)的第二极用于连接至低电平端(VSS)。
  6. 如权利要求1所述的移位寄存器，其特征在于，所述第二维持 单元(32)包括：第九晶体管(T9)、第十晶体管(T10)和第十一晶体管(T11)；
    第九晶体管(T9)的控制极连接至第十晶体管(T10)的第二极，第九晶体管(T9)的第一极连接至第十晶体管(T10)的控制极，第九晶体管(T9)的第二极用于连接至低电平端(VSS)；
    第十晶体管(T10)的第一极连接至驱动模块(20)的控制端(Q)，第十晶体管(T10)的第二极连接至第十一晶体管(T11)的第一极，第十晶体管(T10)的控制极为第二维持使能端(P2)；
    第十一晶体管(T11)的控制极连接至第十晶体管(T10)的控制极，第十一晶体管(T11)的第一极连接至移位寄存器单元的信号输出端，第十一晶体管(T11)的第二极用于连接至低电平端(VSS)。
  7. 如权利要求1所述的移位寄存器，其特征在于，所述驱动模块(20)包括第二晶体管(T2)和第一电容(C1)；
    第二晶体管(T2)的控制极连接至第一电容(C1)的第一端形成驱动模块(20)的控制端(Q)，第二晶体管(T2)的第二极连接至第一电容(C1)的第二端形成移位寄存器单元的信号输出端，第二晶体管(T2)的第一极用于输入第一时钟信号(VA)。
  8. 如权利要求1所述的移位寄存器，其特征在于，所述输入模块(10)包括：第一晶体管(T1)、第三晶体管(T3)和第四晶体管(T4)；
    第一晶体管(T1)的控制极连接至其第一极，用于输入第一脉冲信号(VI1)；第一晶体管(T1)的第二极连接至驱动模块(20)的控制端(Q)；
    第四晶体管(T4)的控制极和第三晶体管(T3)的控制极用于输入第二脉冲信号(VI2)；第四晶体管(T4)的第一极连接至驱动模块(20)的控制端(Q)，第四晶体管(T4)的第二极用于连接至低电平端；
    第三晶体管(T3)的第一极连接至移位寄存器单元的信号输出端，第三晶体管(T3)的第二极用于连接至低电平端；
    第一脉冲输入信号(VI1)的有效电平到来时间比第一时钟信号(VA)有效电平到来时间超前半个时钟周期，第二脉冲输入信号(VI2)的有效电平到来时间比第一时钟信号(VA)有效电平到来时间滞后半个时钟周期。
  9. 一种显示器，包括由多个像素构成的二维像素阵列，以及与阵 列中每个像素相连的第一方向的多条数据线和第二方向的多条栅极扫描线；
    数据驱动电路，为数据线提供数据信号；
    栅极驱动电路，为所述栅极扫描线提供栅极驱动信号；
    其特征在于，所述栅极驱动电路采用如权利要求1-8任意一项所述的移位寄存器构成。
  10. 一种电压调节电路，用于根据第一设备电路的阈值电压信息调节输出给第二设备电路的供电电压，其特征在于，所述电压调节电路包括：耦合电容(CX)和感应晶体管(TX)；
    感应晶体管(TX)的控制极为电压调节电路的感应端，用于感应第一设备电路中待感应晶体管的阈值电压漂移；感应晶体管(TX)的第二极用于连接至低电平端；感应晶体管(TX)的第一极为电压调节电路的信号输出端，用于向第二设备提供供电电压；
    耦合电容(CX)的第一端用于输入时钟信号(VX)，耦合电容(CX)的第二端连接至感应晶体管(TX)的第一极；
    所述感应晶体管(TX)根据感应到的阈值漂移电压调整其导通程度，以调整输出给第二设备电路的供电电压。
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