WO2020015323A1 - 移位暂存器、显示面板、以及移位暂存器的驱动方法 - Google Patents

移位暂存器、显示面板、以及移位暂存器的驱动方法 Download PDF

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Publication number
WO2020015323A1
WO2020015323A1 PCT/CN2018/124214 CN2018124214W WO2020015323A1 WO 2020015323 A1 WO2020015323 A1 WO 2020015323A1 CN 2018124214 W CN2018124214 W CN 2018124214W WO 2020015323 A1 WO2020015323 A1 WO 2020015323A1
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WIPO (PCT)
Prior art keywords
gate
switch
signal
shift register
stage
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PCT/CN2018/124214
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English (en)
French (fr)
Inventor
单剑锋
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惠科股份有限公司
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Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Priority to US17/040,149 priority Critical patent/US11114055B2/en
Publication of WO2020015323A1 publication Critical patent/WO2020015323A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling

Definitions

  • the present application relates to a display panel, and particularly to a shift register and a driving method of the shift register in a display panel.
  • the LCD panel industry has widely adopted the array driver technology.
  • Array GOA
  • the technology of traditional liquid crystal display panel depends on the source driver chip (Source IC) and gate driver chip (Gate IC) to drive, the former controls the voltage to transmit the signal, and the latter uses the transistor as a switch to control and determine the amount of light transmission.
  • Source IC source driver chip
  • Gate IC gate driver chip
  • Array substrate type driving technology is to abandon the traditional gate driving chip and replace it with the gate driving circuit structure directly on the glass substrate of the display panel. Because the gate driving circuit structure uses the exposure and development method, it is on the edge of the glass substrate.
  • the logic circuit that generates a plurality of shift registers is able to achieve the effect of reducing costs in terms of materials or manufacturing processes, and can also achieve the effect of reducing the frame of the liquid crystal display.
  • the principle of the array substrate type driving technology is developed based on the Thompson circuit. In order to achieve a smooth driving effect, it is usually at the working point. point) to pre-charge to achieve a higher voltage level, so that the subsequent signal can be coupled with the clock signal into an ideal signal waveform. Thus, when the switch of the transistor is turned on, the gate scan required by the gate line The signal was passed smoothly.
  • the present application proposes a shift register, a display panel, and a method for driving the shift register, which can assist in charging the operating point at the same time as the end of the gate-level scanning signal, thereby minimizing the time for preventing wrong charging. , Improve the tailing phenomenon, and increase the charging time.
  • An embodiment of the present application provides a shift register, which is configured as an array substrate type driving technology (Gate Driver on Array; GOA) display panel.
  • the display panel has a plurality of cascaded shift registers.
  • n is a positive integer greater than 2, and the nth
  • the shift register receives the gate signal of the previous stage to transmit the gate scanning signal Gn of this stage to the corresponding n-th gate line, wherein the operating point of the n-th shift register has Operating point voltage signal Qn.
  • the shift register includes an output circuit and a pull-down feedback circuit.
  • the output circuit is configured to receive a clock signal CKn and a gate signal of a previous stage to generate a gate scanning signal Gn to transmit to the gate line.
  • the pull-down feedback circuit is a circuit with a feedback pull-down function, and includes a first switch and a second switch.
  • the first terminal of the first switch is electrically coupled to the operating point voltage signal Qn, and the second terminal of the first switch is electrically coupled to the gate-scan signal of the subsequent stage.
  • the control terminal of the first switch receives the operating point voltage signal of the subsequent stage as a feedback signal to pull the operating point voltage Qn to a low level to the gate scanning signal of the subsequent stage.
  • the first terminal of the second switch is electrically coupled to the gate scanning signal Gn of the n-th gate line, and the second terminal of the second switch is electrically coupled to a low preset potential Vss.
  • the control terminal of the second switch receives the gate-stage scanning signal of the subsequent stage as a feedback signal to pull the gate-stage scanning signal Gn of the n-th gate line to a low level to a low preset potential Vss.
  • a shift register, a display panel, and a method for driving the shift register, using a first switch improved by a pull-down feedback circuit in the shift register can assist in charging the working point, thereby reducing the time to prevent mischarging, improving the tailing phenomenon, and increasing the charging time.
  • FIG. 1 is a schematic diagram of a display device according to a first embodiment of the present application
  • FIG. 2 is a schematic diagram of an association between a timing controller and a gate shift register according to the first embodiment of the present application
  • FIG. 4 is a waveform diagram of the levels of various signals according to the first embodiment of the present application
  • FIG. 7 is a schematic diagram of a shift register embodiment according to the second embodiment of the present application
  • FIG. 8 is a diagram of a second embodiment according to the second embodiment of the present application Schematic waveforms of the levels of various signals;
  • FIG. 9 is a flowchart of a driving method according to a second embodiment of the present application; and
  • FIG. 10 is a flowchart of a further embodiment of the driving method shown in FIG. 9.
  • the first embodiment of the present application proposes a timing controller provided in a display device.
  • the display device further includes a display panel.
  • the display panel has a plurality of cascaded gate lines, and an array substrate type is used.
  • Drive Technology Gate Driver on Array; GOA.
  • the display panel is also provided with a corresponding gate shift register with multiple cascades.
  • the display panel is, for example, a liquid crystal display panel, an OLED display panel, a QLED display panel, a curved display panel, or other display panels.
  • FIG. 1 is a schematic diagram of a display device of the present application.
  • the display device includes a display panel 10 and a timing controller 30.
  • the display panel 10 includes a plurality of cascaded gate lines 32 and adopts an array substrate type driving technology (Gate Driver on Array; GOA), the display panel 10 is further provided with a plurality of cascaded gate shift registers 14, and the cascaded gate shift registers 14 are respectively coupled to a plurality of cascaded gate lines 32.
  • GOA array substrate type driving technology
  • the display panel 10 in the figure still has a source driving chip 12, but the array substrate type driving technology does not use a gate driving chip. Instead, the gate shift register 14 is directly disposed on a glass substrate as shown in the figure. For the n-th gate line 32 in a plurality of cascades, the n-th gate shift register 14 generates a gate-scan signal Gn of this stage to drive the n-th gate line 32.
  • the timing controller 30 may be installed on a substrate or a circuit board, and is electrically coupled to the source driving chip 12 and the gate shift register 14 respectively, and the source driving chip 12 and the gate shift register 14 are electrically coupled. Perform signal timing control.
  • the timing controller 30 may generate the clock signal CKn at the stage required by the gate shift register 14 to subsequently cause the gate shift register 14 to The line 32 generates a gate scanning signal Gn.
  • the timing controller 30 is configured to control signals required by the gate shift register 14. Please refer to FIG. 2 in conjunction with FIG. 1.
  • FIG. 2 is a schematic diagram of an association between the timing controller 30 and the gate shift register 14 of the present application.
  • the timing controller 30 includes a timing control circuit (Timing Controller; TCON) 3002 and Level Shifter IC 3004.
  • gate shift register register 14 is set to receive the gate signal of the previous stage or previous stage to generate the gate scan signal of this stage and generate the gate signal required by the next stage or subsequent stage.
  • the gate shift register It further includes a pull-down sustaining circuit 58, a control circuit 56, an input circuit 50, an output circuit 52, and a pull-down feedback circuit 54.
  • the input circuit 50 is electrically coupled to the output circuit 52 and the pull-down sustaining circuit 58 at the operating point NQ.
  • the output circuit 52 is further electrically coupled to the timing controller 30 and is electrically connected to the pull-down feedback circuit 54 and the pull-down sustaining circuit 58.
  • the pull-down sustain circuit 58 and the control circuit 56 receive a low preset level Vss, and the control circuit 56 is electrically coupled to the pull-down sustain circuit 58.
  • the timing control circuit 3002 is configured to generate a clock signal CKn of this stage to the n-th gate shift register 14 and the subsequent gate shift register 14 to the gate line 32 generates a gate scanning signal Gn of this stage.
  • the timing control circuit 3002 generates a clock signal CK4 to the fourth gate shift register 14, and causes the subsequent gate shift register 14 to generate a gate scanning signal G4 to the gate line 32.
  • the level shift circuit 3004 is set to generate three levels of the clock signal, and the three levels are a low preset level, a high level, and an excessively low preset level. Among them, the three levels are high level, low preset level, and too low preset level in order from high to low.
  • the input circuit 50 is configured to receive the gate signal F (n-2) of the first two stages, and generate a signal of the operating point NQ in the gate shift register 14 based on the gate signal F (n-2) of the first two stages.
  • the operating point voltage signal Qn this operating point voltage will be precharged into a precharge level.
  • the gate signal F (n-2) of the first two stages is F2
  • the operating point voltage signal Qn is Q4
  • the clock signal CKn is CK4.
  • the input circuit 50 further includes a fifth switch 48a.
  • the fifth switch 48a is configured to receive the first-stage gate signal Fn-2, and generate the operating point NQ of the shift register 14 according to the first-stage gate signal.
  • the output circuit 52 is configured to receive the clock signal CKn and the precharge level, and couple the clock signal CKn to the precharge level to become the operating point voltage signal Qn.
  • the operating point voltage signal Qn is the operating point voltage signal Q4
  • the clock signal CKn is the clock signal CK4.
  • a gate scanning signal Gn is output to the gate line 32 according to the coupled operating point voltage signal Qn and the clock signal CKn.
  • a gate scanning signal G4 is output to the gate line 32 based on the operating point voltage signal Q4 and the clock signal CK4.
  • the output circuit 52 can generate the gate signal Fn (F4 in the example shown in the figure) required by the second-stage gate shift register.
  • the output circuit 52 further includes a third switch 44a and a fourth switch 46a.
  • the control terminal of the third switch 44a receives the operating point voltage signal Qn, it receives the clock signal CKn and transmits it to the gate circuit 32 of the subsequent stage. Desired gate signal Fn.
  • the control terminal of the fourth switch 46a receives the operating point voltage signal Qn and the clock signal CKn, and transmits a gate scanning signal Gn to the n-th gate line 32.
  • the pull-down feedback circuit 54 is electrically coupled to the gate line 32.
  • the pull-down feedback circuit 54 receives the gate scanning signal Gn + 4 (G8 in the example in the figure) in the last four stages, and pulls down the gate scanning signal G4 to a low preset. Level Vss.
  • the pull-down feedback circuit 54 includes a first switch 40a and a second switch 42a.
  • the control terminals of the first switch 40a and the second switch 42a receive the gate scanning signal G (n + 4) of the last four stages.
  • the first terminal of the first switch 40a receives the operating point voltage signal Qn.
  • the terminal is electrically coupled to a low preset level Vss.
  • the first switch 40a pulls the operating point voltage Qn to a low preset level Vss according to the gate scanning signal Gn + 4 of the last four stages.
  • a first terminal of the second switch 42a receives the gate scanning signal Gn of the n-th gate line 32, and a second terminal of the second switch 42a receives a low preset level Vss.
  • the second switch 42a pulls the gate scanning signal Gn of the n-th gate line 32 to a low preset level Vss according to the gate scanning signal Gn + 4 of the last four stages.
  • the gate scan signal G4 is pulled down from the high potential to the low preset potential. Since the potential difference between the high potential and the too low preset potential is greater than the potential difference between the high potential and the low preset potential, the speed at which the gate scan signal G4 is pulled down from the high potential to the low preset potential is faster than the gate scan signal. G4 is pulled down from the high potential to the low preset potential even faster. In other words, due to the influence of the clock signal CK4 being at an excessively low preset level, the discharge speed of the gate scan signal G4 becomes faster, so the error prevention charging time can be reduced.
  • first switch 40a, second switch 42a, third switch 44a, fourth switch 46a, and fifth switch 48a may be transistor switches.
  • the level shift circuit 3004 is used to generate three levels of the clock signal. While the pull-down feedback circuit 54 pulls down the gate scan signal G4, the high and low levels of the clock signal can be used to preset the voltage. The larger voltage difference between the flats makes the discharge faster, which can minimize the time to prevent mischarging, improve the tailing phenomenon, and increase the charging time.
  • control circuit 56 is electrically coupled to the pull-down sustaining circuit 58 and the low preset level Vss, and is set to generate a correct timing to control the pull-down sustaining circuit 58.
  • the pull-down sustaining circuit 58 is electrically coupled to the low-preset level Vss and is controlled by the control circuit 56 to be set to eliminate noise of the operating point voltage in the gate shift register 14.
  • FIG. 3 is a schematic diagram of three levels of clock signals of the present application.
  • the three levels are low preset level V1, high level V2, and too low preset level V3.
  • the three levels are high level V2, low preset level V1, and too low preset level V3 in order from high to low.
  • the level shift circuit 3004 controls the level of the signal to generate a low preset level V1.
  • the clock signal CKn at this time is an invalid signal, which may be similar to the low preset level Vss, and the gate shift register 14 is regarded as an invalid clock signal CKn.
  • the level shift circuit 3004 controls the level of the signal to generate a high level V2.
  • the clock signal CKn at this time is a valid clock signal CKn for the gate shift register 14, and the gate shift register 14 can be triggered to generate a gate scan signal Gn to subsequently drive the gate line 32.
  • the level shift circuit 3004 controls the level of the signal to generate an excessively low preset level V3.
  • the level of the clock signal CKn is lowered from the high level V2 to the too low preset level V3, which can make the voltage difference of the gate scan signal Gn to the gate line 32 larger, so the discharge will be faster, and Improved tailing.
  • the level of the clock signal CKn is raised slightly to the low preset level V1 to prepare for the next effective clock signal regeneration.
  • the duty cycle of the high-level V2 in the clock signal CKn needs to be less than 1/3 to be in a periodic waveform unit, except
  • a clock signal CKn of the low preset level V1 with a sufficient length of time can be allowed.
  • the unit time length of the high-level V2 level of the clock signal CKn can also be designed to be equal to the unit time length of the V3 level that is too low. In this way, the duty cycle of the high-level V2 level in the clock signal CKn
  • the ratio must be less than 1/3, the time length of the low preset level V1 can exceed the aforementioned unit time length, and a low preset level V1 of sufficient time length can exist.
  • FIG. 4 is a schematic diagram of waveforms of levels of various signals of the present application. Each signal has a different level, that is, a high voltage value can represent a valid signal. The illustration is still illustrated by the embodiment of the 8CK clock signal.
  • the clock signals CKn are CK1, CK2, CK3, CK4, CK5, CK6, CK7, and CK8, respectively.
  • Each clock signal has three levels, which are a low preset level V1, a high level V2, and an excessively low preset level V3.
  • the clock signal CK4 is a high level V2, which is a valid signal for the gate shift register 14.
  • the clock signal is pulled down, the level is directly reduced to the preset level V3. , The pressure difference is larger, so the discharge will be faster. Subsequently, it returns to the low preset level V1 to prepare for the next generation of the clock signal CKn.
  • the operating point voltage signal Q4 is a relatively ideal waveform that has been pre-coupled to the clock signal CK4, in order to smoothly pull up to a high voltage level, efficiently turn on the transistor switch, and the gate scan signal G4 is smoothly transmitted to the gate line 32.
  • the gate scan signal G4 will be followed by a mischarge prevention time Tf, which means that tailing occurs. phenomenon.
  • Tf mischarge prevention time
  • the voltage difference between the high level V2 of the clock signal CK4 and the excessively low preset level V3 is larger, so that the gate line 32 is discharged faster, so that when the gate scan signal G4 is pulled down,
  • the anti-mischarge time Tf can be shortened, thereby improving the tailing phenomenon and increasing the charging time.
  • the display device includes a display panel 10 and a timing controller 30.
  • the display panel 10 uses an array substrate type driving technology.
  • the timing controller 30 further includes a timing control circuit 3002. And level shift circuit 3004.
  • the display panel 10 is provided with a plurality of cascaded gate lines 32.
  • the display panel 10 is further provided with a plurality of cascaded gate shift registers 14, and a plurality of cascaded gate shift registers 14.
  • a plurality of cascaded gate lines 32 are respectively coupled.
  • the display panel 10 generates a clock signal CKn to the n-th gate shift register 14 in a plurality of cascades through the timing control circuit 3002, so that the gate line 32 generates a gate scan signal Gn.
  • Each circuit in the display device may be a corresponding circuit in the above-mentioned embodiment, and the operation method and effect of each circuit are similar to those in the above-mentioned embodiment, and are not repeated here.
  • the duty cycle of the high-level V2 in the clock signal CKn is less than 1/3.
  • the level of the high level V2 of the clock signal CKn has a unit time length
  • the level of the too low preset level V3 also has the same unit time length, that is, the unit time of the high level V2 of the clock signal CKn
  • the duty cycle of the clock signal CKn of the high level V2 needs to be less than 1/3, and the time length of the low preset level V1 can exceed the aforementioned unit time length. Only then can the low preset level V1 exist for a sufficient length of time.
  • the timing controller, the potential transfer circuit, and the clock signal level adjustment method of this embodiment use the potential transfer circuit to generate three levels of the clock signal.
  • the gate line discharge will be faster, the error prevention charging time Tf of the gate scanning signal Gn can be minimized, and the gate level is improved.
  • the tailing phenomenon of the scanning signal Gn increases the charging time.
  • FIG. 5 is a flowchart of a level adjustment method of the present application.
  • Another embodiment of the present application provides a clock signal level adjustment method.
  • the level adjustment method is set in a display device.
  • the display device includes a display panel 10.
  • the display panel 10 includes a plurality of cascaded gate lines 32.
  • the display panel 10 is also provided with a plurality of cascaded gate shift registers 14 correspondingly.
  • the level adjustment method includes the following steps:
  • Step S01 Generate a clock signal CKn to the n-th gate shift register 14 in a plurality of cascades, and then cause the gate shift register 14 to generate a gate scan signal Gn to the n-th gate line 32. .
  • the three levels are a low preset level V1, a high level V2, and an excessively low preset level V3.
  • the three levels are high level V2, low preset level V1, and too low preset level V3 in order from high to low.
  • Step S02 Before the clock signal CKn of the driving gate line 32 is generated, the level shift circuit 3004 controls the level of the signal to generate a low preset level V1.
  • Step S03 When the clock signal CKn driving the gate line 32 is generated, the level shift circuit 3004 controls the level of the signal to generate a high level V2.
  • Step S04 After the clock signal CKn for driving the gate line 32 is generated, the level shift circuit 3004 controls the level of the signal to generate an excessively low preset level V3. Subsequently, the signal level is raised slightly to a low preset level V1 in preparation for the next clock signal regeneration.
  • step S03 When the high level V2 of step S03 is changed to the too low preset level V3 of step S04, the voltage difference between the high level V2 and the too low preset level V3, and the higher level V2 directly enters the low preset
  • the voltage difference between the levels V1 is larger, so the gate line 32 discharges faster, so that the mischarge prevention time Tf can be shortened, and the tailing phenomenon can be effectively improved.
  • the timing controller 30, the display device, and the clock signal level adjustment method use the level shift circuit 3004 to generate three levels of the clock signal, which can be scanned at a low gate level.
  • the larger the voltage difference between the high level V2 and the too low preset level V3 in the clock signal CKn makes the gate line 32 discharge faster, which can reduce the prevention of the gate scanning signal Gn as much as possible.
  • the wrong charging time Tf improves the tailing phenomenon of the gate scanning signal Gn, and thereby increases the charging time.
  • FIG. 6 is a schematic diagram of a display panel according to a second embodiment of the present application.
  • the shift register 14 proposed in this embodiment is set as an array substrate type driving technology (Gate Driver). on Array (GOA) display panel 10, which includes a substrate 15, a display area structure 16, a plurality of gate lines 32, and a plurality of cascaded shift registers 14.
  • the display area structure 16 is disposed on the substrate 15.
  • a plurality of gate lines 32 are also disposed on the substrate 15 and extend into the display area structure 16.
  • a plurality of shift registers 14 are also disposed on the substrate 15 and are adjacent to the display area structure 16 and electrically. Coupled to a plurality of gate lines 32.
  • the display area structure 16 may include pixel units (not shown) arranged in a matrix.
  • An active switch (not shown) is provided in the pixel unit corresponding to the pixel unit, and the gate line 32 will extend to multiple pixel units. And coupled with the active switch.
  • the display panel 10 in the figure still has a source driving chip 12, but the array substrate type driving technology does not use a gate driving chip. Instead, the shift register 14 is directly provided on the glass substrate as the driving gate line 32 as shown in the figure. Circuit. Each shift register 14 receives the gate signal of the previous stage to transmit the gate scan signal through the gate line 32.
  • FIG. 7 is a schematic diagram of a shift register in this embodiment.
  • n is a positive integer greater than 2
  • the n-th shift register 14 receives the gate signal Fn-2 of the previous two stages to pass the n-th stage.
  • the gate lines 32 transmit a gate-level scan signal Gn, where the working point (Quiescent in the n-th shift register 14) point) NQ has an operating point voltage signal Qn.
  • the n-th shift register 14 is described.
  • the circuit connection relationship and operation mode of the n-th shift register 14 are substantially the same as the circuit connection relationship and operation mode in FIG. 2 described above, and are not described herein.
  • the pull-down feedback circuit 54 that originally received the gate scanning signal Gn + 4 of the last four stages and also receives the operating point voltage signal Qn + of the latter four stages. 4 and the gate scanning signals Gn + 2 of the second and subsequent stages.
  • the figure shows an example of an 8-clock signal.
  • the shift register 14 In order to generate a gate scan signal Gn for the n-th gate line 32, the shift register 14 will receive the gate signal Fn-2 of the previous stage and the clock of this stage.
  • the signal CKn generates a desired operating point voltage signal Qn and a gate scanning signal Gn.
  • the gate line 32 is charged to generate a gate scanning signal Gn, and then when the gate scanning signal Gn is to be ended, the gate scanning signal Gn is changed from a high level to a low level The level of the preset level Vss. At this time, in the transistor switch, one end of the gate scanning signal Gn will discharge one end of the clock signal CKn. When the waveform of the gate scanning signal Gn is pulled low, it cannot be immediately pulled down. , There will be a period of time Tf to prevent mischarging, and the so-called tail phenomenon occurs.
  • the input circuit 50 in the shift register 14 is configured to receive the gate signal Fn-2 of the previous stage, and generate the operation of the operating point NQ in the shift register 14 according to the gate signal Fn-2 of the previous stage. Point voltage.
  • the input circuit 50 further includes a fifth switch 48b.
  • the fifth switch 48b is configured to receive the first-stage gate signal Fn-2, and generate the operating point NQ of the shift register 14 according to the first-stage gate signal. The operating point voltage of the shift register 14.
  • the operating point voltage from the input circuit 50 is precharged and coupled with the clock signal CKn into an operating point voltage signal Qn.
  • the output circuit 52 is configured to receive the clock signal CKn and the operating point voltage signal Qn to generate a gate signal Fn required by the post-stage shift register 14 and generate a gate scanning signal Gn required by the gate line 32.
  • the output circuit 52 further includes a third switch 44b and a fourth switch 46b.
  • the control terminal of the third switch 44b receives the operating point voltage signal Qn, it receives the clock signal CKn and transmits it to the gate circuit 32 of the subsequent stage.
  • Gate signal Fn After the control terminal of the fourth switch 46b receives the operating point voltage signal Qn, it receives the clock signal CKn and transmits the gate scanning signal Gn to the n-th gate line 32.
  • the pull-down feedback circuit 54 is a circuit that feedbacks a pull-down function, and includes a first switch 40b and a second switch 42b.
  • the control terminal of the first switch 40b receives the four-stage operating point voltage signal Qn + 4, the first terminal of the first switch 40b receives the operating point voltage signal Qn, and the second terminal of the first switch 40b receives the second-stage gate stage. Scan signal Gn + 2.
  • the control end of the first switch 40b receives the operating point voltage signal Qn + 4 of the last four stages as a feedback signal to pull the operating point voltage Qn low to the gate scanning signal Gn + 2 of the latter two stages.
  • the control terminal of the second switch 42b receives the gate scanning signal Gn + 4 of the last four stages, the first terminal of the second switch 42b receives the gate scanning signal Gn of the n-th gate line 32, and the second of the second switch 42b The terminal receives a low preset level Vss.
  • the control end of the second switch 42b receives the gate scanning signals Gn + 4 of the last four stages as a feedback signal to pull the gate scanning signal Gn of the n-th gate line 32 to a low level to a low preset level Vss.
  • the first switch 40b does not use the gate scanning signal Gn + 4 as the control terminal signal, instead uses the operating point voltage signal Qn + 4 as the control terminal signal, and does not pull down to the low preset level Vss, but changes Level of receiving the gate scanning signal Gn + 2, therefore, using the first switch 40b improved by the pull-down feedback circuit 54 in the shift register 14, when the gate scanning signal Gn ends, it can assist the operating point NQ Charging is performed to maintain or even raise the NQ level of the operating point, thereby minimizing the time to prevent mischarging, improving tailing, and increasing the charging time.
  • first switch 40b, second switch 42b, third switch 44b, fourth switch 46b, and fifth switch 48b may be transistor switches.
  • the display panel 10 shown in FIG. 6 may use the shift register provided in the foregoing embodiment, and its operation mode has been described above, and is not repeated here.
  • FIG. 8 is a schematic waveform diagram of levels of various signals according to the second embodiment of the present application. Each signal has a different level, that is, a high voltage value can represent a valid signal.
  • the illustration is still illustrated by the embodiment of the 8CK clock signal.
  • the clock signals CKn are CK1, CK2, CK3, CK4, CK5, CK6, CK7, and CK8, respectively.
  • the operating point voltage signal Q4 is pre-charged and coupled to the clock signal CK4 into a more ideal waveform, so as to smoothly pull up to a high voltage level, and efficiently turn on the transistor. Switch, and the gate scan signal G4 is smoothly transmitted to the gate line 32.
  • the operating point voltage signal Q8 is generated at the control terminal of the first switch 40b, and the operating point voltage signal Q4 can be pulled down to the waveform of the gate scan signal G6 to form an ideal operating point voltage signal Q4 waveform.
  • the gate scanning signal Gn8 is generated at the control terminal of the second switch 42b, so that the operating point voltage signal Q4 and the gate scanning signal G4 can be pulled down to a low preset level Vss, and the operating point voltage signal is completely ended.
  • the gate line 32 is charged by the first end of the four switches 46b to the second end of the fourth switch 46b at the high level of the clock signal CK4. It is the gate scanning signal G4.
  • the clock signal CK4 changes from high to low level.
  • the second terminal of the fourth switch 46b will discharge the first terminal, so that the gate scan signal G4 has an anti-charge time Tf. , And the so-called tail phenomenon occurs.
  • the first switch 40b proposed in this embodiment can also charge the operating point at the timing unit T2, which helps increase the driving signal (VGS) at the timing unit T2, thereby improving the tailing phenomenon. It is added that the higher the voltage level shown by the waveform of the operating point voltage signal Q4 at the aforementioned timing unit T2, the better, meaning that the larger the driving signal is, the stronger the charging is, which is more helpful to improve the tailing phenomenon of the clock signal CK4.
  • FIG. 9 is a flowchart of a driving method according to the second embodiment.
  • This driving method is set to the array substrate type driving technology shown in FIG. 6 (Gate Driver on (Array; GOA) display panel 10, the display panel 10 has a plurality of cascaded shift registers 14, taking the nth shift register 14 of the cascaded shift registers 14 as an example Note that n is a positive integer greater than 2, and the n-th shift register 14 receives the previous-stage gate signal to transmit the gate-scan signal Gn through the n-th gate line 32, where the n-th shift register The memory 14 has an operating point voltage signal Qn.
  • the driving method includes the following steps:
  • Step S11 receiving the clock signal CKn and the gate signal of the first two stages to generate a gate scanning signal Gn and transmitting it to the gate line 32.
  • Step S12 Receive the four-stage operating point voltage signals as feedback signals.
  • Step S13 Pull the operating point voltage to a low level to the level of the gate scanning signal of the second stage.
  • Step S14 receiving the gate scanning signals of the next four stages as feedback signals.
  • Step S15 the gate scanning signal Gn of the n-th gate line 32 is pulled to a low preset level Vss.
  • the shift register 14 includes a first switch 40b and a second switch 42b.
  • the first switch 40b and the second switch 42b have a control terminal, a first terminal, and a second terminal, respectively.
  • the driving method also includes the following steps:
  • Step S21 The first terminal of the first switch 40b receives the operating point voltage signal Qn.
  • Step S22 The control terminal of the first switch 40b receives a working point voltage signal of a subsequent stage, such as a last four stage shift register, as a feedback signal.
  • Step S33 The second terminal of the first switch 40b pulls the operating point voltage to a low level to a subsequent stage, such as a gate scanning signal of a second stage shift register.
  • Steps S21, S22, and S23 implement steps S12 and S13 in FIG.
  • Step S24 The first terminal of the second switch 42b receives the gate scanning signal Gn.
  • Step S25 The control end of the second switch 42b receives the gate scanning signal of the subsequent stage, such as the last four-stage shift register, as a feedback signal.
  • Step S26 the second terminal of the second switch 42b pulls the gate scanning signal Gn to a low level Vss.
  • Steps S24, S25, and S26 implement steps S14 and S15 in FIG.
  • the first switch 40b in this embodiment does not use the gate-stage scanning signal of the subsequent stage as the control terminal signal, and instead uses the operating point voltage signal of the subsequent stage as the control terminal signal, and does not directly pull down to a low preset level Vss is the level of the gate scanning signal pulled down to another subsequent stage. Therefore, the first switch 40b improved by the pull-down feedback circuit 54 in the shift register 14 is used at the same time as the gate scanning signal Gn ends. , It can assist in charging the working point, which can minimize the wrong charging time, improve the tailing phenomenon, and increase the charging time.
  • the shift register, the display panel, and the drive method of the shift register of this embodiment use the first switch improved by the pull-down feedback circuit in the shift register to complete the scanning at the gate level. At the same time, it can assist in charging the working point, thereby reducing the time to prevent mischarging, improving the tailing phenomenon, and increasing the charging time.
  • the signals related to the shift registers of the first two stages, the second two stages, and the last four stages are respectively used in the foregoing embodiments, this is not intended to limit the protection scope of the present application.
  • the corresponding shift registers of the signals used need not be fixed to a specific order of stages such as first two, last two, and last four. Pay attention to the corresponding level change mode.

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Abstract

本申请揭露了一种移位暂存器、显示面板、以及移位暂存器的驱动方法，设置为阵列基板型驱动技术的显示面板，显示面板具有多个级联的移位暂存器，移位暂存器包括输出电路及下拉反馈电路，下拉反馈电路包括第一开关及第二开关，第一开关的控制端接收后级的工作点电压信号作为反馈信号，以将工作点电压拉低电平至后级的栅级扫描信号，第二开关的控制端接收后级的栅级扫描信号作为反馈信号，以将栅极线路的栅级扫描信号拉低电平至低预设电位。

Description

移位暂存器、显示面板、以及移位暂存器的驱动方法
相关申请
本申请要求2018年07月17日申请的，申请号为201810786392.7，名称为“移位暂存器、显示面板、以及移位暂存器的驱动方法”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及一种显示面板，尤其涉及一种显示面板中移位暂存器以及移位暂存器的驱动方法。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
为节省成本，液晶显示面板的产业已经广泛采用阵列基板型驱动技术(Gate Driver on Array；GOA)。传统液晶显示面板的技术需仰赖源极驱动芯片(Source IC)及栅极驱动芯片(Gate IC)来进行驱动，前者控制电压来传输信号，后者以晶体管当作开关来控制及决定透光量。
阵列基板型驱动技术就是舍弃传统的栅极驱动芯片，取而代之的是将栅极驱动电路结构直接制做在显示面板的玻璃基板上，由于栅极驱动电路结构是利用曝光显影方式，在玻璃基板边缘产生多个移位暂存器的逻辑电路，所以无论是材料或是制造流程上，皆能藉此达到降低成本的效果，并且还能达到缩减液晶显示器边框的效果。
阵列基板型驱动技术的原理是从汤普森(Thompson)电路基础上所发展出来的，为求驱动效果顺畅，通常会在工作点(Quiescent point)进行预充，以达到较高电平的电压准位，使得后续能跟时钟信号耦合成理想的信号波型，藉此，当晶体管的开关打开时，栅极线路所需的栅级扫描信号得以顺利传递。
此外，针对显示面板中一个画素单元充电的充电时间，在信号结束时会有一段防错充时间(gate Tf)来拉低高电平的电压准位，这段防错充时间则是越小越好。
因此，如何在拉低栅级扫描信号的同时，能够尽量减少防错充时间，改善拖尾现象，借以增加充电时间，已成为本领域技术人员欲解决的问题之一。
申请内容
本申请提出一种移位暂存器、显示面板、以及移位暂存器的驱动方法，在栅级扫描信号结束的同时，可以辅助对工作点进行充电，藉此能够尽量减少防错充时间，改善拖尾现象，并可增加充电时间。
本申请的一实施例提出一种移位暂存器，设置为阵列基板型驱动技术(Gate Driver on Array；GOA)的显示面板。所述显示面板具有多个级联的移位暂存器，以多个移位暂存器中的第n个移位暂存器而言，n为大于2的正整数，所述第n个移位暂存器接收前级的栅级信号，以传送这一级的栅级扫描信号Gn至相对应的第n个栅极线路，其中所述第n个移位暂存器的工作点具有工作点电压信号Qn。所述移位暂存器包括输出电路、以及下拉反馈电路。
所述输出电路设置为接收时钟信号CKn以及前级的栅级信号，以产生栅级扫描信号Gn传送予所述栅极线路。
所述下拉反馈电路为一种反馈下拉功能的电路，包含第一开关、及第二开关。
所述第一开关的第一端电性耦接工作点电压信号Qn，所述第一开关的第二端电性耦接后级的栅级扫描信号。第一开关的控制端接收后级的工作点电压信号作为反馈信号，以将工作点电压Qn拉低电平至后级的栅级扫描信号。
所述第二开关的第一端电性耦接第n个栅极线路的栅级扫描信号Gn，所述第二开关的第二端电性耦接低预设电位Vss。第二开关的控制端接收后级的栅级扫描信号作为反馈信号，以将第n个栅极线路的栅级扫描信号Gn拉低电平至低预设电位Vss。
本申请实施例的一种移位暂存器、显示面板、以及移位暂存器的驱动方法，利用移位暂存器中下拉反馈电路所改善的第一开关，在栅级扫描信号结束的同时，可以辅助对工作点进行充电，藉此能够尽量减少防错充时间，改善拖尾现象，并可增加充电时间。
附图说明
图1是根据本申请第一实施例的显示装置的示意图；图2是根据本申请第一实施例的时序控制器与栅极移位暂存器的关联示意图；图3是根据本申请第一实施例的时钟信号三种准位的示意图；图4是根据本申请第一实施例的各种信号的准位的波形示意图；图5是根据本申请第一实施例的电平调整方法的流程图；图6是根据本申请第二实施例的显示装置的示意图；图7是根据本申请第二实施例的移位暂存器实施例的示意图；图8是根据本申请第二实施例的各种信号的准位的波形示意图；图9是根据本申请第二实施例的驱动方法的流程图；图10是图9所示的驱动方法的进一步实施例的流程图。
具体实施方式
本申请的第一实施例提出一种时序控制器，设置为显示装置中，显示装置还包括显示面板，显示面板中具有如多个的多个级联的栅极线路，且采用了阵列基板型驱动技术(Gate Driver on Array；GOA)，显示面板上设置亦对应具有多个级联的栅极移位暂存器。在某些实施例中，显示面板例如为液晶显示面板、OLED显示面板、QLED显示面板、曲面显示面板或其他显示面板。
请参照图1，图1是本申请显示装置的示意图。显示装置包括显示面板10以及时序控制器30，显示面板10包括多个级联的栅极线路32，且采用了阵列基板型驱动技术(Gate Driver on Array；GOA)，显示面板10上还设置有多个级联的栅极移位暂存器14，多个级联的栅极移位暂存器14分别耦接多个级联的栅极线路32。
图中显示面板10仍具有源极驱动芯片12，但阵列基板型驱动技术不使用栅极驱动芯片，取而代之的是如图将栅极移位暂存器14直接设置在玻璃基板上。以多个级联中的第n个栅极线路32而言，第n个栅极移位暂存器14产生这一级的栅级扫描信号Gn来驱动第n个栅极线路32。
时序控制器30可以装设在基板或电路板上，分别电性耦接源极驱动芯片12以及栅极移位暂存器14，并对源极驱动芯片12以及栅极移位暂存器14进行信号的时序控制。针对栅极移位暂存器14而言，时序控制器30可以产生栅极移位暂存器14所需这一级的时钟信号CKn，以后续使栅极移位暂存器14对栅极线路32产生栅级扫描信号Gn。
在本实施例中，时序控制器30设置为控制栅极移位暂存器14所需的信号。配合图1请参照图2，图2是本申请时序控制器30与栅极移位暂存器14的关联示意图。
时序控制器30包括时序控制电路(Timing Controller；TCON)3002、以及电平转移电路(Level Shifter IC)3004。栅极移位暂存器(shift register)14设置为接收前一级或前级的栅级信号，以产生这一级的栅级扫描信号，并产生下一级或后级所需的栅级信号，栅极移位暂存器更包括下拉维持电路58、控制电路56、输入电路50、输出电路52、以及下拉反馈电路54。输入电路50与输出电路52及下拉维持电路58电性耦接于工作点NQ，输出电路52进一步电性耦接至时序控制器30，并与下拉反馈电路54及下拉维持电路58一并电性耦接至对应的一个栅极线路32以输出栅极扫描信号Gn(图示例中为G4，表示此栅极移位暂存器是第4级栅极移位暂存器)，下拉反馈电路54、下拉维持电路58以及控制电路56接收低预设电平Vss，且控制电路56电性耦接至下拉维持电路58。
针对第n个栅极线路32，时序控制电路3002设置为对第n个栅极移位暂存器14产生这一级的时钟信号CKn，以后续栅极移位暂存器14对栅极线路32产生这一级的栅级扫描信号Gn。图示例中是时序控制电路3002对第4个栅极移位暂存器14产生时钟信号CK4，使后续栅极移位暂存器14对栅极线路32产生栅级扫描信号G4。电平转移电路3004设置为对时钟信号产生三种准位的电平，三种准位分别是低预设电平、高电平、以及过低预设电平。其中，三种准位依电平自高而低依序为高电平、低预设电平、过低预设电平。
输入电路50设置为接收前二级的栅级信号F(n-2)，并根据前二级的栅级信号F(n-2)，生成栅级移位暂存器14中工作点NQ的工作点电压信号Qn，此工作点电压会被预充成为预充电平。在图示例中，前二级的栅级信号F(n-2)为F2，工作点电压信号Qn为Q4，时钟信号CKn为CK4。输入电路50还包括第五开关48a，第五开关48a设置为接收前二级的栅级信号Fn-2，并根据前二级的栅级信号，对移位暂存器14的工作点NQ生成移位暂存器14的工作点电压。
输出电路52设置为接收时钟信号CKn以及预充电平，并使时钟信号CKn与预充电平耦合，成为工作点电压信号Qn。在图示例中，工作点电压信号Qn为工作点电压信号Q4，时钟信号CKn为时钟信号CK4。
后续，并根据耦合后的工作点电压信号Qn与时钟信号CKn，对栅极线路32输出栅极扫描信号Gn。图示例中是根据工作点电压信号Q4与时钟信号CK4，对栅极线路32输出栅极扫描信号G4。此外，输出电路52并可产生后二极的栅级移位暂存器所需的本级栅极信号Fn(图示例中为F4)。
在本实施例中，输出电路52还包括第三开关44a及第四开关46a，第三开关44a的控制端接收工作点电压信号Qn后，接收时钟信号CKn并传送后级的栅极线路32所需的栅级信号Fn。第四开关46a的控制端接收工作点电压信号Qn及时钟信号CKn，并传送栅级扫描信号Gn予第n个栅极线路32。
下拉反馈电路54电性耦接栅极线路32，下拉反馈电路54接收后四级的栅极扫描信号Gn+4(图示例中为G8)后，会将栅极扫描信号G4下拉至低预设电平Vss。下拉反馈电路54包括第一开关40a及第二开关42a。第一开关40a及第二开关42a的控制端接收后四级的栅极扫描信号G(n+4)，第一开关40a的第一端接收工作点电压信号Qn，第一开关40a的第二端电性耦接低预设电平Vss。第一开关40a根据后四级的栅极扫描信号Gn+4，将工作点电压Qn拉低电平至低预设电平Vss。第二开关42a的第一端接收第n个栅极线路32的栅级扫描信号Gn，第二开关42a的第二端接收低预设电平Vss。第二开关42a根据后四级的栅级扫描信号Gn+4，将第n个栅极线路32的栅级扫描信号Gn拉低电平至低预设电平Vss。
在下拉栅极扫描信号G4的过程中，由于时钟信号CK4是位于前述的过低预设电位，所以栅极扫描信号G4会自高电位被往过低预设电位下拉。由于高电位到过低预设电位的电位差大于高电位到低预设电位的电位差，因此栅极扫描信号G4被从高电位往过低预设电位下拉的速度，会比栅极扫描信号G4被从高电位往低预设电位下拉的速度还快。也就是说，受时钟信号CK4位于过低预设电平的影响，栅极扫描信号G4的放电速度会变得更快，因此能够减少防错充时间。
补充说明的是，前述的第一开关40a、第二开关42a、第三开关44a、第四开关46a、及第五开关48a，都可以是晶体管开关。
藉此，利用电平转移电路3004对时钟信号产生三种准位的电平，可以在下拉反馈电路54拉低栅极扫描信号G4的同时，藉由时钟信号中高电平与过低预设电平间更大的压差，使得放电更快，能够尽量减少防错充时间，改善拖尾现象，并借以增加充电时间。
此外，控制电路56电性耦接下拉维持电路58以及低预设电平Vss，设置为产生正确的时序来控制下拉维持电路58。下拉维持电路58电性耦接低预设电平Vss，受控制电路56的控制后，设置为消除栅级移位暂存器14中工作点电压的杂讯。
配合图2请参照图3，图3是本申请时钟信号三种准位的示意图。三种准位分别是低预设电平V1、高电平V2、以及过低预设电平V3。其中，三种准位依电平自高而低依序为高电平V2、低预设电平V1、过低预设电平V3。
当驱动栅极线路32的时钟信号CKn产生前，电平转移电路3004控制信号的电平以产生低预设电平V1。此时的时钟信号CKn是无效的信号，可以类似于低预设电平Vss，以栅极移位暂存器14而言，是当作无效的时钟信号CKn。
当驱动栅极线路32的时钟信号CKn产生时，电平转移电路3004控制信号的电平以产生高电平V2。此时的时钟信号CKn对栅极移位暂存器14来说是有效的时钟信号CKn，可以触动栅极移位暂存器14产生栅极扫描信号Gn，以后续驱动栅极线路32。
当时钟信号CKn产生后并要结束时钟信号CKn时，电平转移电路3004控制信号的电平以产生过低预设电平V3。藉此，时钟信号CKn的准位自高电平V2降至过低预设电平V3，可以使得对栅极线路32输出栅极扫描信号Gn的压差更大，因此放电会更快，可以改善拖尾现象。后续，时钟信号CKn的准位再略为提升至低预设电平V1，以准备下一次有效的时钟信号再生。
在一个实施例中，因为整个时钟信号的波形具有三种准位的电平，所以时钟信号CKn中高电平V2的占空比需小于1/3，才能在一个周期性的波形单位中，除了兼具有效信号高电平V2的时钟信号CKn与过低预设电平V3的时钟信号CKn之外，还能容许足够时间长度的低预设电平V1的时钟信号CKn。
其中，也可以设计使时钟信号CKn的高电平V2电平的单位时间长度，等于过低预设电平V3电平的单位时间长度，如此，时钟信号CKn中高电平V2电平的占空比就必须小于1/3，低预设电平V1的时间长度才能超过前述的单位时间长度，也才能有足够时间长度的低预设电平V1存在。
因为在时钟信号CKn中，高电平V2与过低预设电平V3间具有更大的压差，所以在栅极线路32的栅级扫描信号Gn被拉低的同时，使得放电会更快，而能够尽量减少防错充时间，也因此，可以改善拖尾现象，并能增加充电时间。
请参照图4，图4是本申请各种信号的准位的波形示意图。每个信号会有高低不同的电平，也就是高电平的电压值可以代表有效的信号。图示依旧是以8CK时钟信号的实施例来说明，时钟信号CKn分别为CK1、CK2、CK3、CK4、CK5、CK6、CK7、CK8，波形分别如图所示。
每一个时钟信号都有三种准位的电平，分别是低预设电平V1、高电平V2、以及过低预设电平V3。以时钟信号CK4而言，时钟信号CK4为高电平V2，对栅极移位暂存器14而言为有效的信号，拉下时钟信号时准位是直接降至过低预设电平V3，压差更大，因此放电会更快。后续，再回到低预设电平V1，以准备做下一次的时钟信号CKn的产生。
工作点电压信号Q4是已经对时钟信号CK4预充所耦合成较理想的波形，以便顺利拉高至高电压准位，有效率的打开晶体管开关，而使栅极扫描信号G4顺利传递至栅极线路32。
但是，在栅极扫描信号G4结束之时，并非能立刻自高电平V2拉下至低预设电平V1，栅极扫描信号G4后面会有防错充时间Tf，意即出现拖尾的现象。由于本申请中，时钟信号CK4的高电平V2与过低预设电平V3间的压差更大，因此使栅极线路32放电会更快，致使栅极扫描信号G4被拉下时，防错充时间Tf可以缩短，进而改善拖尾现象，并能增加充电时间。
此外，本申请的利另一实施例提出一种显示装置，显示装置包括显示面板10以及时序控制器30，显示面板10是采用阵列基板型驱动技术，时序控制器30还包括时序控制电路3002、以及电平转移电路3004。显示面板10中设置有多个级联的栅极线路32，显示面板10上还设置有多个级联的栅极移位暂存器14，多个级联的栅极移位暂存器14分别耦接多个级联的栅极线路32。显示面板10通过时序控制电路3002，来对多个级联中的第n个栅极移位暂存器14产生时钟信号CKn，以后续使栅极线路32产生栅极扫描信号Gn。显示装置中的各电路可以是上述实施例中相对应的电路，各电路的操作方法及效果也与上述实施例类似，在此不再赘述。
补充说明的是，时钟信号CKn中高电平V2的占空比为小于1/3。特别是当时钟信号CKn的高电平V2的电平具有单位时间长度，过低预设电平V3的电平亦具有相同的单位时间长度时，也就是时钟信号CKn高电平V2的单位时间长度等于过低预设电平V3的单位时间长度时，高电平V2的时钟信号CKn的占空比需小于1/3，低预设电平V1的时间长度才能超过前述的单位时间长度，也才能有足够时间长度的低预设电平V1存在。
综上，本实施例的时序控制器、电位转移电路、以及时钟信号的电平调整方法，利用电位转移电路对时钟信号产生三种准位的电平，可以在拉低栅级扫描信号Gn的同时，藉由时钟信号CKn中高电位与过低预设电位之间更大的压差，使得栅极线路放电会更快，能够尽量减少栅级扫描信号Gn的防错充时间Tf，改善栅级扫描信号Gn的拖尾现象，并增加充电时间。
请参照图5，图5是本申请电平调整方法的流程图。本申请的利另一实施例提出一种时钟信号的电平调整方法，电平调整方法设置为显示装置中，显示装置包括显示面板10，显示面板10中设多个级联的栅极线路32，且采用了阵列基板型驱动技术，显示面板10上亦对应设置有多个级联的栅极移位暂存器14。电平调整方法包括下列步骤：
步骤S01：对多个级联中的第n个栅极移位暂存器14产生时钟信号CKn，进而使栅极移位暂存器14对第n个栅极线路32产生栅极扫描信号Gn。
接着，产生三种准位的电平中的一种准位，三种准位分别是低预设电平V1、高电平V2、以及过低预设电平V3。其中，三种准位依电平自高而低依序为高电平V2、低预设电平V1、过低预设电平V3。
步骤S02：当驱动栅极线路32的时钟信号CKn产生前，电平转移电路3004控制信号的电平以产生低预设电平V1。
步骤S03：当驱动栅极线路32的时钟信号CKn产生时，电平转移电路3004控制信号的电平以产生高电平V2。
步骤S04：当驱动栅极线路32的时钟信号CKn产生后，电平转移电路3004控制信号的电平以产生过低预设电平V3。后续，信号的准位再略为提升至低预设电平V1，以准备下一次时钟信号再生。
由步骤S03的高电平V2改变为步骤S04的过低预设电平V3时，高电平V2与过低预设电平V3之间的压差，较高电平V2直接进入低预设电平V1之间的压差更大，因此栅极线路32放电会更快，致使防错充时间Tf可以缩短，进而有效的改善拖尾现象。
综上，本申请实施例的时序控制器30、显示装置、以及时钟信号的电平调整方法，利用电平转移电路3004对时钟信号产生三种准位的电平，可以在拉低栅级扫描信号Gn的同时，藉由时钟信号CKn中高电平V2与过低预设电平V3之间更大的压差，使得栅极线路32放电会更快，能够尽量减少栅级扫描信号Gn的防错充时间Tf，改善栅级扫描信号Gn的拖尾现象，并借以增加充电时间。
请参照图6，图6是根据本申请的第二实施例的显示面板的示意图。本实施例提出的移位暂存器14，设置为阵列基板型驱动技术(Gate Driver on Array；GOA)的显示面板10，显示面板10具有基板15、显示区结构16、多个栅极线路32、以及多个级联的移位暂存器14，显示区结构16设置于基板15上，多个栅极线路32亦设置于基板15上，并延伸至显示区结构16中，多个移位暂存器14亦设置于基板15上，与显示区结构16相邻，并分别电性耦接多个栅极线路32。进一步说明，显示区结构16则可包含矩阵排列的像素单元(图未示)，对应像素单元而于像素单元中会设置主动开关(图未示)，栅极线路32即会延伸至多个像素单元，并与主动开关耦接。
图中显示面板10仍具有源极驱动芯片12，但阵列基板型驱动技术不采用栅极驱动芯片，取而代之的是如图将移位暂存器14直接设置在玻璃基板上来作为驱动栅极线路32的电路。每一个移位暂存器14会接收前级的栅级信号，以通过栅极线路32传送栅级扫描信号。
图7是本实施例的移位暂存器的示意图。以第n个级联的移位暂存器14为例说明，n为大于2的正整数，第n个移位暂存器14接收前二级的栅级信号Fn-2，以通过第n个栅极线路32传送栅级扫描信号Gn，其中第n个移位暂存器14中的工作点(Quiescent point)NQ具有工作点电压信号Qn。在本实施例中针对第n个移位暂存器14说明，其中的电路连接关系及操作方式与前述图2中的电路连接关系及操作方式大致相同，在此不多加赘述。本实施例与图2所示的实施例的其中一个不同点在于，原本接收后四级的栅极扫描信号Gn+4的下拉反馈电路54，还接收了后四级的工作点电压信号Qn+4以及后二级的栅级扫描信号Gn+2。
如图是一个8时钟信号的实施例，为了对第n条栅极线路32产生栅极扫描信号Gn，移位暂存器14会接收前二级的栅级信号Fn-2以及本级的时钟信号CKn来产生所要的工作点电压信号Qn以及栅级扫描信号Gn。
但是，当时钟信号CKn产生后，会对栅极线路32充电产生栅级扫描信号Gn，而后当栅级扫描信号Gn要结束的同时，栅级扫描信号Gn由高电平的准位转为低预设电平Vss的准位，此时，在晶体管开关中，栅级扫描信号Gn的一端会对时钟信号CKn的一端进行放电动作，栅级扫描信号Gn波形在拉低时并无法立即拉下，会有一段防错充时间Tf，而出现所谓拖尾现象。
因此，在本实施例中藉由改善移位暂存器14来改善问题。移位暂存器14中的输入电路50设置为接收前二级的栅级信号Fn-2，并根据前级的栅级信号Fn-2，生成移位暂存器14中工作点NQ的工作点电压。
输入电路50还包括第五开关48b，第五开关48b设置为接收前二级的栅级信号Fn-2，并根据前二级的栅级信号，对移位暂存器14的工作点NQ生成移位暂存器14的工作点电压。
来自输入电路50的工作点电压，会预充并与时钟信号CKn耦合成工作点电压信号Qn。输出电路52设置为接收时钟信号CKn以及工作点电压信号Qn，以产生后级移位暂存器14所需要的栅级信号Fn，并且产生栅极线路32所需要的栅级扫描信号Gn。
进一步说明，输出电路52还包括第三开关44b、及第四开关46b，第三开关44b的控制端接收工作点电压信号Qn后，接收时钟信号CKn并传送后级的栅极线路32所需的栅级信号Fn。第四开关46b的控制端接收工作点电压信号Qn后，接收时钟信号CKn并传送栅级扫描信号Gn予第n个栅极线路32。
下拉反馈电路54为一种反馈下拉功能的电路，包括第一开关40b、及第二开关42b。第一开关40b的控制端接收后四级的工作点电压信号Qn+4，第一开关40b的第一端接收工作点电压信号Qn，第一开关40b的第二端接收后二级的栅级扫描信号Gn+2。第一开关40b的控制端接收后四级的工作点电压信号Qn+4作为反馈信号，以将工作点电压Qn拉低电平至后二级的栅级扫描信号Gn+2。
第二开关42b的控制端接收后四级的栅级扫描信号Gn+4，第二开关42b的第一端接收第n个栅极线路32的栅级扫描信号Gn，第二开关42b的第二端接收低预设电平Vss。第二开关42b的控制端接收后四级的栅级扫描信号Gn+4作为反馈信号，以将第n个栅极线路32的栅级扫描信号Gn拉低电平至低预设电平Vss。
第一开关40b，不使用栅级扫描信号Gn+4当作控制端信号，取而代之是使用工作点电压信号Qn+4当作控制端信号，并且不是下拉至低预设电平Vss，而是改变成接收栅级扫描信号Gn+2的准位，因此，利用移位暂存器14中下拉反馈电路54所改善的第一开关40b，在栅级扫描信号Gn结束时，可以辅助对工作点NQ进行充电以维持甚或抬高工作点NQ的电平，藉此能够尽量减少防错充时间，改善拖尾现象，并可增加充电时间。
补充说明的是，前述的第一开关40b、第二开关42b、第三开关44b、第四开关46b、及第五开关48b，都可以是晶体管开关。
此外，图6所示的显示面板10可以采用前述实施例所提供的移位暂存器，其运作方式已经描述于前，在此不再重复。
请参阅图8，图8是本申请第二实施例的各种信号的准位的波形示意图。每个信号会有高低不同的电平，也就是高电平的电压值可以代表有效的信号。图示依旧是以8CK时钟信号的实施例来说明，时钟信号CKn分别为CK1、CK2、CK3、CK4、CK5、CK6、CK7、CK8，波形依时序分别如图所示。
若为n=4的移位暂存器14实施例，工作点电压信号Q4是已经对时钟信号CK4预充所耦合成较理想的波形，以便顺利拉高至高电压准位，有效率的打开晶体管开关，而使栅极扫描信号G4顺利传递至栅极线路32。
后续，藉由工作点电压信号Q8产生于第一开关40b的控制端，能将工作点电压信号Q4下拉至栅极扫描信号G6的波形，形成一个理想的工作点电压信号Q4波形。再后续，藉由栅级扫描信号Gn8产生于第二开关42b的控制端，而能将工作点电压信号Q4以及栅极扫描信号G4下拉至低预设电平Vss，就此完全结束工作点电压信号Q4。
但是，在时序单位T1栅极扫描信号G4产生时，是以时钟信号CK4高电平的准位，由四开关46b的第一端对第四开关46b的第二端，向栅极线路32充电为栅级扫描信号G4。在栅极扫描信号G4结束时，时钟信号CK4由高转低准位，此时第四开关46b的第二端会对第一端进行放电动作，使得栅极扫描信号G4出现防错充时间Tf，而出现所谓拖尾现象。
所以本实施例提出的第一开关40b，在时序单位T2时还可以对工作点充电，帮助加大时序单位T2时的驱动信号(VGS)，进而使得拖尾现象改善。补充说明的是，前述时序单位T2时的工作点电压信号Q4波形所示的电压准位愈高愈好，意即驱动信号愈大充电愈强，更有助于改善时钟信号CK4拖尾现象。
请参阅图9，图9是第二实施例的驱动方法的流程图。此驱动方法设置为如图6所示的阵列基板型驱动技术(Gate Driver on Array；GOA)的显示面板10，显示面板10具有多个级联的移位暂存器14，以多个级联的移位暂存器14中的第n个移位暂存器14为例说明，n为大于2的正整数，第n个移位暂存器14接收前级的栅级信号，以通过第n个栅极线路32传送栅级扫描信号Gn，其中第n个移位暂存器14具有工作点电压信号Qn。驱动方法包括下列步骤：
步骤S11：接收时钟信号CKn以及前二级的栅级信号，以产生栅级扫描信号Gn传送予栅极线路32。
步骤S12：接收后四级的工作点电压信号作为反馈信号。
步骤S13：将工作点电压拉低电平至后二级的栅级扫描信号的电平。
步骤S14：接收后四级的栅级扫描信号作为反馈信号。
步骤S15：将第n个栅极线路32的栅级扫描信号Gn拉低电平至低预设电平Vss。
请参阅图10，图10是图9驱动方法的进一步实施例的流程图。如前述的驱动方法，移位暂存器14包含第一开关40b及第二开关42b，第一开关40b与第二开关42b分别具有控制端、第一端、及第二端。驱动方法还包含下列步骤：
步骤S21：第一开关40b的第一端接收工作点电压信号Qn。步骤S22：第一开关40b的控制端接收后级，例如后四级移位暂存器，的工作点电压信号作为反馈信号。步骤S33：第一开关40b的第二端将工作点电压拉低电平至后级，例如后二级移位暂存器，的栅级扫描信号。步骤S21、步骤S22、以及步骤S23，实现图9中步骤S12与步骤S13。步骤S24：第二开关42b的第一端接收栅级扫描信号Gn。步骤S25：第二开关42b的控制端接收后级，例如后四级移位暂存器，的栅级扫描信号作为反馈信号。步骤S26：第二开关42b的第二端将栅级扫描信号Gn拉低电平至低预设电平Vss。
步骤S24、步骤S25、以及步骤S26，实现图9中步骤S14与步骤S15。
本实施例中的第一开关40b不使用后级的栅级扫描信号当作控制端信号，取而代之是使用后级的工作点电压信号当作控制端信号，并且不是直接下拉至低预设电平Vss，而是下拉至另一后级的栅级扫描信号的准位，因此，利用移位暂存器14中下拉反馈电路54所改善的第一开关40b，在栅级扫描信号Gn结束的同时，可以辅助对工作点进行充电，藉此能够尽量减少防错充时间，改善拖尾现象，并可增加充电时间。
综上，本实施例的移位暂存器、显示面板、以及移位暂存器的驱动方法，利用移位暂存器中下拉反馈电路所改善的第一开关，在栅级扫描信号结束的同时，可以辅助对工作点进行充电，藉此能够尽量减少防错充时间，改善拖尾现象，并可增加充电时间。
应注意的是，虽然前述各实施例中分别采用了与前二级、后二级以及后四级的移位暂存器相关的信号，但是这并非用来限制本申请的保护范围。当实施于不同的移位暂存器的电路架构里，所采用的信号的对应移位暂存器可以不必固定为前二级、后二级以及后四级等特定的级数顺序，仅需注意符合对应的电平变化方式即可。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。
以上，仅是本申请的具体实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以具体实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的方法及技术内容作出些许的更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (17)

  1. 一种移位暂存器，设置为阵列基板型驱动技术的显示面板，所述显示面板具有多个级联的移位暂存器，所述移位暂存器接收前级的栅级信号，以传送栅级扫描信号至栅极线路，其中，所述移位暂存器具有工作点电压信号，其中，所述移位暂存器包括：
    输出电路，设置为接收时钟信号以及前级的栅级信号，以产生栅级扫描信号传送予所述栅极线路；以及
    下拉反馈电路，包括第一开关、及第二开关，
    所述第一开关的控制端接收后级的工作点电压信号作为反馈信号，以将本级的工作点电压拉低电平至后级的栅级扫描信号，及
    所述第二开关的控制端接收后级的栅级扫描信号作为反馈信号，以将所述栅极线路的栅级扫描信号拉低电平至低预设电位。
  2. 如权利要求1所述的移位暂存器，其中，所述输出电路还包括第三开关、及第四开关，所述第三开关的控制端接收工作点电压信号后，接收时钟信号并传送后级的栅极线路所需的栅级信号，第四开关的控制端接收工作点电压信号后，接收时钟信号并传送栅级扫描信号予所述栅极线路。
  3. 如权利要求1所述的移位暂存器，其中，所述移位暂存器还包括第五开关，所述第五开关设置为接收前级的栅级信号，并根据前级的栅级信号，生成所述移位暂存器的工作点电压。
  4. 如权利要求1所述的移位暂存器，其中，所述第一开关的第一端电性耦接工作点电压信号，所述第一开关的第二端电性耦接后级的栅级扫描信号，所述第二开关的第一端电性耦接所述栅极线路的栅级扫描信号，所述第二开关的第二端电性耦接低预设电位。
  5. 如权利要求4所述的移位暂存器，其中，所述移位暂存器具有8级时钟信号，所述第一开关的控制端电性耦接后级的工作点电压信号为后四级的工作点电压信号，所述第二开关的控制端电性耦接后级的栅级扫描信号为后四级的栅级扫描信号，所述第一开关的第二端电性耦接后级的栅级扫描信号为后二级的栅级扫描信号。
  6. 如权利要求1所述的移位暂存器，其中，所述输出电路还包括第三开关、及第四开关，所述第三开关的控制端接收工作点电压信号后，接收时钟信号并传送后级的栅极线路所需的栅级信号，第四开关的控制端接收工作点电压信号后，接收时钟信号并传送栅级扫描信号予所述栅极线路；
    所述移位暂存器还包括第五开关，所述第五开关设置为接收前级的栅级信号，并根据前级的栅级信号，生成所述移位暂存器的工作点电压。
  7. 如权利要求1所述的移位暂存器，其中，所述输出电路还包括第三开关、及第四开关，所述第三开关的控制端接收工作点电压信号后，接收时钟信号并传送后级的栅极线路所需的栅级信号，第四开关的控制端接收工作点电压信号后，接收时钟信号并传送栅级扫描信号予所述栅极线路；
    所述第一开关的第一端电性耦接工作点电压信号，所述第一开关的第二端电性耦接后级的栅级扫描信号，所述第二开关的第一端电性耦接所述栅极线路的栅级扫描信号，所述第二开关的第二端电性耦接低预设电位。
  8. 如权利要求7所述的移位暂存器，其中，所述移位暂存器具有8级时钟信号，所述第一开关的控制端电性耦接后级的工作点电压信号为后四级的工作点电压信号，所述第二开关的控制端电性耦接后级的栅级扫描信号为后四级的栅级扫描信号，所述第一开关的第二端电性耦接后级的栅级扫描信号为后二级的栅级扫描信号。
  9. 如权利要求1所述的移位暂存器，其中，所述移位暂存器还包括第五开关，所述第五开关设置为接收前级的栅级信号，并根据前级的栅级信号，生成所述移位暂存器的工作点电压；
    所述第一开关的第一端电性耦接工作点电压信号，所述第一开关的第二端电性耦接后级的栅级扫描信号，所述第二开关的第一端电性耦接所述栅极线路的栅级扫描信号，所述第二开关的第二端电性耦接低预设电位。
  10. 如权利要求9所述的移位暂存器，其中，所述移位暂存器具有8级时钟信号，所述第一开关的控制端电性耦接后级的工作点电压信号为后四级的工作点电压信号，所述第二开关的控制端电性耦接后级的栅级扫描信号为后四级的栅级扫描信号，所述第一开关的第二端电性耦接后级的栅级扫描信号为后二级的栅级扫描信号。
  11. 如权利要求1所述的移位暂存器，其中，所述输出电路还包括第三开关、及第四开关，所述第三开关的控制端接收工作点电压信号后，接收时钟信号并传送后级的栅极线路所需的栅级信号，第四开关的控制端接收工作点电压信号后，接收时钟信号并传送栅级扫描信号予所述栅极线路；
    所述移位暂存器还包括第五开关，所述第五开关设置为接收前级的栅级信号，并根据前级的栅级信号，生成所述移位暂存器的工作点电压；
    所述第一开关的第一端电性耦接工作点电压信号，所述第一开关的第二端电性耦接后级的栅级扫描信号，所述第二开关的第一端电性耦接所述栅极线路的栅级扫描信号，所述第二开关的第二端电性耦接低预设电位。
  12. 如权利要求11所述的移位暂存器，其中，所述移位暂存器具有8级时钟信号，所述第一开关的控制端电性耦接后级的工作点电压信号为后四级的工作点电压信号，所述第二开关的控制端电性耦接后级的栅级扫描信号为后四级的栅级扫描信号，所述第一开关的第二端电性耦接后级的栅级扫描信号为后二级的栅级扫描信号。
  13. 一种显示面板，其中，所述显示面板包括：
    基板，在所述基板上设置多个像素单元和对应多个像素单元的多个主动开关；
    多个栅极线路，设置于所述基板上，并延伸至所述多个像素单元；
    多个级联的移位暂存器，设置于所述基板上，分别电性耦接所述多个栅极线路，所述移位暂存器接收前级的栅级信号，以通过栅极线路传送栅级扫描信号，其中所述移位暂存器具有工作点电压信号，所述移位暂存器包括下拉反馈电路，所述下拉反馈电路包括：
    第一开关，所述第一开关的控制端接收后级的工作点电压信号作为反馈信号，以将工作点电压拉低电平至后级的栅级扫描信号；
    第二开关，所述第二开关的控制端接收后级的栅级扫描信号作为反馈信号，以将所述栅极线路的栅级扫描信号拉低电平至低预设电位。
  14. 如权利要求13所述的显示面板，其中，所述第一开关的第一端电性耦接工作点电压信号，所述第一开关的第二端电性耦接后级的栅级扫描信号，所述第二开关的第一端电性耦接所述栅极线路的栅级扫描信号，所述第二开关的第二端电性耦接低预设电位。
  15. 如权利要求14所述的显示面板，其中，所述移位暂存器具有8级时钟信号，所述第一开关的控制端电性耦接后级的工作点电压信号为后四级的工作点电压信号，所述第二开关的控制端电性耦接后级的栅级扫描信号为后四级的栅级扫描信号，所述第一开关的第二端电性耦接后级的栅级扫描信号为后二级的栅级扫描信号。
  16. 一种移位暂存器的驱动方法，设置为阵列基板型驱动技术的显示面板，所述显示面板具有多个级联的移位暂存器，所述移位暂存器接收前级的栅级信号，以传送栅级扫描信号至所述栅极线路，其中所述移位暂存器具有工作点电压信号，其中，所述驱动方法包括下列步骤：
    接收时钟信号以及前级的栅级信号，以产生栅级扫描信号传送予所述栅极线路；
    接收后级的工作点电压信号作为反馈信号；
    将工作点电压拉低电平至后级的栅级扫描信号；
    接收后级的栅级扫描信号作为反馈信号；以及
    将所述栅极线路的栅级扫描信号拉低电平至低预设电位。
  17. 如权利要求16所述的驱动方法，所述移位暂存器包含第一开关及第二开关，第一开关与第二开关分别具有控制端、第一端、及第二端，其中，所述驱动方法还包含下列步骤：
    所述第一开关的第一端接收所述工作点电压信号；
    所述第一开关的控制端接收后级的工作点电压信号作为反馈信号；
    所述第一开关的第二端将所述工作点电压拉低电平至后级的栅级扫描信号；
    所述第二开关的第一端接收所述栅级扫描信号；
    所述第二开关的控制端接收后级的栅级扫描信号作为反馈信号；以及
    所述第二开关的第二端将所述栅级扫描信号拉低电平至所述低预设电位。
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