WO2017084146A1 - 液晶显示设备及goa电路 - Google Patents

液晶显示设备及goa电路 Download PDF

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Publication number
WO2017084146A1
WO2017084146A1 PCT/CN2015/098427 CN2015098427W WO2017084146A1 WO 2017084146 A1 WO2017084146 A1 WO 2017084146A1 CN 2015098427 W CN2015098427 W CN 2015098427W WO 2017084146 A1 WO2017084146 A1 WO 2017084146A1
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Prior art keywords
terminal connected
transistor
circuit
clock signal
input terminal
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PCT/CN2015/098427
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English (en)
French (fr)
Inventor
杜鹏
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深圳市华星光电技术有限公司
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Priority to GB1802737.5A priority Critical patent/GB2557764B/en
Priority to EA201890995A priority patent/EA034645B1/ru
Priority to KR1020187016732A priority patent/KR102135942B1/ko
Priority to US14/905,876 priority patent/US9786241B2/en
Priority to JP2018523027A priority patent/JP6650518B2/ja
Publication of WO2017084146A1 publication Critical patent/WO2017084146A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a GOA (Gate Driver On) for a liquid crystal display device.
  • GOA Gate Driver On
  • Array, array substrate row scan driver circuit.
  • the Tri-gate architecture is a commonly used method to reduce the cost of the product by increasing the number of scan lines by a factor of three and reducing the number of data lines by a factor of three.
  • the total number of lines will be reduced to a large extent, usually the source chip (Source IC) is higher than the gate chip (Gate IC), thus saving cost.
  • Source IC source chip
  • Gate IC gate chip
  • the number of gate lines is increased by three times, and the space occupied by each stage of the GOA circuit is reduced.
  • the width of the GOA area needs to be sacrificed during design.
  • the popular narrow bezel design is very disadvantageous now.
  • the tri-gate architecture is a commonly used architecture for low-cost panels today, with FHD (Full High For example, the panel of the Convention has a total of 1080 gate lines and 5760 data lines. There are 6840 signal lines in total. After the three-gate architecture, there are 3240 common gate lines and 1920 data lines. There are 5,160 lines, which is less than the conventional architecture. If the structure of the tri-gate with GOA is adopted, all the gate lines can be omitted, and the panel production cost can be minimized.
  • the gate signal point Q(n) is a very important potential in the GOA circuit.
  • the GOA circuit When the gate signal point Q(n) is high, the GOA circuit is in an open and output state, when the gate signal point Q(n) When it is low, the GOA circuit is in the off state, and the output at this time is also the corresponding gate signal low.
  • the GOA circuit 10 includes a plurality of GOA units 15 which are cascaded to each other as a multi-stage GOA unit 15, wherein the nth stage GOA unit 15 charges a corresponding one of the scan lines G(n), and the nth stage GOA unit 15 includes a clock circuit.
  • the basic architecture is a basic architecture consisting of the clock circuit 100, the pull-down circuit 200, the bootstrap capacitor circuit 300, and the pull-up circuit 400.
  • the basic architecture includes four TFTs and one.
  • the pull-down circuit 500 mainly functions to assist the pull-down, and ensures that the GOA circuit output and the gate signal point Q(n) are in a low potential state during the gate line off period, thereby improving the reliability of the GOA circuit during operation.
  • auxiliary pull-down circuits In the current design, two sets of auxiliary pull-down circuits are often designed. Their function is to pull down the gate signal point Q(n) when the GOA circuit is in the off state, so that it is in a low potential state to ensure the normal operation of the panel. And enhance trust. Under normal circumstances, the auxiliary pull-down circuit is composed of more TFT components, and they occupy a relatively large space, which is very disadvantageous for the narrow bezel design.
  • Figure 2 For a description of the two sets of auxiliary pull-down circuits, please refer to Figure 2.
  • FIG. 2 is a block diagram of another GOA circuit 20 of the prior art; and FIG. 3 is a waveform diagram of the GOA circuit of FIG. 2.
  • the pull-down circuit 500 includes a first auxiliary pull-down circuit 510 and a second auxiliary pull-down circuit 520, and the first auxiliary pull-down circuit 510 and the second auxiliary pull-down circuit 520 are respectively composed of two low frequencies.
  • the signals LC1 and LC2 are controlled to alternate between different time periods to ensure that the output of the GOA circuit and the gate signal point Q(n) are maintained at a low potential when the gate line G(n) is turned off.
  • the low frequency signal LC1 and the low frequency signal LC2 are inverted.
  • the auxiliary operation is performed by the first auxiliary pull-down circuit 510.
  • the low frequency signal LC2 is low, in several frames ( After the time of Frame), the low frequency signal LC1 is switched to a low potential, the low frequency signal LC2 is switched to a high potential, and the operation of the auxiliary pulldown is performed by the second auxiliary pull-down circuit 520.
  • the pull-down circuit 500 can also take other forms. 3 is a switch between the low-level signal LC1 and the low-frequency signal LC2 of the 6-level CK signal approximately every 100 frames to generate a corresponding gate line G(n) signal.
  • each stage of the GOA circuit corresponds to only one gate line G(n) output.
  • G(n) gate line
  • the maximum space height that the corresponding GOA circuit can occupy is reduced to the previous 1/3, which is often required to be increased in design.
  • the width of the wiring area, which will widen the border area of the panel, is very disadvantageous for the popular narrow frame design.
  • the present invention provides a GOA circuit for a liquid crystal display device, the GOA circuit comprising a plurality of GOA units cascaded into a multi-level GOA unit, the n-th GOA unit corresponding to at least one level of scanning a line, the at least one scan line includes an nth scan line, an n+1th scan line, and an n+2th scan line charge, and the nth stage GOA unit includes a first pull-down sustain circuit and a pull-up Circuit, bootstrap capacitor circuit, pull-down circuit and clock circuit.
  • the first pull-down maintaining circuit is connected to a gate signal point.
  • the pull-up circuit is connected to the first pull-down maintaining circuit through the gate signal point.
  • the bootstrap capacitor circuit is connected to the pull-up circuit through the gate signal point.
  • the pull-down circuit, The gate signal point is connected to the bootstrap capacitor circuit.
  • the clock circuit is connected to the bootstrap capacitor circuit through the gate signal point and receives a first clock signal.
  • the first pull-down maintaining circuit and the pull-down circuit are commonly connected to a DC low voltage source.
  • the clock circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor.
  • the first transistor includes a first control terminal connected to the gate signal point, a first input terminal connected to the first clock signal, and a first output terminal outputting an nth stage enable signal.
  • the second transistor includes a second control terminal connected to the gate signal point, a second input terminal connected to the first clock signal, and a second output terminal connected to the nth-level scan line.
  • the third transistor includes a third control terminal connected to the gate signal point, a third input terminal connected to the first clock signal, and a third output terminal connected to the n+1th scan line.
  • the fourth transistor includes a fourth control terminal connected to the gate signal point, a fourth input terminal connected to the first clock signal, and a fourth output terminal connected to the n+2th scan line.
  • the bootstrap capacitor circuit includes a first capacitor.
  • the first capacitor has two ends connected to the gate signal point and the nth stage enable signal.
  • the pull up circuit comprises a fifth transistor.
  • the fifth transistor includes a fifth control terminal receiving an n-3th stage enable signal, a fifth input terminal connected to the fifth control terminal, and a fifth output terminal connected to the gate signal point.
  • the first pull-down maintaining circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor.
  • the sixth transistor includes a sixth control terminal receiving an n+3th stage enable signal, a sixth input terminal coupled to the DC low voltage source, and a sixth output terminal coupled to the gate signal point.
  • the seventh transistor includes a seventh control terminal connected to the gate signal point, and a seventh input terminal connected to the DC low voltage source.
  • the eighth transistor includes an eighth control terminal connected to the DC high voltage source, an eighth output terminal connected to the eighth control terminal, and an eighth input terminal connected to the seventh output terminal of the seventh transistor.
  • the ninth transistor includes a ninth control terminal connected to the gate signal point, and a ninth input terminal connected to the DC low voltage source.
  • the tenth transistor includes a tenth control terminal connected to the seventh output terminal, a tenth input terminal connected to the ninth output terminal of the ninth transistor, and a tenth output terminal connected to the eighth output terminal.
  • the eleventh transistor includes an eleventh control terminal connected to the tenth input terminal, an eleventh input terminal connected to the DC low voltage source, and an eleventh output terminal connected to the gate signal point.
  • the twelfth transistor includes a twelfth control terminal connected to the tenth input terminal, a twelfth input terminal connected to the DC low voltage source, and a twelfth output terminal outputting the nth stage enable signal.
  • the pull-down circuit includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth Transistor and twenty-first transistor.
  • the thirteenth transistor includes a thirteenth control terminal connected to the pull-down maintaining circuit, a thirteenth input terminal connected to the DC low voltage source, and a thirteenth output terminal connected to the nth stage scan line.
  • the fourteenth transistor includes a fourteenth control terminal connected to the second clock signal, a fourteenth input terminal connected to the DC low voltage source, and a fourteenth output terminal connected to the nth stage scan line.
  • the fifteenth transistor includes a fifteenth control terminal connected to the fourth clock signal, a fifteenth input terminal connected to the DC low voltage source, and a fifteenth output terminal connected to the nth stage scan line.
  • the sixteenth transistor includes a sixteenth control terminal connected to the pull-down maintaining circuit, a sixteenth input terminal connected to the DC low voltage source, and a sixteenth output terminal connected to the n+1th scan line.
  • the seventeenth transistor includes a seventeenth control terminal connected to the third clock signal, a seventeenth input terminal connected to the DC low voltage source, and a fourteenth output terminal connected to the n+1th scan line.
  • the eighteenth transistor includes an eighteenth control terminal connected to the fifth clock signal, an eighteenth input terminal connected to the DC low voltage source, and an eighteenth output terminal connected to the n+1th scan line.
  • the nineteenth transistor includes a nineteenth control terminal connected to the pull-down maintaining circuit, a nineteenth input terminal connected to the DC low voltage source, and a nineteenth output terminal connected to the n+2th scan line.
  • the twentieth transistor includes a twentieth control terminal connected to the fourth clock signal, a twentieth input terminal connected to the DC low voltage source, and a twentieth output terminal connected to the n+2th scan line.
  • the twenty-first transistor includes a twenty-first control terminal connected to the sixth clock signal, a twenty-first input terminal connected to the DC low voltage source, and a twenty-first output terminal connected to the n+2th scan line.
  • the GOA for a liquid crystal display device The circuit also includes a second pull-down sustain circuit including a twenty-second transistor and a twenty-third transistor.
  • the twenty-second transistor includes a twenty-second control terminal connected to the fourth clock signal, a twenty-second input terminal connected to the DC low voltage source, and a twenty-second output terminal connected to the gate signal point.
  • the twenty-third transistor includes a twenty-third control terminal connected to the fourth clock signal, a twenty-third input terminal connected to the DC low voltage source, and a twenty-third output terminal outputting the nth stage start signal.
  • the first clock signal, the second clock signal, and the third clock signal have the same period and are sequentially activated with a time difference of 1/3 cycle.
  • the fourth clock signal, the fifth clock signal, and the sixth clock signal are respectively associated with the first clock signal, the second clock signal, and the third clock signal Inverted signal.
  • the present invention provides another GOA circuit for a liquid crystal display device, wherein the GOA circuit includes: a plurality of GOA units, which are cascaded to each other as a multi-level GOA unit, and the n-th stage GOA unit corresponds to at least a first scan line, the at least one scan line includes an n+3th scan line, an n+4th scan line, and an n+5th scan line charge, and the nth stage GOA unit includes a first pulldown Maintain circuit, pull-up circuit, bootstrap capacitor circuit, pull-down circuit and clock circuit.
  • the first pull-down maintaining circuit is connected to a gate signal point.
  • the pull-up circuit is connected to the first pull-down maintaining circuit through the gate signal point.
  • the bootstrap capacitor circuit is connected to the pull-up circuit through the gate signal point.
  • the pull-down circuit, The gate signal point is connected to the bootstrap capacitor circuit.
  • the clock circuit is connected to the bootstrap capacitor circuit through the gate signal point and receives a fourth clock signal.
  • the first pull-down maintaining circuit and the pull-down circuit are commonly connected to a DC low voltage source.
  • the clock circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor.
  • the first transistor includes a first control terminal connected to the gate signal point, a first input terminal connected to the fourth clock signal, and a first output terminal outputting an n+3th stage enable signal.
  • the second transistor includes a second control terminal connected to the gate signal point, a second input terminal connected to the fourth clock signal, and a second output terminal connected to the n+3th scan line.
  • the third transistor includes a third control terminal connected to the gate signal point, a third input terminal connected to the fourth clock signal, and a third output terminal connected to the n+4th scan line.
  • the fourth transistor includes a fourth control terminal connected to the gate signal point, a fourth input terminal connected to the fourth clock signal, and a fourth output terminal connected to the n+5th-level scan line.
  • the bootstrap capacitor circuit includes a first capacitor.
  • the first capacitor has two ends connected to the gate signal point and the n+3th stage enable signal.
  • the pull up circuit comprises a fifth transistor.
  • the fifth transistor includes a fifth control terminal receiving an nth stage enable signal, a fifth input terminal connected to the fifth control terminal, and a fifth output terminal connected to the gate signal point.
  • the first pull-down maintaining circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor.
  • the sixth transistor includes a sixth control terminal receiving an n+6th stage enable signal, a sixth input terminal coupled to the DC low voltage source, and a sixth output terminal coupled to the gate signal point.
  • the seventh transistor includes a seventh control terminal connected to the gate signal point, and a seventh input terminal connected to the DC low voltage source.
  • the eighth transistor includes an eighth control terminal connected to the DC high voltage source, an eighth output terminal connected to the eighth control terminal, and an eighth input terminal connected to the seventh output terminal of the seventh transistor.
  • the ninth transistor includes a ninth control terminal connected to the gate signal point, and a ninth input terminal connected to the DC low voltage source.
  • the tenth transistor includes a tenth control terminal connected to the seventh output terminal, a tenth input terminal connected to the ninth output terminal of the ninth transistor, and a tenth output terminal connected to the eighth output terminal.
  • the eleventh transistor includes an eleventh control terminal connected to the tenth input terminal, an eleventh input terminal connected to the DC low voltage source, and an eleventh output terminal connected to the gate signal point.
  • the twelfth transistor includes a twelfth control terminal connected to the tenth input terminal, a twelfth input terminal connected to the DC low voltage source, and a twelfth output terminal outputting the n+3th stage enable signal.
  • the pull-down circuit includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a second Ten transistors and twenty-first transistors.
  • the thirteenth transistor includes a thirteenth control terminal connected to the pull-down maintaining circuit, a thirteenth input terminal connected to the DC low voltage source, and a thirteenth output terminal connected to the n+3th scan line.
  • the fourteenth transistor includes a fourteenth control terminal connected to the first clock signal, a fourteenth input terminal connected to the DC low voltage source, and a fourteenth output terminal connected to the n+3th scan line.
  • the fifteenth transistor includes a fifteenth control terminal connected to the third clock signal, a fifteenth input terminal connected to the DC low voltage source, and a fifteenth output terminal connected to the n+3th scan line.
  • the sixteenth transistor includes a sixteenth control terminal connected to the pull-down maintaining circuit, a sixteenth input terminal connected to the DC low voltage source, and a sixteenth output terminal connected to the n+4th scan line.
  • the seventeenth transistor includes a seventeenth control terminal connected to the second clock signal, a seventeenth input terminal connected to the DC low voltage source, and a fourteenth output terminal connected to the n+4th scan line.
  • the eighteenth transistor includes an eighteenth control terminal connected to the fourth clock signal, an eighteenth input terminal connected to the DC low voltage source, and an eighteenth output terminal connected to the n+4th scan line.
  • the nineteenth transistor includes a nineteenth control terminal connected to the pull-down maintaining circuit, a nineteenth input terminal connected to the DC low voltage source, and a nineteenth output terminal connected to the n+5th scan line.
  • the twentieth transistor includes a twentieth control terminal connected to the third clock signal, a twentieth input terminal connected to the DC low voltage source, and a twentieth output terminal connected to the n+5th scan line.
  • the twenty-first transistor includes a twenty-first control terminal connected to the fifth clock signal, a twenty-first input terminal connected to the DC low voltage source, and a twenty-first output terminal connected to the n+5th scan line.
  • the GOA for a liquid crystal display device The circuit also includes a second pull-down sustain circuit including a twenty-second transistor and a twenty-third transistor.
  • the twenty-second transistor includes a twenty-second control terminal connected to the first clock signal, a twenty-second input terminal connected to the DC low voltage source, and a twenty-second output terminal connected to the gate signal point.
  • the twenty-third transistor includes a twenty-third control terminal connected to the first clock signal, a twenty-third input terminal connected to the DC low voltage source, and a twenty-third output terminal outputting the n+3 Level start signal.
  • the first clock signal, the second clock signal, and the third clock signal have the same period and are sequentially activated with a time difference of 1/3 cycle.
  • the fourth clock signal, the fifth clock signal, and the sixth clock signal are respectively associated with the first clock signal, the second clock signal, and the third clock signal Inverted signal.
  • the present invention revisits a GOA circuit architecture for the problem encountered by the tri-gate with the GOA architecture, that is, the first-level GOA circuit can correspond to the output of three gate lines, so that the number of stages of the GOA circuit can be reduced to the present.
  • the existing architecture is the output of the first-level GOA circuit corresponding to only one gate line. Since the number of GOA circuits is reduced, each stage of the circuit has a larger design space height, which is very advantageous for a narrow bezel design.
  • FIG. 1 is a schematic diagram of a GOA circuit architecture of the prior art
  • FIG. 2 is a diagram showing another GOA circuit architecture of the prior art
  • FIG. 3 is a waveform diagram of the GOA circuit of FIG. 2;
  • FIG. 4 is a block diagram showing a GOA circuit structure of a first preferred embodiment of the present invention.
  • FIG. 5 is a block diagram showing the structure of a GOA circuit according to a second preferred embodiment of the present invention.
  • FIG. 6 is a waveform diagram of the GOA circuit of FIGS. 4 and 5;
  • FIG. 7 is a block diagram showing the structure of a GOA circuit according to a third preferred embodiment of the present invention.
  • FIG. 8 is a block diagram showing the structure of a GOA circuit according to a fourth preferred embodiment of the present invention.
  • the GOA circuit 30 is for a liquid crystal display device.
  • the GOA circuit 30 includes a plurality of GOA units 35, which are cascaded to each other as a multi-level GOA unit 35, the n-th GOA unit 35 corresponding to at least one level of scan lines, and the at least one level scan line includes an n-th scan line G(n), the n+1th scanning line G(n+1), and the n+2th scanning line G(n+2) are charged, and the nth stage GOA unit 35 includes the first pull-down maintaining circuit 500.
  • the pull-up circuit 400, the bootstrap capacitor circuit 300, the pull-down circuit 200, and the clock circuit 100 are examples of the nth stage GOA unit 35.
  • the first pull-down maintaining circuit 500 is connected to a gate signal point Q(n).
  • the pull-up circuit 400 is connected to the first pull-down maintaining circuit 500 through the gate signal point Q(n).
  • the bootstrap capacitor circuit 300 is connected to the pull-up circuit 400 through the gate signal point Q(n).
  • the pull-down circuit 200, The bootstrap capacitor circuit 300 is connected through the gate signal point Q(n).
  • the clock circuit 100, The bootstrap capacitor circuit 300 is connected through the gate signal point Q(n), and receives the first clock signal CK1.
  • the first pull-down maintaining circuit 500 and the pull-down circuit 200 are commonly connected to a DC low voltage source.
  • the clock circuit 100 includes a first transistor T11, a second transistor T21, a third transistor T22, and a fourth transistor T23.
  • the first transistor T11 includes a first control terminal connected to the gate signal point Q(n), a first input terminal connected to the first clock signal CK1, and a first output terminal outputting an nth-level start signal ST ( n).
  • the second transistor T21 includes a second control terminal connected to the gate signal point Q(n), a second input terminal connected to the first clock signal CK1, and a second output terminal connected to the nth-level scan line G(n).
  • the third transistor T22 includes a third control terminal connected to the gate signal point Q(n), a third input terminal connected to the first clock signal CK1, and a third output terminal connected to the n+1th stage.
  • the fourth transistor T23 includes a fourth control terminal connected to the gate signal point Q(n), a fourth input terminal connected to the first clock signal CK1, and a fourth output terminal connected to the n+2th stage. Scan line G(n+2).
  • the bootstrap capacitor circuit 300 includes a first capacitor Cboost.
  • the first capacitor Cboost has two ends connected to the gate signal point Q(n) and the nth stage start signal ST(n).
  • the pull-up circuit 400 includes a fifth transistor T5.
  • the fifth transistor T5 includes a fifth control terminal receiving an n-3th stage enable signal ST(n-3), a fifth input terminal connected to the fifth control terminal, and a fifth output terminal connecting the gate signal Point Q(n).
  • the first pull-down maintaining circuit 500 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T44, and a thirteenth transistor T45.
  • the sixth transistor T6 includes a sixth control terminal receiving an n+3th stage enable signal ST(n+3), a sixth input terminal connected to the DC low voltage source Vss, and a sixth output terminal connected to the gate signal.
  • the seventh transistor T7 includes a seventh control terminal connected to the gate signal point Q(n), and a seventh input terminal connected to the DC low voltage source Vss.
  • the eighth transistor T8 includes an eighth control terminal connected to the DC high voltage source VDD, an eighth output terminal connected to the eighth control terminal, and an eighth input terminal connected to the seventh output terminal of the seventh transistor T7.
  • the ninth transistor T9 includes a ninth control terminal connected to the gate signal point Q(n), and a ninth input terminal connected to the DC low voltage source Vss.
  • the tenth transistor T10 includes a tenth control terminal connected to the seventh output terminal, a tenth input terminal connected to the ninth output terminal of the ninth transistor T9, and a tenth output terminal connected to the eighth output terminal.
  • the eleventh transistor T44 includes an eleventh control terminal connected to the tenth input terminal, an eleventh input terminal connected to the DC low voltage source Vss, and an eleventh output terminal connected to the gate signal point Q ( n).
  • the thirteenth transistor T45 includes a twelfth control terminal connected to the tenth input terminal, a twelfth input terminal connected to the DC low voltage source Vss, and a twelfth output terminal outputting the nth stage start signal ST (n).
  • the pull-down circuit 200 includes a thirteenth transistor T41, a fourteenth transistor T311, a fifteenth transistor T312, a sixteenth transistor T42, a seventeenth transistor T321, an eighteenth transistor T322, a nineteenth transistor T43, and a second Ten transistors T331 and twenty-first transistors T332.
  • the thirteenth transistor T41 includes a thirteenth control terminal connected to the first pull-down maintaining circuit, a thirteenth input terminal connected to the DC low voltage source Vss, and a thirteenth output terminal connected to the nth scan line G (n).
  • the fourteenth transistor T311 includes a fourteenth control terminal connected to the second clock signal CK2, a fourteenth input terminal connected to the DC low voltage source Vss, and a fourteenth output terminal connected to the nth scan line G(n) .
  • the fifteenth transistor T312 includes a fifteenth control terminal connected to the fourth clock signal CK4, a fifteenth input terminal connected to the DC low voltage source Vss, and a fifteenth output terminal connected to the nth stage scan line G(n) .
  • the sixteenth transistor T42 includes a sixteenth control terminal connected to the first pull-down maintaining circuit, a sixteenth input terminal connected to the DC low voltage source Vss, and a sixteenth output terminal connected to the n+1th level scanning Line G(n+1).
  • the seventeenth transistor T321 includes a seventeenth control terminal connected to the third clock signal CK3, a seventeenth input terminal connected to the DC low voltage source Vss, and a fourteenth output terminal connected to the n+1th scan line G ( n+1).
  • the eighteenth transistor T322 includes an eighteenth control terminal connected to the fifth clock signal CK5, an eighteenth input terminal connected to the DC low voltage source Vss, and an eighteenth output terminal connected to the n+1th scan line G ( n+1).
  • the nineteenth transistor T43 includes a nineteenth control terminal connected to the first pull-down maintaining circuit 500, a nineteenth input terminal connected to the DC low voltage source Vss, and a nineteenth output terminal connected to the n+2th stage Scan line G(n+2).
  • the twentieth transistor T331 includes a twentieth control terminal connected to the fourth clock signal CK4, a twentieth input terminal connected to the DC low voltage source Vss, and a twentieth output terminal connected to the n+2th scan line. G(n+2).
  • the twenty-first transistor T332 includes a twenty-first control terminal connected to the sixth clock signal CK6, a twenty-first input terminal connected to the DC low voltage source Vss, and a twenty-first output terminal connected to the n+2th stage. Scan line G(n+2).
  • the input ends of the first transistor T11, the second transistor T21, the third transistor T22, and the fourth transistor T23 are all connected to the first clock signal CK1, and the control terminals (ie, gates) are all connected to the gate.
  • the pole signal point Q(n) is connected.
  • the function of the first transistor T11 is to output an nth stage start signal ST(n) for the next stage GOA circuit (Start) Pulse), the second transistor T21, the third transistor T22, and the fourth transistor T23 correspond to three gate lines G(n), G(n+1), and G(n+, respectively) of the current stage. 2) The output.
  • the control terminals (ie, gates) of the fourteenth transistor T311 and the fifteenth transistor T312 are respectively by the second clock signal CK2 and the Controlled by the fourth clock signal CK4, which is responsible for pulling down the signal of the nth-th scan line G(n) in different time periods, due to the second transistor T21, the third transistor T22, and the
  • the output of the four transistors T23 after the first clock signal CK1 is connected is the same, and the gate pulses of the three gate lines G(n), G(n+1) and G(n+2) (Gate Pulse) signals do not overlap each other, so it is necessary to pull down the signals output by the second transistor T21, the third transistor T22, and the fourth transistor T23 in a suitable period of time, wherein
  • the pull-down of the nth-th scan line G(n) has been described above, and the pull-down of the n+1th-th scan line G(n+1) is completed by the seventeenth transistor T3
  • the pull-down of the n+2th scan line G(n+2) is performed by the twentieth transistor T331 and the Twenty-one transistors T332 are completed, which are respectively controlled by the fourth clock signal CK4 and the sixth clock signal CK6. They cooperate with the second transistor T21, the third transistor T22 and the fourth transistor T23 to ensure that the three gate lines corresponding to the stage GOA circuit 35 can output a correct waveform.
  • the thirteenth transistor T41, the sixteenth transistor T42, and the nineteenth transistor T43 are also used to pull down three gate lines, and their function is when the stage GOA circuit is not working, that is, When the gate signal point Q(n) of the stage circuit is at a low potential, the nth-th scan line G(n), the n+1th-th scan line G(n+1), and the The signals of the n+2 scanning lines G(n+2) are pulled down to ensure that their outputs are at a low potential.
  • the stage GOA circuit When the stage GOA circuit outputs, that is, when the gate signal point Q(n) is high, the thirteenth transistor T41, the sixteenth transistor T42, and the control terminal of the nineteenth transistor T43 ( That is, the gates are low, they are in a closed state, for the nth-th scan line G(n), the n+1th-th scan line G(n+1), and the n+2th stage
  • the signal output of the scanning line G(n+2) has no effect.
  • the eleventh transistor T44 and the thirteenth transistor T41 are also used for pull-down signals, and their function is to ensure the enable signal ST and the gate signal point Q(n) when the stage GOA circuit 35 is not output. ) Maintaining a low potential.
  • the GOA circuit 35 of the preferred embodiment since each stage of the GOA circuit 35 can output signals of three gate lines, the height of the entire GOA circuit wiring is increased, so that its width can be narrowed, and the narrow bezel can be designed. Very beneficial.
  • the GOA circuit 35 of the preferred embodiment has a total of 21 transistors per stage.
  • the prior art GOA circuit 25 of FIG. 2 the three gate lines require a three-stage GOA circuit 25, for a total of 51 TFTs.
  • the space required for the GOA circuit 35 of the preferred embodiment also has a greater degree of compression than the prior art GOA circuit 25.
  • FIG. 5 is a block diagram of a GOA circuit 40 of a second preferred embodiment of the present invention.
  • the preferred embodiment differs from the first preferred embodiment in that the signals connected are different. described as follows:
  • the start signal ST is increased by three levels, that is, n-3 is changed to n, n is changed to n+3, and n+3 is changed to n+6.
  • the input ends of the first transistor T11, the second transistor T21, the third transistor T22, and the fourth transistor T23 are connected to the fourth clock signal CK4.
  • the output ends of the second transistor T21, the third transistor T22, and the fourth transistor T23 are respectively connected to the n+3th scanning line G(n+3) and the n+4th scanning line G ( n+4) and the n+5th scanning line G(n+5).
  • the control terminal of the fourteenth transistor T311 is connected to the first clock signal CK1, and the control terminal of the fifteenth transistor T312 is connected to the third clock signal CK3.
  • the output ends of the fourteenth transistor T311 and the fifteenth transistor T312 are connected to the n+3th scanning line G(n+3).
  • the control terminal of the seventeenth transistor T321 is connected to the second clock signal CK2, and the control terminal of the eighteenth transistor T322 is connected to the fourth clock signal CK4.
  • the output ends of the seventeenth transistor T321 and the eighteenth transistor T322 are connected to the n+4th scanning line G(n+4).
  • the control terminal of the twentieth transistor T331 is connected to the third clock signal CK3, and the control terminal of the twenty-first transistor T332 is connected to the fifth clock signal CK5.
  • the output ends of the twentieth transistor T331 and the twenty-first transistor T332 are connected to the n+5th scanning line G(n+5).
  • the first preferred embodiment is for driving odd-numbered scan lines; the second preferred embodiment is for driving even-numbered scan lines.
  • FIG. 6 is a waveform diagram of the GOA circuit of FIGS. 4 and 5.
  • the periods of the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 are the same and sequentially started with a time difference of 1/3 period
  • the fourth clock signal CK4 The fifth clock signal CK5 and the sixth clock signal CK6 are respectively inverted signals with the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3, so that the The scan line signal (nth level to n+5 level) that is sequentially activated.
  • FIG. 7 is a block diagram of a GOA circuit 50 of a third preferred embodiment of the present invention.
  • the preferred embodiment differs from the first preferred embodiment in that a second pull-down sustain circuit is added that includes a twenty-second transistor T91 and a twenty-third transistor T92.
  • the twenty-second transistor T91 includes a twenty-second control terminal connected to the fourth clock signal CK4, a twenty-second input terminal connected to the DC low-voltage source Vss, and a twenty-second output terminal connected to the gate signal Point Q(n).
  • the twenty-third transistor T92 includes a twenty-third control terminal connected to the fourth clock signal CK4, a twenty-third input terminal connected to the DC low voltage source Vss, and a twenty-third output terminal outputting the first The n-stage start signal ST(n).
  • the GOA circuit 55 of the preferred embodiment employs two sets of pull-down sustain circuits (500, 600) for each stage, and the two sets of pull-down sustain circuits (500, 600) are pulled down at different time periods, thereby preventing the transistors of the pull-down sustain circuit (500, 600). After a long period of stress (Stress), the electrical drift causes the GOA circuit 55 to fail, which improves the reliability of the panel.
  • Stress stress
  • the two sets of pull-down maintaining circuits (500, 600) do not operate, ensuring that the corresponding three gate lines output the correct waveform.
  • the two sets of pull-down maintaining circuits (500, 600) alternately operate to pull down.
  • the fourth clock signal CK4 is low, and the first clock signal CK1 passes through the second transistor T21, the third transistor T22, and the fourth The transistor T23 is connected to the nth-th scan line G(n), the n+1th-th scan line G(n+1), and the n+2-th scan line G(n+2), respectively. Improving the reliability of the GOA circuit requires the nth-th scan line G(n), the n+1th-th scan line G(n+1), and the n+-th scan line G(n+2).
  • the pull-down is performed, and the gate signal point Q(n) and the start signal ST are also pulled down, and the operation mode at this time is the same as that of the GOA circuit in the first preferred embodiment.
  • the fourth clock signal CK4 is high, and it controls the twenty-second transistor T91 and the twenty-third transistor T92 to be turned on, and the gate signal point is turned on.
  • the potential of the first clock signal CK1 is the same, is low, and does not affect the nth-th scan line G(n), the n+1th-th scan line G(n+1), and the n+2th stage.
  • FIG. 8 is a block diagram showing a GOA circuit 60 of a fourth preferred embodiment of the present invention.
  • the preferred embodiment differs from the third preferred embodiment in that the signals connected are different. described as follows:
  • the start signal ST is increased by three levels, that is, n-3 is changed to n, n is changed to n+3, and n+3 is changed to n+6.
  • the input ends of the first transistor T11, the second transistor T21, the third transistor T22, and the fourth transistor T23 are connected to the fourth clock signal CK4.
  • the output ends of the second transistor T21, the third transistor T22, and the fourth transistor T23 are respectively connected to the n+3th scanning line G(n+3) and the n+4th scanning line G ( n+4) and the n+5th scanning line G(n+5).
  • the control terminal of the fourteenth transistor T311 is connected to the first clock signal CK1, and the control terminal of the fifteenth transistor T312 is connected to the third clock signal CK3.
  • the output ends of the fourteenth transistor T311 and the fifteenth transistor T312 are connected to the n+3th scanning line G(n+3).
  • the control terminal of the seventeenth transistor T321 is connected to the second clock signal CK2, and the control terminal of the eighteenth transistor T322 is connected to the fourth clock signal CK4.
  • the output ends of the seventeenth transistor T321 and the eighteenth transistor T322 are connected to the n+4th scanning line G(n+4).
  • the control terminal of the twentieth transistor T331 is connected to the third clock signal CK3, and the control terminal of the twenty-first transistor T332 is connected to the fifth clock signal CK5.
  • the output ends of the twentieth transistor T331 and the twenty-first transistor T332 are connected to the n+5th scanning line G(n+5).
  • the control terminals of the twenty-second transistor T91 and the twenty-third transistor T92 are connected to the first clock signal CK1.
  • the third preferred embodiment is for driving odd-numbered scanning lines; the fourth preferred embodiment is for driving even-numbered scanning lines.

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Abstract

一种用于液晶显示设备的GOA电路（30，40，50，60），所述GOA电路（30，40，50，60）包含多个GOA单元（35，45，55，65），相互级联为多级GOA单元（35，45，55，65），第n级GOA单元（35，45，55，65）对应至少一级扫描线，所述至少一级扫描线包括第n级扫描线、第n+1级扫描线以及第n+2级扫描线，所述第n级GOA单元（35，45，55，65）包括第一下拉维持电路（500）、上拉电路（400）、自举电容电路（300）、下拉电路（200）及时钟电路（100）；一级GOA电路（30，40，50，60）对应3条栅极线的输出，这样GOA电路（30，40，50，60）的级数可以缩减到现有的1/3，现有的架构是一级GOA电路只对应一条栅极线的输出，由于GOA电路（30，40，50，60）数量减少，因而每一级电路有更大的设计空间高度，对窄边框设计非常有利。

Description

液晶显示设备及GOA电路 技术领域
本发明涉及液晶显示技术领域，特别是涉及一种用于液晶显示设备的GOA（Gate Driver On Array，数组基板行扫描驱动）电路。
 背景技术
随着窄边框设计的日益流行，面板设计的周边空间被逐渐压缩，在传统的GOA电路设计中，每一级GOA电路的布线空间高度h和对应的像素尺寸是一致的，现在4k或者更高PPI(pixel per inch)产品的逐渐普及，像素的尺寸越来越小，留给GOA电路进行布线的空间高度也随之减小，由于高度收到限制，在布线时只能用更大的宽度来进行弥补，对窄边框的设计非常不利。
三栅极(Tri-gate)架构是一种常用的降低产品成本的方法，它是通过将扫描线的数量增加到原来的3倍，而数据线的数量则减少为原来的1/3，信号线的数量整体会有较大程度的降低，通常源极芯片(Source IC)的价格高于栅极芯片(Gate IC)，因而可以起到节省成本的目的。如果进一步的搭配GOA技术，则可以省区全部的栅极芯片，整个面板只需要数量很少的源极芯片即可，进一步降低面板的生产成本，提升市场竞争力。
但是采用三栅极架构之后，栅极线的数量增加为原来的3倍，每一级GOA电路所占的空间高度减小，按照现有的电路架构，设计时需要牺牲GOA区域的宽度，对现在流行的窄边框设计是非常不利的。
三栅极架构是现在低成本面板常用的一种架构，以FHD(Full High Definition)的面板为例，常规架构的面板公有栅极线1080条，数据线5760条，总共有信号线6840条，采用三栅极架构之后，公有栅极线3240条，数据线1920条，信号线共有5160条，比常规架构有所减少。如果采用三栅极搭配GOA的架构，则可以省去全部的栅极线，可以实现最大程度的降低面板生产成本。
栅极信号点Q(n)是GOA电路中非常重要的一个电位，当栅极信号点Q(n)为高电位时，GOA电路为打开和输出的状态，当栅极信号点Q(n)为低电位时，GOA电路处于关闭状态，此时的输出也为对应的栅极信号低电位。
参考图1，绘示现有技术的一种GOA电路10架构图。所述GOA电路10包含多个GOA单元15，相互级联为多级GOA单元15，其中第n级GOA单元15对对应的一扫描线G(n)充电，第n级GOA单元15包括时钟电路100、下拉电路200、自举电容电路300、上拉电路400以及下拉电路500。基本的架构是由所述时钟电路100、所述下拉电路200、所述自举电容电路300以及所述上拉电路400所组成的一基本架构，所述基本架构包括的4个TFT和1个电容，由于非晶硅的可靠性问题，除了基本的架构之外，还会需要用于辅助的所述下拉电路500。所述下拉电路500主要是起到辅助下拉的作用，在栅极线关闭期间确保所述GOA电路输出和栅极信号点Q(n)处于低电位状态，提高GOA电路工作时的可靠性。
现在的设计中，往往会设计两组辅助下拉电路，它们的作用是当GOA电路处于关闭状态时对栅极信号点Q(n)进行下拉，使它处于低电位的状态，保证面板的正常工作和提升信赖性。一般情况下，辅助下拉电路由较多的TFT组件构成，它们占用的空间也比较大，这是非常不利于窄边框设计的。关于两组辅助下拉电路的说明，请参考图2。
参考图2以及图3。图2，绘示现有技术的另一种GOA电路20架构图；图3，绘示图2的GOA电路的波形图。与图1的区别在于，所述下拉电路500包括第一辅助下拉电路510以及第二辅助下拉电路520，所述第一辅助下拉电路510以及所述第二辅助下拉电路520各别由两个低频信号LC1和LC2来控制，在不同的时间段内交替工作，确保栅极线G(n)关闭的时候GOA电路的输出端和栅极信号点Q(n)都能维持低电位。低频信号LC1和低频信号LC2两个信号反相，当低频信号LC1为高电位时，辅助下来工作由所述第一辅助下拉电路510进行，此时低频信号LC2为低电位，在若干个帧(Frame)的时间之后，低频信号LC1切换为低电位，低频信号LC2切换为高电位，辅助下拉的工作由所述第二辅助下拉电路520来进行。下拉电路500还可以采用其他的形式。图3是以6级CK信号搭配低频信号LC1以及低频信号LC2大约每100个帧切换一次，以产生相对应的栅极线G(n)信号。图2中的电路一个重要的特点是每一级GOA电路只对应一条栅极线G(n)的输出。当面板采用三栅极架构之后，由于栅极线的数量增加到原来的3倍，相应的每一级GOA电路所能占用的最大空间高度减少到之前的1/3，在设计时往往需要增加布线区域的宽度，这样会造成面板周边(Border)区变宽，对现在流行的窄边框设计是非常不利的。
因此，需要提出一种用于液晶显示设备的GOA电路，以克服上述问题。
 技术问题
本发明的目的在于提供一种用于液晶显示设备GOA电路。
 技术解决方案
为实现上述目的，本发明提供一种用于液晶显示设备的GOA电路，所述GOA电路包含多个GOA单元，相互级联为多级GOA单元，所述第n级GOA单元对应至少一级扫描线，所述至少一级扫描线包括第n级扫描线、第n+1级扫描线以及第n+2级扫描线充电，所述第n级GOA单元包括第一下拉维持电路、上拉电路、自举电容电路、下拉电路及时钟电路。
所述第一下拉维持电路，连接一栅极信号点。所述上拉电路，通过所述栅极信号点与所述第一下拉维持电路连接。所述自举电容电路,通过所述栅极信号点与所述上拉电路连接。所述下拉电路, 通过所述栅极信号点与所述自举电容电路连接。所述时钟电路, 通过所述栅极信号点与所述自举电容电路连接，并接收第一时钟信号。
所述第一下拉维持电路以及所述下拉电路共同连接至直流低压源。
所述时钟电路包括第一晶体管、第二晶体管、第三晶体管以及第四晶体管。
所述第一晶体管，其包括第一控制端连接所述栅极信号点、第一输入端连接所述第一时钟信号以及第一输出端输出第n级启动信号。所述第二晶体管，其包括第二控制端连接所述栅极信号点、第二输入端连接所述第一时钟信号以及第二输出端连接所述第n级扫描线。所述第三晶体管，其包括第三控制端连接所述栅极信号点、第三输入端连接所述第一时钟信号以及第三输出端连接所述第n+1级扫描线。所述第四晶体管，其包括第四控制端连接所述栅极信号点、第四输入端连接所述第一时钟信号以及第四输出端连接所述第n+2级扫描线。
在一优选实施例中，所述自举电容电路包括第一电容。所述第一电容，其两端连接所述栅极信号点以及所述第n级启动信号。
在一优选实施例中，所述上拉电路包括第五晶体管。所述第五晶体管，其包括第五控制端接收第n-3级启动信号、第五输入端连接所述第五控制端以及第五输出端连接所述栅极信号点。
在一优选实施例中，所述第一下拉维持电路包括第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管以及第十二晶体管。
所述第六晶体管，其包括第六控制端接收第n+3级启动信号、第六输入端连接所述直流低压源以及第六输出端连接所述栅极信号点。所述第七晶体管，其包括第七控制端连接所述栅极信号点、第七输入端连接所述直流低压源。所述第八晶体管，其包括第八控制端连接直流高压源、第八输出端连接所述第八控制端以及第八输入端连接所述第七晶体管的第七输出端。所述第九晶体管，其包括第九控制端连接所述栅极信号点、第九输入端连接所述直流低压源。所述第十晶体管，其包括第十控制端连接所述第七输出端、第十输入端连接所述第九晶体管的第九输出端以及第十输出端连接所述第八输出端。所述第十一晶体管，其包括第十一控制端连接所述第十输入端、第十一输入端连接所述直流低压源以及第十一输出端连接所述栅极信号点。所述第十二晶体管，其包括第十二控制端连接所述第十输入端、第十二输入端连接所述直流低压源以及第十二输出端输出所述第n级启动信号。
在一优选实施例中，所述下拉电路包括第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管、第十七晶体管、第十八晶体管、第十九晶体管、第二十晶体管以及第二十一晶体管。
所述第十三晶体管，其包括第十三控制端连接所述下拉维持电路、第十三输入端连接所述直流低压源以及第十三输出端连接第n级扫描线。所述第十四晶体管，其包括第十四控制端连接第二时钟信号、第十四输入端连接所述直流低压源以及第十四输出端连接第n级扫描线。所述第十五晶体管，其包括第十五控制端连接第四时钟信号、第十五输入端连接所述直流低压源以及第十五输出端连接第n级扫描线。所述第十六晶体管，其包括第十六控制端连接所述下拉维持电路、第十六输入端连接所述直流低压源以及第十六输出端连接第n+1级扫描线。所述第十七晶体管，其包括第十七控制端连接第三时钟信号、第十七输入端连接所述直流低压源以及第十四输出端连接第n+1级扫描线。所述第十八晶体管，其包括第十八控制端连接第五时钟信号、第十八输入端连接所述直流低压源以及第十八输出端连接第n+1级扫描线。所述第十九晶体管，其包括第十九控制端连接所述下拉维持电路、第十九输入端连接所述直流低压源以及第十九输出端连接第n+2级扫描线。所述第二十晶体管，其包括第二十控制端连接所述第四时钟信号、第二十输入端连接所述直流低压源以及第二十输出端连接第n+2级扫描线。所述第二十一晶体管，其包括第二十一控制端连接第六时钟信号、第二十一输入端连接所述直流低压源以及第二十一输出端连接第n+2级扫描线。
在一优选实施例中，所述用于液晶显示设备的GOA 电路还包括第二下拉维持电路，其包括第二十二晶体管以及第二十三晶体管。
所述第二十二晶体管，其包括第二十二控制端连接第四时钟信号、第二十二输入端连接所述直流低压源以及第二十二输出端连接所述栅极信号点。所述第二十三晶体管，其包括第二十三控制端连接所述第四时钟信号、第二十三输入端连接所述直流低压源以及第二十三输出端输出所述第n级启动信号。
在一优选实施例中，所述第一时钟信号、所述第二时钟信号以及所述第三时钟信号的周期相同且以1/3周期的时间差依序启动。
在一优选实施例中，所述第四时钟信号、所述第五时钟信号以及所述第六时钟信号分别与所述第一时钟信号、所述第二时钟信号以及所述第三时钟信号为反相信号。
为实现上述目的，本发明提供另一种用于液晶显示设备的GOA电路，其中所述GOA电路包含：多个GOA单元，相互级联为多级GOA单元，所述第n级GOA单元对应至少一级扫描线，所述至少一级扫描线包括第n+3级扫描线、第n+4级扫描线以及第n+5级扫描线充电，所述第n级GOA单元包括第一下拉维持电路、上拉电路、自举电容电路、下拉电路及时钟电路。
所述第一下拉维持电路，连接一栅极信号点。所述上拉电路，通过所述栅极信号点与所述第一下拉维持电路连接。所述自举电容电路,通过所述栅极信号点与所述上拉电路连接。所述下拉电路, 通过所述栅极信号点与所述自举电容电路连接。所述时钟电路, 通过所述栅极信号点与所述自举电容电路连接，并接收第四时钟信号。
所述第一下拉维持电路以及所述下拉电路共同连接至直流低压源。
所述时钟电路包括第一晶体管、第二晶体管、第三晶体管以及第四晶体管。
所述第一晶体管，其包括第一控制端连接所述栅极信号点、第一输入端连接所述第四时钟信号以及第一输出端输出第n+3级启动信号。所述第二晶体管，其包括第二控制端连接所述栅极信号点、第二输入端连接所述第四时钟信号以及第二输出端连接所述第n+3级扫描线。所述第三晶体管，其包括第三控制端连接所述栅极信号点、第三输入端连接所述第四时钟信号以及第三输出端连接所述第n+4级扫描线。所述第四晶体管，其包括第四控制端连接所述栅极信号点、第四输入端连接所述第四时钟信号以及第四输出端连接所述第n+5级扫描线。
在一优选实施例中，所述自举电容电路包括第一电容。所述第一电容，其两端连接所述栅极信号点以及所述第n+3级启动信号。
在一优选实施例中，所述上拉电路包括第五晶体管。所述第五晶体管，其包括第五控制端接收第n级启动信号、第五输入端连接所述第五控制端以及第五输出端连接所述栅极信号点。
在一优选实施例中，所述第一下拉维持电路包括第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管以及第十二晶体管。
所述第六晶体管，其包括第六控制端接收第n+6级启动信号、第六输入端连接所述直流低压源以及第六输出端连接所述栅极信号点。所述第七晶体管，其包括第七控制端连接所述栅极信号点、第七输入端连接所述直流低压源。所述第八晶体管，其包括第八控制端连接直流高压源、第八输出端连接所述第八控制端以及第八输入端连接所述第七晶体管的第七输出端。所述第九晶体管，其包括第九控制端连接所述栅极信号点、第九输入端连接所述直流低压源。所述第十晶体管，其包括第十控制端连接所述第七输出端、第十输入端连接所述第九晶体管的第九输出端以及第十输出端连接所述第八输出端。所述第十一晶体管，其包括第十一控制端连接所述第十输入端、第十一输入端连接所述直流低压源以及第十一输出端连接所述栅极信号点。所述第十二晶体管，其包括第十二控制端连接所述第十输入端、第十二输入端连接所述直流低压源以及第十二输出端输出所述第n+3级启动信号。
在一优选实施例中，所述下拉电路包括包括第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管、第十七晶体管、第十八晶体管、第十九晶体管、第二十晶体管以及第二十一晶体管。
所述第十三晶体管，其包括第十三控制端连接所述下拉维持电路、第十三输入端连接所述直流低压源以及第十三输出端连接第n+3级扫描线。所述第十四晶体管，其包括第十四控制端连接第一时钟信号、第十四输入端连接所述直流低压源以及第十四输出端连接第n+3级扫描线。所述第十五晶体管，其包括第十五控制端连接第三时钟信号、第十五输入端连接所述直流低压源以及第十五输出端连接第n+3级扫描线。所述第十六晶体管，其包括第十六控制端连接所述下拉维持电路、第十六输入端连接所述直流低压源以及第十六输出端连接第n+4级扫描线。所述第十七晶体管，其包括第十七控制端连接第二时钟信号、第十七输入端连接所述直流低压源以及第十四输出端连接第n+4级扫描线。所述第十八晶体管，其包括第十八控制端连接所述第四时钟信号、第十八输入端连接所述直流低压源以及第十八输出端连接第n+4级扫描线。所述第十九晶体管，其包括第十九控制端连接所述下拉维持电路、第十九输入端连接所述直流低压源以及第十九输出端连接第n+5级扫描线。所述第二十晶体管，其包括第二十控制端连接所述第三时钟信号、第二十输入端连接所述直流低压源以及第二十输出端连接第n+5级扫描线。所述第二十一晶体管，其包括第二十一控制端连接第五时钟信号、第二十一输入端连接所述直流低压源以及第二十一输出端连接第n+5级扫描线。
在一优选实施例中，所述用于液晶显示设备的GOA 电路还包括第二下拉维持电路，其包括第二十二晶体管以及第二十三晶体管。
所述第二十二晶体管，其包括第二十二控制端连接第一时钟信号、第二十二输入端连接所述直流低压源以及第二十二输出端连接所述栅极信号点。所述第二十三晶体管，其包括第二十三控制端连接所述第一时钟信号、第二十三输入端连接所述直流低压源以及第二十三输出端输出所述第n+3级启动信号。
在一优选实施例中，所述第一时钟信号、所述第二时钟信号以及所述第三时钟信号的周期相同且以1/3周期的时间差依序启动。
在一优选实施例中，所述第四时钟信号、所述第五时钟信号以及所述第六时钟信号分别与所述第一时钟信号、所述第二时钟信号以及所述第三时钟信号为反相信号。
 有益效果
本发明针对三栅极搭配GOA架构所遇到的这个问题，重新提出了一种GOA电路架构，即一级GOA电路可以对应3条栅极线的输出，这样GOA电路的级数可以缩减到现有的1/3，因为现有的架构是一级GOA电路只对应一条栅极线的输出。由于GOA电路数量减少，因而每一级电路有更大的设计空间高度，对窄边框设计非常有利。
 附图说明
图1，绘示现有技术的一种GOA电路架构图；
图2，绘示现有技术的另一种GOA电路架构图；
图3，绘示图2的GOA电路的波形图；
图4，绘示本发明的第一优选实施例的GOA电路架构图；
图5，绘示本发明的第二优选实施例的GOA电路架构图；
图6，绘示图4以及图5的GOA电路的波形图；
图7，绘示本发明的第三优选实施例的GOA电路架构图；
图8，绘示本发明的第四优选实施例的GOA电路架构图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
图4，绘示本发明的第一优选实施例的GOA电路30架构图。所述GOA电路30是用于液晶显示设备。所述GOA电路30包含多个GOA单元35，相互级联为多级GOA单元35，所述第n级GOA单元35对应至少一级扫描线，所述至少一级扫描线包括第n级扫描线G(n)、第n+1级扫描线G(n+1)以及第n+2级扫描线G(n+2)充电，所述第n级GOA单元35包括第一下拉维持电路500、上拉电路400、自举电容电路300、下拉电路200及时钟电路100。
所述第一下拉维持电路500，连接一栅极信号点Q(n)。所述上拉电路400，通过所述栅极信号点Q(n)与所述第一下拉维持电路500连接。所述自举电容电路300,通过所述栅极信号点Q(n)与所述上拉电路400连接。所述下拉电路200, 通过所述栅极信号点Q(n)与所述自举电容电路300连接。所述时钟电路100, 通过所述栅极信号点Q(n)与所述自举电容电路300连接，并接收第一时钟信号CK1。
所述第一下拉维持电路500以及所述下拉电路200共同连接至直流低压源。
所述时钟电路100包括第一晶体管T11、第二晶体管T21、第三晶体管T22以及第四晶体管T23。
所述第一晶体管T11，其包括第一控制端连接所述栅极信号点Q(n)、第一输入端连接所述第一时钟信号CK1以及第一输出端输出第n级启动信号ST(n)。所述第二晶体管T21，其包括第二控制端连接所述栅极信号点Q(n)、第二输入端连接所述第一时钟信号CK1以及第二输出端连接所述第n级扫描线G(n)。所述第三晶体管T22，其包括第三控制端连接所述栅极信号点Q(n)、第三输入端连接所述第一时钟信号CK1以及第三输出端连接所述第n+1级扫描线G(n+1)。所述第四晶体管T23，其包括第四控制端连接所述栅极信号点Q(n)、第四输入端连接所述第一时钟信号CK1以及第四输出端连接所述第n+2级扫描线G(n+2)。
所述自举电容电路300包括第一电容Cboost。所述第一电容Cboost，其两端连接所述栅极信号点Q(n)以及所述第n级启动信号ST(n)。
所述上拉电路400包括第五晶体管T5。所述第五晶体管T5，其包括第五控制端接收第n-3级启动信号ST(n-3)、第五输入端连接所述第五控制端以及第五输出端连接所述栅极信号点Q(n)。
所述第一下拉维持电路500包括第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T44以及第十三晶体管T45。
所述第六晶体管T6，其包括第六控制端接收第n+3级启动信号ST(n+3)、第六输入端连接所述直流低压源Vss以及第六输出端连接所述栅极信号点Q(n)。所述第七晶体管T7，其包括第七控制端连接所述栅极信号点Q(n)、第七输入端连接所述直流低压源Vss。所述第八晶体管T8，其包括第八控制端连接直流高压源VDD、第八输出端连接所述第八控制端以及第八输入端连接所述第七晶体管T7的第七输出端。所述第九晶体管T9，其包括第九控制端连接所述栅极信号点Q(n)、第九输入端连接所述直流低压源Vss。所述第十晶体管T10，其包括第十控制端连接所述第七输出端、第十输入端连接所述第九晶体管T9的第九输出端以及第十输出端连接所述第八输出端。所述第十一晶体管T44，其包括第十一控制端连接所述第十输入端、第十一输入端连接所述直流低压源Vss以及第十一输出端连接所述栅极信号点Q(n)。所述第十三晶体管T45，其包括第十二控制端连接所述第十输入端、第十二输入端连接所述直流低压源Vss以及第十二输出端输出所述第n级启动信号ST(n)。
所述下拉电路200包括第十三晶体管T41、第十四晶体管T311、第十五晶体管T312、第十六晶体管T42、第十七晶体管T321、第十八晶体管T322、第十九晶体管T43、第二十晶体管T331以及第二十一晶体管T332。
所述第十三晶体管T41，其包括第十三控制端连接所述第一下拉维持电路、第十三输入端连接所述直流低压源Vss以及第十三输出端连接第n级扫描线G(n)。所述第十四晶体管T311，其包括第十四控制端连接第二时钟信号CK2、第十四输入端连接所述直流低压源Vss以及第十四输出端连接第n级扫描线G(n)。所述第十五晶体管T312，其包括第十五控制端连接第四时钟信号CK4、第十五输入端连接所述直流低压源Vss以及第十五输出端连接第n级扫描线G(n)。所述第十六晶体管T42，其包括第十六控制端连接所述第一下拉维持电路、第十六输入端连接所述直流低压源Vss以及第十六输出端连接第n+1级扫描线G(n+1)。所述第十七晶体管T321，其包括第十七控制端连接第三时钟信号CK3、第十七输入端连接所述直流低压源Vss以及第十四输出端连接第n+1级扫描线G(n+1)。所述第十八晶体管T322，其包括第十八控制端连接第五时钟信号CK5、第十八输入端连接所述直流低压源Vss以及第十八输出端连接第n+1级扫描线G(n+1)。所述第十九晶体管T43，其包括第十九控制端连接所述第一下拉维持电路500、第十九输入端连接所述直流低压源Vss以及第十九输出端连接第n+2级扫描线G(n+2)。所述第二十晶体管T331，其包括第二十控制端连接所述第四时钟信号CK4、第二十输入端连接所述直流低压源Vss以及第二十输出端连接第n+2级扫描线G(n+2)。所述第二十一晶体管T332，其包括第二十一控制端连接第六时钟信号CK6、第二十一输入端连接所述直流低压源Vss以及第二十一输出端连接第n+2级扫描线G(n+2)。
其中所述第一晶体管T11、所述第二晶体管T21、所述第三晶体管T22以及所述第四晶体管T23的输入端均与第一时钟信号CK1连接，控制端(即栅极)全部和栅极信号点Q(n)连接。其中所述第一晶体管T11的作用是为下一级GOA电路输出第n级启动信号ST(n)（Start Pulse），所述第二晶体管T21、所述第三晶体管T22以及所述第四晶体管T23分别对应了本级的3条栅极线G(n)，G(n+1)和G(n+2)的输出。对于所述第n级扫描线G(n)来讲，所述第十四晶体管T311和所述第十五晶体管T312的控制端(即栅极)分别由所述第二时钟信号CK2和所述第四时钟信号CK4控制，它们负责在不同的时间段内对所述第n级扫描线G(n)的信号进行下拉，由于所述第二晶体管T21、所述第三晶体管T22以及所述第四晶体管T23连接所述第一时钟信号CK1之后的输出都是相同的，而三条栅极线G(n)，G(n+1)和G(n+2)的栅极脉冲(Gate Pulse)信号相互之间没有重迭的部分，因此需要在合适的时间段内对所述第二晶体管T21、所述第三晶体管T22以及所述第四晶体管T23输出的信号进行下拉，其中所述第n级扫描线G(n)的下拉前面已经介绍了，所述第n+1级扫描线G(n+1)的下拉由所述第十七晶体管T321以及所述第十八晶体管T322完成，它们分别由所述第三时钟信号CK3和所述第五时钟信号CK5控制，所述第n+2级扫描线G(n+2)的下拉由所述第二十晶体管T331以及所述第二十一晶体管T332完成，它们分别由所述第四时钟信号CK4和所述第六时钟信号CK6控制。它们和所述第二晶体管T21、所述第三晶体管T22以及所述第四晶体管T23共同作用，保证所述级GOA电路35对应的3条栅极线能够输出正确的波形。所述第十三晶体管T41、所述第十六晶体管T42以及所述第十九晶体管T43也是用于下拉3条栅极线，它们的作用是当所述级GOA电路不工作时，即所述级电路的所述栅极信号点Q(n)为低电位时，对所述第n级扫描线G(n)、所述第n+1级扫描线G(n+1)以及所述第n+2级扫描线G(n+2)的信号进行下拉，保证它们的输出处于低电位。当所述级GOA电路输出时，即栅极信号点Q(n)位高电位时，所述第十三晶体管T41、所述第十六晶体管T42以及所述第十九晶体管T43的控制端(即栅极)为低电位，它们处于关闭的状态，对所述第n级扫描线G(n)、所述第n+1级扫描线G(n+1)以及所述第n+2级扫描线G(n+2)的信号输出没有任何影响。所述第十一晶体管T44以及所述第十三晶体管T41也是用于下拉信号，它们的作用是当所述级GOA电路35不输出时，保证启动信号ST和所述栅极信号点Q(n)维持在低电位。
采用本优选实施例的GOA电路35之后，由于每一级GOA电路35可以输出3条栅极线的信号，所以整个GOA电路布线的高度增加，因此可以将它的宽度缩窄，对窄边框设计非常有利。另外，本优选实施例的GOA电路35每一级共有21个晶体管，相应的，如果采用图2的现有技术的GOA电路25，3条栅极线需要3级GOA电路25，共有51个TFT，因而本优选实施例的GOA电路35所需的空间相比现有技术的GOA电路25也有较大幅度的压缩。
图5，绘示本发明的第二优选实施例的GOA电路40架构图。本优选实施例与第一优选实施例的区别在于连接的讯号不同。说明如下：
所述启动信号ST分别增加三级，即n-3改为n，n改为n+3以及n+3改为n+6。
所述第一晶体管T11、所述第二晶体管T21、所述第三晶体管T22以及所述第四晶体管T23的输入端改为连接第四时钟信号CK4。所述第二晶体管T21、所述第三晶体管T22以及所述第四晶体管T23的输出端改为分别连接第n+3级扫描线G(n+3)、第n+4级扫描线G(n+4)以及第n+5级扫描线G(n+5)。
所述第十四晶体管T311的控制端改为连接第一时钟信号CK1、所述第十五晶体管T312的控制端改为连接第三时钟信号CK3。所述第十四晶体管T311以及所述第十五晶体管T312的输出端改为连接所述第n+3级扫描线G(n+3)。
所述第十七晶体管T321的控制端改为连接第二时钟信号CK2、所述第十八晶体管T322的控制端改为连接第四时钟信号CK4。所述第十七晶体管T321以及所述第十八晶体管T322的输出端改为连接所述第n+4级扫描线G(n+4)。
所述第二十晶体管T331的控制端改为连接第三时钟信号CK3、所述第二十一晶体管T332的控制端改为连接第五时钟信号CK5。所述第二十晶体管T331以及所述第二十一晶体管T332的输出端改为连接所述第n+5级扫描线G(n+5)。
与第一优选实施例不同的是，第一优选实施例是用于驱动奇数级的扫描线；第二优选实施例是用于驱动偶数级的扫描线。
图6，绘示图4以及图5的GOA电路的波形图。如图所示，所述第一时钟信号CK1、所述第二时钟信号CK2以及所述第三时钟信号CK3的周期相同且以1/3周期的时间差依序启动，所述第四时钟信号CK4、所述第五时钟信号CK5以及所述第六时钟信号CK6分别与所述第一时钟信号CK1、所述第二时钟信号CK2以及所述第三时钟信号CK3为反相信号，因此可以得到依序启动的扫描线信号(第n级至第n+5级)。
图7，绘示本发明的第三优选实施例的GOA电路50架构图。本优选实施例与第一优选实施例的区别在于增加第二下拉维持电路，其包括第二十二晶体管T91以及第二十三晶体管T92。
所述第二十二晶体管T91，其包括第二十二控制端连接第四时钟信号CK4、第二十二输入端连接所述直流低压源Vss以及第二十二输出端连接所述栅极信号点Q(n)。所述第二十三晶体管T92，其包括第二十三控制端连接所述第四时钟信号CK4、第二十三输入端连接所述直流低压源Vss以及第二十三输出端输出所述第n级启动信号ST(n)。
本优选实施例的GOA电路55每一级采用了两组下拉维持电路(500,600)，这两组下拉维持电路(500,600)在不同的时间段进行下拉，这样可以防止下拉维持电路(500,600)的晶体管长时间受到压力(Stress)，电性发生漂移而导致GOA电路55工作失效，提升了面板的可靠性。
当本级GOA电路55在输出时，即栅极信号点Q(n)位于高电位时，两组下拉维持电路(500,600)都不工作，保证对应的3条栅极线输出正确的波形。当本级GOA电路55不输出，栅极信号点Q(n)位于低电位时，两组下拉维持电路(500,600)交替工作进行下拉。当所述第一时钟信号CK1为高电位时，所述第四时钟信号CK4为低电位，所述第一时钟信号CK1通过所述第二晶体管T21、所述第三晶体管T22以及所述第四晶体管T23分别与所述第n级扫描线G(n)、所述第n+1级扫描线G(n+1)以及所述第n+2级扫描线G(n+2)连接，为了提高GOA电路的可靠性需要对所述第n级扫描线G(n)、所述第n+1级扫描线G(n+1)以及所述第n+2级扫描线G(n+2)进行下拉，同时也需要对栅极信号点Q(n)和启动信号ST下拉，这时的工作模式和第一优选实施例中的GOA电路是相同的。当所述第一时钟信号CK1为低电位时，所述第四时钟信号CK4为高电位，它控制所述第二十二晶体管T91和所述第二十三晶体管T92打开，对栅极信号点Q(n)和启动信号ST下拉，此时的所述第一时钟信号CK1为低电位，所以即使所述第二晶体管T21、所述第三晶体管T22以及所述第四晶体管T23发生了漏电，对应的所述第n级扫描线G(n)、所述第n+1级扫描线G(n+1)以及所述第n+2级扫描线G(n+2)也会和所述第一时钟信号CK1的电位相同，为低电位，不影响所述第n级扫描线G(n)、所述第n+1级扫描线G(n+1)以及所述第n+2级扫描线G(n+2)三条栅极线的输出，因此此时它们不需要进行下拉动作。
图8，绘示本发明的第四优选实施例的GOA电路60架构图。本优选实施例与第三优选实施例的区别在于连接的讯号不同。说明如下：
所述启动信号ST分别增加三级，即n-3改为n，n改为n+3以及n+3改为n+6。
所述第一晶体管T11、所述第二晶体管T21、所述第三晶体管T22以及所述第四晶体管T23的输入端改为连接第四时钟信号CK4。所述第二晶体管T21、所述第三晶体管T22以及所述第四晶体管T23的输出端改为分别连接第n+3级扫描线G(n+3)、第n+4级扫描线G(n+4)以及第n+5级扫描线G(n+5)。
所述第十四晶体管T311的控制端改为连接第一时钟信号CK1、所述第十五晶体管T312的控制端改为连接第三时钟信号CK3。所述第十四晶体管T311以及所述第十五晶体管T312的输出端改为连接所述第n+3级扫描线G(n+3)。
所述第十七晶体管T321的控制端改为连接第二时钟信号CK2、所述第十八晶体管T322的控制端改为连接第四时钟信号CK4。所述第十七晶体管T321以及所述第十八晶体管T322的输出端改为连接所述第n+4级扫描线G(n+4)。
所述第二十晶体管T331的控制端改为连接第三时钟信号CK3、所述第二十一晶体管T332的控制端改为连接第五时钟信号CK5。所述第二十晶体管T331以及所述第二十一晶体管T332的输出端改为连接所述第n+5级扫描线G(n+5)。
所述第二十二晶体管T91以及所述第二十三晶体管T92的控制端改为连接第一时钟信号CK1。
与第三优选实施例不同的是，第三优选实施例是用于驱动奇数级的扫描线；第四优选实施例是用于驱动偶数级的扫描线。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (17)

  1. 一种用于液晶显示设备的GOA 电路，其中所述GOA电路包含：多个GOA单元，相互级联为多级GOA单元，所述第n级GOA单元对应至少一级扫描线，所述至少一级扫描线包括第n级扫描线、第n+1级扫描线以及第n+2级扫描线充电，所述第n级GOA单元包括：
    第一下拉维持电路，连接一栅极信号点;
    上拉电路，通过所述栅极信号点与所述第一下拉维持电路连接;
    自举电容电路,通过所述栅极信号点与所述上拉电路连接;
    下拉电路, 通过所述栅极信号点与所述自举电容电路连接;以及
    时钟电路, 通过所述栅极信号点与所述自举电容电路连接，并接收第一时钟信号;
    其中所述第一下拉维持电路以及所述下拉电路共同连接至一直流低压源；
    所述时钟电路包括：
    第一晶体管，其包括第一控制端连接所述栅极信号点、第一输入端连接所述第一时钟信号以及第一输出端输出第n级启动信号；
    第二晶体管，其包括第二控制端连接所述栅极信号点、第二输入端连接所述第一时钟信号以及第二输出端连接所述第n级扫描线；
    第三晶体管，其包括第三控制端连接所述栅极信号点、第三输入端连接所述第一时钟信号以及第三输出端连接所述第n+1级扫描线；
    第四晶体管，其包括第四控制端连接所述栅极信号点、第四输入端连接所述第一时钟信号以及第四输出端连接所述第n+2级扫描线；
    所述下拉电路包括：
    第十三晶体管，其包括第十三控制端连接所述第一下拉维持电路、第十三输入端连接所述直流低压源以及第十三输出端连接第n级扫描线；
    第十四晶体管，其包括第十四控制端连接第二时钟信号、第十四输入端连接所述直流低压源以及第十四输出端连接第n级扫描线；
    第十五晶体管，其包括第十五控制端连接第四时钟信号、第十五输入端连接所述直流低压源以及第十五输出端连接第n级扫描线；
    第十六晶体管，其包括第十六控制端连接所述第一下拉维持电路、第十六输入端连接所述直流低压源以及第十六输出端连接第n+1级扫描线；
    第十七晶体管，其包括第十七控制端连接第三时钟信号、第十七输入端连接所述直流低压源以及第十四输出端连接第n+1级扫描线；
    第十八晶体管，其包括第十八控制端连接第五时钟信号、第十八输入端连接所述直流低压源以及第十八输出端连接第n+1级扫描线；
    第十九晶体管，其包括第十九控制端连接所述第一下拉维持电路、第十九输入端连接所述直流低压源以及第十九输出端连接第n+2级扫描线；
    第二十晶体管，其包括第二十控制端连接所述第四时钟信号、第二十输入端连接所述直流低压源以及第二十输出端连接第n+2级扫描线；
    第二十一晶体管，其包括第二十一控制端连接第六时钟信号、第二十一输入端连接所述直流低压源以及第二十一输出端连接第n+2级扫描线；
    其中所述第一时钟信号、所述第二时钟信号以及所述第三时钟信号的周期相同且以1/3周期的时间差依序启动，所述第四时钟信号、所述第五时钟信号以及所述第六时钟信号分别与所述第一时钟信号、所述第二时钟信号以及所述第三时钟信号为反相信号。
  2. 一种用于液晶显示设备的GOA 电路，其中所述GOA电路包含：多个GOA单元，相互级联为多级GOA单元，所述第n级GOA单元对应至少一级扫描线，所述至少一级扫描线包括第n级扫描线、第n+1级扫描线以及第n+2级扫描线充电，所述第n级GOA单元包括：
    第一下拉维持电路，连接一栅极信号点;
    上拉电路，通过所述栅极信号点与所述第一下拉维持电路连接;
    自举电容电路,通过所述栅极信号点与所述上拉电路连接;
    下拉电路, 通过所述栅极信号点与所述自举电容电路连接;以及
    时钟电路, 通过所述栅极信号点与所述自举电容电路连接，并接收第一时钟信号;
    其中所述第一下拉维持电路以及所述下拉电路共同连接至一直流低压源；
    所述时钟电路包括：
    第一晶体管，其包括第一控制端连接所述栅极信号点、第一输入端连接所述第一时钟信号以及第一输出端输出第n级启动信号；
    第二晶体管，其包括第二控制端连接所述栅极信号点、第二输入端连接所述第一时钟信号以及第二输出端连接所述第n级扫描线；
    第三晶体管，其包括第三控制端连接所述栅极信号点、第三输入端连接所述第一时钟信号以及第三输出端连接所述第n+1级扫描线；
    第四晶体管，其包括第四控制端连接所述栅极信号点、第四输入端连接所述第一时钟信号以及第四输出端连接所述第n+2级扫描线。
  3. 如权利要求2所述的用于液晶显示设备的GOA 电路，其中所述自举电容电路包括：
    第一电容，其两端连接所述栅极信号点以及所述第n级启动信号。
  4. 如权利要求2所述的用于液晶显示设备的GOA 电路，其中所述上拉电路包括：
    第五晶体管，其包括第五控制端接收第n-3级启动信号、第五输入端连接所述第五控制端以及第五输出端连接所述栅极信号点。
  5. 如权利要求2所述的用于液晶显示设备的GOA 电路，其中所述第一下拉维持电路包括：
    第六晶体管，其包括第六控制端接收第n+3级启动信号、第六输入端连接所述直流低压源以及第六输出端连接所述栅极信号点；
    第七晶体管，其包括第七控制端连接所述栅极信号点、第七输入端连接所述直流低压源；
    第八晶体管，其包括第八控制端连接直流高压源、第八输出端连接所述第八控制端以及第八输入端连接所述第七晶体管的第七输出端；
    第九晶体管，其包括第九控制端连接所述栅极信号点、第九输入端连接所述直流低压源；
    第十晶体管，其包括第十控制端连接所述第七输出端、第十输入端连接所述第九晶体管的第九输出端以及第十输出端连接所述第八输出端；
    第十一晶体管，其包括第十一控制端连接所述第十输入端、第十一输入端连接所述直流低压源以及第十一输出端连接所述栅极信号点；
    第十二晶体管，其包括第十二控制端连接所述第十输入端、第十二输入端连接所述直流低压源以及第十二输出端输出所述第n级启动信号。
  6. 如权利要求2所述的用于液晶显示设备的GOA 电路，其中所述下拉电路包括：
    第十三晶体管，其包括第十三控制端连接所述第一下拉维持电路、第十三输入端连接所述直流低压源以及第十三输出端连接第n级扫描线；
    第十四晶体管，其包括第十四控制端连接第二时钟信号、第十四输入端连接所述直流低压源以及第十四输出端连接第n级扫描线；
    第十五晶体管，其包括第十五控制端连接第四时钟信号、第十五输入端连接所述直流低压源以及第十五输出端连接第n级扫描线；
    第十六晶体管，其包括第十六控制端连接所述第一下拉维持电路、第十六输入端连接所述直流低压源以及第十六输出端连接第n+1级扫描线；
    第十七晶体管，其包括第十七控制端连接第三时钟信号、第十七输入端连接所述直流低压源以及第十四输出端连接第n+1级扫描线；
    第十八晶体管，其包括第十八控制端连接第五时钟信号、第十八输入端连接所述直流低压源以及第十八输出端连接第n+1级扫描线；
    第十九晶体管，其包括第十九控制端连接所述第一下拉维持电路、第十九输入端连接所述直流低压源以及第十九输出端连接第n+2级扫描线；
    第二十晶体管，其包括第二十控制端连接所述第四时钟信号、第二十输入端连接所述直流低压源以及第二十输出端连接第n+2级扫描线；
    第二十一晶体管，其包括第二十一控制端连接第六时钟信号、第二十一输入端连接所述直流低压源以及第二十一输出端连接第n+2级扫描线。
  7. 如权利要求2所述的用于液晶显示设备的GOA 电路，其中还包括第二下拉维持电路，其包括：
    第二十二晶体管，其包括第二十二控制端连接第四时钟信号、第二十二输入端连接所述直流低压源以及第二十二输出端连接所述栅极信号点；
    第二十三晶体管，其包括第二十三控制端连接所述第四时钟信号、第二十三输入端连接所述直流低压源以及第二十三输出端输出所述第n级启动信号。
  8. 如权利要求6所述的用于液晶显示设备的GOA 电路，其中所述第一时钟信号、所述第二时钟信号以及所述第三时钟信号的周期相同且以1/3周期的时间差依序启动。
  9. 如权利要求6所述的用于液晶显示设备的GOA 电路，其中所述第四时钟信号、所述第五时钟信号以及所述第六时钟信号分别与所述第一时钟信号、所述第二时钟信号以及所述第三时钟信号为反相信号。
  10. 一种用于液晶显示设备的GOA 电路，其中所述GOA电路包含：多个GOA单元，相互级联为多级GOA单元，所述第n级GOA单元对应至少一级扫描线，所述至少一级扫描线包括第n+3级扫描线、第n+4级扫描线以及第n+5级扫描线充电，所述第n级GOA单元包括：
    第一下拉维持电路，连接一栅极信号点;
    上拉电路，通过所述栅极信号点与所述第一下拉维持电路连接;
    自举电容电路,通过所述栅极信号点与所述上拉电路连接;
    下拉电路, 通过所述栅极信号点与所述自举电容电路连接;以及
    时钟电路, 通过所述栅极信号点与所述自举电容电路连接，并接收第四时钟信号;
    其中
    所述第一下拉维持电路以及所述下拉电路共同连接至一直流低压源；
    所述时钟电路包括：
    第一晶体管，其包括第一控制端连接所述栅极信号点、第一输入端连接所述第四时钟信号以及第一输出端输出第n+3级启动信号；
    第二晶体管，其包括第二控制端连接所述栅极信号点、第二输入端连接所述第四时钟信号以及第二输出端连接所述第n+4级扫描线；
    第三晶体管，其包括第三控制端连接所述栅极信号点、第三输入端连接所述第四时钟信号以及第三输出端连接所述第n+5级扫描线；
    第四晶体管，其包括第四控制端连接所述栅极信号点、第四输入端连接所述第四时钟信号以及第四输出端连接所述第n+5级扫描线。
  11. 如权利要求10所述的用于液晶显示设备的GOA 电路，其中所述自举电容电路包括：
    第一电容，其两端连接所述栅极信号点以及所述第n+3级启动信号。
  12. 如权利要求10所述的用于液晶显示设备的GOA 电路，其中所述上拉电路包括：
    第五晶体管，其包括第五控制端接收第n级启动信号、第五输入端连接所述第五控制端以及第五输出端连接所述栅极信号点。
  13. 如权利要求10所述的用于液晶显示设备的GOA 电路，其中所述第一下拉维持电路包括：
    第六晶体管，其包括第六控制端接收第n+6级启动信号、第六输入端连接所述直流低压源以及第六输出端连接所述栅极信号点；
    第七晶体管，其包括第七控制端连接所述栅极信号点、第七输入端连接所述直流低压源；
    第八晶体管，其包括第八控制端连接直流高压源、第八输出端连接所述第八控制端以及第八输入端连接所述第七晶体管的第七输出端；
    第九晶体管，其包括第九控制端连接所述栅极信号点、第九输入端连接所述直流低压源；
    第十晶体管，其包括第十控制端连接所述第七输出端、第十输入端连接所述第九晶体管的第九输出端以及第十输出端连接所述第八输出端；
    第十一晶体管，其包括第十一控制端连接所述第十输入端、第十一输入端连接所述直流低压源以及第十一输出端连接所述栅极信号点；
    第十二晶体管，其包括第十二控制端连接所述第十输入端、第十二输入端连接所述直流低压源以及第十二输出端输出所述第n+3级启动信号。
  14. 如权利要求10所述的用于液晶显示设备的GOA 电路，其中所述下拉电路包括：
    第十三晶体管，其包括第十三控制端连接所述第一下拉维持电路、第十三输入端连接所述直流低压源以及第十三输出端连接第n+3级扫描线；
    第十四晶体管，其包括第十四控制端连接第一时钟信号、第十四输入端连接所述直流低压源以及第十四输出端连接第n+3级扫描线；
    第十五晶体管，其包括第十五控制端连接第三时钟信号、第十五输入端连接所述直流低压源以及第十五输出端连接第n+3级扫描线；
    第十六晶体管，其包括第十六控制端连接所述第一下拉维持电路、第十六输入端连接所述直流低压源以及第十六输出端连接第n+4级扫描线；
    第十七晶体管，其包括第十七控制端连接第二时钟信号、第十七输入端连接所述直流低压源以及第十四输出端连接第n+4级扫描线；
    第十八晶体管，其包括第十八控制端连接所述第四时钟信号、第十八输入端连接所述直流低压源以及第十八输出端连接第n+4级扫描线；
    第十九晶体管，其包括第十九控制端连接所述第一下拉维持电路、第十九输入端连接所述直流低压源以及第十九输出端连接第n+5级扫描线；
    第二十晶体管，其包括第二十控制端连接所述第三时钟信号、第二十输入端连接所述直流低压源以及第二十输出端连接第n+5级扫描线；
    第二十一晶体管，其包括第二十一控制端连接第五时钟信号、第二十一输入端连接所述直流低压源以及第二十一输出端连接第n+5级扫描线。
  15. 如权利要求10所述的用于液晶显示设备的GOA 电路，其中还包括一第二下拉维持电路，其包括：
    第二十二晶体管，其包括第二十二控制端连接第一时钟信号、第二十二输入端连接所述直流低压源以及第二十二输出端连接所述栅极信号点；
    第二十三晶体管，其包括第二十三控制端连接所述第一时钟信号、第二十三输入端连接所述直流低压源以及第二十三输出端输出所述第n+3级启动信号。
  16. 如权利要求14所述的用于液晶显示设备的GOA 电路，其中所述第一时钟信号、所述第二时钟信号以及所述第三时钟信号的周期相同且以1/3周期的时间差依序启动。
  17. 如权利要求14所述的用于液晶显示设备的GOA 电路，其中所述第四时钟信号、所述第五时钟信号以及所述第六时钟信号分别与所述第一时钟信号、所述第二时钟信号以及所述第三时钟信号为反相信号。
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