WO2017113437A1 - 栅极驱动电路及液晶显示器 - Google Patents

栅极驱动电路及液晶显示器 Download PDF

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Publication number
WO2017113437A1
WO2017113437A1 PCT/CN2016/070601 CN2016070601W WO2017113437A1 WO 2017113437 A1 WO2017113437 A1 WO 2017113437A1 CN 2016070601 W CN2016070601 W CN 2016070601W WO 2017113437 A1 WO2017113437 A1 WO 2017113437A1
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Prior art keywords
transistor
signal
gate
source
drain
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PCT/CN2016/070601
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English (en)
French (fr)
Inventor
杜鹏
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深圳市华星光电技术有限公司
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Priority to US14/908,403 priority Critical patent/US10096293B2/en
Publication of WO2017113437A1 publication Critical patent/WO2017113437A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0213—Addressing of scan or signal lines controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to a liquid crystal scanning driving circuit, and more particularly to a GOA for a liquid crystal display (Gate Driver on Array, array substrate line scan drive) circuit and liquid crystal display.
  • a liquid crystal display Gate Driver on Array, array substrate line scan drive
  • GOA Gate driver On
  • Array technology not only saves the cost of the gate driver chip, but also reduces the width of the panel frame, which is in line with the trend of the narrow bezel panel.
  • the HD resolution (1280*720) panel and the clock signal used by the GOA circuit are Four, and full HD resolution (1920*1080) panels or higher resolution panels often require six or eight clock pulses.
  • the clock pulse signal is a high-frequency signal that frequently switches between high and low potentials, and the power consumption of the gate drive circuit is related to the power consumption of the transistor through-current through-current. Since the power consumption caused by the transistor crossing conduction current is proportional to the square of the clock of the clock pulse switching, the more the number of clock signals and the higher the clock, the greater the power consumption of the entire gate driving circuit.
  • the basic structure of the conventional single-stage GOA circuit 100 is composed of four transistors and one capacitor.
  • the GOA circuit of this stage outputs a gate signal G(n), A level pass signal will be provided to the next stage GOA circuit as its start signal ST(n).
  • the GOA circuit 100 includes a main drive circuit 120 and an output circuit 150.
  • the main drive circuit 120 includes a transistor T1 and a transistor T2.
  • the transistor T1 operates in an on state in response to the start signal ST(n-2).
  • the transistor T2 turns on the voltage source Vss while receiving the gate signal G(n+2) to reset the charging signal Q(n).
  • the output circuit 150 includes a transistor T3, a transistor T4, And transistor T8.
  • the transistor T4 operates in an on state in response to the charging signal Q(n).
  • the clock pulse signal CK is turned on to the drain and the gate signal G(n) is output.
  • the transistor T8 turns on the voltage source Vss to reset the gate signal G(n) when receiving the gate signal G(n+2).
  • the auxiliary pull-down circuit 15 mainly ensures the potential state of the GOA circuit 100 output and the node Q in the off period during the gate line off period, that is, has the function of the pull-down sustain circuit, and improves the reliability of the GOA circuit 100 during operation.
  • FIG. 2 illustrates a schematic diagram of a conventional six phase driven dual driver stage GOA circuit.
  • the first driver stage GOA circuit 210 responds to the two gate line signals G[N-1], G[N+5]
  • Three gate line signals G[N], G[N+1] and G[N+2] are generated with the six input clock pulse signals CK1, CK2, CK3, XCK1, XCK2, XCK3.
  • FIG. 3 illustrates a timing chart when the GOA circuit of FIG. 2 operates.
  • the total width of the signal of the gate line signals G[N] ⁇ G[N+5] and the clock signals CK1 ⁇ CK3 and XCK1 ⁇ XCK3 is equal to 3W, where W is the completion of charging on one scan line. time.
  • the clock signal is the main source of power consumption for the entire GOA circuit
  • the power consumption of the general signal is proportional to the square of the voltage of the clock signal. Therefore, the greater the number of clock signals, the greater the power consumption of the circuit. This problem is particularly serious at high times, and the number of signals also leads to an increase in the cost of the drive circuit, which is very unfavorable for the market competitiveness of the product.
  • Another object of the present invention is to provide a gate driving circuit for driving a display panel.
  • the gate drive circuit passes three signals, That is, the first-level transmission signal and the two mutually inverted clock signals jointly control the potential of the node Q, and control the output of the plurality of gate line signals through the plurality of clock pulse signals, thereby reducing the clock required by the existing scan driving circuit.
  • the number of pulse signals thereby reducing the overall power consumption of the GOA circuit.
  • a gate driving circuit includes a multi-level array substrate line scan driving (GOA) unit,
  • Each of the GOA units includes: a main driving circuit including a first transistor, a second transistor, and a third transistor, and having a first control node and a second control node, the first transistor having a source, a drain, and a gate pole,
  • the second transistor and the third transistor respectively have a source, a drain and a gate, respectively receiving a start signal at a source of the first transistor and receiving a first trigger clock signal at a gate of the first transistor, And responding to the input of the start signal, the first trigger clock signal, and the second trigger clock signal to generate at the first control node when the second transistor's gate receives the second trigger clock signal Charging signal, And generating a control signal at the second control node;
  • the first-stage signal output circuit includes a fourth transistor and a fifth transistor, wherein the fourth transistor is configured to receive the charging signal to output a first-level signal.
  • the fifth transistor is configured to receive the control signal to turn off the level transmission signal; and a plurality of gate output circuits, each of the gate output circuits includes a sixth transistor and a seventh transistor, The sixth transistor is configured to receive the charging signal to output a gate line signal, and the seventh transistor is configured to receive the control signal to turn off the gate line signal.
  • the start signal is a level transmission signal transmitted by a GOA unit of a higher level, Or it is a start signal provided by a scan drive control chip.
  • the first trigger clock signal and the second trigger clock signal are inverted from each other.
  • the main driving circuit further includes an eighth transistor, a ninth transistor, and a tenth transistor,
  • the first transistor operates in an on state in response to the received first trigger clock signal, and causes the eighth transistor, the ninth transistor, and the tenth transistor to also operate in a conductive state
  • the charging signal is generated at a first control node and generated at a second control node.
  • each of the sixth transistors of each of the gate output circuits has a source, a drain, and a gate, respectively.
  • Each source is electrically connected to a different clock signal, and each gate is connected to the charging signal.
  • Each drain sequentially outputs a gate line signal.
  • a seventh transistor of each of the gate output circuits has a source, a drain and a gate, and a source of each of the seventh transistors is electrically connected to a sixth transistor of each gate output circuit. a drain, the drain of each seventh transistor is electrically connected to the first voltage source, The gate of each seventh transistor receives the control signal, and when each of the seventh transistors sequentially operates in a conducting state in response to the received control signal, Each of the seventh transistors turns on the first voltage source to cause the gate line signal to be turned off.
  • the fourth transistor of the level signal output circuit has a source, a drain and a gate. a source of the fourth transistor is electrically connected to the second trigger clock signal, and a gate of the fourth transistor is connected to the charging signal, When the fourth transistor of the level signal output circuit operates in an on state in response to the received second trigger clock signal, the drain of the fourth transistor of the level signal output circuit outputs the level signal.
  • the fifth transistor of the level signal output circuit has a source, a drain and a gate, and a source thereof is electrically connected to a drain of the first transistor of the level signal output circuit, The drain is electrically connected to the first voltage source, The gate receives the control signal, and when the fifth transistor operates in an on state in response to the received control signal, the fifth transistor turns on the first voltage source to cause the level signal to be turned off.
  • each of the single-stage gate driving circuits further includes a forward scan transistor and a reverse scan transistor for receiving a forward scan control signal and a reverse scan control signal, respectively, to control the cascade
  • the gate drive circuit operates in a forward scan or a reverse scan.
  • a liquid crystal display includes a gate driving circuit including a multi-level array substrate line scan driving (GOA) unit,
  • GOA multi-level array substrate line scan driving
  • Each of the GOA units includes: a main driving circuit including a first transistor, a second transistor, and a third transistor, and having a first control node and a second control node, the first transistor having a source, a drain, and a gate pole,
  • the second transistor and the third transistor respectively have a source, a drain and a gate, respectively receiving a start signal at a source of the first transistor and receiving a first trigger clock signal at a gate of the first transistor, And responding to the input of the start signal, the first trigger clock signal, and the second trigger clock signal to generate at the first control node when the second transistor's gate receives the second trigger clock signal Charging signal, And generating a control signal at the second control node;
  • the first-stage signal output circuit includes a fourth transistor and a fifth transistor, wherein the fourth transistor is configured to receive the charging signal
  • the fifth transistor is configured to receive the control signal to turn off the level transmission signal; and a plurality of gate output circuits, each of the gate output circuits includes a sixth transistor and a seventh transistor, The sixth transistor is configured to receive the charging signal to output a gate line signal, and the seventh transistor is configured to receive the control signal to turn off the gate line signal.
  • the start signal is a level transmission signal transmitted by a GOA unit of a higher level, Or it is a start signal provided by a scan drive control chip.
  • the first trigger clock signal and the second trigger clock signal are inverted from each other.
  • the main driving circuit further includes an eighth transistor, a ninth transistor, and a tenth transistor,
  • the first transistor operates in an on state in response to the received first trigger clock signal, and causes the eighth transistor, the ninth transistor, and the tenth transistor to also operate in a conductive state
  • the charging signal is generated at a first control node and generated at a second control node.
  • each of the sixth transistors of each of the gate output circuits has a source, a drain, and a gate, respectively.
  • Each source is electrically connected to a different clock signal, and each gate is connected to the charging signal.
  • Each drain sequentially outputs a gate line signal.
  • a seventh transistor of each of the gate output circuits has a source, a drain and a gate, and a source of each of the seventh transistors is electrically connected to a sixth transistor of each gate output circuit. a drain, the drain of each seventh transistor is electrically connected to the first voltage source, The gate of each seventh transistor receives the control signal, and when each of the seventh transistors sequentially operates in a conducting state in response to the received control signal, Each of the seventh transistors turns on the first voltage source to cause the gate line signal to be turned off.
  • the fourth transistor of the level signal output circuit has a source, a drain and a gate. a source of the fourth transistor is electrically connected to the second trigger clock signal, and a gate of the fourth transistor is connected to the charging signal, When the fourth transistor of the level signal output circuit operates in an on state in response to the received second trigger clock signal, the drain of the fourth transistor of the level signal output circuit outputs the level signal.
  • the fifth transistor of the level signal output circuit has a source, a drain and a gate, and a source thereof is electrically connected to a drain of the first transistor of the level signal output circuit, The drain is electrically connected to the first voltage source, The gate receives the control signal, and when the fifth transistor operates in an on state in response to the received control signal, the fifth transistor turns on the first voltage source to cause the level signal to be turned off.
  • each of the single-stage gate driving circuits further includes a forward scan transistor and a reverse scan transistor for receiving a forward scan control signal and a reverse scan control signal, respectively, to control the cascade
  • the gate drive circuit operates in a forward scan or a reverse scan.
  • the transistors mentioned in all of the above embodiments of the present invention include at least one PMOS type or an NMOS type transistor.
  • the invention passes two clock signals which are mutually inverted,
  • the timing of charging and discharging of the gate driving circuit is controlled together with the level transmission signal, and the output of three or four gate line signals is controlled by three or four clock pulse signals, that is, a total of five or six clocks are utilized.
  • the pulse signal is used to achieve the effect of using 6 or 8 clock signals in the existing scan drive circuit. It can effectively reduce the number of clock pulse signals required by existing scan drive circuits. Thereby reducing the overall power consumption of the GOA circuit.
  • Figure 1 illustrates a schematic diagram of a conventional single stage GOA circuit.
  • Figure 2 illustrates a schematic diagram of a dual driver stage GOA circuit with six clock signal inputs.
  • FIG. 3 illustrates a timing chart when the GOA circuit of FIG. 2 operates.
  • Figure 4 illustrates a circuit diagram of a single stage GOA circuit of a first preferred embodiment of the present invention.
  • FIG. 5 illustrates a timing chart when the GOA circuit of FIG. 4 operates.
  • Figure 6 is a circuit diagram showing a single-stage GOA circuit of a second preferred embodiment of the GOA circuit of the present invention.
  • Fig. 7 is a timing chart showing the operation of the GOA circuit of Fig. 6.
  • FIG. 4 illustrates a circuit diagram of a single stage GOA circuit 400 in accordance with a first preferred embodiment of the present invention.
  • the entire circuit has only five clock signals, which are respectively used to control the driving of the first trigger clock signal XCKL and the second trigger clock signal CKL, and the clock pulse for controlling the gate line signal output.
  • the first trigger clock signal XCKL and the second trigger clock signal CKL are mutually inverted, and VSS and VDD represent the high and low voltage source signals, and ST(n-1) is the start signal from the upper level GOA circuit, or referred to as the level transfer signal. If it is a first-level GOA circuit, the corresponding one here is the STV start signal, which is provided by the scan driver chip or the timing control chip.
  • FIG. 5 illustrates a timing chart when the GOA circuit of FIG. 4 operates.
  • the clock signals CK1, CK2 and CK3 in FIG. 5 the waveforms of the low potential portions of the three clock signals do not overlap each other in terms of timing, and the frequencies of the three clock signals are each All are twice the first trigger clock signal XCKL or the second trigger clock signal CKL,
  • the first trigger clock signal XCKL and the second trigger clock signal CKL have the same frequency but are mutually inverted.
  • FIG. 4 and FIG. 5 Please refer to FIG. 4 and FIG. 5 together, and the gate line signal and the first trigger clock signal XCKL and the second trigger clock signal CKL can be seen. And the temporal relationship between the clock signals CK1, CK2 and CK3.
  • the operation of the GOA circuit 400 according to the first embodiment of the present invention is described as follows:
  • the GOA circuit 400 includes a main drive circuit 420 and an output circuit 450.
  • the main driving circuit 420 includes a first transistor T41, a second transistor T42, a third transistor T43, and an eighth transistor T44.
  • the source of transistor T41 is used to receive the start signal ST(n-1) from the GOA circuit of the previous stage.
  • the corresponding STV signal is here, allowing it to start charging at node Q to generate a charging signal Q(n).
  • the gate of the transistor T42 receives the second trigger clock signal CKL, And the gate of the transistor T41 receives the first trigger clock signal XCKL to cooperate with the level-one signal ST(n-1) of the previous stage to jointly control the potential of the node Q.
  • the output circuit 450 includes a first stage signal output circuit 451 and three gate output circuits 452, 453, 454,
  • the level signal output circuit 451 is configured to receive the charging signal of the node Q to output the level transmission signal ST(n), and to receive the control signal K(n) of the node K to turn off the level transmission signal.
  • Gate output circuit 452, 453, The 454 provides three gate line signals G(3n), G(3n+1), G(3n+2).
  • the output circuit 450 has a clock signal source to receive the trigger clock signal CKL and three clock signal sources to receive the clock signals CK1, CK2 and CK3, respectively.
  • the transistor T41 has a source, a drain, and a gate.
  • the source of the transistor T41 receives the start signal ST(n-1) from the upper stage GOA circuit, Its gate receives the first trigger clock signal XCKL.
  • the charging period driving of the GOA circuit 400 is such that when the start signal ST(n-1) and the first trigger clock signal XCKL transmitted from the upper level GOA circuit stage are simultaneously low, the start transistor T41 operates in an on state, Its drain outputs a low potential signal,
  • the transistor T44, the transistor T45, and the transistor T46 are sequentially operated in an on state, so that the node Q of the GOA circuit of the present stage is charged to a low potential to generate a charging signal Q(n).
  • the source of the transistor T42 is electrically connected to the drain of the transistor T41, the drain of the transistor T42 is electrically connected to the source of the transistor T43, and the gate of the transistor T42 is electrically connected to the second trigger clock signal CKL.
  • the drain of the transistor T43 is electrically connected to the voltage source VDD,
  • the gate of the transistor T43 is connected to the node K.
  • the node K generates a control signal K (n) upon charging, so that the transistor T43 is in an on state, and the drain of the transistor T43 is connected to the voltage source VDD.
  • the potential of the node K is different from the potential of the node Q.
  • the discharge period of the GOA circuit 400 is started until the first trigger clock signal XCKL turns high and CKL is low.
  • the potential of the node Q starts to drop, and the transistor T41 becomes in a non-conducting state.
  • the transistor T42 operates in an on state in response to the trigger clock signal CKL signal received by its gate, and is effectively connected to the drain of the transistor T42 to the voltage source VDD because the transistor T43 is in an on state.
  • the level signal output circuit 451 includes a fourth transistor M3 and a fifth transistor M5, the source of the fourth transistor M3 being configured to receive the second trigger clock signal CKL, The gate receives the charging signal Q(n), When the first transistor M3 operates in an on state in response to the second trigger clock signal CKL, the drain of the first transistor M3 of the level signal output circuit 451 is caused to generate a start signal ST(n) of the next stage GOA circuit, The so-called level transmission signal.
  • the fifth transistor M5 of the level signal output circuit 451 has a source, a drain, and a gate.
  • the source of the fifth transistor M5 is electrically connected to the drain of the fourth transistor M3 of the signal output circuit 451, and the drain of the fifth transistor M5 is electrically connected to the voltage source VDD.
  • the gate of the fifth transistor M5 is connected to the node K.
  • Each of the gate output circuits 452, 453, and 454 includes a sixth transistor M6 and a seventh transistor M8.
  • Gate output circuit 452, The sixth transistors M6 of 453, and 454 each have a source, a drain, and a gate.
  • the sixth transistor M6 respectively responds to the charging signal Q(n) received by the gate thereof.
  • the source is configured to receive the clock signals CK1, CK2, and CK3, respectively, and the gate line signals G(3n) are sequentially generated in response to the clock signals CK1, CK2, and CK3. , G(3n+1), G(3n+2).
  • Gate output circuit 452 The seventh transistors M8 of 453 and 454 each have a source, a drain and a gate, and the sources of the seventh transistors M8 are electrically connected to the gate output circuit 452, respectively.
  • the drains of the sixth transistors M6 of 453 and 454, the drains of the seventh transistors M8 are electrically connected to the voltage source VDD, and the gates of the seventh transistors M8 are connected to the node K.
  • the gate output circuit 452 When the gate output circuit 452, When the sixth transistor M4 of 453, and 454 is operated in an on state, the seventh transistor M8 is in a closed state at this time. It does not affect the output of the gate line signals G(3n), G(3n+1), G(3n+2), respectively.
  • the seventh transistor M8 of 453, and 454 sequentially operates in a conducting state in response to the K(n) control signal received by the gate thereof, and at this time, the gate output circuit 452, 453, and the sixth transistor M4 of 454 is in a closed state,
  • the drain of the seventh transistor M8 is sequentially connected to the voltage source VDD, and the gate line signals G(3n), G(3n+1), G(3n+2) are sequentially turned off.
  • FIG. 6 is a circuit diagram showing a single-stage GOA circuit of a second preferred embodiment of the GOA circuit of the present invention. Users also have a variety of needs for scanning the display device. The functions of forward and reverse scanning are added in the second embodiment.
  • two signals SF and SR are added to control the scanning direction. These two signals are DC signals. When the panel is working normally, one of the signals is low and the other signal is high. .
  • SF is low
  • SR high
  • the GOA circuit performs a forward scan mode, that is, gate line driving is performed in the order of increasing rank of the cascaded GOA circuits.
  • the GOA circuit is in the reverse scan mode, that is, the gate line is driven in descending order of the cascaded GOA circuits.
  • Figure 7 is a waveform diagram of the circuit of Figure 6 under different scanning direction conditions. Please take a picture together with Figure 7 and Figure 6, The scan direction control signals SF and SR, the gate line signal and the first trigger clock signal XCKL and the second trigger clock signal CKL can be seen, And the temporal relationship between the clock signals CK1, CK2 and CK3.
  • the operation of the GOA circuit 600 according to the second preferred embodiment of the present invention is described as follows:
  • the GOA circuit 600 of the preferred embodiment includes a main drive circuit 620 and an output circuit 650.
  • the main driving circuit 620 has the same six transistors as the main driving circuit 420 of the first preferred embodiment,
  • a forward scanning transistor T61 and a reverse scanning transistor T62 are further provided for respectively receiving the scanning direction control signals SF and SR, and respectively receiving the signal ST(n-1) from the upper stage at its source.
  • the next stage transmits a signal ST(n+1) to control whether the GOA circuit 600 is currently operating as a function of forward scanning or reverse scanning.
  • the principle of operation of other specific circuits has been described in the first preferred embodiment. Please refer to the detailed description above.
  • the GOA circuits 400, 600 of the embodiments of the present invention are applicable to liquid crystal displays.
  • the present invention passes two clock signals which are mutually inverted,
  • the timing of charging and discharging of the gate driving circuit is controlled together with the level transmission signal, and the output of three or four gate line signals is controlled by three or four clock pulse signals, that is, a total of five or six clocks are utilized.
  • the pulse signal is used to achieve the effect of the existing scan driving circuit.
  • the full HD resolution panel needs to use 6 or 8 clock signals. It can effectively reduce the number of clock pulse signals required by existing scan drive circuits. Thereby reducing the overall power consumption of the GOA circuit.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Shift Register Type Memory (AREA)

Abstract

一种级联的栅极驱动电路，所述级联的栅极驱动电路包括多级栅极驱动电路，各单级栅极驱动电路包含一主驱动电路(420)，一级传信号输出电路(451)，以及多个栅极输出电路(452,453,454)。通过两个互为反相的时钟脉冲信号(CLK,XCLK)，配合级传信号(ST(n))一起控制栅极驱动电路的充电及放电的时序，可有效减少现有栅极驱动电路所需时钟脉冲信号的数量，从而降低栅极驱动电路的整体功耗。

Description

栅极驱动电路及液晶显示器 技术领域
本发明涉及液晶扫描驱动电路，特别是涉及一种用于液晶显示的GOA (Gate Driver on Array, 阵列基板行扫描驱动)电路及液晶显示器。
 背景技术
现在的面板设计已经广泛采用GOA（Gate driver On Array）技术，这样不但可节省栅极驱动芯片的成本，也能够缩减面板边框的宽度，符合窄边框面板的潮流。
随着面板的尺寸逐渐增大，分辨率逐渐提高，GOA电路所用的时钟脉冲信号（CK）也越来越多，通常高清分辨率(1280*720)面板，GOA电路所使用的时钟脉冲信号为4个，而全高清分辨率(1920*1080)面板或者更高分辨率的面板往往需要使用到6个或者8个时钟脉冲信号。时钟脉冲信号是高低电位频繁切换的高频信号，而栅极驱动电路的功耗与晶体管交越导通穿通电流产生功耗相关, 因晶体管交越导通穿通电流产生的功耗与时钟脉冲信号切换的时钟之平方成正比，所以时钟脉冲信号的数量越多以及时钟越高，整个栅极驱动电路的功耗就越大。
请参照图1，由4个晶体管和1个电容构成了传统的单级GOA电路100的基本架构。本级GOA电路输出栅极信号G(n), 并将提供级传信号给下一级GOA电路作为其起始信号ST(n)。GOA电路100包含主驱动电路120和输出电路150。主驱动电路120包括晶体管T1以及晶体管T2。晶体管T1响应起始信号ST(n-2)而操作于一导通状态。晶体管T2在接收栅极信号G(n+2)时导通电压源Vss以重置充电信号Q(n)。
输出电路150包含晶体管T3, 晶体管T4, 以及晶体管T8。晶体管T4响应充电信号Q(n)而操作于导通状态。当晶体管T4操作于导通状态时，会将时钟脉冲信号CK导通至漏极而输出栅极信号G(n)。另外，晶体管T8在接收栅极信号G(n+2)时导通电压源Vss以重置栅极信号G(n)。
由于非晶硅的可靠性问题，除了上述基本的架构之外，还会有一个辅助下拉电路15。辅助下拉电路15主要是在栅极线关闭期间确保GOA电路100输出和节点Q处于关闭期的电位状态，即具有下拉维持电路的作用，提高GOA电路100工作时的可靠性。
大尺寸高分辨率面板的GOA电路往往采用多个时钟脉冲信号的设计，例如6个或者8个时钟脉冲信号的设计以确保操作时的可靠性。图2例示现有六相位驱动的双驱动级GOA电路之示意图。在此电路示意图中，第一驱动级GOA电路210响应两栅极线信号G[N-1]、G[N+5] 与六个输入时钟脉冲信号CK1、CK2、CK3、XCK1、XCK2、XCK3而产生三个栅极线信号G[N], G[N+1]和G[N+2]。
图3例示图2中GOA电路操作时的时序图。如图3所示，栅极线信号G[N]~G[N+5]与时钟脉冲信号CK1~CK3及XCK1~XCK3的信号总宽度等同于3W，其中W是充电完成一条扫描线上像素的时间。因为时钟脉冲信号是整个GOA电路的主要功耗来源，一般信号的功耗和时钟脉冲信号的电压平方成正比，因此时钟脉冲信号数量越多，电路的功耗就越大，当面板的分辨率高的时候这个问题尤为严重，而且信号数量也会导致驱动电路的成本增加，这对产品的市场竞争力是非常不利的。
为了解决时钟脉冲信号的数量过多，造成功耗过大的问题，有必要重新设计GOA电路，使得需要使用到的时钟脉冲信号数量可以减少，从而降低GOA电路的整体功耗，符合现在绿色节能的环保要求。
 技术问题
本发明的目的在于提供一种栅极驱动电路, 所述栅极驱动电路通过三个信号, 即一级传信号以及两个互为反相的时钟信号, 来共同控制栅极驱动电路充电及放电的时序，并通过多个时钟脉冲信号来控制多个栅极线信号的输出，减少现有扫描驱动电路所需时钟脉冲信号的数量,从而降低GOA电路的整体功耗。
本发明的另一目的在于提供一种用以驱动显示面板的栅极驱动电路。所述栅极驱动电路通过三个信号, 即一级传信号以及两个互为反相的时钟信号来共同控制节点Q的电位，并通过多个时钟脉冲信号来控制多个栅极线信号的输出，减少现有扫描驱动电路所需时钟脉冲信号的数量,从而降低GOA电路的整体功耗。
 技术解决方案
依据本发明的实施例，一种栅极驱动电路包含多级阵列基板行扫描驱动(GOA)单元, 各GOA单元包含：一主驱动电路，包括第一晶体管, 第二晶体管, 和第三晶体管, 并具有第一控制节点及第二控制节点,所述第一晶体管具有一源极、漏极以及栅极, 所述第二晶体管及所述第三晶体管分别具有源极、漏极以及栅极, 分别在第一晶体管的源极接收一起始信号，并在第一晶体管的栅极接收第一触发时钟信号, 以及在第二晶体管的栅极接收第二触发时钟信号时,响应所述起始信号、所述第一触发时钟信号以及所述第二触发时钟信号的输入以在所述第一控制节点处产生充电信号, 并在所述第二控制节点处产生控制信号；一级传信号输出电路, 包括第四晶体管和第五晶体管, 所述第四晶体管用以接收所述充电信号以输出一级传信号, 所述第五晶体管用以接收所述控制信号以关闭所述级传信号; 以及多个栅极输出电路, 各栅极输出电路包括第六晶体管和第七晶体管, 所述第六晶体管用以接收所述充电信号以输出一栅极线信号, 所述第七晶体管用以接收所述控制信号以关闭所述栅极线信号。
依据本发明的实施例，所述起始信号是上一级GOA单元传来的级传信号, 或者是一扫描驱动控制芯片提供的起始信号。
依据本发明的实施例，第一触发时钟信号和第二触发时钟信号互为反相。
依据本发明的实施例，所述主驱动电路更包含第八晶体管, 第九晶体管, 以及第十晶体管, 其中当所述第一晶体管响应接收的所述第一触发时钟信号操作于一导通状态时, 并使得第八晶体管、第九晶体管以及第十晶体管也操作于ー导通状态, 使得在第一控制节点处产生所述充电信号, 并在第二控制节点处产生所述控制信号。
依据本发明的实施例，所述各栅极输出电路的各第六晶体管分别具有源极、漏极以及栅极, 各源极分别电性连接不同的时钟脉冲信号, 各栅极连接所述充电信号, 当各所述第一晶体管响应接收不同的时钟脉冲信号操作于ー导通状态时, 各漏极依序输出一栅极线信号。
依据本发明的实施例，每一所述栅极输出电路的第七晶体管具有源极、漏极以及栅极，每一第七晶体管的源极电性连接各栅极输出电路的第六晶体管的漏极，每一第七晶体管的漏极电性连接所述第一电压源, 每一第七晶体管的栅极接收所述控制信号, 当每一所述第七晶体管依序响应接收的控制信号操作于导通状态时, 每一所述第七晶体管导通所述第一电压源以使得所述栅极线信号关闭。
依据本发明的实施例，所述级传信号输出电路的第四晶体管具有源极、漏极以及栅极, 所述第四晶体管的源极电性连接所述第二触发时钟信号, 所述第四晶体管的栅极连接所述充电信号, 当所述级传信号输出电路的第四晶体管响应接收的所述第二触发时钟信号操作于导通状态时，所述级传信号输出电路的第四晶体管的漏极输出所述级传信号。
依据本发明的实施例，所述级传信号输出电路的第五晶体管具有源极、漏极以及栅极，其源极电性连接所述级传信号输出电路的第一晶体管的漏极，其漏极电性连接所述第一电压源, 其栅极接收所述控制信号, 当所述第五晶体管响应接收的控制信号操作于导通状态时, 所述第五晶体管导通所述第一电压源以使得所述级传信号关闭。
依据本发明的实施例，所述各单级栅极驱动电路还包括一正向扫描晶体管和一反向扫描晶体管用以分别接收正向扫描控制信号和反向扫描控制信号以控制所述级联的栅极驱动电路操作于正向扫描或者是反向扫描。
依据本发明的实施例，一种液晶显示器包含栅极驱动电路，所述栅极驱动电路包含多级阵列基板行扫描驱动(GOA)单元, 各GOA单元包含：一主驱动电路，包括第一晶体管, 第二晶体管, 和第三晶体管, 并具有第一控制节点及第二控制节点,所述第一晶体管具有一源极、漏极以及栅极, 所述第二晶体管及所述第三晶体管分别具有源极、漏极以及栅极, 分别在第一晶体管的源极接收一起始信号，并在第一晶体管的栅极接收第一触发时钟信号, 以及在第二晶体管的栅极接收第二触发时钟信号时,响应所述起始信号、所述第一触发时钟信号以及所述第二触发时钟信号的输入以在所述第一控制节点处产生充电信号, 并在所述第二控制节点处产生控制信号；一级传信号输出电路, 包括第四晶体管和第五晶体管, 所述第四晶体管用以接收所述充电信号以输出一级传信号, 所述第五晶体管用以接收所述控制信号以关闭所述级传信号; 以及多个栅极输出电路, 各栅极输出电路包括第六晶体管和第七晶体管, 所述第六晶体管用以接收所述充电信号以输出一栅极线信号, 所述第七晶体管用以接收所述控制信号以关闭所述栅极线信号。
依据本发明的实施例，所述起始信号是上一级GOA单元传来的级传信号, 或者是一扫描驱动控制芯片提供的起始信号。
依据本发明的实施例，第一触发时钟信号和第二触发时钟信号互为反相。
依据本发明的实施例，所述主驱动电路更包含第八晶体管, 第九晶体管, 以及第十晶体管, 其中当所述第一晶体管响应接收的所述第一触发时钟信号操作于一导通状态时, 并使得第八晶体管、第九晶体管以及第十晶体管也操作于ー导通状态, 使得在第一控制节点处产生所述充电信号, 并在第二控制节点处产生所述控制信号。
依据本发明的实施例，所述各栅极输出电路的各第六晶体管分别具有源极、漏极以及栅极, 各源极分别电性连接不同的时钟脉冲信号, 各栅极连接所述充电信号, 当各所述第一晶体管响应接收不同的时钟脉冲信号操作于ー导通状态时, 各漏极依序输出一栅极线信号。
依据本发明的实施例，每一所述栅极输出电路的第七晶体管具有源极、漏极以及栅极，每一第七晶体管的源极电性连接各栅极输出电路的第六晶体管的漏极，每一第七晶体管的漏极电性连接所述第一电压源, 每一第七晶体管的栅极接收所述控制信号, 当每一所述第七晶体管依序响应接收的控制信号操作于导通状态时, 每一所述第七晶体管导通所述第一电压源以使得所述栅极线信号关闭。
依据本发明的实施例，所述级传信号输出电路的第四晶体管具有源极、漏极以及栅极, 所述第四晶体管的源极电性连接所述第二触发时钟信号, 所述第四晶体管的栅极连接所述充电信号, 当所述级传信号输出电路的第四晶体管响应接收的所述第二触发时钟信号操作于导通状态时，所述级传信号输出电路的第四晶体管的漏极输出所述级传信号。
依据本发明的实施例，所述级传信号输出电路的第五晶体管具有源极、漏极以及栅极，其源极电性连接所述级传信号输出电路的第一晶体管的漏极，其漏极电性连接所述第一电压源, 其栅极接收所述控制信号, 当所述第五晶体管响应接收的控制信号操作于导通状态时, 所述第五晶体管导通所述第一电压源以使得所述级传信号关闭。
依据本发明的实施例，所述各单级栅极驱动电路还包括一正向扫描晶体管和一反向扫描晶体管用以分别接收正向扫描控制信号和反向扫描控制信号以控制所述级联的栅极驱动电路操作于正向扫描或者是反向扫描。
在上述本发明所有实施例中所提到的晶体管包含至少一PMOS型或者是一NMOS型的晶体管。
 有益效果
相较于现有驱动显示面板的栅极驱动电路,例如全高清分辨率面板往往需要使用到6个或者8个时钟脉冲信号, 本发明通过两个互为反相的时钟脉冲信号, 配合级传信号一起控制栅极驱动电路的充电及放电的时序，并通过3个或者4个时钟脉冲信号来控制3个或者4个栅极线信号的输出，即利用总共5个或者6个时钟脉冲信号来达到现有扫描驱动电路需要使用到6个或者8个时钟脉冲信号的效果。可有效减少现有扫描驱动电路所需时钟脉冲信号的数量, 从而降低GOA电路的整体功耗。
附图说明
图1例示传统的单级GOA电路之示意图。
图2例示现有六个时钟脉冲信号输入的双驱动级GOA电路之示意图。
图3例示图2中GOA电路操作时的时序图。
图4例示本发明之第一优选实施例的单级GOA电路之电路图。
图5例示图4中GOA电路操作时的时序图。
图6例示本发明GOA电路之第二优选实施例的单级GOA电路之电路图。
图7例示图6中GOA电路操作时的时序图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。实施例中相同标号指示同样或相似的组件, 所例举之实施例是用以说明及理解本发明，而非用以限制本发明。
图4例示本发明第一优选实施例的单级GOA电路400之电路图。以PMOS型晶体管实施单级GOA电路为例，整个电路只有5个时钟信号，分别是作用于控制驱动第一触发时钟信号XCKL和第二触发时钟信号CKL，以及控制栅极线信号输出的时钟脉冲信号CK1，CK2和CK3。第一触发时钟信号XCKL和第二触发时钟信号CKL互为反相，此外, VSS和VDD表示高低电位的电压源信号，ST(n-1)是来自上一级GOA电路的起始信号，或者称为级传信号。若是第一级GOA电路，此处对应的则是STV起始信号，它是由扫描驱动芯片或者时序控制芯片提供。
图5例示图4中GOA电路操作时的时序图。如图5中的时钟脉冲信号CK1，CK2和CK3所示，从时序上来看，这三个时钟脉冲信号的低电位部分的波形不会相互重叠，而且这三个时钟脉冲信号的频率每一者皆是第一触发时钟信号XCKL或者是第二触发时钟信号CKL的两倍, 第一触发时钟信号XCKL和第二触发时钟信号CKL两者频率相同, 但互为反相。
请一并照图4和图5, 可看出栅极线信号与第一触发时钟信号XCKL和第二触发时钟信号CKL, 以及时钟脉冲信号CK1，CK2和CK3之间的时态关系。依据本发明第一实施例GOA电路400之操作内容说明如下:
如图4所示, GOA电路400包含主驱动电路420和输出电路450。主驱动电路420包括第一晶体管T41, 第二晶体管T42, 第三晶体管T43, 第八晶体管T44, 第九晶体管T45以及第十晶体管T46。晶体管T41的源极用来接收来自上一级GOA电路的起始信号ST(n-1)。若是第一级GOA电路，此处对应的则是STV信号，使其允许开始在节点Q充电而产生充电信号Q(n)。晶体管T42的栅极接收第二触发时钟信号CKL, 及晶体管T41的栅极以接收第一触发时钟信号XCKL，使其配合上一级的级传信号ST(n-1)来共同控制节点Q的电位。
如图4所示, 输出电路450包含一级传信号输出电路451以及三个栅极输出电路452, 453, 454, 级传信号输出电路451用以接收节点Q的充电信号以输出级传信号ST(n), 以及用以接收节点K的控制信号K(n)以关闭级传信号。栅极输出电路452, 453, 454提供三个栅极线信号G(3n)、G(3n+1)、G(3n+2)。输出电路450具有一个时钟信号源极以接收触发时钟信号CKL以及三个时钟信号源极以分别接收时钟脉冲信号CK1，CK2和CK3。
具体而言,晶体管T41具有源极、漏极以及栅极。晶体管T41的源极接收来自上一级GOA电路的起始信号ST(n-1), 其栅极接收第一触发时钟信号XCKL。GOA电路400的充电期驱动是当上一级GOA电路级传来的起始信号ST(n-1)和第一触发时钟信号XCKL同时为低电位时，启动晶体管T41操作于导通状态，使其漏极输出低电位信号, 依序使得晶体管T44, 晶体管T45以及晶体管T46操作于导通状态, 使得本级GOA电路的节点Q充电至低电位而产生充电信号Q(n)。
晶体管T42的源极电性连接晶体管T41的漏极，晶体管T42的漏极电性连接晶体管T43的源极,晶体管T42的栅极电性连接第二触发时钟信号CKL。晶体管T43的漏极电性连接电压源VDD, 而晶体管T43的栅极连接节点K。此时,节点K一经充电而产生控制信号K (n), 使得晶体管T43处于导通状态, 而连接晶体管T43的漏极至电压源VDD, 始得节点K的电位相异于节点Q的电位。
直到第一触发时钟信号XCKL转为高电位且CKL为低电位时, 开始GOA电路400的放电期, 节点Q的电位开始下降, 晶体管T41变成处于非导通状态, 而晶体管T42响应其栅极所接收的触发时钟信号CKL信号操作于导通状态，并因晶体管T43处于导通状态,得以有效连接晶体管T42的漏极至电压源VDD。
如图4所示,级传信号输出电路451包括第四晶体管M3以及第五晶体管M5,第四晶体管M3的源极经配置为接收第二触发时钟信号CKL, 栅极接收充电信号Q(n), 当第一晶体管M3响应第二触发时钟信号CKL操作于一导通状态时，使级传信号输出电路451的第一晶体管M3之漏极产生下一级GOA电路的起始信号ST(n), 即所谓的级传信号。
级传信号输出电路451的第五晶体管M5具有源极、漏极以及栅极。第五晶体管M5的源极电性连接级传信号输出电路451的第四晶体管M3的漏极，第五晶体管M5的漏极电性连接电压源VDD, 第五晶体管M5的栅极连接节点K。当级传信号输出电路451的第一晶体管M3操作于一导通状态时，此时级传信号输出电路451的第五晶体管M5是处于关闭状态。当第五晶体管M5响应其栅极所接收的K(n)控制信号操作于一导通状态，得以有效连接级传信号输出电路451的第五晶体管M5的漏极至电压源VDD，并让级传信号ST(n)关闭。
各栅极输出电路452, 453,和454包括第六晶体管M6以及第七晶体管M8。栅极输出电路452, 453,和454的第六晶体管M6各自具有源极、漏极以及栅极，当GOA电路400操作于充电期时,第六晶体管M6分别响应其栅极所接收的充电信号Q(n) 操作于一导通状态时，其源极经配置为分别接收时钟脉冲信号CK1，CK2和CK3，而在其漏极响应时钟脉冲信号CK1，CK2和CK3依序产生栅极线信号G(3n)、G(3n+1)、G(3n+2)。
栅极输出电路452, 453,和454的第七晶体管M8各自具有源极、漏极以及栅极，各第七晶体管M8的源极分别电性连接栅极输出电路452, 453,和454的各第六晶体管M6的漏极，各第七晶体管M8的漏极分别电性连接电压源VDD，各第七晶体管M8的栅极连接节点K。当栅极输出电路452, 453,和454的第六晶体管M4操作于导通状态时, 此时第七晶体管M8是处于关闭状态, 使其分别不影响栅极线信号G(3n)、G(3n+1)、G(3n+2)的输出。
当栅极输出电路452, 453,和454的第七晶体管M8依序响应其栅极所接收的K(n)控制信号操作于一导通状态时, 此时栅极输出电路452, 453,和454的第六晶体管M4是处于关闭状态, 得以有效依序连接第七晶体管M8的漏极至电压源VDD，并依序关闭栅极线信号G(3n)、G(3n+1)、G(3n+2)。
图6例示本发明GOA电路之第二优选实施例的单级GOA电路之电路图。使用者对于显示设备之扫描方式也具有多样性之需求, 在第二个实施例中增加了正向和反向扫描的功能。在图6的GOA电路中，增加了两个信号SF和SR来对扫描方向进行控制，这两个信号都是直流信号，面板正常工作时，其中一个信号为低电位，另外一个信号为高电位。当SF为低电位时，SR为高电位时，GOA电路进行正向扫描模式，即按照级联GOA电路的级别递增顺序进行栅极线驱动。相反的，当SF为高电位，SR为低电位时，GOA电路为反向扫描模式，即按照级联GOA电路的级别递减顺序进行栅极线驱动。
图7是图6中的电路在不同的扫描方向条件下的波形示意图。请一并照图7和图6, 可看出扫描方向控制信号SF和SR, 栅极线信号与第一触发时钟信号XCKL和第二触发时钟信号CKL, 以及时钟脉冲信号CK1，CK2和CK3之间的时态关系。依据本发明第二优选实施例GOA电路600之操作内容说明如下:
在第一优选实施例的基础上，本优选实施例的GOA电路600包含主驱动电路620和输出电路650, 主驱动电路620除了具有与第一优选实施例的主驱动电路420相同的6个晶体管外, 还设置有正向扫描晶体管T61和反向扫描晶体管T62用以分别接收扫描方向控制信号SF和SR, 并分别在其源极接收来自上一级级传信号ST(n-1) 和下一级级传信号ST(n+1)以控制GOA电路600目前工作是操作于正向扫描或者是反向扫描的功能。其他具体电路的操作原理在第一优选实施例中已经说明, 请参照如上的具体描述。本发明实施例的GOA电路400、600可应用于液晶显示器上。
相较于现有技术，本发明通过两个互为反相的时钟脉冲信号, 配合级传信号一起控制栅极驱动电路的充电及放电的时序，并通过3个或者4个时钟脉冲信号来控制3个或者4个栅极线信号的输出，即利用总共5个或者6个时钟脉冲信号来达到现有扫描驱动电路的效果,例如全高清分辨率面板需要使用到6个或者8个时钟脉冲信号。可有效减少现有扫描驱动电路所需时钟脉冲信号的数量, 从而降低GOA电路的整体功耗。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种栅极驱动电路，包含多级阵列基板行扫描驱动(GOA)单元, 各GOA单元包含：
    一主驱动电路，包括第一晶体管, 第二晶体管, 和第三晶体管, 并具有第一控制节点及第二控制节点,所述第一晶体管具有一源极、漏极以及栅极, 所述第二晶体管及所述第三晶体管分别具有源极、漏极以及栅极, 分别在第一晶体管的源极接收一起始信号，并在第一晶体管的栅极接收第一触发时钟信号, 以及在第二晶体管的栅极接收第二触发时钟信号时,响应所述起始信号、所述第一触发时钟信号以及所述第二触发时钟信号的输入以在所述第一控制节点处产生充电信号, 并在所述第二控制节点处产生控制信号；
    一级传信号输出电路, 包括第四晶体管和第五晶体管, 所述第四晶体管用以接收所述充电信号以输出一级传信号, 所述第五晶体管用以接收所述控制信号以关闭所述级传信号; 以及
    多个栅极输出电路, 各栅极输出电路包括第六晶体管和第七晶体管, 所述第六晶体管用以接收所述充电信号以输出一栅极线信号, 所述第七晶体管用以接收所述控制信号以关闭所述栅极线信号。
  2. 如权利要求1所述栅极驱动电路，其中所述起始信号是上一级GOA单元传来的级传信号, 或者是一扫描驱动控制芯片提供的起始信号。
  3. 如权利要求1所述栅极驱动电路，其中第一触发时钟信号和第二触发时钟信号互为反相。
  4. 如权利要求1所述栅极驱动电路，其中所述主驱动电路更包含第八晶体管, 第九晶体管, 以及第十晶体管, 其中当所述第一晶体管响应接收的所述第一触发时钟信号操作于一导通状态时, 并使得第八晶体管、第九晶体管以及第十晶体管也操作于ー导通状态, 使得在第一控制节点处产生所述充电信号, 并在第二控制节点处产生所述控制信号。
  5. 如权利要求1所述栅极驱动电路，其中所述各栅极输出电路的各第六晶体管分别具有源极、漏极以及栅极, 各源极分别电性连接不同的时钟脉冲信号, 各栅极连接所述充电信号, 当各所述第一晶体管响应接收不同的时钟脉冲信号操作于ー导通状态时, 各漏极依序输出一栅极线信号。
  6. 如权利要求5所述栅极驱动电路，其中每一所述栅极输出电路的第七晶体管具有源极、漏极以及栅极，每一第七晶体管的源极电性连接各栅极输出电路的第六晶体管的漏极，每一第七晶体管的漏极电性连接所述第一电压源, 每一第七晶体管的栅极接收所述控制信号, 当每一所述第七晶体管依序响应接收的控制信号操作于导通状态时, 每一所述第七晶体管导通所述第一电压源以使得所述栅极线信号关闭。
  7. 如权利要求1所述栅极驱动电路，其中所述级传信号输出电路的第四晶体管具有源极、漏极以及栅极, 所述第四晶体管的源极电性连接所述第二触发时钟信号, 所述第四晶体管的栅极连接所述充电信号, 当所述级传信号输出电路的第四晶体管响应接收的所述第二触发时钟信号操作于导通状态时，所述级传信号输出电路的第四晶体管的漏极输出所述级传信号。
  8. 如权利要求7所述栅极驱动电路，其中所述级传信号输出电路的第五晶体管具有源极、漏极以及栅极，其源极电性连接所述级传信号输出电路的第一晶体管的漏极，其漏极电性连接所述第一电压源, 其栅极接收所述控制信号, 当所述第五晶体管响应接收的控制信号操作于导通状态时, 所述第五晶体管导通所述第一电压源以使得所述级传信号关闭。
  9. 如权利要求1所述栅极驱动电路，其中所述各单级栅极驱动电路还包括一正向扫描晶体管和一反向扫描晶体管用以分别接收正向扫描控制信号和反向扫描控制信号以控制所述级联的栅极驱动电路操作于正向扫描或者是反向扫描。
  10. 一种液晶显示器，包含栅极驱动电路，所述栅极驱动电路包含多级阵列基板行扫描驱动(GOA)单元, 各GOA单元包含：
    一主驱动电路，包括第一晶体管, 第二晶体管, 和第三晶体管, 并具有第一控制节点及第二控制节点,所述第一晶体管具有一源极、漏极以及栅极, 所述第二晶体管及所述第三晶体管分别具有源极、漏极以及栅极, 分别在第一晶体管的源极接收一起始信号，并在第一晶体管的栅极接收第一触发时钟信号, 以及在第二晶体管的栅极接收第二触发时钟信号时,响应所述起始信号、所述第一触发时钟信号以及所述第二触发时钟信号的输入以在所述第一控制节点处产生充电信号, 并在所述第二控制节点处产生控制信号；
    一级传信号输出电路, 包括第四晶体管和第五晶体管, 所述第四晶体管用以接收所述充电信号以输出一级传信号, 所述第五晶体管用以接收所述控制信号以关闭所述级传信号; 以及
    多个栅极输出电路, 各栅极输出电路包括第六晶体管和第七晶体管, 所述第六晶体管用以接收所述充电信号以输出一栅极线信号, 所述第七晶体管用以接收所述控制信号以关闭所述栅极线信号。
  11. 如权利要求10所述液晶显示器，其中所述起始信号是上一级GOA单元传来的级传信号, 或者是一扫描驱动控制芯片提供的起始信号。
  12. 如权利要求10所述液晶显示器，其中第一触发时钟信号和第二触发时钟信号互为反相。
  13. 如权利要求10所述液晶显示器，其中所述主驱动电路更包含第八晶体管, 第九晶体管, 以及第十晶体管, 其中当所述第一晶体管响应接收的所述第一触发时钟信号操作于一导通状态时, 并使得第八晶体管、第九晶体管以及第十晶体管也操作于ー导通状态, 使得在第一控制节点处产生所述充电信号, 并在第二控制节点处产生所述控制信号。
  14. 如权利要求10所述液晶显示器，其中所述各栅极输出电路的各第六晶体管分别具有源极、漏极以及栅极, 各源极分别电性连接不同的时钟脉冲信号, 各栅极连接所述充电信号, 当各所述第一晶体管响应接收不同的时钟脉冲信号操作于ー导通状态时, 各漏极依序输出一栅极线信号。
  15. 如权利要求14所述液晶显示器，其中每一所述栅极输出电路的第七晶体管具有源极、漏极以及栅极，每一第七晶体管的源极电性连接各栅极输出电路的第六晶体管的漏极，每一第七晶体管的漏极电性连接所述第一电压源, 每一第七晶体管的栅极接收所述控制信号, 当每一所述第七晶体管依序响应接收的控制信号操作于导通状态时, 每一所述第七晶体管导通所述第一电压源以使得所述栅极线信号关闭。
  16. 如权利要求10所述液晶显示器，其中所述级传信号输出电路的第四晶体管具有源极、漏极以及栅极, 所述第四晶体管的源极电性连接所述第二触发时钟信号, 所述第四晶体管的栅极连接所述充电信号, 当所述级传信号输出电路的第四晶体管响应接收的所述第二触发时钟信号操作于导通状态时，所述级传信号输出电路的第四晶体管的漏极输出所述级传信号。
  17. 如权利要求16所述液晶显示器，其中所述级传信号输出电路的第五晶体管具有源极、漏极以及栅极，其源极电性连接所述级传信号输出电路的第一晶体管的漏极，其漏极电性连接所述第一电压源, 其栅极接收所述控制信号, 当所述第五晶体管响应接收的控制信号操作于导通状态时, 所述第五晶体管导通所述第一电压源以使得所述级传信号关闭。
  18. 如权利要求10所述液晶显示器，其中所述各单级栅极驱动电路还包括一正向扫描晶体管和一反向扫描晶体管用以分别接收正向扫描控制信号和反向扫描控制信号以控制所述级联的栅极驱动电路操作于正向扫描或者是反向扫描。
PCT/CN2016/070601 2015-12-28 2016-01-11 栅极驱动电路及液晶显示器 WO2017113437A1 (zh)

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