WO2018126754A1 - 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置 - Google Patents

一种移位寄存器、其驱动方法、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2018126754A1
WO2018126754A1 PCT/CN2017/105505 CN2017105505W WO2018126754A1 WO 2018126754 A1 WO2018126754 A1 WO 2018126754A1 CN 2017105505 W CN2017105505 W CN 2017105505W WO 2018126754 A1 WO2018126754 A1 WO 2018126754A1
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Prior art keywords
signal
node
transistor
control
module
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PCT/CN2017/105505
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English (en)
French (fr)
Inventor
王洪军
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/066,729 priority Critical patent/US11100841B2/en
Publication of WO2018126754A1 publication Critical patent/WO2018126754A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register, a driving method thereof, a gate driving circuit, and a display device.
  • the Gate Driver on Array (GOA) technology integrates a Thin Film Transistor (TFT) gate switching circuit on the array substrate of the display panel to enable scan driving of the display panel, thereby eliminating the need for a control electrode.
  • TFT Thin Film Transistor
  • this integrated process eliminates the need for a bonding process that controls the direction of the scan lines, increasing throughput and yield.
  • a typical gate drive circuit consists of a plurality of cascaded shift registers.
  • the scanning signals are sequentially input to the respective gate lines on the display panel through the shift registers of the stages.
  • the shift register outputs the effective pulse signal of the scan signal
  • the pull-down transistor provides the low potential reference signal under the control of the signal of the pull-down node.
  • the drive signal output terminal is provided so that the drive signal output terminal is at a low potential output state.
  • the potential of the control electrode of the pull-down transistor will leak, that is, the potential of the signal of the pull-down node will change, causing the pull-down transistor not to be completely turned on, or even causing the pull-down transistor to be turned off, thereby causing the output of the driving signal. It is not possible to maintain a low potential. Such a situation may reduce the stability of the shift register, which may cause an abnormality in the display.
  • Embodiments of the present disclosure provide a shift register, a driving method thereof, a gate driving circuit, and a display device that are capable of at least partially alleviating or even eliminating the above-mentioned problems in the prior art.
  • an embodiment of the present disclosure provides a shift register including an input module, a reset module, a potential maintaining module, a node control module, a first output module, and a second output module.
  • the input module is respectively connected to the input signal end and the first node, and is configured to provide the signal of the input signal end to the first node under the control of the signal of the input signal end.
  • the reset module is respectively connected to the reset signal end, the reference signal end, and the first node, and configured to provide the signal of the reference signal end to the first node under the control of the signal of the reset signal end.
  • the potential maintaining module is respectively connected to the clock signal end and the second node, and is configured to keep the voltage difference between the clock signal end and the second node stable when the second node is in a floating state.
  • the node control module is respectively connected to the input signal end, the reset signal end, the reference signal end, the second node, and a driving signal output end of the shift register, and is configured to be at the input Providing, by the signal of the signal end, the signal of the reference signal end to the second node, providing the signal of the reset signal end to the second node under the control of the signal of the reset signal end, and The signal of the reference signal end is supplied to the second node under the control of a signal at the output of the drive signal.
  • the first output module is respectively connected to the clock signal end, the first node, and the driving signal output end, and configured to provide a signal of the clock signal end under the control of a signal of the first node And the voltage difference between the first node and the drive signal output is stabilized when the first signal is in a floating state.
  • the second output module is respectively connected to the reference signal end, the second node, and the driving signal output end, and configured to provide a signal of the reference signal end under the control of a signal of the second node The drive signal output is provided.
  • the potential maintaining module includes a first capacitor. One end of the first capacitor is connected to the clock signal end, and the other end of the first capacitor is connected to the second node.
  • the input module includes a first transistor.
  • the control electrode and the first pole of the first transistor are both connected to the input signal terminal, and the second pole of the first transistor is connected to the first node.
  • the reset module includes a second transistor. Said A control electrode of the second transistor is coupled to the reset signal terminal, a first pole of the second transistor is coupled to the reference signal terminal, and a second pole of the second transistor is coupled to the first node.
  • the node control module includes a third transistor, a fourth transistor, and a fifth transistor.
  • a control electrode of the third transistor is connected to the input signal terminal, a first pole of the third transistor is connected to the reference signal terminal, and a second pole of the third transistor is connected to the second node .
  • the control electrode and the first pole of the fourth transistor are both connected to the reset signal terminal, and the second pole of the fourth transistor is connected to the second node.
  • a control electrode of the fifth transistor is connected to the output end of the driving signal, a first pole of the fifth transistor is connected to the reference signal end, and a second pole of the fifth transistor is connected to the second node Connected.
  • the first output module includes a sixth transistor and a second capacitor.
  • a control electrode of the sixth transistor is connected to the first node, a first pole of the sixth transistor is connected to the clock signal end, and a second pole of the sixth transistor and the driving signal output end Connected.
  • One end of the second capacitor is connected to the first node, and the other end of the second capacitor is connected to the drive signal output end.
  • the second output module includes a seventh transistor.
  • a control electrode of the seventh transistor is connected to the second node, a first pole of the seventh transistor is connected to the reference signal end, and a second pole of the seventh transistor and the driving signal output end Connected.
  • the shift register further includes a first node stabilization module.
  • the first node stabilization module is respectively connected to the reference signal end, the first node, and the second node, and configured to provide a signal of the reference signal end under the control of a signal of the second node Give the first node.
  • the first node stabilization module includes an eighth transistor. a control electrode of the eighth transistor is connected to the second node, a first pole of the eighth transistor is connected to the reference signal end, and a second pole of the eighth transistor is connected to the first node .
  • the shift register further includes a second node stabilization module.
  • the second node stabilization module is respectively connected to the node stability control signal end and the second node, and configured to provide the signal of the node stability control signal end to the signal under the control of the signal of the node stability control signal end The second node.
  • the second node stabilization module includes a ninth transistor.
  • the control electrode and the first pole of the ninth transistor are both connected to the node stabilization control signal end, and the second pole of the ninth transistor is connected to the second node.
  • an embodiment of the present disclosure further provides a gate driving circuit, including any one of the above-mentioned shift registers provided by the M embodiments of the present disclosure, wherein M is an integer greater than or equal to 3.
  • M is an integer greater than or equal to 3.
  • the input signal end of the first stage shift register is connected to the first frame trigger signal end; the input signal end of the second stage shift register is connected to the second frame trigger signal end; the input signal of the Nth stage shift register
  • the terminals are respectively connected to the driving signal output ends of the N-2th stage shift register; and the reset signal terminals of the N-2th stage shift register are respectively connected to the driving signal output ends of the Nth stage shift register.
  • N is an integer greater than or equal to 3 and less than or equal to M.
  • an embodiment of the present disclosure further provides a display device including the above-described gate driving circuit provided by an embodiment of the present disclosure.
  • the embodiment of the present disclosure further provides a driving method of any one of the above shift registers provided by the embodiment of the present disclosure.
  • the driving method includes a first stage, a second stage, a third stage, a fourth stage, and a fifth stage.
  • the input module provides a signal of the input signal end to the first node under control of a signal of the input signal end;
  • the first output module is at the first node Providing a signal of the clock signal end to the drive signal output end under control of a signal; and
  • the node control module provides a signal of the reference signal end to the second node under control of a signal of the input signal end .
  • the first output module keeps a voltage difference between the first node and the driving signal output terminal stable when the first node is in a floating state, and in the The signal of the clock signal end is supplied to the output of the drive signal under the control of the signal of the first node; the node control module provides the signal of the reference signal end to the control under the control of the signal of the output end of the drive signal Said second node.
  • the first output module keeps a voltage difference between the first node and the drive signal output terminal stable when the first node is in a floating state, and in the The signal of the clock signal end is supplied to the drive signal output terminal under the control of the signal of the first node; the potential maintaining module keeps the clock signal end and the The voltage difference between the second nodes is stable.
  • the control of the signal of the reset module at the reset signal end Providing a signal of the reference signal end to the first node; the node control module provides a signal of the reset signal end to the second node under control of a signal of the reset signal end;
  • the two output module supplies the signal of the reference signal end to the driving signal output end under the control of the signal of the second node;
  • the potential maintaining module keeps a voltage difference between the clock signal end and the second node stable when the second node is in a floating state; the second output module And providing a signal of the reference signal end to the driving signal output end under the control of the signal of the second node.
  • the driving method further includes, in the fourth stage, the first node stabilization module is in the Providing a signal of the reference signal end to the first node under control of a signal of the second node, and controlling the signal of the first node stabilization module at the second node in the fifth stage The signal of the reference signal end is provided to the first node.
  • the driving method further includes, in the fourth stage, the second node stabilization module is in the The signal of the node stabilization control signal end is provided to the second node under the control of the signal of the node stabilization control signal end.
  • FIG. 1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 1b is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.
  • FIG. 2a is a schematic diagram of a specific structure of the shift register shown in FIG. 1a;
  • FIG. 2b is another schematic structural diagram of the shift register shown in FIG. 1a;
  • FIG. 3a is a schematic diagram of a specific structure of the shift register shown in FIG. 1b;
  • FIG. 3a is a schematic diagram of a specific structure of the shift register shown in FIG. 1b;
  • FIG. 3b is another schematic structural diagram of the shift register shown in FIG. 1b;
  • 4a is a timing diagram of input and output of the shift register shown in FIG. 3a;
  • Figure 4b is a timing diagram of input and output of the shift register shown in Figure 3b;
  • FIG. 5 is a flowchart of a driving method according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a shift register, as shown in FIG. 1a and FIG. 1b, including an input module 1, a reset module 2, a potential maintaining module 3, a node control module 4, a first output module 5, and a second output module. 6.
  • the input module 1 is respectively connected to the input signal terminal Input and the first node A, and is configured to provide the signal of the input signal terminal Input to the first node A under the control of the signal of the input signal terminal Input.
  • the reset module 2 is respectively connected to the reset signal terminal Reset, the reference signal terminal VSS, and the first node A, and is configured to provide the signal of the reference signal terminal VSS to the first node A under the control of the signal of the reset signal terminal Reset.
  • the potential maintaining module 3 is connected to the clock signal terminal CLK and the second node B, respectively, and is configured to keep the voltage difference between the clock signal terminal CLK and the second node B stable when the second node B is in the floating state.
  • the node control module 4 is respectively connected to the input signal terminal Input, the reset signal terminal Reset, the reference signal terminal VSS, the second node B, and the drive signal output terminal Output of the shift register, and is configured to be under the control of the signal of the input signal terminal Input.
  • the signal of the reference signal terminal VSS is supplied to the second node B, and the signal of the reset signal terminal Reset is supplied to the second node B under the control of the signal of the reset signal terminal Reset, and under the control of the signal of the output terminal of the driving signal output
  • the signal of the reference signal terminal VSS is supplied to the second node B.
  • the first output module 5 is respectively connected to the clock signal terminal CLK, the first node A and the driving signal output terminal Output, and is configured to provide the signal of the clock signal terminal CLK to the driving signal output terminal under the control of the signal of the first node A. Output, and keep the voltage difference between the first node A and the drive signal output terminal stable when the first node A is in the floating state.
  • the second output module 6 is respectively connected to the reference signal terminal VSS, the second node B, and the driving signal output terminal Output, and is configured to provide the signal of the reference signal terminal VSS to the driving signal output terminal under the control of the signal of the second node B. Output.
  • the above shift register includes: an input module, a reset module, a node control module, a potential maintaining module, a first output module, and a second output module, wherein the input module is configured to be under the control of a signal at the input signal end Providing a signal of the input signal end to the first node; the reset module is configured to be under the control of the signal of the reset signal end The signal of the reference signal end is provided to the first node; the potential maintaining module is configured to keep the voltage difference between the clock signal end and the second node stable when the second node is in the floating state; the node control module is configured to signal at the input signal end Controlling, the signal of the reference signal end is supplied to the second node, and the signal of the reset signal end is supplied to the second node under the control of the signal of the reset signal end, and the signal of the reference signal end is provided to the control under the control of the signal of the output end of the drive signal a second node; the first output module is configured to provide a signal
  • the above-mentioned shift register provided by the embodiment of the present disclosure can enable the potential maintaining module to maintain the potential of the second node by the mutual cooperation of the above six modules to ensure the normal output of the second output module, thereby improving the output of the shift register. Stability makes the output of the drive signal output more stable.
  • the reference signal terminal when the effective pulse signal of the input signal terminal is at a high potential, the reference signal terminal is at a low potential. Alternatively, when the effective pulse signal of the input signal terminal is at a low potential, the reference signal terminal is at a high potential.
  • the above-mentioned shift register may further include a first node stabilization module 7.
  • the first node stabilization module 7 is respectively connected to the reference signal terminal VSS, the first node A, and the second node B, and is configured to provide the signal of the reference signal terminal VSS to the first node A under the control of the signal of the second node B. .
  • the above shift register provided by the embodiment of the present disclosure, as shown in FIG. 1b, may further include a second node stabilization module 8.
  • the second node stabilization module 8 is respectively connected to the node stability control signal terminal CS and the second node B, and is configured to provide the signal of the node stability control signal terminal CS to the second node under the control of the signal of the node stability control signal terminal CS. B.
  • the foregoing shift register provided by the embodiment of the present disclosure, as shown in FIG. 1b, may include the first node stabilization module 7 and the first Both nodes are stable modules 8.
  • the first node stabilization module 7 is respectively connected to the reference signal terminal VSS, the first node A, and the second node B, and is configured to provide the signal of the reference signal terminal VSS to the first node A under the control of the signal of the second node B. .
  • the second node stabilization module 8 and the node stability control signal terminal CS and The second node B is connected and configured to provide the signal of the node stabilization control signal terminal CS to the second node B under the control of the signal of the node stabilization control signal terminal CS.
  • the node stabilization control signal end may be the same signal end as the reset signal end.
  • the input module 1 may specifically include the first transistor M1.
  • the control electrode and the first pole of the first transistor M1 are both connected to the input signal terminal Input, and the second pole of the first transistor M1 is connected to the first node A.
  • the first transistor M1 when the effective pulse signal of the input signal terminal Input is at a high potential, as shown in FIGS. 2a and 3a, the first transistor M1 may be an N-type transistor. Alternatively, when the effective pulse signal of the input signal terminal Input is low, as shown in FIG. 2b and FIG. 3b, the first transistor M1 may be a P-type transistor, which is not limited herein.
  • the first transistor supplies the signal of the input signal terminal to the first node when it is in an on state under the control of the signal at the input signal terminal.
  • the above is only an example of the specific structure of the input module in the shift register.
  • the specific structure of the input module is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, but may also have other structures known to those skilled in the art, which are not limited herein.
  • the reset module 2 may specifically include a second transistor M2.
  • the control electrode of the second transistor M2 is connected to the reset signal terminal Reset, the first electrode of the second transistor M2 is connected to the reference signal terminal VSS, and the second electrode of the second transistor M2 is connected to the first node A.
  • the second transistor M2 when the effective pulse signal of the reset signal terminal Reset is high, as shown in FIGS. 2a and 3a, the second transistor M2 may be an N-type transistor. Alternatively, when the effective pulse signal of the reset signal terminal Reset is low, as shown in FIG. 2b and FIG. 3b, the second transistor M2 may be a P-type transistor, which is not limited herein.
  • the specific structure of the reset module in the shift register.
  • the specific structure of the reset module is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, but may also have other structures known to those skilled in the art, which are not limited herein.
  • the potential maintaining module 3 may specifically include a first capacitor C1. One end of the first capacitor C1 is connected to the clock signal terminal CLK, and the other end of the first capacitor C1 is connected to the second node B.
  • the voltage difference across the first capacitor can be kept stable, that is, the second node and the clock are maintained.
  • the voltage difference between the signal terminals is stable.
  • the above is merely an example of a specific structure of the potential maintaining module in the shift register.
  • the specific structure of the potential maintaining module is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, but may also have other structures known to those skilled in the art, which are not limited herein.
  • the node control module 4 may specifically include a third transistor M3, a fourth transistor M4, and a fifth transistor M5.
  • the control electrode of the third transistor M3 is connected to the input signal terminal Input, the first electrode of the third transistor M3 is connected to the reference signal terminal VSS, and the second electrode of the third transistor M3 is connected to the second node B.
  • the control electrode and the first pole of the fourth transistor M4 are both connected to the reset signal terminal Reset, and the second pole of the fourth transistor M4 is connected to the second node B.
  • the control electrode of the fifth transistor M5 is connected to the drive signal output terminal Output, the first electrode of the fifth transistor M5 is connected to the reference signal terminal VSS, and the second electrode of the fifth transistor M5 is connected to the second node B.
  • the third transistor M3 and the fifth transistor M5 when the effective pulse signal of the input signal terminal Input is high, as shown in FIG. 2a and FIG. 3a, the third transistor M3 and the fifth transistor M5 may be N-type transistors. . Alternatively, when the effective pulse signal of the input signal terminal Input is low, as shown in FIG. 2b and FIG. 3b, the third transistor M3 and the fifth transistor M5 may be P-type transistors, which are not limited herein.
  • the fourth transistor M4 when the effective pulse signal of the reset signal terminal Reset is at a high potential, as shown in FIGS. 2a and 3a, the fourth transistor M4 may be an N-type transistor.
  • the fourth transistor M4 when the effective pulse signal of the reset signal end Reset is When the potential is low, as shown in FIG. 2b and FIG. 3b, the fourth transistor M4 may be a P-type transistor, which is not limited herein.
  • the third transistor supplies the signal of the reference signal terminal to the second node when it is in an on state under the control of the signal at the input signal terminal.
  • the fourth transistor supplies a signal of the reset signal terminal to the second node when it is in an on state under the control of the signal at the reset signal terminal.
  • the fifth transistor provides a signal of the reference signal terminal to the second node when it is in an on state under the control of the output of the driving signal.
  • the specific structure of the node control module is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, but may also have other structures known to those skilled in the art, which are not limited herein.
  • the first output module 5 may specifically include a sixth transistor M6 and a second capacitor C2.
  • the control electrode of the sixth transistor M6 is connected to the first node A
  • the first electrode of the sixth transistor M6 is connected to the clock signal terminal CLK
  • the second electrode of the sixth transistor M6 is connected to the drive signal output terminal Output.
  • One end of the second capacitor C2 is connected to the first node A, and the other end of the second capacitor C2 is connected to the drive signal output terminal Output.
  • the sixth transistor M6 when the effective pulse signal of the input signal terminal Input is at a high potential, as shown in FIGS. 2a and 3a, the sixth transistor M6 may be an N-type transistor. Alternatively, when the effective pulse signal of the input signal terminal Input is low, as shown in FIG. 2b and FIG. 3b, the sixth transistor M6 may be a P-type transistor, which is not limited herein.
  • the sixth transistor when the sixth transistor is in an on state under the control of the signal of the first node, the signal of the clock signal end is supplied to the output end of the driving signal; In the connected state, due to the bootstrap action of the second capacitor, the voltage difference across the second capacitor can be kept stable, that is, the voltage difference between the first node and the drive signal output terminal is kept stable.
  • the above is merely an example of the specific structure of the first output module in the shift register.
  • the specific structure of the first output module is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, but may also have other structures known to those skilled in the art, which are not limited herein.
  • the second output module 6 may specifically include a seventh transistor M7.
  • the control electrode of the seventh transistor M7 is connected to the second node B, the first electrode of the seventh transistor M7 is connected to the reference signal terminal VSS, and the second electrode of the seventh transistor M7 is connected to the drive signal output terminal Output.
  • the seventh transistor M7 when the effective pulse signal of the input signal terminal Input is at a high potential, as shown in FIGS. 2a and 3a, the seventh transistor M7 may be an N-type transistor. Alternatively, when the effective pulse signal of the input signal terminal Input is low, as shown in FIG. 2b and FIG. 3b, the seventh transistor M7 may be a P-type transistor, which is not limited herein.
  • the seventh transistor supplies the signal of the reference signal terminal to the driving signal output terminal when it is in an on state under the control of the signal of the second node.
  • the specific structure of the second output module in the shift register is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, but may also have other structures known to those skilled in the art, which are not limited herein.
  • the first node stabilization module 7 may specifically include an eighth transistor M8.
  • the control electrode of the eighth transistor M8 is connected to the second node B, the first electrode of the eighth transistor M8 is connected to the reference signal terminal VSS, and the second electrode of the eighth transistor M8 is connected to the first node A.
  • the eighth transistor M8 when the effective pulse signal of the input signal terminal Input is at a high potential, as shown in FIG. 3a, the eighth transistor M8 may be an N-type transistor. Alternatively, when the effective pulse signal of the input signal terminal Input is low, as shown in FIG. 3b, the eighth transistor M8 may be a P-type transistor, which is not limited herein.
  • the eighth transistor supplies the signal of the reference signal terminal to the first node when it is in an on state under the control of the signal of the second node.
  • the specific structure of the first node stabilization module is not limited to the foregoing structure provided by the embodiment of the present disclosure, but may also have other structures known to those skilled in the art, which are not limited herein.
  • the second node stabilization module 8 may specifically include a ninth transistor M9.
  • the control electrode and the first pole of the ninth transistor M9 are both connected to the node stabilization control signal terminal CS, and the second pole of the ninth transistor M9 is connected to the second node B.
  • the ninth transistor M9 when the effective pulse signal of the node stabilization control signal terminal CS is high, as shown in FIG. 3a, the ninth transistor M9 may be an N-type transistor. Alternatively, when the effective pulse signal of the node stabilization control signal terminal CS is low, as shown in FIG. 3b, the ninth transistor M9 may be a P-type transistor, which is not limited herein.
  • the ninth transistor supplies the signal of the node stabilization control signal terminal to the second node when it is in an on state under the control of the signal of the node stabilization control signal terminal.
  • the specific structure of the second node stabilization module is not limited to the foregoing structure provided by the embodiment of the present disclosure, but may also have other structures known to those skilled in the art, which are not limited herein.
  • all the transistors when the effective pulse signal of the input signal terminal Input is high, as shown in FIG. 2a and FIG. 3a, all the transistors may be N-type transistor. Alternatively, when the effective pulse signal of the input signal terminal Input is low, as shown in FIG. 2b and FIG. 3b, all the transistors may be P-type transistors, which is not limited herein.
  • the N-type transistor is turned on under the action of the high potential at the gate electrode, and is turned off by the low potential at the gate electrode.
  • the P-type transistor is turned off by the high potential at the gate, and is turned on by the low potential at the gate.
  • the transistor mentioned in the above embodiments of the present disclosure may be an amorphous silicon thin film transistor (a-Si TFT) or a metal oxide semiconductor (MOS, Metal Oxide Scmiconductor) field effect transistor. Not limited.
  • a-Si TFT amorphous silicon thin film transistor
  • MOS Metal Oxide Scmiconductor
  • the first and second poles of these transistors may be interchanged according to the type of transistor and the input signal, and no specific distinction is made here.
  • both the first transistor M1 and the third transistor M3 are turned on. Since the first transistor M1 is turned on to supply the signal of the high-potential input signal terminal Input to the first node A, the potential of the first node A is high. Since the potential of the first node A is high, the sixth transistor M6 is turned on. Since the sixth transistor M6 is turned on to supply the signal of the low potential clock signal terminal CLK to the driving signal output terminal Output, the second capacitor C2 is charged, and the driving signal output terminal Output is low, that is, the low potential scanning signal is output. . Since the third transistor M3 is turned on to supply the signal of the low potential reference signal terminal VSS to the second node B, the potential of the second node B is low.
  • the second capacitor C2 is connected between the first node A and the driving signal output terminal Output, in order to maintain the stability of the voltage difference across the second capacitor C2, the potential of the first node A passes through the bootstrap action of the second capacitor C2. It is further pulled high, so that the sixth transistor M6 is completely turned on, so that the signal of the high-potential clock signal terminal CLK is supplied to the driving signal output terminal Output without voltage loss, thereby making the driving signal output terminal output high, that is, A high-potential scan signal is output. Since the drive signal output terminal Output is at a high potential, the fifth transistor M5 is turned on.
  • the fifth transistor M5 Since the fifth transistor M5 is turned on to supply the signal of the low potential reference signal terminal VSS to the second node B, the potential of the second node B is low. Since the potential of the second node B is low, the seventh transistor M7 and the eighth transistor M8 are both turned off.
  • the second capacitor C2 is connected between the first node A and the driving signal output terminal Output, in order to maintain the stability of the voltage difference across the second capacitor C2, the potential of the first node A passes through the bootstrap action of the second capacitor C2. Return to a high potential from a state of further pulling up.
  • the signal of the terminal VSS is supplied to the output of the drive signal output, so that the output of the drive signal output is low, that is, the scan signal of the low potential is output. Since the second transistor M2 is turned on to supply the signal of the low potential reference signal terminal VSS to the first node A, the potential of the first node A is low, and the second capacitor C2 is discharged. Since the eighth transistor M8 is turned on to supply the signal of the low potential reference signal terminal VSS to the first node A, it is further ensured that the first node A is at a low potential. Since the potential of the first node A is low, the sixth transistor M6 is turned off.
  • the eighth transistor M8 is turned on to supply the signal of the low potential reference signal terminal VSS to the first node A, it is further ensured that the first node A is at a low potential. Since the potential of the first node A is low, the sixth transistor M6 is turned off.
  • the drive signal output terminal Output is at a low potential, that is, a low potential scan signal is output. Since the eighth transistor M8 is fully turned on and the signal of the low potential reference signal terminal VSS is supplied to the first node A without voltage loss, it is further ensured that the first node A is at a low potential. Since the potential of the first node A is low, the sixth transistor M6 is turned off.
  • the potential of the second node can be maintained at a high potential state to ensure the seventh
  • the transistor is always turned on, thereby supplying a signal of the low potential reference signal terminal to the drive signal output terminal, thereby keeping the drive signal output terminal always at a low potential state. Therefore, the stability of the shift register is improved.
  • display stability of the display device can be improved.
  • both the first transistor M1 and the third transistor M3 are turned on. Since the first transistor M1 is turned on to supply the signal of the low-potential input signal terminal Input to the first node A, the potential of the first node A is low. Since the potential of the first node A is low, the sixth transistor M6 is turned on. Since the sixth transistor M6 is turned on to supply the signal of the high-potential clock signal terminal CLK to the driving signal output terminal Output, the second capacitor C2 is charged, and the driving signal output terminal Output is at a high potential, that is, a high-potential scanning signal is output. .
  • the second capacitor C2 is connected between the first node A and the driving signal output terminal Output, in order to maintain the stability of the voltage difference across the second capacitor C2, the potential of the first node A passes through the bootstrap action of the second capacitor C2. It is further pulled down, so that the sixth transistor M6 is completely turned on, so that the signal of the low-potential clock signal terminal CLK is supplied to the driving signal output terminal Output without voltage loss, thereby making the driving signal output terminal Output low, that is, A low potential scan signal is output. Since the drive signal output terminal Output is at a low potential, the fifth transistor M5 is turned on.
  • the fifth transistor M5 Since the fifth transistor M5 is turned on to supply the signal of the high potential reference signal terminal VSS to the second node B, the potential of the second node B is high. Since the potential of the second node B is high, the seventh transistor M7 and the eighth transistor M8 are both turned off.
  • the second capacitor C2 is connected between the first node A and the driving signal output terminal Output, in order to maintain the stability of the voltage difference across the second capacitor C2, the potential of the first node A passes through the bootstrap action of the second capacitor C2. Return to a low potential from a state of further pulling down.
  • the seventh transistor M7 Since the seventh transistor M7 is turned on to supply the signal of the high potential reference signal terminal VSS to the driving signal output terminal Output, the driving signal output terminal Output is at a high potential, that is, a high potential scanning signal is output. Since the second transistor M2 is turned on to supply the signal of the high potential reference signal terminal VSS to the first node A, the potential of the first node A is high, and the second capacitor C2 is discharged. Since the eighth transistor M8 is turned on to supply the signal of the high potential reference signal terminal VSS to the first node A, it is further ensured that the first node A is at a high potential. Since the potential of the first node A is high, the sixth transistor M6 is turned off.
  • the eighth transistor M8 is turned on to supply the signal of the high potential reference signal terminal VSS to the first node A, it is further ensured that the first node A is at a high potential. Since the potential of the first node A is high, the sixth transistor M6 is turned off.
  • the output of the output is high, that is, the high-level scanning signal is output. Since the eighth transistor M8 is fully turned on and the signal of the high potential reference signal terminal VSS is supplied to the first node A without voltage loss, the first node A is further ensured to be at a high potential. Since the potential of the first node A is high, the sixth transistor M6 is turned off.
  • the fifth stage of the working process is repeatedly executed until the next frame starts.
  • the potential of the second node can be maintained at a low potential state to ensure the seventh
  • the transistor is always turned on, thereby supplying a signal of the high potential reference signal terminal to the drive signal output terminal, thereby keeping the drive signal output terminal always at a high potential state. Therefore, the stability of the shift register is provided.
  • display stability of the display device can be improved.
  • the embodiment of the present disclosure further provides a driving method of any one of the above shift registers provided by the embodiment of the present disclosure.
  • the driving method includes a first stage, a second stage, a third stage, a fourth stage, and a fifth stage.
  • the method includes, at step S501, in the first stage, the input module provides a signal of the input signal end to the first node under the control of the signal of the input signal end; the first output module is The signal of the clock signal terminal is supplied to the drive signal output terminal under the control of the signal of the first node; and the node control module supplies the signal of the reference signal terminal to the second node under the control of the signal of the input signal terminal.
  • the first output module maintains a voltage difference between the first node and the drive signal output terminal when the first node is in the floating state, and controls the signal at the first node.
  • the signal of the clock signal end is supplied to the driving signal output end; the node control module supplies the signal of the reference signal end to the second node under the control of the signal of the driving signal output end.
  • the first output module keeps the voltage difference between the first node and the drive signal output terminal stable when the first node is in the floating state, and controls the signal at the first node.
  • the signal of the clock signal end is supplied to the driving signal output end; and the potential maintaining module keeps the voltage difference between the clock signal end and the second node stable when the second node is in the floating state.
  • the reset module provides the signal of the reference signal end to the first node under the control of the signal of the reset signal end; the node control module is in the reset signal The signal of the reset signal terminal is supplied to the second node under the control of the signal of the number terminal; the second output module supplies the signal of the reference signal terminal to the drive signal output terminal under the control of the signal of the second node.
  • the potential maintaining module keeps the voltage difference between the clock signal end and the second node stable when the second node is in the floating state; the signal of the second output module at the second node The signal of the reference signal terminal is supplied to the drive signal output terminal under control.
  • the potential maintaining module can maintain the potential of the second node to ensure the normal output of the second output module, thereby improving the output stability of the shift register and outputting the output of the driving signal. more stable.
  • the driving method may further include: in the fourth stage, the first node stabilization module is at the second node The signal of the reference signal end is supplied to the first node under the control of the signal, and in the fifth stage, the first node stabilization module provides the signal of the reference signal end to the first node under the control of the signal of the second node.
  • the driving method may further include: in the fourth stage, the signal of the second node stabilization module at the node stability control signal end The signal of the node stability control signal end is supplied to the second node under control.
  • the driving method may further include: in the fourth stage, the first node stabilization module Providing, by the control of the signal of the second node, the signal of the reference signal end to the first node; the second node stabilization module provides the signal of the node stable control signal end to the second node under the control of the signal of the node stable control signal end; In the five stages, the first node stabilization module provides the signal of the reference signal end to the first node under the control of the signal of the second node.
  • the embodiment of the present disclosure further provides a gate driving circuit, as shown in FIG. 6 (FIG. 6 is an example in which a node stable control signal end and a reset signal end in each stage shift register are the same signal end), including a level.
  • M shift registers provided by the disclosed embodiments: SR(1), SR(2)...SR(N-2), SR(N-1), SR(N), SR(N+1 ), SR(N+2), SR(N+3)...SR(M-1), SR(M), wherein M is an integer greater than or equal to 3.
  • the input signal terminal Input of the first stage shift register SR(1) and the first frame trigger signal end The STV1 is connected; the input signal terminal Input of the second stage shift register SR(2) is connected to the second frame trigger signal terminal STV2; the input signal terminal Input of the Nth stage shift register SR(N) is respectively associated with the N-2th stage.
  • the drive signal output terminal Output of the shift register SR(N-2) is connected; and the reset signal end Reset of the N-2th shift register SR(N-2) is respectively associated with the Nth stage shift register SR(N)
  • the drive signal output terminal is connected.
  • N is an integer greater than or equal to 3 and less than or equal to M.
  • each shift register in the above-mentioned gate driving circuit is the same as the above-mentioned shift register of the present disclosure, and the details are not described again.
  • the node stabilization control signal terminal and the input signal terminal in each stage of the shift register may be the same signal terminal.
  • the reference signal terminals VSS of the shift registers of the respective stages are connected to the same DC reference terminal vss.
  • the clock signal terminal CLK of the 4k-3th stage shift register is connected to the first clock terminal ck1 of the same clock terminal, and the clock signal terminal CLK of the 4k-2th stage shift register is connected to the second clock terminal ck2 of the same clock terminal.
  • the clock signal terminal CLK of the 4k-1th stage shift register is connected to the third clock terminal ck3 of the same clock terminal, and the clock signal terminal CLK of the 4kth stage shift register is connected to the fourth clock terminal ck4, where k is greater than Or an integer equal to 1.
  • Embodiments of the present disclosure also provide a display device including the above-described gate driving circuit.
  • the display device provided by the embodiment of the present disclosure further includes a plurality of gate lines: Gate1, Gate2, Gate3, Gate4...GateN-2, GateN-1, GateN, GateN+1, GateN+2 GateN+3...GateM-3, GateM-2, GateM-1, GateM, each gate line GateN corresponds to a drive signal output terminal Output_N of the one-stage shift register SR(N) in the gate drive circuit.
  • Stage shift registers SR(1), SR(2)...SR(N-2), SR(N-1), SR(N), SR(N+1), SR(N+2), SR(N+3)...SR(M-1), SR(M) respectively correspond to the corresponding gate lines Gate1, Gate2, Gate3, Gate4...GateN-2, GateN-1 , GateN, GateN+1, GateN+2, GateN+3...GateM-3, GateM-2, GateM-1, GateM provide scan signals.
  • GateM-2, GateM-1, GateM provide scan signals.
  • the gate driving circuit may be disposed on both sides of the display panel in the display device.
  • the gate driving circuit can also be disposed on the same side of the display panel in the display device, which is not limited herein.
  • the display device may be: a hand Any product or component with display function, such as a computer, tablet, TV, monitor, laptop, digital photo frame, navigator, etc.
  • Other indispensable components of the display device are understood by those skilled in the art, and are not described herein, nor should they be construed as limiting the disclosure.
  • Embodiments of the present disclosure provide a shift register, a driving method thereof, a gate driving circuit, and a display device.
  • the provided shift register comprises: an input module, a reset module, a node control module, a potential maintaining module, a first output module and a second output module, wherein the input module is configured to input the signal end under the control of the signal at the input signal end The signal is provided to the first node; the reset module is configured to provide the signal of the reference signal end to the first node under the control of the signal of the reset signal end; the potential maintaining module is configured to maintain the clock signal end and the second node when the second node is in the floating state The voltage difference between the two nodes is stable; the node control module is configured to provide the signal of the reference signal end to the second node under the control of the signal of the input signal end, and provide the signal of the reset signal end to the second under the control of the signal of the reset signal end a node, and a signal of the reference signal end is provided to the second node under

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Abstract

一种移位寄存器，移位寄存器包括输入模块（1）、复位模块（2）、节点控制模块（4）、电位维持模块（3）、第一输出模块（5）以及第二输出模块（6），该移位寄存器能够保证第二输出模块（6）的正常输出，提高移位寄存器的输出稳定性。还提供了一种移位寄存器的驱动方法、栅极驱动电路及显示装置。

Description

一种移位寄存器、其驱动方法、栅极驱动电路及显示装置
相关申请
本申请要求享有2017年1月5日提交的中国专利申请No.201710008480.X的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开涉及显示技术领域，特别涉及一种移位寄存器、其驱动方法、栅极驱动电路及显示装置。
背景技术
随着显示技术的飞速发展，显示面板越来越向着高集成度和低成本的方向发展。阵列基板行驱动(Gate Driver on Array，GOA)技术将薄膜晶体管(Thin Film Transistor，TFT)控制极开关电路集成在显示面板的阵列基板上以实现对显示面板的扫描驱动，从而可以省去控制极集成电路(Integrated Circuit，IC)的键合(Bonding)区域以及扇出(Fan-out)区域的布线空间。因此，GOA技术不仅可以在材料成本和制备工艺两方面降低产品成本，而且可以使显示面板实现两边对称和窄边框的美观设计。此外，这种集成工艺还可以省去控制极扫描线方向的键合工艺，从而提高产能和良率。
一般的栅极驱动电路由多个级联的移位寄存器组成。通过各级移位寄存器依次向显示面板上的各行栅线输入扫描信号。目前，在各级移位寄存器输出扫描信号的有效脉冲信号之后，当移位寄存器的驱动信号输出端处于低电位维持阶段时，下拉晶体管在下拉节点的信号的控制下将低电位的参考信号提供给驱动信号输出端，以使驱动信号输出端处于低电位的输出状态。然而在低电位维持阶段，下拉晶体管的控制极的电位会出现泄漏，即下拉节点的信号的电位会发生变化，导致下拉晶体管不能完全开启，甚至可能会导致下拉晶体管截止，从而造成驱动信号输出端不能维持低电位的情况。这样的情况可能降低移位寄存器的稳定性，进而可能会造成显示出现异常。
发明内容
本公开实施例提供了一种移位寄存器、其驱动方法、栅极驱动电路及显示装置，其能够至少部分地缓解或甚至消除以上提到的现有技术中的问题。
相应地，本公开实施例提供了一种移位寄存器，包括输入模块、复位模块、电位维持模块、节点控制模块、第一输出模块和第二输出模块。所述输入模块分别与输入信号端以及第一节点相连，并且配置成在所述输入信号端的信号的控制下将所述输入信号端的信号提供给所述第一节点。所述复位模块分别与复位信号端、参考信号端以及所述第一节点相连，并且配置成在所述复位信号端的信号的控制下将所述参考信号端的信号提供给所述第一节点。所述电位维持模块分别与时钟信号端以及第二节点相连，并且配置成在所述第二节点处于浮接状态时，保持所述时钟信号端与所述第二节点之间的电压差稳定。所述节点控制模块分别与所述输入信号端、所述复位信号端、所述参考信号端、所述第二节点以及所述移位寄存器的驱动信号输出端相连，并且配置成在所述输入信号端的信号的控制下将所述参考信号端的信号提供给所述第二节点，在所述复位信号端的信号的控制下将所述复位信号端的信号提供给所述第二节点，以及在所述驱动信号输出端的信号的控制下将所述参考信号端的信号提供给所述第二节点。所述第一输出模块分别与所述时钟信号端、所述第一节点以及所述驱动信号输出端相连，并且配置成在所述第一节点的信号的控制下将所述时钟信号端的信号提供给所述驱动信号输出端，以及在所述第一节点处于浮接状态时，保持所述第一节点与所述驱动信号输出端之间的电压差稳定。所述第二输出模块分别与所述参考信号端、所述第二节点以及所述驱动信号输出端相连，并且配置成在所述第二节点的信号的控制下将所述参考信号端的信号提供给所述驱动信号输出端。
在本公开的一些实施例中，所述电位维持模块包括第一电容器。所述第一电容器的一端与所述时钟信号端相连，并且所述第一电容器的另一端与所述第二节点相连。
在本公开的一些实施例中，所述输入模块包括第一晶体管。所述第一晶体管的控制极和第一极均与所述输入信号端相连，并且所述第一晶体管的第二极与所述第一节点相连。
在本公开的一些实施例中，所述复位模块包括第二晶体管。所述 第二晶体管的控制极与所述复位信号端相连，所述第二晶体管的第一极与所述参考信号端相连，并且所述第二晶体管的第二极与所述第一节点相连。
在本公开的一些实施例中，所述节点控制模块包括第三晶体管、第四晶体管以及第五晶体管。所述第三晶体管的控制极与所述输入信号端相连，所述第三晶体管的第一极与所述参考信号端相连，并且所述第三晶体管的第二极与所述第二节点相连。所述第四晶体管的控制极和第一极均与所述复位信号端相连，并且所述第四晶体管的第二极与所述第二节点相连。所述第五晶体管的控制极与所述驱动信号输出端相连，所述第五晶体管的第一极与所述参考信号端相连，并且所述第五晶体管的第二极与所述第二节点相连。
在本公开的一些实施例中，所述第一输出模块包括第六晶体管和第二电容器。所述第六晶体管的控制极与所述第一节点相连，所述第六晶体管的第一极与所述时钟信号端相连，并且所述第六晶体管的第二极与所述驱动信号输出端相连。所述第二电容器的一端与所述第一节点相连，并且所述第二电容器的另一端与所述驱动信号输出端相连。
在本公开的一些实施例中，所述第二输出模块包括第七晶体管。所述第七晶体管的控制极与所述第二节点相连，所述第七晶体管的第一极与所述参考信号端相连，并且所述第七晶体管的第二极与所述驱动信号输出端相连。
在本公开的一些实施例中，上述移位寄存器还包括第一节点稳定模块。所述第一节点稳定模块分别与所述参考信号端、所述第一节点以及所述第二节点相连，并且配置成在所述第二节点的信号的控制下将所述参考信号端的信号提供给所述第一节点。
在本公开的一些实施例中，所述第一节点稳定模块包括第八晶体管。所述第八晶体管的控制极与所述第二节点相连，所述第八晶体管的第一极与所述参考信号端相连，并且所述第八晶体管的第二极与所述第一节点相连。
在本公开的一些实施例中，上述移位寄存器还包括第二节点稳定模块。所述第二节点稳定模块分别与节点稳定控制信号端以及所述第二节点相连，并且配置成在所述节点稳定控制信号端的信号的控制下将所述节点稳定控制信号端的信号提供给所述第二节点。
在本公开的一些实施例中，所述第二节点稳定模块包括第九晶体管。所述第九晶体管的控制极和第一极均与所述节点稳定控制信号端相连，并且所述第九晶体管的第二极与所述第二节点相连。
相应地，本公开实施例还提供了一种栅极驱动电路，包括级联的M个本公开实施例提供的上述任一种移位寄存器，其中，M为大于或等于3的整数。具体地，第1级移位寄存器的输入信号端与第一帧触发信号端相连；第2级移位寄存器的输入信号端与第二帧触发信号端相连；第N级移位寄存器的输入信号端分别与第N-2级移位寄存器的驱动信号输出端相连；并且第N-2级移位寄存器的复位信号端分别与第N级移位寄存器的驱动信号输出端相连。N为大于或等于3且小于或等于M的整数。
相应地，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述栅极驱动电路。
相应地，本公开实施例还提供了一种本公开实施例提供的上述任一种移位寄存器的驱动方法。所述驱动方法包括第一阶段、第二阶段、第三阶段、第四阶段以及第五阶段。
在所述第一阶段中，所述输入模块在所述输入信号端的信号的控制下将所述输入信号端的信号提供给所述第一节点；所述第一输出模块在所述第一节点的信号的控制下将所述时钟信号端的信号提供给所述驱动信号输出端；并且所述节点控制模块在所述输入信号端的信号的控制下将所述参考信号端的信号提供给所述第二节点。
在所述第二阶段中，所述第一输出模块在所述第一节点处于浮接状态时，保持所述第一节点与所述驱动信号输出端之间的电压差稳定，以及在所述第一节点的信号的控制下将所述时钟信号端的信号提供给所述驱动信号输出端；所述节点控制模块在所述驱动信号输出端的信号的控制下将所述参考信号端的信号提供给所述第二节点。
在所述第三阶段中，所述第一输出模块在所述第一节点处于浮接状态时，保持所述第一节点与所述驱动信号输出端之间的电压差稳定，以及在所述第一节点的信号的控制下将所述时钟信号端的信号提供给所述驱动信号输出端；所述电位维持模块在所述第二节点处于浮接状态时，保持所述时钟信号端与所述第二节点之间的电压差稳定。
在所述第四阶段中，所述复位模块在所述复位信号端的信号的控 制下将所述参考信号端的信号提供给所述第一节点；所述节点控制模块在所述复位信号端的信号的控制下将所述复位信号端的信号提供给所述第二节点；所述第二输出模块在所述第二节点的信号的控制下将所述参考信号端的信号提供给所述驱动信号输出端；
在所述第五阶段中，所述电位维持模块在所述第二节点处于浮接状态时，保持所述时钟信号端与所述第二节点之间的电压差稳定；所述第二输出模块在所述第二节点的信号的控制下将所述参考信号端的信号提供给所述驱动信号输出端。
在本公开的一些实施例中，在各所述移位寄存器还包括所述第一节点稳定模块时，所述驱动方法还包括在所述第四阶段中，所述第一节点稳定模块在所述第二节点的信号的控制下将所述参考信号端的信号提供给所述第一节点，以及在所述第五阶段中，所述第一节点稳定模块在所述第二节点的信号的控制下将所述参考信号端的信号提供给所述第一节点。
在本公开的一些实施例中，在各所述移位寄存器还包括所述第二节点稳定模块时，所述驱动方法还包括在所述第四阶段中，所述第二节点稳定模块在所述节点稳定控制信号端的信号的控制下将所述节点稳定控制信号端的信号提供给所述第二节点。
附图说明
图1a为本公开的一个实施例提供的移位寄存器的结构示意图；
图1b为本公开的另一实施例提供的移位寄存器的结构示意图；
图2a为图1a所示的移位寄存器的一种具体结构示意图；
图2b为图1a所示的移位寄存器的另一种具体结构示意图；
图3a为图1b所示的移位寄存器的一种具体结构示意图；
图3b为图1b所示的移位寄存器的另一种具体结构示意图；
图4a为图3a所示的移位寄存器的输入输出时序图；
图4b为图3b所示的移位寄存器的输入输出时序图；
图5为本公开实施例提供的驱动方法的流程图；以及
图6为本公开实施例提供的栅极驱动电路的结构示意图。
具体实施方式
下面结合附图，对本公开实施例提供的移位寄存器、其驱动方法、栅极驱动电路及显示装置的具体实施方式进行详细的说明。应当理解，此处所描述的示例性实施例仅用于说明和解释本公开，并不用于限定本公开。在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
本公开实施例提供了一种移位寄存器，如图1a和图1b所示，包括输入模块1、复位模块2、电位维持模块3、节点控制模块4、第一输出模块5和第二输出模块6。输入模块1分别与输入信号端Input以及第一节点A相连，并且配置成在输入信号端Input的信号的控制下将输入信号端Input的信号提供给第一节点A。复位模块2分别与复位信号端Reset、参考信号端VSS以及第一节点A相连，并且配置成在复位信号端Reset的信号的控制下将参考信号端VSS的信号提供给第一节点A。电位维持模块3分别与时钟信号端CLK以及第二节点B相连，并且配置成在第二节点B处于浮接状态时，保持时钟信号端CLK与第二节点B之间的电压差稳定。节点控制模块4分别与输入信号端Input、复位信号端Reset、参考信号端VSS、第二节点B以及移位寄存器的驱动信号输出端Output相连，并且配置成在输入信号端Input的信号的控制下将参考信号端VSS的信号提供给第二节点B，在复位信号端Reset的信号的控制下将复位信号端Reset的信号提供给第二节点B，以及在驱动信号输出端Output的信号的控制下将参考信号端VSS的信号提供给第二节点B。第一输出模块5分别与时钟信号端CLK、第一节点A以及驱动信号输出端Output相连，并且配置成在第一节点A的信号的控制下将时钟信号端CLK的信号提供给驱动信号输出端Output，以及在第一节点A处于浮接状态时，保持第一节点A与驱动信号输出端Output之间的电压差稳定。第二输出模块6分别与参考信号端VSS、第二节点B以及驱动信号输出端Output相连，并且配置成在第二节点B的信号的控制下将参考信号端VSS的信号提供给驱动信号输出端Output。
本公开实施例提供的上述移位寄存器包括：输入模块、复位模块、节点控制模块、电位维持模块、第一输出模块以及第二输出模块，其中，输入模块配置成在输入信号端的信号的控制下将输入信号端的信号提供给第一节点；复位模块配置成在复位信号端的信号的控制下将 参考信号端的信号提供给第一节点；电位维持模块配置成在第二节点处于浮接状态时保持时钟信号端与第二节点之间的电压差稳定；节点控制模块配置成在输入信号端的信号的控制下将参考信号端的信号提供给第二节点，在复位信号端的信号的控制下将复位信号端的信号提供给第二节点，以及在驱动信号输出端的信号的控制下将参考信号端的信号提供给第二节点；第一输出模块配置成在第一节点的信号的控制下将时钟信号端的信号提供给驱动信号输出端，以及在第一节点处于浮接状态时，保持第一节点与驱动信号输出端之间的电压差稳定；并且，第二输出模块配置成在第二节点的信号的控制下将参考信号端的信号提供给驱动信号输出端。因此，本公开实施例提供的上述移位寄存器通过上述六个模块的相互配合，可以使电位维持模块保持第二节点的电位，以保证第二输出模块的正常输出，从而提高移位寄存器的输出稳定性，使驱动信号输出端的输出更加稳定。
需要说明的是，在本公开实施例提供的上述移位寄存器中，当输入信号端的有效脉冲信号为高电位时，参考信号端为低电位。可替换地，当输入信号端的有效脉冲信号为低电位时，参考信号端为高电位。
进一步地，为了使第一节点的电位处于稳定状态，本公开实施例提供的上述移位寄存器，如图1b所示，还可以包括第一节点稳定模块7。第一节点稳定模块7分别与参考信号端VSS、第一节点A以及第二节点B相连，并且配置成在第二节点B的信号的控制下将参考信号端VSS的信号提供给第一节点A。
进一步地，为了使第二节点的电位处于稳定状态，本公开实施例提供的上述移位寄存器，如图1b所示，还可以包括第二节点稳定模块8。第二节点稳定模块8分别与节点稳定控制信号端CS以及第二节点B相连，并且配置成在节点稳定控制信号端CS的信号的控制下将节点稳定控制信号端CS的信号提供给第二节点B。
可选地，为了使第一节点A的电位以及第二节点B的电位处于稳定状态，本公开实施例提供的上述移位寄存器，如图1b所示，可以包括第一节点稳定模块7与第二节点稳定模块8二者。第一节点稳定模块7分别与参考信号端VSS、第一节点A以及第二节点B相连，并且配置成在第二节点B的信号的控制下将参考信号端VSS的信号提供给第一节点A。第二节点稳定模块8分别与节点稳定控制信号端CS以及 第二节点B相连，并且配置成在节点稳定控制信号端CS的信号的控制下将节点稳定控制信号端CS的信号提供给第二节点B。
进一步地，为了减少信号线的数量，在本公开实施例提供的上述移位寄存器中，节点稳定控制信号端可以与复位信号端为同一信号端。
下面结合具体实施例，对本公开进行详细说明。需要说明的是，提供这些具体实施例来更好地解释本公开，但不限制本公开的范围。
在本公开实施例提供的上述移位寄存器中，如图2a至图3b所示，输入模块1具体可以包括第一晶体管M1。第一晶体管M1的控制极和第一极均与输入信号端Input相连，并且第一晶体管M1的第二极与第一节点A相连。
在本公开实施例提供的上述移位寄存器中，当输入信号端Input的有效脉冲信号为高电位时，如图2a和图3a所示，第一晶体管M1可以为N型晶体管。可替换地，当输入信号端Input的有效脉冲信号为低电位时，如图2b和图3b所示，第一晶体管M1可以为P型晶体管，在此不作限定。
在本公开实施例提供的上述移位寄存器中，第一晶体管当在输入信号端的信号的控制下处于导通状态时，将输入信号端的信号提供给第一节点。
以上仅是举例说明移位寄存器中的输入模块的具体结构。在具体实施时，输入模块的具体结构不限于本公开实施例提供的上述结构，而是还可以具有本领域技术人员可知的其他结构，在此不作限定。
在本公开实施例提供的上述移位寄存器中，如图2a至图3b所示，复位模块2具体可以包括第二晶体管M2。第二晶体管M2的控制极与复位信号端Reset相连，第二晶体管M2的第一极与参考信号端VSS相连，并且第二晶体管M2的第二极与第一节点A相连。
在本公开实施例提供的上述移位寄存器中，当复位信号端Reset的有效脉冲信号为高电位时，如图2a和图3a所示，第二晶体管M2可以为N型晶体管。可替换地，当复位信号端Reset的有效脉冲信号为低电位时，如图2b和图3b所示，第二晶体管M2可以为P型晶体管，在此不作限定。
在本公开实施例提供的上述移位寄存器中，第二晶体管当在复位信号端的信号的控制下处于导通状态时，将参考信号端的信号提供给 第一节点。
以上仅是举例说明移位寄存器中的复位模块的具体结构。在具体实施时，复位模块的具体结构不限于本公开实施例提供的上述结构，而是还可以具有本领域技术人员可知的其他结构，在此不作限定。
在本公开实施例提供的上述移位寄存器中，如图2a至图3b所示，电位维持模块3具体可以包括第一电容器C1。第一电容器C1的一端与时钟信号端CLK相连，并且第一电容器C1的另一端与第二节点B相连。
在本公开实施例提供的上述移位寄存器中，在第二节点处于浮接状态时，由于第一电容器的自举作用，可以保持第一电容器两端的电压差稳定，即保持第二节点与时钟信号端之间的电压差稳定。
以上仅是举例说明移位寄存器中的电位维持模块的具体结构。在具体实施时，电位维持模块的具体结构不限于本公开实施例提供的上述结构，而是还可以具有本领域技术人员可知的其他结构，在此不作限定。
在本公开实施例提供的上述移位寄存器中，如图2a至图3b所示，节点控制模块4具体可以包括第三晶体管M3、第四晶体管M4以及第五晶体管M5。第三晶体管M3的控制极与输入信号端Input相连，第三晶体管M3的第一极与参考信号端VSS相连，并且第三晶体管M3的第二极与第二节点B相连。第四晶体管M4的控制极和第一极均与复位信号端Reset相连，并且第四晶体管M4的第二极与第二节点B相连。第五晶体管M5的控制极与驱动信号输出端Output相连，第五晶体管M5的第一极与参考信号端VSS相连，并且第五晶体管M5的第二极与第二节点B相连。
在本公开实施例提供的上述移位寄存器中，当输入信号端Input的有效脉冲信号为高电位时，如图2a和图3a所示，第三晶体管M3和第五晶体管M5可以为N型晶体管。可替换地，当输入信号端Input的有效脉冲信号为低电位时，如图2b和图3b所示，第三晶体管M3和第五晶体管M5可以为P型晶体管，在此不作限定。
在本公开实施例提供的上述移位寄存器中，当复位信号端Reset的有效脉冲信号为高电位时，如图2a和图3a所示，第四晶体管M4可以为N型晶体管。可替换地，当复位信号端Reset的有效脉冲信号为 低电位时，如图2b和图3b所示，第四晶体管M4可以为P型晶体管，在此不作限定。
在本公开实施例提供的上述移位寄存器中，第三晶体管当在输入信号端的信号的控制下处于导通状态时，将参考信号端的信号提供给第二节点。第四晶体管当在复位信号端的信号的控制下处于导通状态时，将复位信号端的信号提供给第二节点。第五晶体管当在驱动信号输出端的控制下处于导通状态时，将参考信号端的信号提供给第二节点。
以上仅是举例说明移位寄存器中的节点控制模块的具体结构。在具体实施时，节点控制模块的具体结构不限于本公开实施例提供的上述结构，而是还可以具有本领域技术人员可知的其他结构，在此不作限定。
在本公开实施例提供的上述移位寄存器中，如图2a至图3b所示，第一输出模块5具体可以包括第六晶体管M6和第二电容器C2。第六晶体管M6的控制极与第一节点A相连，第六晶体管M6的第一极与时钟信号端CLK相连，并且第六晶体管M6的第二极与驱动信号输出端Output相连。第二电容器C2的一端与第一节点A相连，并且第二电容器C2的另一端与驱动信号输出端Output相连。
在本公开实施例提供的上述移位寄存器中，当输入信号端Input的有效脉冲信号为高电位时，如图2a和图3a所示，第六晶体管M6可以为N型晶体管。可替换地，当输入信号端Input的有效脉冲信号为低电位时，如图2b和图3b所示，第六晶体管M6可以为P型晶体管，在此不作限定。
在本公开实施例提供的上述移位寄存器中，第六晶体管当在第一节点的信号的控制下处于导通状态时，将时钟信号端的信号提供给驱动信号输出端；在第一节点处于浮接状态时，由于第二电容器的自举作用，可以保持第二电容器两端的电压差稳定，即保持第一节点与驱动信号输出端之间的电压差稳定。
以上仅是举例说明移位寄存器中的第一输出模块的具体结构。在具体实施时，第一输出模块的具体结构不限于本公开实施例提供的上述结构，而是还可以具有本领域技术人员可知的其他结构，在此不作限定。
在本公开实施例提供的上述移位寄存器中，如图2a至图3b所示，第二输出模块6具体可以包括第七晶体管M7。第七晶体管M7的控制极与第二节点B相连，第七晶体管M7的第一极与参考信号端VSS相连，并且第七晶体管M7的第二极与驱动信号输出端Output相连。
在本公开实施例提供的上述移位寄存器中，当输入信号端Input的有效脉冲信号为高电位时，如图2a和图3a所示，第七晶体管M7可以为N型晶体管。可替换地，当输入信号端Input的有效脉冲信号为低电位时，如图2b和图3b所示，第七晶体管M7可以为P型晶体管，在此不作限定。
在本公开实施例提供的上述移位寄存器中，第七晶体管当在第二节点的信号的控制下处于导通状态时，将参考信号端的信号提供给驱动信号输出端。
以上仅是举例说明移位寄存器中的第二输出模块的具体结构。在具体实施时，第二输出模块的具体结构不限于本公开实施例提供的上述结构，而是还可以具有本领域技术人员可知的其他结构，在此不作限定。
在本公开实施例提供的上述移位寄存器中，如图3a和图3b所示，第一节点稳定模块7具体可以包括第八晶体管M8。第八晶体管M8的控制极与第二节点B相连，第八晶体管M8的第一极与参考信号端VSS相连，并且第八晶体管M8的第二极与第一节点A相连。
在本公开实施例提供的上述移位寄存器中，当输入信号端Input的有效脉冲信号为高电位时，如图3a所示，第八晶体管M8可以为N型晶体管。可替换地，当输入信号端Input的有效脉冲信号为低电位时，如图3b所示，第八晶体管M8可以为P型晶体管，在此不作限定。
在本公开实施例提供的上述移位寄存器中，第八晶体管当在第二节点的信号的控制下处于导通状态时，将参考信号端的信号提供给第一节点。
以上仅是举例说明移位寄存器中的第一节点稳定模块的具体结构。在具体实施时，第一节点稳定模块的具体结构不限于本公开实施例提供的上述结构，而是还可以具有本领域技术人员可知的其他结构，在此不作限定。
在本公开实施例提供的上述移位寄存器中，如图3a和图3b所示， 第二节点稳定模块8具体可以包括第九晶体管M9。第九晶体管M9的控制极和第一极均与节点稳定控制信号端CS相连，并且第九晶体管M9的第二极与第二节点B相连。
在本公开实施例提供的上述移位寄存器中，当节点稳定控制信号端CS的有效脉冲信号为高电位时，如图3a所示，第九晶体管M9可以为N型晶体管。可替换地，当节点稳定控制信号端CS的有效脉冲信号为低电位时，如图3b所示，第九晶体管M9可以为P型晶体管，在此不作限定。
在本公开实施例提供的上述移位寄存器中，第九晶体管当在节点稳定控制信号端的信号的控制下处于导通状态时，将节点稳定控制信号端的信号提供给第二节点。
以上仅是举例说明移位寄存器中的第二节点稳定模块的具体结构。在具体实施时，第二节点稳定模块的具体结构不限于本公开实施例提供的上述结构，而是还可以具有本领域技术人员可知的其他结构，在此不作限定。
可选地，为了简化制备工艺，在本公开实施例提供的上述移位寄存器中，当输入信号端Input的有效脉冲信号为高电位时，如图2a和图3a所示，所有晶体管均可以为N型晶体管。可替换地，当输入信号端Input的有效脉冲信号为低电位时，如图2b和图3b所示，所有晶体管均可以为P型晶体管，在此不作限定。
进一步的，在本公开实施例提供的上述移位寄存器中，N型晶体管在控制极处的高电位的作用下导通，并且在控制极处的低电位的作用下截止。P型晶体管在控制极处的高电位的作用下截止，并且在控制极处的低电位的作用下导通。
需要说明的是，在本公开的上述实施例中提到的晶体管可以是非晶硅薄膜晶体管(a-Si TFT)，也可以是金属氧化物半导体(MOS，Metal Oxide Scmiconductor)场效应晶体管，在此不作限定。在具体实施中，这些晶体管的第一极和第二极可以根据晶体管类型以及输入信号的不同而进行互换，在此不做具体区分。
下面结合电路时序图对本公开实施例提供的上述移位寄存器的工作过程进行描述。在以下描述中，以1表示高电位信号，0表示低电位信号，其中，1和0代表逻辑电位，并且仅是为了更好的解释本公开实 施例提供的上述移位寄存器的工作过程，而不是施加在各晶体管的控制极上的实际电位。
以图3a所示的移位寄存器的结构为例对其工作过程进行描述。在图3a所示的移位寄存器中，所有晶体管均为N型晶体管，各N型晶体管在控制极处的高电位的作用下导通，并且在控制极处的低电位的作用下截止。对应的输入输出时序图如图4a所示。
在第一阶段T1中，Input＝1，Reset＝0，CLK＝0，CS＝0。
由于Input＝1，因此第一晶体管M1和第三晶体管M3均导通。由于第一晶体管M1导通而将高电位的输入信号端Input的信号提供给第一节点A，因此第一节点A的电位为高电位。由于第一节点A的电位为高电位，因此第六晶体管M6导通。由于第六晶体管M6导通而将低电位的时钟信号端CLK的信号提供给驱动信号输出端Output，因此第二电容器C2充电，并且驱动信号输出端Output为低电位，即输出低电位的扫描信号。由于第三晶体管M3导通而将低电位的参考信号端VSS的信号提供给第二节点B，因此第二节点B的电位为低电位。由于第二节点B的电位为低电位，因此第七晶体管M7和第八晶体管M8均截止。由于驱动信号输出端Output为低电位，因此第五晶体管M5截止。由于CS＝0，因此第九晶体管M9截止。由于Reset＝0，因此第二晶体管M2和第四晶体管M4均截止。
在第二阶段T2中，在前半阶段，Input＝0，Reset＝0，CLK＝0，CS＝0。
由于Input＝0，因此第一晶体管M1和第三晶体管M3均截止。由于CS＝0，因此第九晶体管M9截止。由于Reset＝0，因此第二晶体管M2和第四晶体管M4均截止，使得第一节点A处于浮接状态。当第一节点A处于浮接状态时，第一节点A的电位保持为高电位，使得第六晶体管M6导通。由于第六晶体管M6导通而将低电位的时钟信号端CLK的信号提供给驱动信号输出端Output，因此驱动信号输出端Output为低电位，即输出低电位的扫描信号。
在第二阶段T2中，在后半阶段，Input＝0，Reset＝0，CLK＝1，CS＝0。
由于Input＝0，因此第一晶体管M1和第三晶体管M3均截止。由于CS＝0，因此第九晶体管M9截止。由于Reset＝0，因此第二晶体管M2和第四晶体管M4均截止，并且第一节点A处于浮接状态。由于第一节点A处于浮接状态，因此第一节点A的电位保持为高电位，使得 第六晶体管M6导通。由于第六晶体管M6导通而将高电位的时钟信号端CLK的信号提供给驱动信号输出端Output，因此驱动信号输出端Output为高电位，即输出高电位的扫描信号。由于第二电容器C2连接于第一节点A和驱动信号输出端Output之间，因此为了保持第二电容器C2两端的电压差的稳定，第一节点A的电位通过第二电容器C2的自举作用而被进一步拉高，使得第六晶体管M6完全导通，从而使高电位的时钟信号端CLK的信号被无电压损失的提供给驱动信号输出端Output，进而使得驱动信号输出端Output为高电位，即输出高电位的扫描信号。由于驱动信号输出端Output为高电位，因此第五晶体管M5导通。由于第五晶体管M5导通而将低电位的参考信号端VSS的信号提供给第二节点B，因此第二节点B的电位为低电位。由于第二节点B的电位为低电位，因此第七晶体管M7和第八晶体管M8均截止。
在第三阶段T3中，Input＝0，Reset＝0，CLK＝0，CS＝0。
由于Input＝0，因此第一晶体管M1和第三晶体管M3均截止。由于CS＝0，因此第九晶体管M9截止。由于Reset＝0，因此第二晶体管M2和第四晶体管M4均截止，并且第一节点A处于浮接状态。由于第一节点A处于浮接状态，因此第一节点A的电位保持为高电位，使得第六晶体管M6导通。由于第六晶体管M6导通而将低电位的时钟信号端CLK的信号提供给驱动信号输出端Output，因此驱动信号输出端Output为低电位，即输出低电位的扫描信号。由于第二电容器C2连接于第一节点A和驱动信号输出端Output之间，因此为了保持第二电容器C2两端的电压差的稳定，第一节点A的电位通过第二电容器C2的自举作用而从进一步拉高的状态恢复到高电位。
在第四阶段T4中，Input＝0，Reset＝1，CLK＝0，CS＝1。
由于Input＝0，因此第一晶体管M1和第三晶体管M3均截止。由于Reset＝1，因此第二晶体管M2和第四晶体管M4均导通。由于第四晶体管M4导通而将高电位的复位信号端Reset的信号提供给第二节点B，因此第二节点B为高电位，从而对第一电容器C1充电。由于CS＝1，因此第九晶体管M9导通。由于第九晶体管M9导通而将高电位的节点稳定控制信号端CS的信号提供给第二节点B，因此进一步保证第二节点B为高电位。由于第二节点B为高电位，因此第七晶体管M7和第八晶体管M8均导通。由于第七晶体管M7导通而将低电位的参考信号 端VSS的信号提供给驱动信号输出端Output，因此驱动信号输出端Output为低电位，即输出低电位的扫描信号。由于第二晶体管M2导通而将低电位的参考信号端VSS的信号提供给第一节点A，因此第一节点A的电位为低电位，并且使得第二电容器C2放电。由于第八晶体管M8导通而将低电位的参考信号端VSS的信号提供给第一节点A，因此进一步保证第一节点A为低电位。由于第一节点A的电位为低电位，因此第六晶体管M6截止。
在第五阶段T5中，在前半阶段，Input＝0，Reset＝0，CLK＝0，CS＝0。
由于Input＝0，因此第一晶体管M1和第三晶体管M3均截止。由于CS＝0，因此第九晶体管M9截止。由于Reset＝0，因此第二晶体管M2和第四晶体管M4均截止，并且第二节点B处于浮接状态。由于第二节点B处于浮接状态，因此第二节点B的电位保持为高电位，使得第七晶体管M7和第八晶体管M8均导通。由于第七晶体管M7导通而将低电位的参考信号端VSS的信号提供给驱动信号输出端Output，因此驱动信号输出端Output为低电位，即输出低电位的扫描信号。由于第八晶体管M8导通而将低电位的参考信号端VSS的信号提供给第一节点A，因此进一步保证第一节点A为低电位。由于第一节点A的电位为低电位，因此第六晶体管M6截止。
在第五阶段T5中，在后半阶段，Input＝0，Reset＝0，CLK＝1，CS＝0。
由于Input＝0，因此第一晶体管M1和第三晶体管M3均截止。由于CS＝0，因此第九晶体管M9截止。由于Reset＝0，因此第二晶体管M2和第四晶体管M4均截止，并且第二节点B处于浮接状态。由于第二节点B处于浮接状态，CLK＝1并且第一电容器C1连接于第二节点B和时钟信号端CLK之间，因此第二节点B的电位通过第一电容器C1的自举作用而被进一步拉高，使得第七晶体管M7和第八晶体管M8完全导通。由于第七晶体管M7完全导通而将低电位的参考信号端VSS的信号无电压损失地提供给驱动信号输出端Output，因此驱动信号输出端Output为低电位，即输出低电位的扫描信号。由于第八晶体管M8完全导通而将低电位的参考信号端VSS的信号无电压损失地提供给第一节点A，因此进一步保证第一节点A为低电位。由于第一节点A的电位为低电位，因此第六晶体管M6截止。
在本公开实施例提供的上述移位寄存器中，在第五阶段之后，一 直重复执行第五阶段的工作过程，直至下一帧开始。
在本公开实施例提供的上述移位寄存器中，在第五阶段及第五阶段之后，由于第一电容器的自举作用，可以使第二节点的电位保持为高电位的状态，以保证第七晶体管始终导通，从而将低电位的参考信号端的信号提供给驱动信号输出端，进而保持驱动信号输出端始终为低电位的状态。因此，移位寄存器的稳定性被提高。当该移位寄存器应用于显示装置时，可以提高显示装置的显示稳定性。
以图3b所示的移位寄存器的结构为例对其工作过程进行描述。在图3b所示的移位寄存器中，所有晶体管均为P型晶体管，各P型晶体管在控制极处的低电位的作用下导通，并且在控制极处的高电位的作用下截止。对应的输入输出时序图如图4b所示。
在第一阶段T1中，Input＝0，Reset＝1，CLK＝1，CS＝1。
由于Input＝0，因此第一晶体管M1和第三晶体管M3均导通。由于第一晶体管M1导通而将低电位的输入信号端Input的信号提供给第一节点A，因此第一节点A的电位为低电位。由于第一节点A的电位为低电位，因此第六晶体管M6导通。由于第六晶体管M6导通二将高电位的时钟信号端CLK的信号提供给驱动信号输出端Output，因此第二电容器C2充电，并且驱动信号输出端Output为高电位，即输出高电位的扫描信号。由于第三晶体管M3导通而将高电位的参考信号端VSS的信号提供给第二节点B，因此第二节点B的电位为高电位。由于第二节点B的电位为高电位，因此第七晶体管M7和第八晶体管M8均截止。由于驱动信号输出端Output为高电位，因此第五晶体管M5截止。由于CS＝1，因此第九晶体管M9截止。由于Reset＝1，因此第二晶体管M2和第四晶体管M4均截止。
在第二阶段T2中，在前半阶段，Input＝1，Reset＝1，CLK＝1，CS＝1。
由于Input＝1，因此第一晶体管M1和第三晶体管M3均截止。由于CS＝1，因此第九晶体管M9截止。由于Reset＝1，因此第二晶体管M2和第四晶体管M4均截止，使得第一节点A处于浮接状态。当第一节点A处于浮接状态时，第一节点A的电位保持为低电位，使得第六晶体管M6导通。由于第六晶体管M6导通而将高电位的时钟信号端CLK的信号提供给驱动信号输出端Output，因此驱动信号输出端Output为高电位，即输出高电位的扫描信号。
在第二阶段T2中，在后半阶段，Input＝1，Reset＝1，CLK＝0，CS＝1。
由于Input＝1，因此第一晶体管M1和第三晶体管M3均截止。由于CS＝1，因此第九晶体管M9截止。由于Reset＝1，因此第二晶体管M2和第四晶体管M4均截止，并且第一节点A处于浮接状态。由于第一节点A处于浮接状态，因此第一节点A的电位保持为低电位，使得第六晶体管M6导通。由于第六晶体管M6导通而将低电位的时钟信号端CLK的信号提供给驱动信号输出端Output，因此驱动信号输出端Output为低电位，即输出低电位的扫描信号。由于第二电容器C2连接于第一节点A和驱动信号输出端Output之间，因此为了保持第二电容器C2两端的电压差的稳定，第一节点A的电位通过第二电容器C2的自举作用而被进一步拉低，使得第六晶体管M6完全导通，从而使低电位的时钟信号端CLK的信号被无电压损失的提供给驱动信号输出端Output，进而使得驱动信号输出端Output为低电位，即输出低电位的扫描信号。由于驱动信号输出端Output为低电位，因此第五晶体管M5导通。由于第五晶体管M5导通而将高电位的参考信号端VSS的信号提供给第二节点B，因此第二节点B的电位为高电位。由于第二节点B的电位为高电位，因此第七晶体管M7和第八晶体管M8均截止。
在第三阶段T3中，Input＝1，Reset＝1，CLK＝1，CS＝1。
由于Input＝1，因此第一晶体管M1和第三晶体管M3均截止。由于CS＝1，因此第九晶体管M9截止。由于Reset＝1，因此第二晶体管M2和第四晶体管M4均截止，并且第一节点A处于浮接状态。由于第一节点A处于浮接状态，因此第一节点A的电位保持为低电位，使得第六晶体管M6导通。由于第六晶体管M6导通而将高电位的时钟信号端CLK的信号提供给驱动信号输出端Output，因此驱动信号输出端Output为高电位，即输出高电位的扫描信号。由于第二电容器C2连接于第一节点A和驱动信号输出端Output之间，因此为了保持第二电容器C2两端的电压差的稳定，第一节点A的电位通过第二电容器C2的自举作用而从进一步拉低的状态恢复到低电位。
在第四阶段T4中，Input＝1，Reset＝0，CLK＝1，CS＝0。
由于Input＝1，因此第一晶体管M1和第三晶体管M3均截止。由于Reset＝0，因此第二晶体管M2和第四晶体管M4均导通。由于第四晶体管M4导通而将低电位的复位信号端Reset的信号提供给第二节点 B，因此第二节点B为低电位，从而对第一电容器C1充电。由于CS＝0，因此第九晶体管M9导通。由于第九晶体管M9导通而将低电位的节点稳定控制信号端CS的信号提供给第二节点B，因此进一步保证第二节点B为低电位。由于第二节点B为低电位，因此第七晶体管M7和第八晶体管M8均导通。由于第七晶体管M7导通而将高电位的参考信号端VSS的信号提供给驱动信号输出端Output，因此驱动信号输出端Output为高电位，即输出高电位的扫描信号。由于第二晶体管M2导通而将高电位的参考信号端VSS的信号提供给第一节点A，因此第一节点A的电位为高电位，并且使得第二电容器C2放电。由于第八晶体管M8导通而将高电位的参考信号端VSS的信号提供给第一节点A，因此进一步保证第一节点A为高电位。由于第一节点A的电位为高电位，因此第六晶体管M6截止。
在第五阶段T5中，在前半阶段，Input＝1，Reset＝1，CLK＝1，CS＝1。
由于Input＝1，因此第一晶体管M1和第三晶体管M3均截止。由于CS＝1，因此第九晶体管M9截止。由于Reset＝1，因此第二晶体管M2和第四晶体管M4均截止，并且第二节点B处于浮接状态。由于第二节点B处于浮接状态，因此第二节点B的电位保持为低电位，使得第七晶体管M7和第八晶体管M8均导通。由于第七晶体管M7导通而将高电位的参考信号端VSS的信号提供给驱动信号输出端Output，因此驱动信号输出端Output为高电位，即输出高电位的扫描信号。由于第八晶体管M8导通而将高电位的参考信号端VSS的信号提供给第一节点A，因此进一步保证第一节点A为高电位。由于第一节点A的电位为高电位，因此第六晶体管M6截止。
在第五阶段T5中，在后半阶段，Input＝1，Reset＝1，CLK＝0，CS＝1。
由于Input＝1，因此第一晶体管M1和第三晶体管M3均截止。由于CS＝1，因此第九晶体管M9截止。由于Reset＝1，因此第二晶体管M2和第四晶体管M4均截止，并且第二节点B处于浮接状态。由于第二节点B处于浮接状态，CLK＝0并且第一电容器C1连接于第二节点B和时钟信号端CLK之间，因此第二节点B的电位通过第一电容器C1的自举作用而被进一步拉低，使得第七晶体管M7和第八晶体管M8完全导通。由于第七晶体管M7完全导通而将高电位的参考信号端VSS的信号无电压损失地提供给驱动信号输出端Output，因此驱动信号输 出端Output为高电位，即输出高电位的扫描信号。由于第八晶体管M8完全导通而将高电位的参考信号端VSS的信号无电压损失地提供给第一节点A，因此进一步保证第一节点A为高电位。由于第一节点A的电位为高电位，因此第六晶体管M6截止。
在本公开实施例提供的上述移位寄存器中，在第五阶段之后，一直重复执行第五阶段的工作过程，直至下一帧开始。
在本公开实施例提供的上述移位寄存器中，在第五阶段及第五阶段之后，由于第一电容器的自举作用，可以使第二节点的电位保持为低电位的状态，以保证第七晶体管始终导通，从而将高电位的参考信号端的信号提供给驱动信号输出端，进而保持驱动信号输出端始终为高电位的状态。因此，移位寄存器的稳定性被提供。当该移位寄存器应用于显示装置时，可以提高显示装置的显示稳定性。
本公开实施例还提供了一种本公开实施例提供的上述任一种移位寄存器的驱动方法。所述驱动方法包括第一阶段、第二阶段、第三阶段、第四阶段以及第五阶段。
具体地，如图5所述，所述方法包括在步骤S501处，在第一阶段中，输入模块在输入信号端的信号的控制下将输入信号端的信号提供给第一节点；第一输出模块在第一节点的信号的控制下将时钟信号端的信号提供给驱动信号输出端；并且节点控制模块在输入信号端的信号的控制下将参考信号端的信号提供给第二节点。
在步骤S502处，在第二阶段中，第一输出模块在第一节点处于浮接状态时，保持第一节点与驱动信号输出端之间的电压差稳定，以及在第一节点的信号的控制下将时钟信号端的信号提供给驱动信号输出端；节点控制模块在驱动信号输出端的信号的控制下将参考信号端的信号提供给第二节点。
在步骤S503处，在第三阶段中，第一输出模块在第一节点处于浮接状态时，保持第一节点与驱动信号输出端之间的电压差稳定，以及在第一节点的信号的控制下将时钟信号端的信号提供给驱动信号输出端；电位维持模块在第二节点处于浮接状态时，保持时钟信号端与第二节点之间的电压差稳定。
在步骤S504处，在第四阶段中，复位模块在复位信号端的信号的控制下将参考信号端的信号提供给第一节点；节点控制模块在复位信 号端的信号的控制下将复位信号端的信号提供给第二节点；第二输出模块在第二节点的信号的控制下将参考信号端的信号提供给驱动信号输出端。
在步骤S505处，在第五阶段中，电位维持模块在第二节点处于浮接状态时，保持时钟信号端与第二节点之间的电压差稳定；第二输出模块在第二节点的信号的控制下将参考信号端的信号提供给驱动信号输出端。
通过本公开实施例提供的上述驱动方法，可以使电位维持模块保持第二节点的电位，以保证第二输出模块的正常输出，从而提高了移位寄存器的输出稳定性，使驱动信号输出端的输出更加稳定。
进一步地，在本公开实施例提供的上述驱动方法中，在各移位寄存器还包括第一节点稳定模块时，驱动方法还可以包括在第四阶段中，第一节点稳定模块在第二节点的信号的控制下将参考信号端的信号提供给第一节点，并且在第五阶段中，第一节点稳定模块在第二节点的信号的控制下将参考信号端的信号提供给第一节点。
在本公开实施例提供的上述驱动方法中，在各移位寄存器还包括第二节点稳定模块时，驱动方法还可以包括在第四阶段中，第二节点稳定模块在节点稳定控制信号端的信号的控制下将节点稳定控制信号端的信号提供给第二节点。
在本公开实施例提供的上述驱动方法中，在各移位寄存器还包括第一节点稳定模块和第二节点稳定模块二者时，驱动方法还可以包括在第四阶段中，第一节点稳定模块在第二节点的信号的控制下将参考信号端的信号提供给第一节点；第二节点稳定模块在节点稳定控制信号端的信号的控制下将节点稳定控制信号端的信号提供给第二节点；在第五阶段中，第一节点稳定模块在第二节点的信号的控制下将参考信号端的信号提供给第一节点。
本公开实施例还提供了一种栅极驱动电路，如图6(图6是以每级移位寄存器中的节点稳定控制信号端与复位信号端为同一信号端为例)所示，包括级联的M个本公开实施例提供的移位寄存器：SR(1)、SR(2)...SR(N-2)、SR(N-1)、SR(N)、SR(N+1)、SR(N+2)、SR(N+3)...SR(M-1)、SR(M)，其中，M为大于或等于3的整数。具体地，第1级移位寄存器SR(1)的输入信号端Input与第一帧触发信号端 STV1相连；第2级移位寄存器SR(2)的输入信号端Input与第二帧触发信号端STV2相连；第N级移位寄存器SR(N)的输入信号端Input分别与第N-2级移位寄存器SR(N-2)的驱动信号输出端Output相连；并且第N-2级移位寄存器SR(N-2)的复位信号端Reset分别与第N级移位寄存器SR(N)的驱动信号输出端Output相连。N为大于或等于3且小于或等于M的整数。
具体地，上述栅极驱动电路中的每个移位寄存器的具体结构与本公开上述移位寄存器在功能和结构上均相同，重复之处不再赘述。
在一些示例性实施例中，为了减少信号线的数量，每级移位寄存器中的节点稳定控制信号端与输入信号端可以为同一信号端。
在本公开实施例提供的上述栅极驱动电路中，如图6所示，各级移位寄存器的参考信号端VSS均与同一直流参考端vss相连。第4k-3级移位寄存器的时钟信号端CLK均与同一时钟端第一时钟端ck1相连，第4k-2级移位寄存器的时钟信号端CLK均与同一时钟端第二时钟端ck2相连，第4k-1级移位寄存器的时钟信号端CLK均与同一时钟端第三时钟端ck3相连，并且第4k级移位寄存器的时钟信号端CLK与第四时钟端ck4相连，其中，k为大于或等于1的整数。
本公开实施例还提供了一种显示装置，包括上述的栅极驱动电路。
本公开实施例提供的上述显示装置，如图6所示，还包括多条栅线：Gate1、Gate2、Gate3、Gate4...GateN-2、GateN-1、GateN、GateN+1、GateN+2、GateN+3...GateM-3、GateM-2、GateM-1、GateM，每一条栅线GateN对应连接栅极驱动电路中的一级移位寄存器SR(N)的驱动信号输出端Output_N。该栅极驱动电路中的各级移位寄存器SR(1)、SR(2)...SR(N-2)、SR(N-1)、SR(N)、SR(N+1)、SR(N+2)、SR(N+3)...SR(M-1)、SR(M)分别向对应的栅线Gate1、Gate2、Gate3、Gate4...GateN-2、GateN-1、GateN、GateN+1、GateN+2、GateN+3...GateM-3、GateM-2、GateM-1、GateM提供扫描信号，其具体实施可参见上述栅极驱动电路的描述，相同之处不再赘述。
在本公开实施例提供的上述显示装置中，如图6所示，栅极驱动电路可以设置在显示装置中的显示面板的两侧。当然，栅极驱动电路也可以设置在显示装置中的显示面板的同一侧，在此不作限定。
在本公开实施例提供的上述显示装置中，该显示装置可以为：手 机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供了移位寄存器、其驱动方法、栅极驱动电路及显示装置。所提供的移位寄存器包括：输入模块、复位模块、节点控制模块、电位维持模块、第一输出模块以及第二输出模块，其中，输入模块配置成在输入信号端的信号的控制下将输入信号端的信号提供给第一节点；复位模块配置成在复位信号端的信号的控制下将参考信号端的信号提供给第一节点；电位维持模块配置成在第二节点处于浮接状态时保持时钟信号端与第二节点之间的电压差稳定；节点控制模块配置成在输入信号端的信号的控制下将参考信号端的信号提供给第二节点，在复位信号端的信号的控制下将复位信号端的信号提供给第二节点，以及在驱动信号输出端的信号的控制下将参考信号端的信号提供给第二节点；第一输出模块配置成在第一节点的信号的控制下将时钟信号端的信号提供给驱动信号输出端，以及在第一节点处于浮接状态时，保持第一节点与驱动信号输出端之间的电压差稳定；并且，第二输出模块配置成在第二节点的信号的控制下将参考信号端的信号提供给驱动信号输出端。因此，通过上述六个模块的相互配合，可以使电位维持模块保持第二节点的电位，以保证第二输出模块的正常输出，从而提高移位寄存器的输出稳定性，使驱动信号输出端的输出更加稳定。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (16)

  1. 一种移位寄存器，包括输入模块、复位模块、电位维持模块、节点控制模块、第一输出模块以及第二输出模块，
    其中，
    所述输入模块分别与输入信号端以及第一节点相连，并且配置成在所述输入信号端的信号的控制下将所述输入信号端的信号提供给所述第一节点；
    所述复位模块分别与复位信号端、参考信号端以及所述第一节点相连，并且配置成在所述复位信号端的信号的控制下将所述参考信号端的信号提供给所述第一节点；
    所述电位维持模块分别与时钟信号端以及第二节点相连，并且配置成在所述第二节点处于浮接状态时，保持所述时钟信号端与所述第二节点之间的电压差稳定；
    所述节点控制模块分别与所述输入信号端、所述复位信号端、所述参考信号端、所述第二节点以及所述移位寄存器的驱动信号输出端相连，并且配置成在所述输入信号端的信号的控制下将所述参考信号端的信号提供给所述第二节点，在所述复位信号端的信号的控制下将所述复位信号端的信号提供给所述第二节点，以及在所述驱动信号输出端的信号的控制下将所述参考信号端的信号提供给所述第二节点；
    所述第一输出模块分别与所述时钟信号端、所述第一节点以及所述驱动信号输出端相连，并且配置成在所述第一节点的信号的控制下将所述时钟信号端的信号提供给所述驱动信号输出端，以及在所述第一节点处于浮接状态时，保持所述第一节点与所述驱动信号输出端之间的电压差稳定；
    所述第二输出模块分别与所述参考信号端、所述第二节点以及所述驱动信号输出端相连，并且配置成在所述第二节点的信号的控制下将所述参考信号端的信号提供给所述驱动信号输出端。
  2. 如权利要求1所述的移位寄存器，其中，所述电位维持模块包括第一电容器，
    其中，
    所述第一电容器的一端与所述时钟信号端相连，并且所述第一电 容器的另一端与所述第二节点相连。
  3. 如权利要求1所述的移位寄存器，其中，所述输入模块包括第一晶体管，
    其中，
    所述第一晶体管的控制极和第一极均与所述输入信号端相连，并且所述第一晶体管的第二极与所述第一节点相连。
  4. 如权利要求1所述的移位寄存器，其中，所述复位模块包括第二晶体管，
    其中，
    所述第二晶体管的控制极与所述复位信号端相连，所述第二晶体管的第一极与所述参考信号端相连，并且所述第二晶体管的第二极与所述第一节点相连。
  5. 如权利要求1所述的移位寄存器，其中，所述节点控制模块包括第三晶体管、第四晶体管以及第五晶体管，
    其中，
    所述第三晶体管的控制极与所述输入信号端相连，所述第三晶体管的第一极与所述参考信号端相连，并且所述第三晶体管的第二极与所述第二节点相连；
    所述第四晶体管的控制极和第一极均与所述复位信号端相连，并且所述第四晶体管的第二极与所述第二节点相连；
    所述第五晶体管的控制极与所述驱动信号输出端相连，所述第五晶体管的第一极与所述参考信号端相连，并且所述第五晶体管的第二极与所述第二节点相连。
  6. 如权利要求1所述的移位寄存器，其中，所述第一输出模块包括第六晶体管与第二电容器，
    其中，
    所述第六晶体管的控制极与所述第一节点相连，所述第六晶体管的第一极与所述时钟信号端相连，并且所述第六晶体管的第二极与所述驱动信号输出端相连；
    所述第二电容器的一端与所述第一节点相连，并且所述第二电容器的另一端与所述驱动信号输出端相连。
  7. 如权利要求1所述的移位寄存器，其中，所述第二输出模块包 括第七晶体管，
    其中，
    所述第七晶体管的控制极与所述第二节点相连，所述第七晶体管的第一极与所述参考信号端相连，并且所述第七晶体管的第二极与所述驱动信号输出端相连。
  8. 如权利要求1-7任一项所述的移位寄存器，还包括第一节点稳定模块，
    其中，
    所述第一节点稳定模块分别与所述参考信号端、所述第一节点以及所述第二节点相连，并且配置成在所述第二节点的信号的控制下将所述参考信号端的信号提供给所述第一节点。
  9. 如权利要求8所述的移位寄存器，其中，所述第一节点稳定模块包括第八晶体管，
    其中，
    所述第八晶体管的控制极与所述第二节点相连，所述第八晶体管的第一极与所述参考信号端相连，并且所述第八晶体管的第二极与所述第一节点相连。
  10. 如权利要求1-7任一项所述的移位寄存器，还包括第二节点稳定模块，
    其中，
    所述第二节点稳定模块分别与节点稳定控制信号端以及所述第二节点相连，并且配置成在所述节点稳定控制信号端的信号的控制下将所述节点稳定控制信号端的信号提供给所述第二节点。
  11. 如权利要求10所述的移位寄存器，其中，所述第二节点稳定模块包括第九晶体管，
    其中，
    所述第九晶体管的控制极和第一极均与所述节点稳定控制信号端相连，并且所述第九晶体管的第二极与所述第二节点相连。
  12. 一种栅极驱动电路，包括级联的M个如权利要求1-11任一项所述的移位寄存器，M为大于或等于3的整数，
    其中，
    第1级移位寄存器的输入信号端与第一帧触发信号端相连；
    第2级移位寄存器的输入信号端与第二帧触发信号端相连；
    第N级移位寄存器的输入信号端分别与第N-2级移位寄存器的驱动信号输出端相连；并且
    第N-2级移位寄存器的复位信号端分别与第N级移位寄存器的驱动信号输出端相连，N为大于或等于3且小于或等于M的整数。
  13. 一种显示装置，包括如权利要求12所述的栅极驱动电路。
  14. 一种如权利要求1-11任一项所述的移位寄存器的驱动方法，包括第一阶段、第二阶段、第三阶段、第四阶段以及第五阶段，
    其中，
    在所述第一阶段中，所述输入模块在所述输入信号端的信号的控制下将所述输入信号端的信号提供给所述第一节点；所述第一输出模块在所述第一节点的信号的控制下将所述时钟信号端的信号提供给所述驱动信号输出端；并且所述节点控制模块在所述输入信号端的信号的控制下将所述参考信号端的信号提供给所述第二节点；
    在所述第二阶段中，所述第一输出模块在所述第一节点处于浮接状态时，保持所述第一节点与所述驱动信号输出端之间的电压差稳定，以及在所述第一节点的信号的控制下将所述时钟信号端的信号提供给所述驱动信号输出端；所述节点控制模块在所述驱动信号输出端的信号的控制下将所述参考信号端的信号提供给所述第二节点；
    在所述第三阶段中，所述第一输出模块在所述第一节点处于浮接状态时，保持所述第一节点与所述驱动信号输出端之间的电压差稳定，以及在所述第一节点的信号的控制下将所述时钟信号端的信号提供给所述驱动信号输出端；所述电位维持模块在所述第二节点处于浮接状态时，保持所述时钟信号端与所述第二节点之间的电压差稳定；
    在所述第四阶段中，所述复位模块在所述复位信号端的信号的控制下将所述参考信号端的信号提供给所述第一节点；所述节点控制模块在所述复位信号端的信号的控制下将所述复位信号端的信号提供给所述第二节点；所述第二输出模块在所述第二节点的信号的控制下将所述参考信号端的信号提供给所述驱动信号输出端；
    在所述第五阶段中，所述电位维持模块在所述第二节点处于浮接状态时，保持所述时钟信号端与所述第二节点之间的电压差稳定；所述第二输出模块在所述第二节点的信号的控制下将所述参考信号端的 信号提供给所述驱动信号输出端。
  15. 如权利要求14所述的驱动方法，其中，在各所述移位寄存器还包括所述第一节点稳定模块时，所述驱动方法还包括：
    在所述第四阶段中，所述第一节点稳定模块在所述第二节点的信号的控制下将所述参考信号端的信号提供给所述第一节点；以及
    在所述第五阶段中，所述第一节点稳定模块在所述第二节点的信号的控制下将所述参考信号端的信号提供给所述第一节点。
  16. 如权利要求14或15所述的驱动方法，其中，在各所述移位寄存器还包括所述第二节点稳定模块时，所述驱动方法还包括：
    在所述第四阶段中，所述第二节点稳定模块在所述节点稳定控制信号端的信号的控制下将所述节点稳定控制信号端的信号提供给所述第二节点。
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