WO2014161229A1 - 移位寄存器单元、移位寄存器和显示装置 - Google Patents

移位寄存器单元、移位寄存器和显示装置 Download PDF

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Publication number
WO2014161229A1
WO2014161229A1 PCT/CN2013/076954 CN2013076954W WO2014161229A1 WO 2014161229 A1 WO2014161229 A1 WO 2014161229A1 CN 2013076954 W CN2013076954 W CN 2013076954W WO 2014161229 A1 WO2014161229 A1 WO 2014161229A1
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WIPO (PCT)
Prior art keywords
transistor
pull
shift register
node
potential
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PCT/CN2013/076954
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English (en)
French (fr)
Inventor
青海刚
祁小敬
聂磊森
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/367,035 priority Critical patent/US9508450B2/en
Publication of WO2014161229A1 publication Critical patent/WO2014161229A1/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/282—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
    • G11C19/285—Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • Shift register unit shift register and display device
  • the present invention relates to the field of organic light emitting display, and more particularly to a shift register unit, a shift register, and a display device. Background technique
  • Figure 1 is a circuit diagram of a conventional basic shift register unit.
  • the basic shift register unit includes a pull-up thin film transistor, a pull-down thin film transistor, a first capacitor C1, a pull-up control thin film transistor T100, a pull-down control thin film transistor ⁇ 200, a second capacitor C2, and a first clock signal.
  • the pull-up node (PU point) is a node connected to the gate of the pull-up thin film transistor
  • the pull-down node (PD point) is a node connected to the gate of the pull-down thin film transistor
  • FIG. 2 is a timing diagram of signals of the basic shift register unit shown in FIG. 1 during operation, and VGH is at a high level.
  • the circuit of the basic shift register unit can operate normally, as shown in the solid line portion of FIG. 2, however, if an oxide transistor (depletion transistor) is used.
  • oxide transistor depletion transistor
  • Figure 3 shows the enhanced crystal.
  • the characteristic curve of the tube, the vertical axis of Fig. 3 is the drain current iD of the enhancement transistor, and the horizontal axis of Fig. 3 is the gate-source voltage Vgs of the enhancement transistor.
  • Vgs when Vgs is zero, iD is zero, indicating that the enhancement transistor is completely turned off when Vgs is zero.
  • Figure 4 is a characteristic diagram of the depletion transistor.
  • the vertical axis of Figure 4 is the drain current iD of the depletion transistor
  • the horizontal axis of Figure 4 Is the gate-source voltage Vgs of the depletion transistor, but Figure 4 shows that when Vgs is zero, iD is much larger than zero, and only when the gate-source voltage Vgs is -6V, iD is zero, therefore, in the gate source
  • the depletion transistor is still in the on state and cannot be turned off. Therefore, the existing circuit that can operate normally using the a-si technology or the p-si technology is used in the fabrication of the oxide transistor due to the oxide transistor. It cannot be turned off, and the leakage current is large, so the circuit of the conventional basic shift register unit as described in FIG. 1 is no longer applicable. Summary of the invention
  • embodiments of the present invention provide a shift register unit, a shift register, and a display device to solve the influence of a leakage current problem of a depletion TFT on a shift register.
  • Embodiments of the present invention provide a shift register unit, including:
  • a first capacitor for storing a first-level electrical signal
  • An output pull-up module connected to the drain of the driving transistor for pulling the drain of the driving transistor to a high level
  • a driving output terminal connected to a source of the driving transistor
  • An output pull-down module connected to a source of the driving transistor for pulling a source of the driving transistor to a second potential
  • a first pull-down module connected to the gate of the driving transistor through the pull-up node, and connected to the output pull-down module through the pull-down node, for pulling the pull-up node to the second potential or pulling down to the first potential
  • a pull-up node is a connection point of the first pull-down module and a gate of the driving transistor
  • the pull-down node is a connection point of the first pull-down node and the output pull-down module
  • an isolation pull-up module Connected between the pull-up node and the first capacitor to pull the pull-up node high.
  • Embodiments of the present invention also provide a shift register including a plurality of stages of the shift register unit
  • Embodiments of the present invention also provide a display device including the shift register.
  • the shift register unit of the embodiment of the present invention isolates the starting charging capacitor from the gate of the driving tube, and adopts a double pull-down structure for the gate and the output of the driving tube, using two different pull-down potentials, in non-working In the state, the gate of the driving transistor is pulled down to the second potential or pulled down to the first potential lower than the second potential, and the source of the driving transistor is pulled down to the second potential, so that the transistor can be normally turned off to prevent leakage.
  • 1 is a circuit diagram of a conventional basic shift register unit
  • Figure 3 is a characteristic diagram of an enhancement transistor
  • Figure 4 is a characteristic diagram of a depletion transistor
  • Figure 5 is a circuit diagram of a shift register unit of the first embodiment of the present invention.
  • Figure 6 is a circuit diagram of a shift register unit of a second embodiment of the present invention.
  • Figure 7 is a circuit diagram of a shift register unit of a third embodiment of the present invention.
  • Figure 8 is a circuit diagram of a shift register unit of a fourth embodiment of the present invention.
  • Figure 9 is a circuit diagram of a shift register unit of a fifth embodiment of the present invention.
  • Figure 10 is a circuit diagram of a shift register unit of a sixth embodiment of the present invention.
  • Figure 11 is a timing chart of the first embodiment and the second embodiment of the present invention.
  • Figure 12 is a timing chart of the third embodiment and the fourth embodiment of the present invention.
  • Figure 13 is a timing chart of the fifth embodiment and the sixth embodiment of the present invention.
  • Figure 14 is a diagram showing the cascade structure of the first embodiment, the third embodiment, and the fifth embodiment of the present invention.
  • Figure 15 is a diagram showing the cascade structure of the second embodiment, the fourth embodiment, and the sixth embodiment of the present invention. detailed description
  • Embodiments of the present invention provide a shift register unit, a shift register, and a display device, To solve the influence of the leakage current problem of the depletion TFT on the shift register.
  • the shift register unit includes:
  • a first capacitor C1 for storing the upper level electrical signal
  • the output pull-up module 400 is connected to the drain of the driving transistor T1 for pulling the drain of the driving transistor T1 to a high level VGH;
  • the carry signal output terminal is connected to the gate of the driving transistor T1 or connected to the driving output terminal for outputting an electrical signal to the next stage;
  • the output pull-down module 100 is connected to the source of the driving transistor T1 for pulling down the source of the driving transistor T1 to the second potential VGL2;
  • the first pull-down module 200 is connected to the gate of the driving transistor T1 through the pull-up node PU, and is connected to the output pull-down module 100 through the pull-down node PD for pulling down the pull-up node PU to the second potential VGL2 or pull-down To the first potential VGL1;
  • the isolation pull-up module 300 is connected between the pull-up node PU and the first capacitor C1 for pulling up the PU to a high level VGH.
  • the shift register unit of the embodiment of the present invention isolates the starting charging capacitor from the gate of the driving tube, and adopts a double pull-down structure for the gate and the output of the driving tube, using two different pull-down potentials, in non-working In the state, the gate of the driving transistor is pulled down to the second potential or pulled down to the first potential, and the source of the driving transistor is pulled down to the second potential, so that the transistor can be normally turned off to prevent leakage.
  • the pull-down potential second potential VGL2 of the embodiment of the present invention is greater than the first potential VGL1 and satisfies: VGL2-VGL1>IVthl, Vth is the threshold voltage of the transistor, when VGL1 acts on the TFT gate and VGL2 acts on the TFT source, For the depletion transistor, the condition is satisfied: Vgs ⁇ -IVthl, therefore, the transistor can be normally turned off.
  • the embodiment of the present invention is designed according to the above principle for the driving transistor to ensure the normal shutdown of the driving transistor and prevent leakage of the driving transistor.
  • the output pull-down module 100 of this embodiment includes a second transistor T2 and a third transistor T3.
  • the gate of the second transistor T2 receives the first clock signal CK, the source is connected to the second potential VGL2, and the drain is connected.
  • the gate of the third transistor T3 is connected to the pull-down node PD, the source is connected to the second potential VGL2, and the drain is connected to the source of the driving transistor T1 Extreme.
  • the source of the driving transistor T1 is pulled down to the second potential VGL2 in the non-operating state by the operation of the second transistor T2 and the third transistor T3, and the source of the driving transistor T1 is stopped in the operating state.
  • the second transistor T2 can be controlled to be turned on or off.
  • the second transistor T2 and the third transistor T3 realize that the driving output terminal OUT (N) is at the second potential VGL2 in the non-operating state.
  • the shift register unit of the embodiment of the present invention further includes a second pull-down module 500, and the second pull-down module 500 is connected to the output pull-down module 100 through the pull-down node PD, and is configured to pull down the pull-down node PD to the first state in the working state.
  • the second pull-down module of the embodiment of the present invention may be a transistor or a plurality of transistors connected in series, or may be a series of transistors and capacitors for pulling down the gate of the third transistor T3 to the first potential VGL1 and turning on the first Three transistor T3.
  • the first pull-down module 200 of the embodiment of the present invention is configured to pull down the pull-up node PU to the second potential VGL2 or pull down to the first potential VGL1 to participate in FIG. 5 again.
  • the first pull-down module 200 of the embodiment includes the first The four transistors T4, the fifth transistor ⁇ 5 and the sixth transistor ⁇ 6, the gates of the fourth transistor ⁇ 4 and the gate of the fifth transistor ⁇ 5 are connected to the pull-down node PD, and the source of the fourth transistor ⁇ 4 and the drain of the fifth transistor ⁇ 5 The pole is connected, the source of the fifth transistor ⁇ 5 is connected to the first potential VGL1, the drain of the fourth transistor ⁇ 4 is connected to the pull-up node PU; the gate of the sixth transistor ⁇ 6 receives the first clock signal CK, and the source is connected to The second potential VGL2, the drain is connected to the pull-up node PU.
  • the transistors T4 and ⁇ 5 of this embodiment are connected in series, and the resistance is increased compared with a single transistor, and the pull-down current of the pull-up node PU can be reduced.
  • the two transistors connected in series in the embodiment of the present invention may also be two or more transistors. Since a plurality of transistors are connected in series, the resistance is further increased, and the pull-down current of the pull-up node PU is reduced.
  • the first capacitor C1 of the embodiment of the present invention is used for storing the initial electrical signal, and if the shift register unit is the first stage, the initial electrical signal STV is received, and if it is the intermediate level unit, the electrical signal of the previous stage is received. .
  • the first capacitor C1 is connected to the gate of the driving transistor T1 through the isolation pull-up module 300, and is used for isolating the storage capacitor and the driving transistor to prevent the transistor from being output without being turned off.
  • the isolated pull-up module 300 of the embodiment is connected to one end of the first capacitor C 1 through the isolation node Q, and the other end is connected to the pull-up node PU, and the other end of the first capacitor C 1 is connected to the second potential VGL2.
  • the pull-up node PU pulls down to the second potential VGL2, and when the second clock signal CKB is high, the pull-up node PU pulls down to the first potential VGL1, turning off
  • the transistor T1 is driven to prevent a high level from being output through the driving transistor T1.
  • the first capacitor C1 of the embodiment receives the previous level carry signal Input(N-1) through the ninth transistor T9, the gate of the ninth transistor T9 receives the first clock signal CK, and the drain receives the previous level carry signal Input ( N-1), the source is connected to the first capacitor CI and the isolation node Q.
  • the output pull-up module 400 of the embodiment of the present invention is used to pull the drain of the driving transistor T1 to a high level VGH.
  • the output pull-up module 400 of this embodiment includes a second clock signal CKB, and the driving transistor T1 The drain receives the second clock signal CKB.
  • the output pull-up module 400 further includes a tenth transistor T10 whose gate receives the second clock signal CKB, the drain is connected to the high level, and the source is connected to the drain of the driving transistor T1.
  • the carry signal output terminal of the embodiment of the present invention is configured to output an electrical signal to the next stage, and may be connected to the pull-up node PU or to the drive output terminal OUT (N) to output an electrical signal to the next stage.
  • FIG. 6 a circuit diagram of a shift register unit according to a second embodiment of the present invention
  • the circuit of this embodiment is basically the same as the first one, and the difference is: the output pull-up module includes only the second clock signal CKB, The load of the second clock signal CKB is increased.
  • FIG. 7 is a circuit diagram of a shift register unit according to a third embodiment of the present invention
  • the circuit diagram of the embodiment is basically the same as the first one, and the difference is: the carry signal output end and the drive output end OUT (N) Connected. This will keep the low potential of the input terminal at the second potential VGL2, and the low potential of the isolation node Q can only be the second potential VGL2.
  • FIG. 8 is a circuit diagram of a shift register unit according to a fourth embodiment of the present invention
  • the circuit diagram of the embodiment is basically the same as the first one, and the difference is: the carry signal output end and the drive output end OUT (N) Connected, the output pull-up module only includes the second clock signal CKB, so that the load of the second clock signal CKB is increased, so that the low potential of the carry signal output terminal is always maintained at the second power Bit VGL2, the low potential of the isolated node Q point can only be the second potential VGL2.
  • the circuit diagram of the embodiment is basically the same as the first one, the difference is: the first pull-down module 200 includes a fourth transistor T4, The source is connected to the second potential VGL2, the gate is connected to the pull-down node PD, and the drain is connected to the pull-up node PU.
  • the carry signal output of this embodiment is coupled to the drive output OUT ( N ).
  • FIG. 10 it is a circuit diagram of a shift register unit according to a sixth embodiment of the present invention.
  • the circuit diagram of this embodiment is basically the same as the fifth one. The difference is that the output pull-up module includes only the second clock signal CKB. The load of the second clock signal CKB is increased.
  • FIG. 11-13 is a timing chart of an embodiment of the present invention.
  • FIG. 11 is a timing chart of the first embodiment and the second embodiment of the present invention.
  • the first embodiment and the second embodiment have the same in common.
  • the output signal Input(N+l) for the next stage is given from the pull-up node PU, and the pull-down potential of the PU point of the two embodiments can be pulled down to the first potential VGL1 through T4, ⁇ 5, and through the sixth
  • the transistor T6 is also pulled down to the second potential VGL2, and therefore, the pull-up node PU is alternately changed in low level. Therefore, the low level of the carry signal output also alternates.
  • Figure 12 is a timing chart of the third embodiment and the fourth embodiment of the present invention.
  • the third embodiment and the fourth embodiment have in common that the output signal Input(N+) for the next stage is given from the drive output. l), therefore, the low level of the carry signal Input(Nl) does not change, only the second potential VGL2, but the pull-down potential of the pull-up node PU of the two embodiments can be pulled down to the first potential through the transistors T4, ⁇ 5 VGL1 is also pulled down to the second potential VGL2 through the sixth transistor ⁇ 6, and therefore, the pull-up node PU is alternately changed at a low level.
  • Figure 13 is a timing chart of the fifth embodiment and the sixth embodiment of the present invention.
  • the fifth embodiment and the sixth embodiment have in common that the output signal Input(N+) for the next stage is given from the drive output. l), therefore, there is no change in the low level of the carry signal output terminal, only the second potential VGL2, the pull-down potential of the PU point of the pull-up node of the two schemes is pulled down to the second potential VGL2 through the fourth transistor T4, and The sixth transistor T6 is also pulled down to the second potential VGL2, and the pull-up node PU point low level does not alternately appear.
  • Phase 1 The first clock CK and the received carry signal Input(Nl) at this stage are high level VGH, N is a natural number, the second clock signal CKB is a low level VGL1, and the pull-down node PD potential is VGL1.
  • the second transistor T2, the sixth transistor ⁇ 6, and the ninth transistor ⁇ 9 are turned on. when The ninth transistor T9 is turned on, and the carry signal Input (N1) charges the first capacitor CI. At this time, the potential of the isolation node Q is charged to the high level VGH, and the seventh transistor T7 and the eighth transistor ⁇ 8 are turned on.
  • the second clock signal CKB is the first potential VGL1
  • the ⁇ 6 is also turned on
  • the second potential VGL2 is greater than the first potential VGL1
  • the pull-up node PU potential is pulled down to the first potential VGL1
  • the second transistor ⁇ 2 Turned on, causing the drive output terminal OUT(N) to be pulled down to the second potential VGL2.
  • the voltage difference Vgs ⁇ -IVthl of the gate and the source of the driving transistor T1 is the threshold voltage of the transistor, and the driving transistor T1 is normally turned off; at this time, the potential of the pull-down node PD is the first potential VGL1, and the third transistor T3
  • the source is at the second potential VGL2, and the voltage difference Vgs ⁇ -IVth1 between the gate and the source of the third transistor T3, therefore, the third transistor T3 is normally turned off, and the driving output terminal OUT(N) outputs the second potential VGL2.
  • Phase 2 The second clock signal CKB at this stage is a high level VGH, and the first clock signal CK is a first potential VGL1. Since the signal at the input end of the carry signal comes from the pull-up node PU of the upper stage, the second clock of the stage The signal CKB is in phase with the first clock signal CK of the upper stage, and is all at a high level. Therefore, the pull-up node PU of the previous stage is pulled down to the second potential VGL2, so the level of the carry signal input terminal of this stage is the second potential VGL2. At this time, the ninth transistor T9 is sourced at the second potential VGL2, and the gate is at the first potential VGL1. Therefore, the sixth transistor T6 is normally turned off.
  • the potential of the isolation node Q remains at VGH, and the potential of the pull-down node PD is the first potential VGL1.
  • the third transistor T3 is still turned off, and the first clock signal CK level of the second transistor T2 is the first potential VGL1, the source.
  • the second potential VGL2 is extremely high, and therefore, the second transistor T2 is normally turned off.
  • the high level of the isolation node Q causes the transistors T7 and ⁇ 8 to be continuously turned on, and the high level of the second clock signal CKB charges the PU point of the pull-up node through the transistors ⁇ 7 and ⁇ 8.
  • the potential of the pull-down node PD is the first potential VGL1.
  • the source of the fifth transistor T5 is also the first potential VGL1.
  • the fifth transistor T5 is in the linear region, and the fourth transistor T4 is also in the linear region. Open state, but there is a certain resistance, the two are connected in series, the resistance is larger, so the pull-down currents of the transistors T4 and ⁇ 5 for the pull-up node PU are small, and the load capacity of the second clock signal CKB is large, so that the pull-up node can be made.
  • the potential of the PU is stabilized at a high level VGH. Therefore, the driving transistor T1 is turned on, and the high level VGH is output to the driving output terminal OUT(N) through the driving transistor T1.
  • Phase 3 The second clock signal CKB of this stage jumps to the first potential VGL1, the tenth transistor T10 is turned off, the first clock signal CK jumps to the high level VGH, the second transistor T2, the sixth transistor ⁇ 6, the ninth Transistor ⁇ 9 is turned on, second transistor ⁇ 2 is turned on, and drive output terminal OUT(N) Pulled down to the second potential VGL2, the sixth transistor T6 is turned on, and the pull-up node PU point is pulled down to the second potential VGL2.
  • the pull-down node PD of the upper stage Since the pull-down node PD of the upper stage is at a high level, the pull-up node PU of the upper stage is pulled down to the first potential VGL1, and the carry signal input end of the current stage is from the potential of the upper pull-up node PU, at this time, The potential of the carry signal input terminal of the stage is VGL1, the ninth transistor T9 is turned on, the potential of the isolated node Q is pulled down to the first potential VGL1, and the seventh transistor T7 and the eighth transistor ⁇ 8 are turned off. At this time, the pull-down node PD potential is still the first potential VGL1, and therefore, the third transistor ⁇ 3 is turned off.
  • the PD potential of the pull-down node will become high, the third transistor ⁇ 3 will be turned on, and the pull-up node PU will be pulled down to the first potential VGL1 to repeat the above operation.
  • an embodiment of a shift register is constructed by connecting a level shift register unit as an active matrix line scanner, typically an active matrix.
  • the number of lines, ⁇ is a positive integer;
  • the clock signal outputted by the first clock signal input terminal and the clock signal input to the second clock signal input end are opposite in phase, and the duty ratio is 50%;
  • the input terminal (1) of the first stage shift register is connected to the initial pulse signal STV, and the STV is active high;
  • each stage of the shift register unit is connected to the carry signal output of the shift register unit of the previous stage;
  • the clock control signals of the adjacent two-stage shift register unit are inverted with each other, for example: if the clock input terminal of the first stage shift register unit is connected to the first clock signal CK, adjacent to the first stage shift register unit The clock signal input end of the second stage shift register unit is connected to the second clock signal
  • the CKB, the first clock signal CK and the second clock signal CKB are mutually inverted.
  • Embodiments of the present invention also provide a display device including the shift register as described in the above embodiments, and the display device may include a liquid crystal display device such as a liquid crystal panel, a liquid crystal television, a mobile phone, or a liquid crystal display.
  • the display device may further include an organic light emitting display or other type of display device such as an electronic reader or the like.
  • the shift register can be used as a scanning circuit or a gate driving circuit of the display device to provide a progressive scanning function for sending a scanning signal to the display area.

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Abstract

一种移位寄存器单元、移位寄存器和显示装置，采用了将起始充电电容与驱动管栅极相隔离，同时对驱动管的栅极和输出端采用双下拉结构，可以实现晶体管正常关闭，防止漏电的产生。该移位寄存器单元包括：驱动晶体管（T1）；第一电容（C1），用于存储上一级电信号；输出上拉模块（400），与驱动晶体管（T1）的漏极相连接；驱动输出端（OUT（N）），与驱动晶体管（T1）的源极相连接；进位信号输出端，与驱动晶体管（T1）的栅极相连接或者与驱动输出端（OUT（N））相连接；输出下拉模块（100），与驱动晶体管（T1）的源极相连接；第一下拉模块（200），通过上拉节点（PU）与驱动晶体管（T1）的栅极相连接，以及通过下拉节点（PD）与输出下拉模块（100）相连接，隔离上拉模块（300），连接在上拉节点（PU）和第一电容（C1）之间。

Description

移位寄存器单元、 移位寄存器和显示装置 技术领域
本发明涉及有机发光显示领域， 尤其涉及一种移位寄存器单元、 移位寄 存器和显示装置。 背景技术
随着平板显示的发展， 高分辨率， 窄边框成为发展的潮流， 而要实现高 分辨率， 窄边框显示， 面板上集成栅极驱动电路是最重要的解决办法。 对于 a-si (非晶硅）和 p-si (多晶硅）技术， 现有的各种成熟移位寄存电路可以很 好的实现这个目标。 氧化物 TFT (晶体管）作为一种非常有潜力的半导体技 术， 相比于 p-si工艺更筒单， 成本更低， 相比于 a-si迁移率更高， 因而越来 越受到重视， 未来很可能是 OLED (有机发光二极管）， 柔性显示的主流背板 驱动技术。 然而氧化物 TFT是一种耗尽型晶体管， 而前面提到的 a-si TFT和 p-si TFT为增强型的晶体管。
图 1为传统的基本的移位寄存器单元的电路图。 如图 1所示， 该基本的 移位寄存器单元包括上拉薄膜晶体管、 下拉薄膜晶体管、 第一电容 Cl、 上拉 控制薄膜晶体管 T100、 下拉控制薄膜晶体管 Τ200、 第二电容 C2、 第一时钟 信号输入端 CK、 第二时钟信号输入端 CKB、 输入端 Input、 复位端 Reset和 输出端 Output;
上拉节点（ PU点）为与上拉薄膜晶体管的栅极连接的节点，下拉节点（ PD 点） 为与下拉薄膜晶体管的栅极连接的节点；
并且从输入端 Input输入起始信号 STV, VGL为低电平。
图 2是如图 1所示的基本的移位寄存器单元在工作时各信号的时序图， VGH为高电平。
当使用增强型 TFT技术制作该基本的移位寄存器单元的电路时，该基本 的移位寄存器单元的电路可以正常工作， 见图 2实线部分， 然而如果使用氧 化物晶体管 （耗尽型晶体管）制作该电路时， 由于下拉晶体管无法关闭， 电 路失效， 从图 2中的 PU节点和输出 Output的时序图可以看出， 存在没有关 闭的情况。
增强型晶体管和耗尽型晶体管的差别见图 3和图 4, 图 3为增强型晶体 管的特性曲线图， 图 3的纵轴为增强型晶体管的漏极电流 iD, 图 3的横轴为 增强型晶体管的栅源电压 Vgs, 从图 3上可以看到， 当 Vgs为零时， iD为零， 说明 Vgs为零时， 增强型晶体管完全关闭； 图 4为耗尽型晶体管的特性曲线 图， 同样图 4的纵轴为耗尽型晶体管的漏极电流 iD, 图 4的横轴为耗尽型晶 体管的栅源电压 Vgs, 但图 4显示的却是 Vgs为零时， iD远大于零， 而只有 在栅源电压 Vgs为 -6V时， iD才为零， 因此， 在栅源电压 Vgs为 0时耗尽型 晶体管仍然处于导通状态， 无法关闭， 因此现有的使用 a-si技术或 p-si技术 能正常工作的电路， 在运用氧化物晶体管制作时， 由于氧化物晶体管不能关 闭， 漏电流较大， 因此如图 1所述的传统的基本的移位寄存器单元的电路就 不再适用。 发明内容
为了解决现有技术的问题， 本发明的实施例提供一种移位寄存器单元、 移位寄存器和显示装置， 以解决耗尽型 TFT的漏电流问题对移位寄存器的影 响。
本发明的实施例提供了一种移位寄存器单元， 包括：
驱动晶体管；
第一电容， 用于存储上一级电信号；
输出上拉模块， 与驱动晶体管的漏极相连接， 用于将驱动晶体管的漏极 上拉为高电平；
驱动输出端， 与驱动晶体管的源极相连接；
进位信号输出端，与驱动晶体管的栅极相连接或者与驱动输出端相连接， 用于向下一级输出电信号；
输出下拉模块， 与驱动晶体管的源极相连接， 用于将驱动晶体管的源极 下拉到第二电位；
第一下拉模块， 通过上拉节点与驱动晶体管的栅极相连接， 以及通过下 拉节点与输出下拉模块相连接， 用于将上拉节点下拉到第二电位或者下拉到 第一电位， 所述上拉节点为所述第一下拉模块与所述驱动晶体管的栅极的连 接点， 所述下拉节点为所述第一下拉节点与所述输出下拉模块的连接点； 隔离上拉模块， 连接在上拉节点和第一电容之间， 用于将上拉节点上拉 到高电平。 本发明的实施例还提供了一种移位寄存器， 包括多级所述的移位寄存器 单元
本发明的实施例还提供了一种显示装置， 包括所述的移位寄存器。
本发明的实施例的移位寄存器单元将起始充电电容与驱动管栅极相隔 离， 同时对驱动管的栅极和输出端采用双下拉结构， 使用了两个不同的下拉 电位， 在非工作状态下将驱动晶体管的栅极下拉到第二电位或者下拉到低于 第二电位的第一电位， 并将驱动晶体管的源极下拉到第二电位， 可以实现晶 体管正常关闭， 防止漏电的产生。 附图说明
图 1是传统的基本的移位寄存器单元的电路图；
图 2是该基本的移位寄存器单元在工作时各信号的时序图；
图 3是增强型晶体管的特性曲线图；
图 4是耗尽型晶体管的特性曲线图；
图 5本发明的第一种实施例的移位寄存器单元的电路图；
图 6本发明的第二种实施例的移位寄存器单元的电路图；
图 7本发明的第三种实施例的移位寄存器单元的电路图；
图 8本发明的第四种实施例的移位寄存器单元的电路图；
图 9本发明的第五种实施例的移位寄存器单元的电路图；
图 10本发明的第六种实施例的移位寄存器单元的电路图；
图 11本发明的第一种实施例和第二实施例的时序图；
图 12本发明的第三种实施例和第四实施例的时序图；
图 13本发明的第五种实施例和第六实施例的时序图；
图 14本发明的第一实施例、第三实施例和第五实施例的级联结构图； 以 及
图 15本发明的第二实施例、 第四实施例和第六实施例的级联结构图。 具体实施方式
为使得本发明的技术方案和优点表达得更加清楚明白， 下面结合附图及 具体实施例对本发明再做进一步详细的说明。
本发明的实施例提供了一种移位寄存器单元、 移位寄存器和显示装置， 以解决耗尽型 TFT的漏电流问题对移位寄存器的影响。
如图 5所示， 为本发明的实施例的第一种实施例的移位寄存器单元的电 路图， 该移位寄存器单元包括：
驱动晶体管 T1;
第一电容 C1 , 用于存储上一级电信号；
输出上拉模块 400, 与驱动晶体管 T1的漏极相连接， 用于将驱动晶体管 T1的漏极上拉为高电平 VGH;
驱动输出端 OUT ( N ), 与驱动晶体管 T1的源极相连接；
进位信号输出端，与驱动晶体管 T1的栅极相连接或者与驱动输出端相连 接， 用于向下一级输出电信号；
输出下拉模块 100, 与驱动晶体管 T1的源极相连接， 用于将驱动晶体管 T1的源极下拉到第二电位 VGL2;
第一下拉模块 200, 通过上拉节点 PU与驱动晶体管 T1的栅极相连接， 以及通过下拉节点 PD与输出下拉模块 100相连接，用于将上拉节点 PU下拉 到第二电位 VGL2或者下拉到第一电位 VGL1;
隔离上拉模块 300, 连接在上拉节点 PU和第一电容 C1之间， 用于上拉 节点 PU上拉到高电平 VGH。
本发明的实施例的移位寄存器单元将起始充电电容与驱动管栅极相隔 离， 同时对驱动管的栅极和输出端采用双下拉结构， 使用了两个不同的下拉 电位， 在非工作状态下将驱动晶体管的栅极下拉到第二电位或者下拉到第一 电位， 并将驱动晶体管的源极下拉到第二电位， 可以实现晶体管正常关闭， 防止漏电的产生。
本发明的实施例的下拉电位第二电位 VGL2大于第一电位 VGL1 , 且满 足： VGL2-VGLl>IVthl , Vth为晶体管的阈值电压， 当 VGL1作用在 TFT栅 极， VGL2作用在 TFT源极时， 对于耗尽型晶体管满足条件： Vgs<-IVthl, 因 此， 可以实现晶体管正常关闭。 本发明的实施例对驱动晶体管依据上述原理 进行设计， 保证了驱动晶体管的正常关闭， 防止了驱动晶体管的漏电。
再次参阅图 5, 本实施例的输出下拉模块 100包括第二晶体管 T2和第三 晶体管 T3 , 第二晶体管 T2的栅极接收第一时钟信号 CK, 源极连接到第二电 位 VGL2, 漏极连接到驱动晶体管 T1的源极； 第三晶体管 T3的栅极连接到 下拉节点 PD, 源极连接到第二电位 VGL2, 漏极连接到驱动晶体管 T1的源 极。 本实施例通过第二晶体管 T2和第三晶体管 T3的操作， 在非工作状态下 将驱动晶体管 T1的源极下拉到第二电位 VGL2,在工作状态下停止对驱动晶 体管 T1的源极进行下拉。 而且， 利用第一时钟信号 CK与第二晶体管 T2的 栅极相连接，可以控制第二晶体管 T2开启或者关闭。本实施例通过第二晶体 管 T2和第三晶体管 T3, 实现了驱动输出端 OUT ( N )在非工作状态下处于 第二电位 VGL2。
本发明的实施例的移位寄存器单元还包括第二下拉模块 500, 所述第二 下拉模块 500通过下拉节点 PD与输出下拉模块 100相连接， 用于在工作状 态下将下拉节点 PD下拉到第一电位 VGL1。本发明的实施例的第二下拉模块 可以是一个晶体管或者多个串联的晶体管， 还可以是串联的晶体管和电容组 成， 用于将第三晶体管 T3的栅极下拉到第一电位 VGL1和开启第三晶体管 T3。本实施例的第二下拉模块 500包括第十一晶体管 Tll、第十二晶体管 T12 和第二电容 C2,第十一晶体管 T11和第十二晶体管 T12的栅极连接到第一电 容 C1 , 第十一晶体管 T11的漏极连接下拉节点 PD, 源极连接到第十二晶体 管 T12的漏极， 第十二晶体管 T12的源极连接到第一电位 VGL1 , 第二电容 C2一端连接到下拉节点 PD, 另一端接收第二时钟信号 CKB。
本发明的实施例的第一下拉模块 200用于将上拉节点 PU下拉到第二电 位 VGL2或者下拉到第一电位 VGL1 ,再次参与图 5, 本实施例的第一下拉模 块 200包括第四晶体管 T4、第五晶体管 Τ5和第六晶体管 Τ6,第四晶体管 Τ4 的栅极和第五晶体管 Τ5的栅极与下拉节点 PD相连接， 第四晶体管 Τ4的源 极与第五晶体管 Τ5的漏极相连接， 第五晶体管 Τ5的源极连接到第一电位 VGL1 , 第四晶体管 Τ4的漏极连接到上拉节点 PU; 第六晶体管 Τ6的栅极接 收第一时钟信号 CK, 源极连接到第二电位 VGL2, 漏极连接到上拉节点 PU。 本实施例的晶体管 T4、 Τ5相串接， 相比较与单个个晶体管而言， 增大了电 阻， 可以降低上拉节点 PU的下拉电流。 当然， 本发明的实施例的串接的两 个晶体管还可以是两个以上的晶体管， 由于采用多个晶体管串联， 进一步增 大了电阻， 降低上拉节点 PU的下拉电流。
本发明的实施例的第一电容 C1用于存储起始电信号，如果该移位寄存器 单元为第一级则接收起始电信号 STV, 如果是中间级单元， 则接受上一级的 电信号。第一电容 C1通过隔离上拉模块 300与驱动晶体管 T1的栅极相连接， 用于隔离存储电容和驱动晶体管， 避免晶体管没有关闭即进行输出。 本发明 的实施例的隔离上拉模块 300通过隔离节点 Q与第一电容 C 1的一端相连接， 另一端与上拉节点 PU相连接，第一电容 C 1的另一端连接到第二电位 VGL2。
再次参阅图 5, 本实施例的隔离上拉模块 300包括第七晶体管 T7和第八 晶体管 T8, 第七晶体管 T7和第八晶体管 T8的栅极通过隔离节点 Q连接到 第一电容 C1 , 第七晶体管 T7的源极连接到上拉节点 PU, 第七晶体管 T7漏 极连接到第八晶体管 T8的源极； 第八晶体管 T8的漏极接收第二时钟信号 CKB。 在非工作阶段， 当第二时钟信号 CKB为低电平时， 上拉节点 PU下拉 为第二电位 VGL2, 当第二时钟信号 CKB为高电平时， 上拉节点 PU下拉为 第一电位 VGL1 , 关闭驱动晶体管 T1 , 避免高电平通过驱动晶体管 T1输出。 本实施例的第一电容 C1通过第九晶体管 T9接收上一级进位信号 Input( N-1 ), 第九晶体管 T9的栅极接收第一时钟信号 CK,漏极接收上一级进位信号 Input ( N-1 ), 源极连接到第一电容 CI和隔离节点 Q。
本发明的实施例的输出上拉模块 400用于将驱动晶体管 T1的漏极上拉为 高电平 VGH, 本实施例的输出上拉模块 400包括第二时钟信号 CKB, 所述 驱动晶体管 T1的漏极接收第二时钟信号 CKB。 该输出上拉模块 400还包括 第十晶体管 T10, 其栅极接收第二时钟信号 CKB, 漏极与高电平相连接， 源 极与驱动晶体管 T1的漏极相连接。
本发明的实施例的进位信号输出端， 用于向下一级输出电信号， 可以与 上拉节点 PU相连接或者与驱动输出端 OUT ( N )相连接， 以给下一级输出 电信号。
如图 6所示， 为本发明的第二种实施例的移位寄存器单元的电路图， 该 实施例的电路与第一种基本相同， 区别是： 输出上拉模块仅包括第二时钟信 号 CKB, 使得第二时钟信号 CKB的负载会增加。
如图 7所示， 为本发明的第三种实施例的移位寄存器单元的电路图， 该 实施例的电路图与第一种基本相同， 区别是： 进位信号输出端与驱动输出端 OUT ( N )相连接。 这样做会使得输入端的低电位一直都保持在第二电位 VGL2, 隔离节点 Q的低电位也只能是第二电位 VGL2。
如图 8所示， 为本发明的第四种实施例的移位寄存器单元的电路图， 该 实施例的电路图与第一种基本相同， 区别是： 进位信号输出端与驱动输出端 OUT ( N )相连接， 输出上拉模块仅包括第二时钟信号 CKB, 使得第二时钟 信号 CKB的负载会增加，使得进位信号输出端的低电位一直都保持在第二电 位 VGL2, 隔离节点 Q点的低电位也只能是第二电位 VGL2。
如图 9所示， 为本发明的第五种实施例的移位寄存器单元的电路图， 该 实施例的电路图与第一种基本相同， 区别是： 第一下拉模块 200包括第四晶 体管 T4, 其源极连接到第二电位 VGL2, 栅极连接下拉节点 PD, 漏极连接上 拉节点 PU。 该实施例的进位信号输出端与驱动输出端 OUT ( N )相连接。
如图 10所示， 为本发明的第六种实施例的移位寄存器单元的电路图， 该 实施例的电路图与第五种基本相同， 区别是： 输出上拉模块仅包括第二时钟 信号 CKB, 使得第二时钟信号 CKB的负载会增加。
如图 11-13所示， 为本发明实施例的时序图， 图 11本发明的第一种实施 例和第二实施例的时序图， 第一实施例和第二实施例的共同点是都从上拉节 点 PU给出对下一级的输出信号 Input(N+l), 由于这两个实施例的 PU点的下 拉电位通过 T4、 Τ5可以被下拉到第一电位 VGLl , 同时通过第六晶体管 T6 也被下拉到第二电位 VGL2, 因此，上拉节点 PU低电平出现交替变化。因此， 进位信号输出端的低电平也出现交替变化。
图 12本发明的第三种实施例和第四实施例的时序图，第三实施例和第四 实施例的共同点是都从驱动输出端给出对下一级的输出信号 Input(N+l), 因 此 进位信号 Input(N-l)的低电平没有任何变化， 只有第二电位 VGL2, 但这 两个实施例的上拉节点 PU的下拉电位通过晶体管 T4、 Τ5可以被下拉到第一 电位 VGL1 , 同时通过第六晶体管 Τ6也被下拉到第二电位 VGL2, 因此， 上 拉节点 PU低电平出现交替变化。
图 13本发明的第五种实施例和第六实施例的时序图，第五实施例和第六 实施例的共同点是都从驱动输出端给出对下一级的输出信号 Input(N+l), 因 此， 进位信号输出端的低电平没有任何变化， 只有第二电位 VGL2, 这两个 方案的上拉节点 PU点的下拉电位通过第四晶体管 T4被下拉到第二电位 VGL2, 同时， 通过第六晶体管 T6也被下拉到第二电位 VGL2, 上拉节点 PU 点低电平没有交替的变化出现。
以下结合第一实施例对其电路工作过程进行说明， 本实施例的电路的工 作过程分为三个阶段， 分别是：
阶段一： 该阶段的第一时钟 CK和接收的进位信号 Input(N-l)为高电平 VGH, N为自然数， 第二时钟信号 CKB为低电平 VGL1 , 下拉节点 PD电位 为 VGL1 , 此时， 第二晶体管 T2、 第六晶体管 Τ6和第九晶体管 Τ9开启。 当 第九晶体管 T9开启， 进位信号 Input ( N-l )对第一电容 CI充电， 此时， 隔 离节点 Q电位充到高电平 VGH, 第七晶体管 T7、 第八晶体管 Τ8开启。 由于 第二时钟信号 CKB为第一电位 VGL1 , 虽然 Τ6也开启， 由于第二电位 VGL2 大于第一电位 VGL1 , 此时， 上拉节点 PU电位被下拉到第一电位 VGL1 , 而 第二晶体管 Τ2的开启， 使得驱动输出端 OUT(N)被下拉到第二电位 VGL2。 此时， 驱动晶体管 T1栅级和源极的电压差 Vgs<-IVthl, Vth为晶体管的阈值 电压， 驱动晶体管 T1正常关闭； 此时， 下拉节点 PD电位为第一电位 VGL1 , 第三晶体管 T3的源极为第二电位 VGL2, 第三晶体管 T3的栅级和源极的电 压差 Vgs<-IVthl, 因此， 第三晶体管 T3正常关闭， 驱动输出端 OUT(N)输出 第二电位 VGL2。
阶段二： 该阶段的第二时钟信号 CKB为高电平 VGH, 第一时钟信号 CK 为第一电位 VGL1 , 由于进位信号输入端的信号来自上一级的上拉节点 PU, 该阶段的第二时钟信号 CKB与上级的第一时钟信号 CK同相， 都为高电平， 因此上一级的上拉节点 PU被下拉到第二电位 VGL2,因此本阶段的进位信号 输入端的电平为第二电位 VGL2, 此时， 第九晶体管 T9源极为第二电位 VGL2, 栅极为第一电位 VGL1 , 因此， 第六晶体管 T6正常关闭。 隔离节点 Q的电位仍然保持为 VGH, 下拉节点 PD的电位为第一电位 VGL1 , 此时， 第三晶体管 T3仍然关闭， 第二晶体管 T2的第一时钟信号 CK电平为第一电 位 VGL1 , 源极为第二电位 VGL2, 因此， 第二晶体管 T2正常关闭。 隔离节 点 Q的高电平使得晶体管 T7、 Τ8持续开启， 第二时钟信号 CKB的高电平通 过晶体管 Τ7、 Τ8对上拉节点 PU点充电， 此时， 下拉节点 PD点电位为第一 电位 VGL1 , 而第五晶体管 T5的源极也为第一电位 VGL1 , 根据耗尽型晶体 管的特性曲线图 4可知， 第五晶体管 T5处于线性区， 而第四晶体管 T4也处 于线性区， 两者处于一定的开启状态， 但存在一定的电阻， 两者串联， 电阻 更大， 因此晶体管 T4、 Τ5对于上拉节点 PU的下拉电流 4艮小， 第二时钟信号 CKB较大的负载能力可以使得上拉节点 PU的电位稳定在高电平 VGH。因此， 驱动晶体管 T1开启，高电平 VGH通过驱动晶体管 T1向驱动输出端 OUT(N) 输出。
阶段三： 本阶段的第二时钟信号 CKB跳变为第一电位 VGL1 , 第十晶体 管 T10关闭， 第一时钟信号 CK跳变为高电平 VGH, 第二晶体管 T2、 第六 晶体管 Τ6、 第九晶体管 Τ9开启， 第二晶体管 Τ2开启， 驱动输出端 OUT(N) 被下拉到第二电位 VGL2, 第六晶体管 T6开启， 上拉节点 PU点被下拉到第 二电位 VGL2。 由于上级的下拉节点 PD为高电平， 因此上一级的上拉节点 PU被下拉到第一电位 VGL1 ,本级的进位信号输入端来自上一级上拉节点 PU 的电位， 此时， 本级的进位信号输入端电位为 VGL1 , 第九晶体管 T9开启， 隔离节点 Q点电位被下拉到第一电位 VGL1 , 第七晶体管 T7、 第八晶体管 Τ8关闭。 此时， 下拉节点 PD电位仍然为第一电位 VGL1 , 因此， 第三晶体 管 Τ3关闭。
到此一个单元的操作结束， 到下一个阶段， 下拉节点 PD电位会变成高 电平， 第三晶体管 Τ3会开启， 上拉节点 PU会被下拉到第一电位 VGL1 , 重 复执行上述操作。
如图 14-15所示， 本发明的实施例所述的移位寄存器的一实施例由 Ν级 移位寄存器单元连接构成， 以作为有源矩阵的行扫描器， Ν通常为有源矩阵 的行数， Ν为正整数；
第一时钟信号输入端输出的时钟信号和第二时钟信号输入端输入的时钟 信号相位相反， 占空比为 50%;
其中， 第一级移位寄存器的输入端 Input ( 1 )接入初始脉沖信号 STV, STV为高电平有效；
除了第一级移位寄存器单元之外， 每一级移位寄存器单元的输入端和上 一级移位寄存器单元的进位信号输出端连接；
相邻两级移位寄存器单元的时钟控制信号互为反相， 比如： 如果第一级 移位寄存器单元的时钟输入端连接第一时钟信号 CK则与该第一级移位寄存 器单元相邻的第二级移位寄存器单元的时钟信号输入端连接第二时钟信号
CKB, 第一时钟信号 CK和第二时钟信号 CKB互为反相。
本发明的实施例还提供一种显示装置， 包括如以上实施例所述的移位寄 存器， 所述显示装置可以包括液晶显示装置， 例如液晶面板、 液晶电视、 手 机、 液晶显示器。 除了液晶显示装置外， 所述显示装置还可以包括有机发光 显示器或者其他类型的显示装置， 比如电子阅读器等。 该移位寄存器可以作 为显示装置的扫描电路或者栅极驱动电路等， 以提供逐行扫描功能， 将扫描 信号送至显示区域。
以上说明对本发明而言只是说明性的， 而非限制性的， 本领域普通技术 人员理解， 在不脱离所附权利要求所限定的精神和范围的情况下， 可做出许 10

Claims

权 利 要 求 书
1、 一种移位寄存器单元， 包括：
驱动晶体管；
第一电容， 用于存储上一级电信号；
输出上拉模块， 与驱动晶体管的漏极相连接， 用于将驱动晶体管的漏极 上拉为高电平；
驱动输出端， 与驱动晶体管的源极相连接；
进位信号输出端，与驱动晶体管的栅极相连接或者与驱动输出端相连接， 用于向下一级输出电信号；
输出下拉模块， 与驱动晶体管的源极相连接， 用于将驱动晶体管的源极 下拉到第二电位；
第一下拉模块， 通过上拉节点与驱动晶体管的栅极相连接， 以及通过下 拉节点与输出下拉模块相连接， 用于将上拉节点下拉到第二电位或者下拉到 第一电位， 所述上拉节点为所述第一下拉模块与所述驱动晶体管的栅极的连 接点， 所述下拉节点为所述第一下拉节点与所述输出下拉模块的连接点； 以 及
隔离上拉模块， 连接在上拉节点和第一电容之间， 用于将上拉节点上拉 到高电平。
2、 如权利要求 1所述的移位寄存器单元， 其中， 所述第二电位高于第一 电位， 并且两者的电位差的绝对值大于晶体管的阈值电压的绝对值。
3、 如权利要求 2所述的移位寄存器单元， 其中， 所述移位寄存器单元还 包括第二下拉模块，所述第二下拉模块通过下拉节点与输出下拉模块相连接， 用于将下拉节点下拉到第一电位。
4、 如权利要求 3所述的移位寄存器单元， 其中， 所述输出下拉模块包括 第二晶体管和第三晶体管， 第二晶体管的栅极接收第一时钟信号， 源极连接 到第二电位， 漏极连接到驱动晶体管的源极； 第三晶体管的栅极连接到下拉 节点， 源极连接到第二电位， 漏极连接到驱动晶体管的源极。
5、 如权利要求 3或者 4所述的移位寄存器单元， 其中， 所述第二下拉模 块包括第十一晶体管、 第十二晶体管和第二电容， 第十一晶体管和第十二晶 体管的栅极连接到第一电容， 第十一晶体管的漏极连接下拉节点， 源极连接 到第十二晶体管的漏极， 第十二晶体管的源极连接到第一电位， 第二电容一 端连接到下拉节点， 另一端接收第二时钟信号。
6、如权利要求 3或者 4所述的移位寄存器单元， 其中， 所述第一下拉模 块包括第四晶体管、 第五晶体管和第六晶体管， 第四晶体管的栅极、 第五晶 体管的栅极与下拉节点相连接， 第四晶体管的源极与第五晶体管的漏极相连 接， 第五晶体管的源极连接到第一电位， 第四晶体管的漏极连接到上拉节点； 第六晶体管的栅极接收第一时钟信号， 源极连接到第二电位， 漏极连接到上 拉节点。
7、如权利要求 3或者 4所述的移位寄存器单元， 其中， 所述第一下拉模 块包括第四晶体管和第六晶体管， 第四晶体管的栅极连接到下拉节点， 漏极 连接到上拉节点， 源极连接到第二电位； 第六晶体管的栅极接收第一时钟信 号， 源极连接到第二电位， 漏极连接到上拉节点。
8、 如权利要求 1-4任何一项所述的移位寄存器单元， 其中， 所述隔离上 拉模块包括第七晶体管和第八晶体管， 第七晶体管和第八晶体管的栅极通过 隔离节点连接到第一电容， 第七晶体管的源极连接到上拉节点， 漏极连接到 第八晶体管的源极； 第八晶体管的漏极接收第二时钟信号。
9、如权利要求 8所述的移位寄存器单元， 其中， 所述第一电容通过第九 晶体管接收上一级进位信号， 第九晶体管的栅极接收第一时钟信号， 漏极接 收上一级进位信号， 源极连接到第一电容和隔离节点。
10、 如权利要求 1-4任何一项所述的移位寄存器单元， 其中， 所述输出 上拉模块包括第二时钟信号， 所述驱动晶体管的漏极接收第二时钟信号。
11、 如权利要求 10所述的移位寄存器单元， 其中， 所述输出上拉模块还 包括第十晶体管， 其栅极接收第二时钟信号， 漏极与高电平相连接， 源极与 驱动晶体管的漏极相连接。
12、一种移位寄存器， 包括多级如权利要求 1至 11中任一权利要求所述 的移位寄存器单元， 每一级移位寄存器单元包括进位信号输入端和进位信号 输出端，除了第一级移位寄存器单元的进位信号输入端用于接收起始信号夕卜， 其他级的移位寄存器单元的进位信号输入端与上一级移位寄存器单元的进位 信号输出端相连接；
除了最后一级移位寄存器单元外， 其他级的移位寄存器单元的进位信号 输出端与下一级移位寄存进位信号输入端相连接。 、 一种显示装置， 包括如权利要求 12所述的移位寄存器。
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