WO2014180074A1 - 移位寄存单元、移位寄存器和显示装置 - Google Patents

移位寄存单元、移位寄存器和显示装置 Download PDF

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Publication number
WO2014180074A1
WO2014180074A1 PCT/CN2013/081660 CN2013081660W WO2014180074A1 WO 2014180074 A1 WO2014180074 A1 WO 2014180074A1 CN 2013081660 W CN2013081660 W CN 2013081660W WO 2014180074 A1 WO2014180074 A1 WO 2014180074A1
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WIPO (PCT)
Prior art keywords
pull
transistor
signal input
shift register
input terminal
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Application number
PCT/CN2013/081660
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English (en)
French (fr)
Inventor
青海刚
祁小敬
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/423,252 priority Critical patent/US9887013B2/en
Publication of WO2014180074A1 publication Critical patent/WO2014180074A1/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • Shift register unit shift register and display device
  • the present invention relates to the field of organic light emitting display, and in particular to a shift register unit, a shift register including the shift register unit, and a display device including the shift register. Background technique
  • FIG. 1 Shown in FIG. 1 is a circuit diagram of a conventional basic shift register unit.
  • the basic shift register unit includes a driving transistor T1, an output pull-down transistor ⁇ 2, a reset transistor ⁇ 9, and a bootstrap capacitor 20.
  • the storage capacitor 30 the first clock signal input terminal CK, the second clock signal input terminal CKB, the drive signal input terminal OUT (nl), the reset terminal Reset, and the drive signal output terminal OUT(n).
  • the pull-up node PU point is a node connected to the gate of the driving transistor T1
  • the pull-down node PD is a node connected to the gate of the output pull-down transistor T2.
  • the start signal STV is input from the drive signal input terminal OUT (n-1), and VGL is at a low level.
  • Figure 2 is a timing diagram of the signals of the shift register unit of Figure 1 during operation, with VGH being high.
  • a thin film transistor made of a-si (amorphous silicon) and p-si (polysilicon) is an enhancement type thin film transistor, and when the basic shift register unit circuit is fabricated using the enhanced TFT technology, the shift shown in FIG.
  • the bit register unit can work normally (as shown by the solid line in Figure 2).
  • oxide thin film transistors As a very promising semiconductor technology, are more compact and less expensive than the p-si process, and are more and more important than the a-si mobility. The future is likely to be the mainstream backplane drive technology for OLED, flexible displays.
  • the oxide thin film transistor has a depletion type characteristic (the difference from the enhancement type thin film transistor is shown in FIG. 3 and FIG. 4, and FIG. 3 is a characteristic diagram of the enhancement type thin film transistor).
  • the vertical axis is the current of the drain of the thin film transistor, and the horizontal axis As the voltage of the gate source, it can be seen from the characteristic diagram of the enhancement thin film transistor shown in FIG.
  • Embodiments of the present invention provide a shift register unit, a shift register including the shift register unit, and a display device including the shift register, wherein a depletion thin film transistor can be used in the shift register unit .
  • a shift register unit includes a drive signal input end, a drive signal output end, a first clock signal input end, and a first a clock signal input terminal, a driving transistor, and an output pull-down transistor, wherein a gate of the output pull-down transistor is connected to the second clock signal input end, and a low level input by the driving signal input end is a first low voltage Ping, the source of the output pull-down transistor is connected to the first low-level output terminal, and the low level input by the first clock signal input end and the second clock signal input end is the second low level.
  • the difference between the first low level and the second low level is greater than the absolute value of the threshold voltage of the pull-down transistor, such that the pull-down transistor can be turned off during the evaluation phase.
  • a gate of the driving transistor is formed as a pull-up node
  • the shift register unit further includes a switching unit connected to the pull-up node, the switching unit being capable of pulling the pull-up node in a pre-charging stage Conducting with the driving signal input terminal to charge a capacitor connected in parallel with the driving transistor, and the switching unit can disconnect the pull-up node from the driving signal input end during an evaluation phase to prevent The pull-up node leaks electricity.
  • the switching unit includes a first switching transistor and a second switching transistor, a gate of the first switching transistor is connected to the second clock signal input end, a drain of the first switching transistor and the a driving signal input end is connected, a source of the first switching transistor is connected to a drain of the second switching transistor, a gate of the second switching transistor is connected to the driving signal input end, and the second switch A source of the transistor is coupled to the pull up node.
  • the shift register unit includes a pull-down unit and a pull-down transistor, a gate of the pull-down transistor is connected to the pull-down unit, and a source of the pull-down transistor is connected to a second low-level output, the pull-down The cell is capable of turning off the pull-down transistor during an evaluation phase and turning the pull-down transistor on during a reset phase and an inactive phase, such that the pull-down transistor can pull the pull-up during the reset phase and the non-working phase The level of the node is pulled low to the second low level.
  • the pull-down unit includes a first pull-down control transistor and a second pull-down control transistor, a gate of the first pull-down control transistor is connected to the pull-up node, and a source of the first pull-down control transistor
  • the pole is connected to the third low level output terminal
  • the gate of the second pull-down control transistor is connected to the second clock signal input end
  • the drain of the first pull-down control transistor and the gate of the pull-down transistor a drain connection
  • a drain of the second pull-down control transistor is connected to a high-level output terminal
  • a source of the second pull-down control transistor is connected to a gate of the pull-down transistor
  • the second low level The difference of the third low level is greater than the threshold voltage of the pull-down transistor.
  • the pull-down unit further includes a third pull-down control transistor, a gate of the third pull-down control transistor is connected to the first clock signal input end, a source of the third pull-down control transistor and the third The low level output is connected, and the drain of the third pull-down control transistor is connected to the source of the second pull-down control transistor.
  • a third pull-down control transistor a gate of the third pull-down control transistor is connected to the first clock signal input end, a source of the third pull-down control transistor and the third The low level output is connected, and the drain of the third pull-down control transistor is connected to the source of the second pull-down control transistor.
  • the driving transistor, the output pull-down transistor, the first switching transistor, the second switching transistor, the pull-down transistor, the first pull-down control transistor, the second pull-down control transistor, and At least one of the third pull-down control transistors is a depletion transistor.
  • a shift register is provided, the shift register includes a multi-stage shift register unit, wherein the shift register unit is the shift register unit provided by the embodiment of the present invention.
  • the drive signal input end of the shift register unit of the next stage is connected to the drive signal output end of the shift register of the previous stage.
  • a display device is provided, wherein the display device includes the above shift register provided by an embodiment of the present invention.
  • the second clock signal input end is connected to the gate of the output pull-down transistor, and the source of the pull-down transistor and the first low level that can output the first low level are output.
  • the inputs are connected. Since the low level input by the second clock signal input end in the evaluation stage is the second low level, and the difference between the second low level and the first low level is greater than the threshold voltage of the pull-down transistor, The two clock signal inputs directly control the pull-down transistor to turn off completely during the evaluation phase. Since the difference between the second low level and the first low level is greater than the threshold voltage of the pull-down transistor, even if the pull-down transistor is a depletion transistor, the pull-down transistor can be completely turned off during the evaluation phase.
  • 1 is a circuit diagram of a conventional basic shift register unit
  • FIG. 2 is a timing chart of signals of the shift register unit shown in FIG. 1 during operation;
  • FIG. 3 is a characteristic diagram of the enhancement transistor;
  • Figure 4 is a characteristic diagram of a depletion transistor
  • FIG. 5 is a circuit diagram of an embodiment of a shift register unit according to an embodiment of the present invention
  • FIG. 6 is a circuit diagram of another embodiment of a shift register unit according to an embodiment of the present invention
  • Fig. 7 is a timing chart of signals in operation of the shift register unit shown in Fig. 6. Description of the reference numerals
  • T1 Drive transistor T2: Output pull-down transistor
  • T3 second pull-down control transistor
  • T4 third pull-down control transistor
  • T5 first pull-down control transistor
  • T6 pull-down transistor
  • T7 second switching transistor
  • T8 first switching transistor
  • CK first clock signal input terminal PU: pull-up node
  • VGH High level
  • VGL Low level
  • VGL1 first low level
  • VGL2 second low level
  • VGL3 third low level
  • T9 reset transistor
  • a shift register unit including a drive signal input terminal OUT (n-1) and a drive signal output terminal OUT (n) is provided.
  • the low level of the OUT (n-1) input is the first low level VGL1, and the source of the output pull-down transistor T2 and the first low level output terminal (the first low level output terminal can be the source of the output pull-down transistor T2)
  • the first output of the first low level VGL1 is connected, and the low level input by the first clock signal input terminal CK and the second clock signal input terminal CKB is the second low level VGL2, the first low level VGL1 and the second low level
  • the difference of the flat VGL2 is greater than the absolute value of the threshold voltage (ie, the threshold voltage) of the output pull-down transistor T2 (ie, VGL1-VGL2 > IVtht2l), so that the output pull-down transistor T2 can be turned off during the evaluation
  • the high level signal input from the driving signal input terminal OUT (n-1) is a high level VGH, and is driven from the driving signal input terminal OUT (n- 1)
  • the input low level signal is the first low level VGL1; the high level first clock signal input from the first clock signal input terminal CK is the high level VGH, and the input from the first clock signal input terminal CK is low.
  • the level is the second low level VGL2; the high level input from the second clock signal input terminal CKB is VGH, and the low level input from the second clock signal input terminal CKB is the second low level VGL2.
  • the output clock of the output pull-down transistor T2 can be directly controlled by using the second clock signal input from the second clock signal input terminal CKB. Turn it on and off.
  • the first clock signal input terminal CK inputs the first clock signal to a high level VGH
  • the second clock signal input terminal CKB inputs a second clock signal.
  • the signal input to the driving signal input terminal OUT (n-1) is the first low level VGL1
  • the gate level of the output pull-down transistor T2 is the second low level VGL2
  • the output pull-down transistor T2 The source level is the first low level VGL1.
  • VGL1-VGL2 > IVthT2l even in the evaluation stage, even if the output pull-down transistor T2 is a depletion transistor, the output pull-down transistor T2 can still be normally turned off, and will not A leakage has occurred.
  • a node connected to the gate of the driving transistor T1 is referred to as a pull-up node (ie, a gate of the driving transistor T1 is formed as a pull-up node PU), and a potential of the pull-up node PU and a gate of the driving transistor T1 are The potentials are consistent.
  • the shift register unit may further include a switch unit 11 connected to the pull-up node PU, and the switch unit 11 may be in a pre-charge phase (ie, FIG. 7 Phase 1) turns on the pull-up node PU and the drive signal input terminal OUT (n-1) to charge the capacitor C in parallel with the driving transistor T1, and the switching unit 11 can be in the evaluation phase (ie, in FIG. 7 Phase 2) disconnects the pull-up node PU from the drive signal input terminal OUT (n-1) to prevent the pull-up node PU from leaking.
  • a pre-charge phase ie, FIG. 7 Phase 1
  • the switch unit 11 may be in a pre-charge phase (ie, FIG. 7 Phase 1) turns on the pull-up node PU and the drive signal input terminal OUT (n-1) to charge the capacitor C in parallel with the driving transistor T1
  • the switching unit 11 can be in the evaluation phase (ie, in FIG. 7 Phase 2) disconnects the pull-up node PU from the drive signal input terminal OUT
  • the switching unit 11 turns on the pull-up node PU and the driving signal input terminal OUT(n-1), so that the driving signal input terminal OUT(n-1) can normally charge the capacitor C to make the pull-up node
  • the voltage of the PU rises rapidly; in the evaluation phase, the second clock signal input terminal CKB inputs the second low level VGL2 to turn off the output pull-down transistor T2, and the first clock signal input terminal CK inputs the high level VGH, which is high.
  • the flat VGH couples the pull-up node PU to a higher potential through the capacitor C through the driving transistor T1, and the switching unit 11 disconnects the pull-up node PU from the driving signal input terminal OUT (n-1) to prevent the pull-up node PU from leaking.
  • an output signal having a sufficient pulse width can be obtained at the drive signal output terminal OUT(n).
  • the switching unit 11 can have various forms as long as the pull-up node PU and the driving signal input terminal OUT (n-1) are turned on in the pre-charging phase to be in parallel with the driving transistor T1.
  • the capacitor C is charged, and the switching unit 11 can disconnect the pull-up node PU from the drive signal input terminal OUT (n-1) during the evaluation phase to prevent the pull-up node PU from leaking.
  • the switching unit 11 may include a first switching transistor T8 and a second switching transistor T7, and a gate of the first switching transistor T8 and a second clock signal input.
  • the terminal CKB is connected, the drain of the first switching transistor T8 is connected to the driving signal input terminal OUT (n-1), the source of the first switching transistor T8 is connected to the drain of the second switching transistor T7, and the second switching transistor T7 is connected.
  • the gate is connected to the driving signal input terminal OUT(n1), and the source of the second switching transistor T7 is connected to the pull-up node PU.
  • the signal input to the driving signal input terminal OUT (n-1) is a high level VGH
  • the first clock signal input to the first clock signal input terminal CK is a second.
  • the low level VGL2 the second clock signal input by the second clock signal input terminal CKB is a high level VGH.
  • the gate of the first switching transistor T8 is connected to the second clock signal input terminal CKB, the gate of the second switching transistor T7 is connected to the driving signal input terminal OUT(n-1), and therefore, the first switching transistor T8 and the second The open transistor T7 is turned on, and the driving signal input terminal OUT(n-1) can charge the capacitor C through the first switching transistor T8 and the second switching transistor T7, the pull-up section The voltage at the point PU will rise rapidly.
  • the signal input to the driving signal input terminal OUT (n-1) is the first low level VGL1
  • the second clock signal input to the second clock signal input terminal CKB is The second low level VGL2, therefore, the first switching transistor T8 and the second switching transistor T7 are both turned off. Since the first switching transistor T8 and the second switching transistor T7 are turned off, the first clock signal input by the first clock signal input terminal CK is at a high level VGH, and the first clock signal may be pulled up by the node PU. The potential is coupled to a higher potential through capacitor C without leakage.
  • the first switching transistor T8 and the second switching transistor T7 are depletion transistors, the difference between the first low level VGL1 and the second low level VGL2 is greater than the threshold voltage of the first switching transistor T8.
  • the absolute value ie, VGLl-VGL2 > IVtht8l is ensured that the first switching transistor T8 can be normally turned off during the evaluation phase.
  • the shift control unit may further include a pull-down unit 12 and a pull-down transistor T6.
  • the gate of the pull-down transistor T6 is connected to the pull-down unit 12, and the pull-down transistor T6 is The source is connected to the second low level output (the second low level output can output the second low level VGL2 to the source of the pull-down transistor T6), and the pull-down unit 12 can be in the evaluation stage (ie, in FIG.
  • Phase 2) turns off pull-down transistor T6, and turns on pull-down transistor T6 during the reset phase (ie, phase 3 in Figure 7) and the non-working phase (ie, the portion to the right of phase 3 in Figure 7), causing the pull-down transistor T6 is capable of pulling the level of the pull-up node PU to the second low level during the reset phase and the non-working phase.
  • the pull-down transistor T6 is turned off to prevent the pull-up node PU from leaking.
  • the pull-down transistor T6 is turned on to discharge the pull-up node PU, thereby ensuring that the drive signal output terminal OUT ( n ) outputs a low level during the reset phase and the non-operation phase.
  • the pull-down transistor T6 can be turned off during the evaluation phase, and the pull-down transistor T6 can be turned on in the reset phase and the non-operation phase.
  • the pull-down unit 12 includes a first pull-down control transistor T5 and a second pull-down control transistor T3, and the gate of the first pull-down control transistor T5 is connected to the pull-up node PU.
  • a source of the first pull-down control transistor T5 and a third low-level output terminal (the third low-level output terminal may output a third low level to the source of the first pull-down control transistor T5) VGL3) is connected, the drain of the first pull-down transistor T5 is connected to the gate of the pull-down transistor T6, the gate of the second pull-down control transistor ⁇ 3 is connected to the second clock signal input terminal CKB, and the drain of the second pull-down control transistor ⁇ 3 And a high level output terminal (the high level output terminal may be connected to the drain output high level VGH of the second pull-down control transistor ⁇ 3), and the source of the second pull-down control transistor ⁇ 3 is connected to the gate of the pull-down transistor ⁇ 6,
  • the difference between the two low level VGL2 and the third low level VGL3 is greater than the threshold voltage of the pull-down transistor ⁇ 6 (ie, VGL2-VGL3 > IVthT6l).
  • the signal input by the driving signal input terminal OUT (n-1) is the first low level VGL1
  • the second clock signal input by the second clock signal input terminal CKB is jumped to the second low level VGL2
  • the first clock signal input by a clock signal input terminal CK transitions to a high level VGH.
  • the output pull-down transistor T2 is turned off. Since the pull-up node PU is coupled to a higher level, the first pull-down control transistor T5 is turned on, and the second pull-down control transistor T3 is turned off, thereby pulling down the gate voltage of the pull-down transistor T6 to the third low level VGL3.
  • the pull-down transistor T6 is turned off completely.
  • the gate of the pull-down transistor T6 may be referred to as a pull-down node PD.
  • the second clock signal input terminal CKB directly controls the output pull-down transistor T2, so the pull-down node PD has no influence on the drive signal output terminal OUT(n).
  • the second clock signal input by the second clock signal input terminal CKB transitions to a high level VGH, and the driving signal input terminal OUT (n-1) maintains a first low level VGL1, and the first clock signal input terminal CK The input first clock signal jumps to the second low level VGL2.
  • the output pull-down transistor T2 is turned on, the driving signal output terminal OUT ( n ) is pulled down to the first low level VGL1 , and the voltage jump of the driving signal output terminal OUT ( n ) is rapidly coupled to the potential of the pull-up node PU through the coupling of the capacitor C Pulling down to a lower potential than the evaluation stage, of course, the potential is still sufficient to enable the driving transistor T1 to be turned on, except that the first clock signal input by the first clock signal input terminal CK is the second low level VGL2, and the driving signal output end OUT ( n ) has no pull-up effect.
  • the gate potential of the first pull-down control transistor T5 is also lowered, but is still in a certain on state, but the current through which the turn-on is passed is small, and the pull-down effect on the PD point of the pull-down node is weak.
  • the gate of the second pull-down control transistor T3 is the high level VGH input by the second clock signal input terminal CKB, so the second pull-down control transistor T3 is fully turned on, although the first pull-down control transistor T5 is not turned off, but the pull-down effect is weakened.
  • the pull-down node PD will still be pulled up to the high level of the second pull-down control transistor T3, so that the pull-down transistor T6 is turned on, so that the potential of the pull-up node PU is rapidly pulled down, and the pull-down node PD potential is quickly pulled down.
  • the first pull-down control transistor T5 is further turned off, and this interaction causes the potential of the pull-up node PU to drop faster.
  • the driving transistor T1 is caused to lower the potential of the pull-up node PU to the second low level VGL2 before the next high level input of the first clock signal input terminal CK, thereby completely turning off the driving transistor T1.
  • the pull-down of the pull-down node PD does not make any sense.
  • the pull-down level is used in addition to the pull-down capability in the working phase to quickly turn off the pull-down transistor ⁇ 6, another function is Therefore, the gate of the pull-down transistor ⁇ 6, that is, the pull-down node PD can be in an alternating voltage state, avoiding the long-term DC bias causing the transmission curve of the pull-down transistor ⁇ 6 to shift to the right and aging failure, thereby improving the entire shift register unit. Service life.
  • the pull-down unit 12 can further include a third pull-down control transistor ⁇ 4, the gate of which is connected to the first clock signal input terminal CK.
  • the source of the third pull-down control transistor ⁇ 4 is connected to the third low-level output terminal, and the drain of the third pull-down control transistor ⁇ 4 is connected to the source of the second pull-down control transistor ⁇ 3.
  • the driving transistor T1, the output pull-down transistor ⁇ 2, the first switching transistor ⁇ 8, the second switching transistor ⁇ 7, the pull-down transistor ⁇ 6, the first lower At least one of the pull control transistor ⁇ 5, the second pull-down control transistor ⁇ 3, and the third pull-down control transistor ⁇ 4 is a depletion transistor.
  • the driving transistor T1, the output pull-down transistor ⁇ 2, the first switching transistor ⁇ 8, the second switching transistor ⁇ 7, the pull-down transistor ⁇ 6, the first pull-down control will be described below with reference to the specific embodiment in FIG.
  • the transistor ⁇ 5, the second pull-down control transistor ⁇ 3, and the third pull-down control transistor ⁇ 4 are all depletion transistors, and the threshold voltages of the transistors are equal, the operation principle of each of the transistors described above.
  • the third pull-down control transistor ⁇ 4 is all an oxide transistor.
  • the precharge phase (ie, phase 1 in FIG. 7): the second clock signal input from the second clock signal input terminal CKB and the signal input from the drive signal input terminal OUT (n-1) are at a high level VGH, the first clock The first clock signal input by the signal input terminal CK is the second low level VGL2, so the output pull-down transistor T2, the second pull-down control transistor ⁇ 3, the second switching transistor ⁇ 7 and the first switch Transistor T8 is turned on.
  • the third pull-down control transistor ⁇ 4 Since the source voltage of the third pull-down control transistor ⁇ 4 is the third low level VGL3, and the gate voltage of the third pull-down control transistor ⁇ 4 is the second low level VGL2 input by the first clock signal input terminal CK, the third The pull-down control transistor ⁇ 4 is not completely turned off but there is a certain leakage.
  • the second switching transistor ⁇ 7 and the first switching transistor ⁇ 8 are turned on, and the driving signal input terminal OUT(n-1) charges the capacitor C through the second switching transistor T7 and the first switching transistor T8, and the voltage of the pull-up node PU rises rapidly.
  • the first pull-down control transistor T5 is turned on, although the second pull-down control transistor T3 is also turned on, so that the high level VGH input to the high level input terminal has a certain pull-up effect on the pull-down node PD, but due to the third pull-down control
  • the leakage of the transistor T4 and the opening of the first pull-down control transistor T5 will quickly pull down the potential of the pull-down node PD by the third low level VGL3.
  • the gate potential of the pull-down transistor T6 is completely turned off due to the cooperation of the second pull-down control transistor T3 and the third pull-down control transistor T4 and the second pull-down control transistor ⁇ 5 not completely falling to the third low level VGL3,
  • the drain current of the pull-down transistor ⁇ 6 is greatly reduced, so that the potential of the pull-up node PU is not excessively pulled down, so that the pre-charge phase drive transistor T1 can still obtain a sufficient turn-on potential.
  • the driving signal output terminal OUT(n) will be pulled down by the low level of the first clock signal input by the first clock signal input terminal CK, and the output terminal OUT will also be turned on when the output pull-down transistor T2 is turned on ( The potential of n) is pulled down.
  • the evaluation phase (ie, phase 2 in FIG. 7): the signal input to the drive signal input terminal OUT (n-1) is the first low level VGL1, and the second clock signal input from the second clock signal input terminal CKB is changed. For the second low level VGL2, the first clock signal input by the first clock signal input terminal CK jumps to a high level VGH.
  • the source of the output pull-down transistor T2 is extremely first low level VGL1, and the gate of the output pull-down transistor T2 is the second low level VGL2 input by the second clock signal input terminal CKB, so the output pull-down transistor T2 is turned off.
  • the source potential of the first switching transistor T8 is the first low level VGL1 input by the driving signal input terminal OUT(n-1), and the gate potential of the first switching transistor T8 is the second clock signal input terminal CKB.
  • the clock signal ie, the second low level VGL2
  • the first switching transistor T8 is turned off.
  • the second clock signal input by the second clock signal input terminal CKB is the second low level VGL2, the second pull-down control transistor T3 is not completely turned off, but a small leak current is passed.
  • the driving transistor T1 Since the first clock signal (high level VGH) outputted by the first clock signal input terminal CK passes through the driving transistor T1, the potential of the pull-up node PU is coupled to a higher potential through the capacitor C, so the first pull-down control transistor T5 is fully turned on, and the third pull-down control transistor T4 is also turned on. Although the second pull-down control transistor T3 is not completely turned off, the potential of the pull-down node PD will still be pulled down to the third low level VGL3, so the pull-down transistor T6 is completely turned off. This further creates a condition for the pull-up node PU to save the high potential, and the sufficient turn-on of the driving transistor T1 causes the driving signal output terminal OUT (n) terminal to output a high level VGH.
  • the reset phase (ie, phase 3 in FIG. 7): the second clock signal input from the second clock signal input terminal CKB transitions to the high level VGH, and the signal input from the drive signal input terminal OUT (n-1) remains first Low level VGL1.
  • the first clock signal input by the first clock signal input terminal CK is the second low level VGL2. Therefore, the output pull-down transistor T2, the second pull-down control transistor ⁇ 3, the second switching transistor ⁇ 7, and the first switching transistor ⁇ 8 are turned on.
  • the third pull-down control transistor ⁇ 4 Since the source level of the third pull-down control transistor T4 is the third low level VGL3, and the gate of the third pull-down control transistor T4 is the first clock signal input by the first clock signal input terminal CK (ie, the second low voltage) Flat VGL2), so the third pull-down control transistor ⁇ 4 is not completely turned off but there is a certain leakage. Due to the turn-on of the output pull-down transistor ⁇ 2, the drive signal output terminal OUT(n) is pulled down to the first low level VGL1, and the voltage jump of the drive signal output terminal OUT(n) is coupled to the pull-up node PU by the coupling of the capacitor C. The potential is quickly pulled down to a lower potential than the evaluation phase. Of course, the potential is still sufficient to turn on the driving transistor T1, but the first clock signal input terminal CK is also at a low potential, and the driving signal output terminal OUT (n) is not pulled up. effect.
  • the gate potential of the first pull-down control transistor T5 also decreases, but is still in a certain on state, but the current through which the turn-on is passed is small, and the pull-down effect on the pull-down node PD is weakened. . Due to the high level VGH of the second clock signal input terminal CKB, the second pull-down control transistor T3 is fully turned on.
  • the pull-down control transistor T5 is not turned off, since the pull-down effect is weakened, the pull-down node PD is still pulled up to the high level by the second pull-down control transistor T3, so that the pull-down transistor T6 is turned on, and the pull-up node The potential of the PU is quickly pulled down, and the rapid pull-down of the pull-up node PU further turns off the first pull-down control transistor T5.
  • This interaction causes the potential of the pull-up node PU to drop faster, so that the driving transistor T1 is at the first Before the next high level of the clock signal input terminal CK, the potential of the pull-up node PU is lowered to the second low level VGL2, thereby completely turning off the driving transistor T1.
  • first low level Three different low levels (first low level) are used in the shift register unit shown in FIG. VGL1, the second low level VGL2 and the third low level VGL3) can make the gate-source voltage of the output pull-down transistor T2 a negative value, so that the output pull-down transistor T2 can be completely turned off during the evaluation phase.
  • the shift register unit can also maintain the potential of the pull-up node PU so that the drive transistor T1 is completely turned off during the non-operational phase, so that a signal having a desired pulse width and a desired voltage can be output.
  • a shift register is provided, the shift register includes a multi-stage shift register unit, wherein the shift register unit is the shift register unit provided by the embodiment of the present invention.
  • the drive signal input end of the shift register unit of the next stage is connected to the drive signal output end of the shift register of the previous stage.
  • n is a positive integer.
  • a display device including the above shift register provided by the embodiment of the present invention.
  • the display device may include a liquid crystal display device such as a liquid crystal panel, a liquid crystal television, a mobile phone, a liquid crystal display, or the like.
  • the display device may further include an organic light emitting display or other type of display device such as an electronic reader or the like.
  • the shift register can be used as a scanning circuit or a gate driving circuit of the display device or the like to provide a progressive scanning function for transmitting a scanning signal to the display area.

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Abstract

一种移位寄存单元、一种移位寄存器和一种显示装置。该移位寄存单元包括驱动信号输入端（OUT（n-1））、驱动信号输出端（OUT（n））、第一时钟信号输入端（CK）、第二时钟信号输入端（CKB）、驱动晶体管（T1）和输出下拉晶体管（T2），其中，输出下拉晶体管（T2）的栅极与第二时钟信号输入端（CKB）相连，驱动信号输入端（OUT（n-1））输入的低电平为第一低电平（VGL1），输出下拉晶体管（T2）的源极与第一低电平（VGL1）输出端连接，第一时钟信号输入端（CK）和第二时钟信号输入端（CKB）输入的低电平均为第二低电平（VGL2），第一低电平（VGL1）与第二低电平（VGL2）的差值大于输出下拉晶体管（T2）的临界电压的绝对值，使得下拉晶体管（T2）能够在求值阶段关闭。该移位寄存单元中可以使用耗尽型薄膜晶体管。

Description

移位寄存单元、 移位寄存器和显示装置 技术领域
本发明涉及有机发光显示领域， 具体地， 涉及一种移位寄存单元、 一种 包括该移位寄存单元的移位寄存器和一种包括该移位寄存器的显示装置。 背景技术
随着平板显示的发展， 高分辨率、 窄边框成为发展的潮流， 而在显示面 板上集成栅极驱动电路是实现高分辨率、 窄边框显示最重要的解决办法。
图 1中所示的是现有的基本的移位寄存单元的电路图， 如图 1所示， 该 基本的移位寄存单元包括驱动晶体管 Tl、 输出下拉晶体管 Τ2、 复位晶体管 Τ9、 自举电容 20、 存储电容 30、 第一时钟信号输入端 CK、 第二时钟信号输 入端 CKB、 驱动信号输入端 OUT ( n-l )、 复位端 Reset和驱动信号输出端 OUT ( n )。
在图 1中， 上拉节点 PU点为与驱动晶体管 T1的栅极连接的节点， 下 拉节点 PD为与输出下拉晶体管 T2的栅极连接的节点。 从驱动信号输入端 OUT ( n-1 )输入起始信号 STV, VGL为低电平。 图 2中所示的是图 1中的 移位寄存单元在工作时各信号的时序图， VGH为高电平。
a-si (非晶硅）和 p-si (多晶硅）制成的薄膜晶体管为增强型薄膜晶体 管， 当使用增强型 TFT技术制作该基本的移位寄存单元电路时， 图 1中所示 的移位寄存单元可以正常工作 （如图 2的实线部分所示）。
近年来， 氧化物薄膜晶体管作为一种非常有潜力的半导体技术，相比于 p-si工艺更筒单， 成本更低， 相比于 a-si迁移率更高， 因而越来越受到重视， 未来很可能是 OLED, 柔性显示的主流背板驱动技术。 然而氧化物薄膜晶体 管具有耗尽型的特点 （与增强型薄膜晶体管的差别见图 3和图 4, 图 3为增 强型薄膜晶体管的特性曲线图）纵轴为薄膜晶体管漏极的电流， 横轴为栅源 极的电压， 从图 3中所示的增强型薄膜晶体管的特性曲线图中可以看出， 当 Vgs (栅源电压）电压为零时， id (漏极电流)为零， 说明 Vgs为零时， 增强型 薄膜晶体管完全关闭；从图 4中耗尽型薄膜晶体管的特性曲线图中可以看出， 同样纵轴为漏极电流， 横轴为栅源电压， 但该图显示的却是 Vgs为零时， id 远大于零， 而只有在栅源电压为一定的负电压时， id才为零。 如图 2中虚线部分所示，将耗尽型薄膜晶体管应用于图 1中所示的电路 时， 并不能正常工作。 发明内容
本发明实施例提供一种移位寄存单元、一种包括该移位寄存单元的移位 寄存器和一种包括该移位寄存器的显示装置， 所述移位寄存单元中可以使用 耗尽型薄膜晶体管。
为了解决现有技术中的缺陷，作为本发明实施例的一个方面， 提供一种 移位寄存单元， 该移位寄存单元包括驱动信号输入端、 驱动信号输出端、 第 一时钟信号输入端、 第二时钟信号输入端、 驱动晶体管和输出下拉晶体管， 其中， 所述输出下拉晶体管的栅极与所述第二时钟信号输入端相连， 所述驱 动信号输入端输入的低电平为第一低电平， 所述输出下拉晶体管的源极与第 一低电平输出端连接，所述第一时钟信号输入端和所述第二时钟信号输入端 输入的低电平均为第二低电平， 所述第一低电平与所述第二低电平的差值大 于所述下拉晶体管的临界电压的绝对值，使得所述下拉晶体管能够在求值阶 段关闭。
优选地， 所述驱动晶体管的栅极形成为上拉节点， 所述移位寄存单元还 包括与所述上拉节点连接的开关单元， 所述开关单元能够在预充电阶段将所 述上拉节点与所述驱动信号输入端导通， 以对与所述驱动晶体管并联的电容 充电， 并且所述开关单元能够在求值阶段将所述上拉节点与所述驱动信号输 入端断开， 以防止所述上拉节点漏电。
优选地， 所述开关单元包括第一开关晶体管和第二开关晶体管， 所述第 一开关晶体管的栅极与所述第二时钟信号输入端相连， 所述第一开关晶体管 的漏极与所述驱动信号输入端相连，所述第一开关晶体管的源极与所述第二 开关晶体管的漏极相连， 所述第二开关晶体管的栅极与所述驱动信号输入端 相连， 所述第二开关晶体管的源极与所述上拉节点相连。
优选地， 所述移位寄存器单元包括下拉单元和下拉晶体管， 所述下拉晶 体管的栅极与所述下拉单元相连， 所述下拉晶体管的源极与第二低电平输出 端相连， 所述下拉单元能够在求值阶段将所述下拉晶体管关闭， 并且在复位 阶段和非工作阶段将所述下拉晶体管开启，使得所述下拉晶体管能够在所述 复位阶段和所述非工作阶段将所述上拉节点的电平拉低至所述第二低电平。 优选地， 所述下拉单元包括第一下拉控制晶体管和第二下拉控制晶体 管， 所述第一下拉控制晶体管的栅极与所述上拉节点相连， 所述第一下拉控 制晶体管的源极与第三低电平输出端连接， 所述第二下拉控制晶体管的栅极 与所述第二时钟信号输入端相连， 所述第一下拉控制晶体管的漏极与所述下 拉晶体管的栅极连接， 所述第二下拉控制晶体管的漏极与高电平输出端连 接， 所述第二下拉控制晶体管的源极与所述下拉晶体管的栅极连接， 所述第 二低电平与所述第三低电平的差值大于所述下拉晶体管的临界电压。
优选地， 所述下拉单元还包括第三下拉控制晶体管， 该第三下拉控制晶 体管的栅极与所述第一时钟信号输入端相连， 所述第三下拉控制晶体管的源 极与所述第三低电平输出端相连， 所述第三下拉控制晶体管的漏极与所述第 二下拉控制晶体管的源极相连。
优选地，所述驱动晶体管、所述输出下拉晶体管、所述第一开关晶体管、 所述第二开关晶体管、 所述下拉晶体管、 所述第一下拉控制晶体管、 所述第 二下拉控制晶体管和所述第三下拉控制晶体管中的至少一者为耗尽型晶体 管。
作为本发明实施例的另一个方面， 提供一种移位寄存器， 该移位寄存器 包括多级移位寄存单元， 其中， 所述移位寄存单元为本发明实施例所提供的 上述移位寄存单元， 下一级所述移位寄存单元的驱动信号输入端与上一级所 述移位寄存器的驱动信号输出端相连。
作为本发明实施例的还一个方面， 提供一种显示装置， 其中， 该显示装 置包括本发明实施例所提供的上述移位寄存器。
在本发明实施例所提供的移位寄存单元中，利用第二时钟信号输入端与 输出下拉晶体管的栅极相连，输出下拉晶体管的源极与可以输出第一低电平 的第一低电平输入端相连。 由于第二时钟信号输入端在求值阶段输入的低电 平为第二低电平，且第二低电平与第一低电平的差值大于下拉晶体管的临界 电压， 因此， 可以利用第二时钟信号输入端直接控制下拉晶体管在求值阶段 时完全关闭。 由于， 第二低电平与第一低电平的差值大于下拉晶体管的临界 电压， 因此， 即便下拉晶体管为耗尽型晶体管， 在求值阶段， 所述下拉晶体 管仍能完全关闭。 附图说明 附图是用来提供对本发明实施例的进一步理解，并且构成说明书的一部 分， 与下面的具体实施方式一起用于解释本发明实施例， 但并不构成对本发 明的限制。 在附图中：
图 1是现有基本的移位寄存单元的电路图；
图 2是图 1中所示的移位寄存单元在工作时各信号的时序图； 图 3是增强型晶体管的特性曲线图；
图 4是耗尽型晶体管的特性曲线图；
图 5是本发明实施例所提供的移位寄存单元一种实施方式的电路图； 图 6 是本发明实施例所提供的移位寄存单元的另一种实施方式的电路 图； 以及
图 7是图 6中所示的移位寄存单元的工作时各信号的时序图。 附图标记说明
T1: 驱动晶体管 T2: 输出下拉晶体管
T3: 第二下拉控制晶体管 T4: 第三下拉控制晶体管
T5: 第一下拉控制晶体管 T6: 下拉晶体管
T7: 第二开关晶体管 T8: 第一开关晶体管
CK: 第一时钟信号输入端 PU: 上拉节点
PD: 下拉节点 11 : 开关单元
12: 下拉单元 20: 自举电容
30: 存储电容 CKB: 第二时钟信号输入端
VGH: 高电平 VGL: 低电平
VGL1: 第一低电平 VGL2: 第二低电平
VGL3: 第三低电平 T9: 复位晶体管
OUT ( n-1 ): 驱动信号输入端
OUT ( n ): 驱动信号输出端 具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。 应当理解的是, 此处所描述的具体实施方式仅用于说明和解释本发明， 并不用于限制本发 明。 如图 5和图 6所示， 作为本发明实施例的一个方面， 提供一种移位寄存 单元， 该移位寄存单元包括驱动信号输入端 OUT ( n-1 )、 驱动信号输出端 OUT ( n )、 第一时钟信号输入端 CK、 第二时钟信号输入端 CKB、 驱动晶体 管 T1和输出下拉晶体管 T2, 其中， 输出下拉晶体管 T2的栅极与第二时钟 信号输入端 CKB相连， 驱动信号输入端 OUT ( n-1 )输入的低电平为第一低 电平 VGL1 , 输出下拉晶体管 T2的源极与第一低电平输出端 （第一低电平 输出端可以向输出下拉晶体管 T2的源极输出第一低电平 VGL1 )连接， 第 一时钟信号输入端 CK和第二时钟信号输入端 CKB输入的低电平均为第二 低电平 VGL2, 第一低电平 VGL1与第二低电平 VGL2的差值大于输出下拉 晶体管 T2的临界电压（即，阈值电压）的绝对值（即， VGL1-VGL2 > IVtht2l ), 使得输出下拉晶体管 T2能够在求值阶段关闭。
应当理解的是， 在本发明实施例中， 如图 7所示， 从驱动信号输入端 OUT ( n-1 )输入的高电平信号为高电平 VGH,从驱动信号输入端 OUT ( n-1 ) 输入的低电平信号为第一低电平 VGL1 ; 从第一时钟信号输入端 CK输入的 高电平第一时钟信号为高电平 VGH, 从第一时钟信号输入端 CK输入的低 电平为第二低电平 VGL2; 从第二时钟信号输入端 CKB输入的高电平为 VGH, 从第二时钟信号输入端 CKB输入的低电平为第二低电平 VGL2。
在本发明实施例中， 由于第二时钟信号输入端 CKB直接与输出下拉晶 体管 T2的栅极相连，因此可以利用从第二时钟信号输入端 CKB输入的第二 时钟信号直接控制输出下拉晶体管 T2的开启和关闭。
在移位寄存单元的求值阶段（即， 图 7中的阶段②）， 第一时钟信号输 入端 CK输入第一时钟信号为高电平 VGH, 第二时钟信号输入端 CKB输入 第二时钟信号为第二低电平 VGL2, 驱动信号输入端 OUT ( n-1 )输入的信 号为第一低电平 VGL1，输出下拉晶体管 T2的栅极电平为第二低电平 VGL2 , 输出下拉晶体管 T2的源极电平为第一低电平 VGL1 , 由于 VGL1-VGL2 > IVthT2l, 因此， 在求值阶段， 即便输出下拉晶体管 T2为耗尽型晶体管， 该 输出下拉晶体管 T2仍然可以正常关闭， 不会发生漏电。
通常地， 将与驱动晶体管 T1的栅极相连的节点称之为上拉节点 （即驱 动晶体管 T1的栅极形成为上拉节点 PU ), 上拉节点 PU的电位与驱动晶体 管 T1的栅极的电位相一致。
为了保证本发明实施例所提供的移位寄存单元可以输出具有足够脉宽 的方波， 优选地， 如图 5和图 6所示， 所述移位寄存单元还可以包括与上拉 节点 PU连接的开关单元 11 , 开关单元 11可以在预充电阶段（即， 图 7中 的阶段① )将上拉节点 PU与驱动信号输入端 OUT ( n-1 )导通， 以对与驱 动晶体管 T1并联的电容 C充电， 并且开关单元 11可以在求值阶段（即， 图 7中的阶段② )将上拉节点 PU与驱动信号输入端 OUT ( n-1 )断开， 以防止 上拉节点 PU漏电。
在预充电阶段，开关单元 11将上拉节点 PU与驱动信号输入端 OUT( n-1 ) 导通， 使得驱动信号输入端 OUT ( n-1 ) 可以对电容 C进行正常充电， 使上 拉节点 PU的电压迅速升起； 而在求值阶段， 第二时钟信号输入端 CKB输 入第二低电平 VGL2将输出下拉晶体管 T2关闭， 第一时钟信号输入端 CK 输入高电平 VGH, 该高电平 VGH通过驱动晶体管 T1 ,将上拉节点 PU通过 电容 C耦合到较高的电位， 开关单元 11将上拉节点 PU与驱动信号输入端 OUT ( n-1 ) 断开可以防止上拉节点 PU漏电， 从而可以在驱动信号输出端 OUT ( n )获得具有足够脉宽的输出信号。
在本发明实施例中， 开关单元 11可以具有多种形式， 只要可以满足在 预充电阶段将上拉节点 PU与驱动信号输入端 OUT ( n-1 )导通， 以对与驱 动晶体管 T1并联的电容 C充电，并且开关单元 11可以在求值阶段将上拉节 点 PU与驱动信号输入端 OUT ( n-1 ) 断开， 以防止上拉节点 PU漏电即可。
作为本发明的一种优选实施方式， 如图 5和图 6所示， 开关单元 11可 以包括第一开关晶体管 T8和第二开关晶体管 T7, 第一开关晶体管 T8的栅 极与第二时钟信号输入端 CKB相连，第一开关晶体管 T8的漏极与驱动信号 输入端 OUT ( n-1 )相连， 第一开关晶体管 T8的源极与第二开关晶体管 T7 的漏极相连，第二开关晶体管 T7的栅极与驱动信号输入端 OUT( n-l )相连， 第二开关晶体管 T7的源极与所述上拉节点 PU相连。
在预充电阶段（即， 图 7中的阶段① ), 驱动信号输入端 OUT ( n-1 )输 入的信号为高电平 VGH, 第一时钟信号输入端 CK输入的第一时钟信号为 第二低电平 VGL2, 第二时钟信号输入端 CKB输入的第二时钟信号为高电 平 VGH。由于第一开关晶体管 T8的栅极与第二时钟信号输入端 CKB相连， 第二开关晶体管 T7的栅极与驱动信号输入端 OUT ( n-1 )相连， 因此， 第一 开关晶体管 T8和第二开管晶体管 T7都是开启的，驱动信号输入端 OUT( n-1 ) 可以通过第一开关晶体管 T8和第二开关晶体管 T7对电容 C充电， 上拉节 点 PU处的电压将迅速升起。
在求值阶段（即， 图 7中的阶段② ), 驱动信号输入端 OUT ( n-1 )输入 的信号为第一低电平 VGL1 , 第二时钟信号输入端 CKB输入的第二时钟信 号为第二低电平 VGL2, 因此， 第一开关晶体管 T8和第二开关晶体管 T7都 是关闭的。 由于第一开关晶体管 T8和第二开关晶体管 T7是关闭的， 所以， 第一时钟信号输入端 CK输入的第一时钟信号为高电平 VGH, 此时第一时 钟信号可以将上拉节点 PU的电位通过电容 C耦合到较高的电位， 而不会漏 电。
应当注意的是，如果第一开关晶体管 T8和第二开关晶体管 T7为耗尽型 晶体管，那么第一低电平 VGL1与第二低电平 VGL2的差值大于第一开关晶 体管 T8的临界电压的绝对值（即， VGLl-VGL2 > IVtht8l ), 以确保第一开关 晶体管 T8可以在求值阶段正常关闭。
为了使所述移位寄存单元输出的信号更加稳定， 优选地， 所述移位控制 单元还可以包括下拉单元 12和下拉晶体管 T6, 下拉晶体管 T6的栅极与下 拉单元 12相连， 下拉晶体管 T6的源极与第二低电平输出端（第二低电平输 出端可以向下拉晶体管 T6的源极输出第二低电平 VGL2 )相连， 下拉单元 12可以在求值阶段（即， 图 7中的阶段②）将下拉晶体管 T6关闭， 并且在 复位阶段（即， 图 7中的阶段③）和非工作阶段（即， 图 7中阶段③右侧的 部分 )将下拉晶体管 T6开启，使得下拉晶体管 T6能够在所述复位阶段和所 述非工作阶段将上拉节点 PU的电平拉低至所述第二低电平。
在求值阶段， 下拉晶体管 T6断开， 可以防止上拉节点 PU漏电。 在复 位阶段和非工作阶段， 下拉晶体管 T6开启， 可以对上拉节点 PU进行放电， 从而可以确保驱动信号输出端 OUT ( n )在复位阶段和非工作阶段输出低电 平。
在本发明实施例中， 对下拉单元 12的具体结构并没有特殊要求， 只要 可以在求值阶段将下拉晶体管 T6关闭， 并且在复位阶段和非工作阶段将下 拉晶体管 T6开启即可。
作为本发明的优选实施方式， 如图 6所示， 下拉单元 12包括第一下拉 控制晶体管 T5和第二下拉控制晶体管 T3, 第一下拉控制晶体管 T5的栅极 与上拉节点 PU相连， 第一下拉控制晶体管 T5的源极与第三低电平输出端 (第三低电平输出端可以向第一下拉控制晶体管 T5的源极输出第三低电平 VGL3 )连接， 第一下拉晶体管 T5的漏极与下拉晶体管 T6的栅极连接， 第 二下拉控制晶体管 Τ3的栅极与第二时钟信号输入端 CKB相连，第二下拉控 制晶体管 Τ3的漏极与高电平输出端 （高电平输出端可以向第二下拉控制晶 体管 Τ3的漏极输出高电平 VGH )连接， 第二下拉控制晶体管 Τ3的源极与 下拉晶体管 Τ6的栅极连接， 第二低电平 VGL2与第三低电平 VGL3的差值 大于所述下拉晶体管 Τ6的临界电压 （即， VGL2-VGL3 > IVthT6l )。
在求值阶段， 驱动信号输入端 OUT ( n-1 )输入的信号为第一低电平 VGL1 , 第二时钟信号输入端 CKB输入的第二时钟信号跳变为第二低电平 VGL2, 第一时钟信号输入端 CK输入的第一时钟信号跳变为高电平 VGH。 输出下拉晶体管 T2关闭。 由于上拉节点 PU被耦合到较高的电平， 因此第 一下拉控制晶体管 T5开启， 第二下拉控制晶体管 T3关闭，从而将下拉晶体 管 T6的栅极电压下拉到第三低电平 VGL3 , 使下拉晶体管 T6完全关闭。
在本发明实施例中， 可以将下拉晶体管 T6的栅极称之为下拉节点 PD。 在本发明实施例中，第二时钟信号输入端 CKB直接控制输出下拉晶体管 T2, 所以下拉节点 PD对驱动信号输出端 OUT ( n )并没有影响。
在复位阶段， 第二时钟信号输入端 CKB输入的第二时钟信号跳变为高 电平 VGH, 驱动信号输入端 OUT ( n-1 )保持第一低电平 VGL1 , 第一时钟 信号输入端 CK输入的第一时钟信号跳变为第二低电平 VGL2。 输出下拉晶 体管 T2开启， 驱动信号输出端 OUT ( n )被下拉为第一低电平 VGL1 , 驱动 信号输出端 OUT ( n ) 的电压跳变通过电容 C的耦合作用将上拉节点 PU的 电位迅速下拉到较求值阶段低的电位， 当然该电位还是足以使得驱动晶体管 T1开启，只是此时第一时钟信号输入端 CK输入的第一时钟信号为第二低电 平 VGL2, 对驱动信号输出端 OUT ( n ) 没有上拉作用。 由于上拉节点 PU 电位降低， 第一下拉控制晶体管 T5的栅极电位也降低， 但仍然处于一定的 开启状态， 只是这种开启通过的电流较小， 对下拉节点 PD点的下拉作用较 弱。第二下拉控制晶体管 T3的栅极为第二时钟信号输入端 CKB输入的高电 平 VGH, 因此第二下拉控制晶体管 T3完全开启， 虽然第一下拉控制晶体管 T5并未关闭， 但由于下拉作用减弱， 因此， 下拉节点 PD仍然会被通过第二 下拉控制晶体管 T3的高电平上拉到开启， 因此下拉晶体管 T6开启，使上拉 节点 PU的电位被迅速拉低， 下拉节点 PD电位的迅速下拉又会进一步关闭 第一下拉控制晶体管 T5,这种相互作用会使得上拉节点 PU的电位下降更快， 使得驱动晶体管 T1在第一时钟信号输入端 CK的下一个高电平输入之前， 使得上拉节点 PU的电位下降到第二低电平 VGL2, 从而彻底的关闭驱动晶 体管 Tl。
在非工作阶段， 对于下拉节点 PD, 除了第二时钟信号输入端 CKB控制 的上拉电平外， 还有第一时钟信号输入端 CK控制的下拉电平。 仅从功能上 来说， 在移位寄存单元的非工作阶段， 下拉节点 PD的下拉没有任何意义， 此处采用下拉电平除了在工作阶段增加下拉能力快速关闭下拉晶体管 Τ6 夕卜， 另一个功能在于， 使得下拉晶体管 Τ6的栅极， 即下拉节点 PD可以处 在交变电压状态， 避免长时间的直流偏压导致下拉晶体管 Τ6的传输曲线向 右偏移老化失效， 进而提高整个移位寄存单元的使用寿命。
为了在求值阶段确保下拉晶体管 Τ6可以更加迅速的关闭， 优选地， 下 拉单元 12还可以包括第三下拉控制晶体管 Τ4, 该第三下拉控制晶体管 Τ4 的栅极与第一时钟信号输入端 CK相连， 第三下拉控制晶体管 Τ4的源极与 第三低电平输出端相连， 第三下拉控制晶体管 Τ4的漏极与第二下拉控制晶 体管 Τ3的源极相连。
在本发明实施例所述的移位寄存单元中， 驱动晶体管 Tl、 输出下拉晶 体管 Τ2、 所述第一开关晶体管 Τ8、 所述第二开关晶体管 Τ7、 所述下拉晶体 管 Τ6、 所述第一下拉控制晶体管 Τ5、 第二下拉控制晶体管 Τ3和第三下拉 控制晶体管 Τ4中的至少一者为耗尽型晶体管。
下面将参考图 6中的具体实施方式介绍当驱动晶体管 Tl、 输出下拉晶 体管 Τ2、 所述第一开关晶体管 Τ8、 所述第二开关晶体管 Τ7、 所述下拉晶体 管 Τ6、 所述第一下拉控制晶体管 Τ5、 第二下拉控制晶体管 Τ3和第三下拉 控制晶体管 Τ4全部为耗尽型晶体管， 且上述晶体管的临界电压相等时， 上 述各个晶体管的工作原理。 优选地， 驱动晶体管 τΐ、 输出下拉晶体管 Τ2、 所述第一开关晶体管 Τ8、 所述第二开关晶体管 Τ7、 所述下拉晶体管 Τ6、 所 述第一下拉控制晶体管 Τ5、 第二下拉控制晶体管 Τ3和第三下拉控制晶体管 Τ4全部为氧化物晶体管。
预充电阶段（即， 图 7中的阶段① ): 第二时钟信号输入端 CKB输入的 第二时钟信号和驱动信号输入端 OUT ( n-1 )输入的信号为高电平 VGH, 第 一时钟信号输入端 CK输入的第一时钟信号为第二低电平 VGL2, 因此输出 下拉晶体管 T2、 第二下拉控制晶体管 Τ3、 第二开关晶体管 Τ7和第一开关 晶体管 T8开启。
由于第三下拉控制晶体管 Τ4的源极电压为第三低电平 VGL3, 而第三 下拉控制晶体管 Τ4的栅极电压为第一时钟信号输入端 CK输入的第二低电 平 VGL2, 因此第三下拉控制晶体管 Τ4并没有完全关闭而是有一定的漏电 存在。
第二开关晶体管 Τ7和第一开关晶体管 Τ8开启， 驱动信号输入端 OUT ( n-1 )通过第二开关晶体管 T7和第一开关晶体管 T8对电容 C充电， 上拉 节点 PU的电压将迅速升起， 使第一下拉控制晶体管 T5开启， 虽然第二下 拉控制晶体管 T3也开启，使得高电平输入端输入的高电平 VGH对下拉节点 PD有一定的上拉作用，但是由于第三下拉控制晶体管 T4的漏电和第一下拉 控制晶体管 T5的开启将会迅速的使下拉节点 PD的电位被第三低电平 VGL3 下拉下去。
虽然下拉晶体管 T6的栅极电位由于第二下拉控制晶体管 T3和第三下拉 控制晶体管 T4、 第二下拉控制晶体管 Τ5的共同作用不会完全下降到第三低 电平 VGL3而完全关闭， 但会使得下拉晶体管 Τ6的漏电流大大减小， 从而 使得上拉节点 PU的电位不至于被过度下拉，因此预充电阶段驱动晶体管 T1 仍然能够获得足够的开启电位。 因此在预充电阶段， 驱动信号输出端 OUT ( n )将会被第一时钟信号输入端 CK输入的第一时钟信号的低电平下拉， 同时输出下拉晶体管 T2的开启也会将输出端 OUT ( n ) 的电位下拉。
求值阶段（即， 图 7中的阶段② ): 驱动信号输入端 OUT ( n-1 )输入的 信号为第一低电平 VGL1 , 第二时钟信号输入端 CKB输入的第二时钟信号 跳变为第二低电平 VGL2, 第一时钟信号输入端 CK输入的第一时钟信号跳 变为高电平 VGH。
输出下拉晶体管 T2的源极为第一低电平 VGL1 ,输出下拉晶体管 T2的 栅极为第二时钟信号输入端 CKB输入的第二低电平 VGL2, 因此输出下拉 晶体管 T2关闭。第一开关晶体管 T8的源极电位为驱动信号输入端 OUT( n-1 ) 输入的第一低电平 VGL1 , 而第一开关晶体管 T8的栅极电位为第二时钟信 号输入端 CKB的第二时钟信号（即， 第二低电平 VGL2 ), 因此第一开关晶 体管 T8关闭。虽然第二时钟信号输入端 CKB输入的第二时钟信号为第二低 电平 VGL2, 但第二下拉控制晶体管 T3并未完全关闭， 而是有较小的漏电 流通过。 由于第一时钟信号输入端 CK输出的第一时钟信号 （高电平 VGH )通 过驱动晶体管 T1后，将上拉节点 PU的电位通过电容 C耦合到较高的电位， 因此第一下拉控制晶体管 T5充分开启，同时第三下拉控制晶体管 T4也开启， 虽然第二下拉控制晶体管 T3未完全关闭， 但下拉节点 PD的电位仍将被下 拉到第三低电平 VGL3 , 因此下拉晶体管 T6完全关闭， 这为上拉节点 PU保 存高电位进一步创造了条件， 驱动晶体管 T1的充分开启使得驱动信号输出 端 OUT ( n )端输出高电平 VGH。
复位阶段（即， 图 7中的阶段③）： 第二时钟信号输入端 CKB输入的第 二时钟信号跳变为高电平 VGH, 驱动信号输入端 OUT ( n-1 )输入的信号保 持第一低电平 VGL1。 第一时钟信号输入端 CK输入的第一时钟信号为第二 低电平 VGL2。 因此输出下拉晶体管 T2、 第二下拉控制晶体管 Τ3、 第二开 关晶体管 Τ7和第一开关晶体管 Τ8开启。
由于第三下拉控制晶体管 Τ4的源极电平为第三低电平 VGL3, 而第三 下拉控制晶体管 Τ4的栅极为第一时钟信号输入端 CK输入的第一时钟信号 (即， 第二低电平 VGL2 ), 因此第三下拉控制晶体管 Τ4并没有完全关闭而 是有一定的漏电存在。由于输出下拉晶体管 Τ2的开启，驱动信号输出端 OUT ( n )被下拉为第一低电平 VGL1 , 驱动信号输出端 OUT ( n )的电压跳变通 过电容 C的耦合作用将上拉节点 PU的电位迅速下拉到较求值阶段低的电 位， 当然该电位还是足以使得驱动晶体管 T1开启， 只是此时第一时钟信号 输入端 CK也为低电位， 对驱动信号输出端 OUT ( n ) 没有上拉作用。
由于上拉节点 PU电位的降低， 第一下拉控制晶体管 T5的栅极电位也 跟着下降， 但仍然处于一定的开启状态， 只是这种开启通过的电流较小， 对 下拉节点 PD的下拉作用减弱。 由于第二时钟信号输入端 CKB的高电平 VGH, 第二下拉控制晶体管 T3完全打开。 虽然第一下拉控制晶体管 T5并 未关闭， 但由于下拉作用减弱， 因此下拉节点 PD仍然会被通过第二下拉控 制晶体管 T3的高电平上拉到开启， 使得下拉晶体管 T6开启， 上拉节点 PU 的电位被迅速下拉， 而上拉节点 PU的迅速下拉又会进一步关闭第一下拉控 制晶体管 T5, 这种相互作用会使得上拉节点 PU的电位更快下降， 使得驱动 晶体管 T1在第一时钟信号输入端 CK的下一个高电平来之前， 使得上拉节 点 PU的电位下降到第二低电平 VGL2, 从而彻底的关闭驱动晶体管 Tl。
在图 6中所示的移位寄存单元中使用了三种不同的低电平（第一低电平 VGL1、第二低电平 VGL2和第三低电平 VGL3 ) ,可以使输出下拉晶体管 T2 的栅源电压为负值， 从而可以在求值阶段将输出下拉晶体管 T2完全关闭。 并且所述移位寄存单元还可以 4艮好的保持上拉节点 PU的电位， 使得驱动晶 体管 T1在非工作阶段完全关闭， 因此可以输出具有所需脉宽和所需电压的 信号。
作为本发明实施例的另外一个方面， 提供一种移位寄存器， 该移位寄存 器包括多级移位寄存单元， 其中， 所述移位寄存单元为本发明实施例所提供 的上述移位寄存单元， 下一级所述移位寄存单元的驱动信号输入端与上一级 所述移位寄存器的驱动信号输出端相连。 在本发明实施例中， n为正整数。
作为本发明实施例的再一个方面， 还提供一种显示装置， 其中， 该显示 装置包括本发明实施例所提供的上述移位寄存器。所述显示装置可以包括液 晶显示装置， 例如， 液晶面板、 液晶电视、 手机、 液晶显示器等。 出了液晶 显示装置外， 所述显示装置还可以包括有机发光显示器或者其他类型的显示 装置， 例如电子阅读器等。 所述移位寄存器可以作为显示装置的扫描电路或 者栅极驱动电路等， 以提供逐行扫描功能， 将扫描信号传送至显示区域。 例性实施方式， 然而本发明并不局限于此。 对于本领域内的普通技术人员而 言， 在不脱离本发明的精神和实质的情况下， 可以做出各种变型和改进， 这 些变型和改进也视为本发明的保护范围。

Claims

权 利 要 求 书
1、 一种移位寄存单元， 包括： 驱动信号输入端、 驱动信号输出端、 第 一时钟信号输入端、 第二时钟信号输入端、 驱动晶体管和输出下拉晶体管， 其中， 所述输出下拉晶体管的栅极与所述第二时钟信号输入端相连， 所述驱 动信号输入端输入的低电平为第一低电平， 所述输出下拉晶体管的源极与第 一低电平输出端连接，所述第一时钟信号输入端和所述第二时钟信号输入端 输入的低电平均为第二低电平， 所述第一低电平与所述第二低电平的差值大 于所述输出下拉晶体管的临界电压的绝对值，使得所述下拉晶体管能够在求 值阶段关闭。
2、 根据权利要求 1所述的移位寄存单元， 其中， 所述驱动晶体管的栅 极形成为上拉节点， 所述移位寄存单元还包括与所述上拉节点连接的开关单 元， 所述开关单元能够在预充电阶段将所述上拉节点与所述驱动信号输入端 导通， 以对与所述驱动晶体管并联的电容充电， 并且所述开关单元能够在求 值阶段将所述上拉节点与所述驱动信号输入端断开， 以防止所述上拉节点漏 电。
3、 根据权利要求 2所述的移位寄存单元， 其中， 所述开关单元包括第 一开关晶体管和第二开关晶体管， 所述第一开关晶体管的栅极与所述第二时 钟信号输入端相连， 所述第一开关晶体管的漏极与所述驱动信号输入端相 连， 所述第一开关晶体管的源极与所述第二开关晶体管的漏极相连， 所述第 二开关晶体管的栅极与所述驱动信号输入端相连，所述第二开关晶体管的源 极与所述上拉节点相连。
4、 根据权利要求 2或 3所述的移位寄存单元， 其中， 所述移位寄存单 元包括下拉单元和下拉晶体管， 所述下拉晶体管的栅极与所述下拉单元相 连， 所述下拉晶体管的源极与第二低电平输出端相连， 所述下拉单元能够在 求值阶段将所述下拉晶体管关闭， 并且在复位阶段和非工作阶段将所述下拉 晶体管开启，使得所述下拉晶体管能够在所述复位阶段和所述非工作阶段将 所述上拉节点的电平拉低至所述第二低电平。
5、 根据权利要求 4所述的移位寄存单元， 其中， 所述下拉单元包括第 一下拉控制晶体管和第二下拉控制晶体管， 所述第一下拉控制晶体管的栅极 与所述上拉节点相连，所述第一下拉控制晶体管的源极与第三低电平输出端 连接， 所述第一下拉控制晶体管的漏极与所述下拉晶体管的栅极连接， 所述 第二下拉控制晶体管的栅极与所述第二时钟信号输入端相连， 所述第二下拉 控制晶体管的漏极与高电平输出端连接， 所述第二下拉控制晶体管的源极与 所述下拉晶体管的栅极连接， 所述第二低电平与所述第三低电平的差值大于 所述下拉晶体管的临界电压。
6、 根据权利要求 5所述的移位寄存器单元， 其中， 所述下拉单元还包 括第三下拉控制晶体管， 该第三下拉控制晶体管的栅极与所述第一时钟信号 输入端相连， 所述第三下拉控制晶体管的源极与所述第三低电平输出端相 连， 所述第三下拉控制晶体管的漏极与所述第二下拉控制晶体管的源极相 连。
7、 根据权利要求 6所述的移位寄存器单元， 其中， 所述驱动晶体管、 所述输出下拉晶体管、 所述第一开关晶体管、 所述第二开关晶体管、 所述下 拉晶体管、 所述第一下拉控制晶体管、 所述第二下拉控制晶体管和所述第三 下拉控制晶体管中的至少一者为耗尽型晶体管。
8、 一种移位寄存器， 该移位寄存器包括多级移位寄存单元， 其中， 所 述移位寄存单元为权利要求 1至 7中任意一项所述的移位寄存单元， 下一级 所述移位寄存单元的驱动信号输入端与上一级所述移位寄存器的驱动信号 输出端相连。
9、 一种显示装置， 包括权利要求 8所述的移位寄存器。
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