WO2021226870A1 - 显示基板、制作方法和显示装置 - Google Patents

显示基板、制作方法和显示装置 Download PDF

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Publication number
WO2021226870A1
WO2021226870A1 PCT/CN2020/090003 CN2020090003W WO2021226870A1 WO 2021226870 A1 WO2021226870 A1 WO 2021226870A1 CN 2020090003 W CN2020090003 W CN 2020090003W WO 2021226870 A1 WO2021226870 A1 WO 2021226870A1
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WO
WIPO (PCT)
Prior art keywords
signal line
voltage signal
output
node control
transistor
Prior art date
Application number
PCT/CN2020/090003
Other languages
English (en)
French (fr)
Inventor
王领然
颜俊
高文辉
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/090003 priority Critical patent/WO2021226870A1/zh
Priority to US17/280,160 priority patent/US11373601B2/en
Priority to EP20897619.1A priority patent/EP4152305A4/en
Priority to CN202080000729.2A priority patent/CN114144828B/zh
Publication of WO2021226870A1 publication Critical patent/WO2021226870A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a manufacturing method, and a display device.
  • AMOLED Active-Matrix Organic Light-Emitting Diode
  • the AMOLED display panel includes a pixel circuit located in the display area and a scan drive circuit located in the edge area.
  • the pixel circuit includes a plurality of sub-pixel circuits distributed in an array.
  • the scan drive circuit includes a plurality of shift register units. The unit is used to provide a light-emitting control signal for the corresponding sub-pixel circuit.
  • the transistor electrically connected to the gate and the node may leak due to the excessive change in the potential of the node, which may cause the output error of the shift register unit.
  • the main purpose of the present disclosure is to provide a display substrate, a manufacturing method, and a display device.
  • an embodiment of the present disclosure provides a display substrate, including a scan driving circuit disposed on a substrate, the scan driving circuit includes a plurality of shift register units, at least one of the plurality of shift register units
  • the shift register unit includes an output circuit, a first tank circuit, and a first leakage prevention circuit;
  • the scan driving circuit also includes a first voltage signal line and a second voltage signal line; the first voltage signal line is used to provide a first voltage signal line A voltage, the second voltage signal line is used to provide a second voltage;
  • the first voltage signal line is located on a side of the second voltage signal line away from the display area;
  • the output circuit is respectively coupled to the first voltage signal line and the second voltage signal line
  • the first tank circuit is respectively coupled to the output circuit and the second voltage signal line
  • the The first anti-leakage circuit is respectively coupled to the output circuit and the first voltage signal line
  • the output circuit is arranged between the first voltage signal line and the second voltage signal line;
  • the orthographic projection of the first tank circuit on the substrate partially overlaps the orthographic projection of the second voltage signal line on the substrate;
  • the first anti-leakage circuit is arranged on a side of the first voltage signal line away from the second voltage signal line.
  • the scan driving circuit further includes a third voltage signal line and a fourth voltage signal line, the fourth voltage signal line is used to provide a first voltage; the third voltage signal line is used to provide a second voltage The third voltage signal line is located on the side of the first voltage signal line away from the display area, and the fourth voltage signal line is located on the side of the third voltage signal line away from the display area;
  • the orthographic projection of the first tank circuit on the substrate partially overlaps the orthographic projection of the fourth voltage signal line on the substrate;
  • the first anti-leakage circuit is located between the first voltage signal line and the third voltage signal line.
  • the first voltage signal line, the second voltage signal line, the third voltage signal line, and the fourth voltage signal line all extend in a first direction.
  • the at least one shift register unit further includes a reset control circuit; the reset control circuit is coupled to the output circuit;
  • the reset control circuit is provided between the first voltage signal line and the second voltage signal line.
  • the at least one shift register unit further includes a second node control circuit, a second energy storage circuit, and a second leakage prevention circuit;
  • the second node control circuit is coupled to a second tank circuit; the second anti-leakage circuit is respectively coupled to the first anti-leakage circuit and the first voltage signal line;
  • the second node control circuit is arranged on a side of the first voltage signal line away from the second voltage signal line;
  • the orthographic projection of the second tank circuit on the substrate partially overlaps the orthographic projection of the first voltage signal line on the substrate;
  • the second anti-leakage circuit is located on a side of the first voltage signal line away from the second voltage signal line.
  • the at least one shift register unit further includes a third node control circuit; the third node control circuit is located on a side of the first voltage signal line away from the second voltage signal line.
  • the scan driving circuit further includes a third voltage signal line; the third voltage signal line is located on a side of the first voltage signal line away from the display area; the third node control circuit and the first voltage signal line Three-voltage signal line coupling;
  • the third node control circuit is located between the first voltage signal line and the third voltage signal line.
  • the at least one shift register unit further includes a fifth node control circuit;
  • the scan driving circuit further includes a third voltage signal line and a fourth voltage signal line;
  • the third voltage signal line is located in the first A voltage signal line on a side away from the display area, and the fourth voltage signal line is located on a side of the third voltage signal line away from the display area;
  • the fifth node control circuit is respectively coupled to the fourth voltage signal line and the first tank circuit
  • the fifth node control circuit is located between the third voltage signal line and the fourth voltage signal line.
  • the scan driving circuit further includes a first clock signal line and a second clock signal line that are arranged on the fourth voltage signal line away from the display area;
  • the first tank circuit is coupled to the first clock signal line
  • Both the first clock signal line and the second clock signal line extend in a first direction.
  • the second voltage signal line, the first voltage signal line, the third voltage signal line, the fourth voltage signal line, and the second clock signal Line and the first clock signal line are arranged in sequence; or,
  • the second voltage signal line, the first voltage signal line, the third voltage signal line, the fourth voltage signal line, the first clock signal line, and the The second clock signal lines are arranged in sequence.
  • the display substrate further includes a plurality of rows of pixel circuits arranged in a display area on the base;
  • the pixel circuit includes a light-emitting control terminal;
  • the shift register unit further includes a signal output line;
  • the shift register unit and the row pixel circuit have a one-to-one correspondence
  • the signal output line of the shift register unit is coupled to the light emission control end of the corresponding row of pixel circuits, and is used to provide light emission control signals for the light emission control end of the corresponding row of pixel circuits.
  • the signal output line includes a first output line part and a second output line part
  • the first output line part is located between the output circuit and the second voltage signal line;
  • the first output line part is coupled to the second output line part, the first output line part extends in a first direction, and the second output line part extends in a second direction.
  • the second direction intersects;
  • the second output line partially extends to the display area to provide light emission control signals for a row of pixel circuits located in the display area.
  • the output circuit includes an output transistor and an output reset transistor
  • the output reset transistor and the output transistor are arranged along a first direction;
  • the first electrode of the output reset transistor is coupled to the second voltage signal line, and the first electrode of the output transistor is coupled to the first voltage signal line;
  • Both the second electrode of the output transistor and the second electrode of the output reset transistor are coupled to a signal output line included in the at least one shift register unit.
  • the width of the active layer of the output reset transistor in the second direction is smaller than the width of the active layer of the output transistor in the second direction
  • the first direction intersects the second direction.
  • the at least one shift register unit further includes a reset control circuit;
  • the reset control circuit includes a reset control transistor;
  • the output circuit includes an output transistor and an output reset transistor;
  • the gate of the reset control transistor is coupled to the gate of the output transistor, the first electrode of the reset control transistor is coupled to the first electrode of the output reset transistor, and the second electrode of the reset control transistor It is coupled to the gate of the output reset transistor.
  • the reset control transistor is located between the output reset transistor and the first voltage signal line;
  • the reset control transistor includes a first active pattern, and the first active pattern extends in a first direction.
  • the first tank circuit includes an output reset capacitor; the output circuit includes an output reset transistor;
  • the orthographic projection of the second plate of the output reset capacitor on the substrate is within the orthographic projection of the first plate of the output reset capacitor on the substrate;
  • the orthographic projection of the second plate of the output reset capacitor on the substrate partially overlaps the orthographic projection of the second voltage signal line on the substrate;
  • the first plate of the output reset capacitor is coupled to the gate of the output reset transistor
  • the second plate of the output reset capacitor is coupled to the second voltage signal line through a plate connection via.
  • the first leakage prevention circuit includes a first control transistor;
  • the output circuit includes an output transistor;
  • the first control transistor is located on a side of the first voltage signal line away from the display area;
  • the first electrode of the first control transistor is coupled to the gate of the output transistor.
  • the at least one shift register unit further includes a second leakage prevention circuit;
  • the second leakage prevention circuit includes a second control transistor, and the first leakage prevention circuit includes a first control transistor;
  • the second control transistor is located on a side of the first voltage signal line away from the display area; the gate of the first control transistor and the gate of the second control transistor are coupled to each other;
  • the gate of the second control transistor is coupled to an electrode conductive connection part, and there is between an orthographic projection of the electrode conductive connection part on the substrate and an orthographic projection of the first voltage signal line on the substrate In the electrode overlap area, the electrode conductive connection portion is coupled to the first voltage signal line through an electrode connection via provided in the electrode overlap area.
  • the scan driving circuit further includes a third voltage signal line; the third voltage signal line is used to provide a second voltage; the at least one shift register unit further includes a third node control circuit; the first The three-node control circuit includes an input transistor, a first node control transistor, and a second node control transistor;
  • the active layer of the input transistor, the active layer of the first node control transistor, and the active layer of the second node control transistor are formed by a continuous second semiconductor layer;
  • the second semiconductor layer extends along the first direction
  • the active layer of the input transistor includes a first third conductive portion, a third channel portion, and a second third conductive portion sequentially arranged along a first direction;
  • the second third conductive part is multiplexed into the first fourth conductive part
  • the active layer of the first node control transistor includes a first fourth conductive portion, a fourth channel portion, and a second fourth conductive portion sequentially arranged along a first direction;
  • the second fourth conductive part is multiplexed into the first fifth conductive part
  • the active layer of the second node control transistor includes a first fifth conductive portion, a fifth channel portion, and a second fifth conductive portion sequentially arranged along the first direction;
  • the first electrode of the input transistor is coupled to the input terminal, and the first electrode of the second node control transistor is coupled to the third voltage signal line.
  • the input transistor, the first node control transistor, and the second node control transistor are located between the third voltage signal line and the first voltage signal line;
  • the third voltage signal line extends along a first direction, and the third voltage signal line is located on a side of the first voltage signal line away from the display area.
  • the at least one shift register unit further includes a second tank circuit and a second node control circuit; the second tank circuit includes a first capacitor, and the second node control circuit includes a third node control circuit.
  • the transistor and the fourth node control the transistor;
  • the active layer of the fourth node control transistor and the active layer of the third node control transistor are formed by a continuous third semiconductor layer; the third semiconductor layer extends along the first direction;
  • the active layer of the fourth node control transistor includes a first sixth conductive portion, a sixth channel portion, and a second sixth conductive portion sequentially arranged along the first direction;
  • the second sixth conductive part is multiplexed into the first seventh conductive part
  • the active layer of the third node control transistor includes a first seventh conductive portion, a seventh channel portion, and a second seventh conductive portion sequentially arranged along the first direction;
  • the gate of the fourth node control transistor is coupled to the gate of the first node control transistor, and the second electrode of the fourth node control transistor is coupled to the gate of the output reset transistor;
  • the gate of the third node control transistor is coupled to the first plate of the first capacitor, and the first electrode of the third node control transistor is coupled to the gate of the first node control transistor;
  • the second sixth conductive portion is used as the second electrode of the third node control transistor and the first electrode of the fourth node control transistor;
  • the first electrode of the fourth node control transistor is coupled to the second plate of the first capacitor.
  • the orthographic projection of the second electrode plate of the first capacitor on the substrate is within the orthographic projection of the first electrode plate of the first capacitor on the substrate;
  • the orthographic projection of the second plate of the first capacitor on the substrate partially overlaps the orthographic projection of the first voltage signal line on the substrate;
  • the third node control transistor and the fourth node control transistor are located on a side of the first capacitor away from the display area.
  • the at least one shift register unit further includes a fifth node control circuit, and the fifth node control circuit includes a fifth node control transistor;
  • the fifth node control transistor includes a second active pattern, and the second active pattern is a U-shaped structure
  • the second active pattern includes a first fifth node control channel portion, a second fifth node control channel portion, and a first first fifth node control channel portion coupled to the first fifth node control channel portion.
  • the gate of the fifth node control transistor includes a first gate pattern and a second gate pattern that are coupled to each other;
  • the first gate pattern corresponds to the first fifth node control channel portion, and the second gate pattern corresponds to the second fifth node control channel portion;
  • the first fifth node control conductive portion serves as the second electrode of the fifth node control transistor, and the second fifth node control conductive portion serves as the first electrode of the fifth node control transistor.
  • the at least one shift register unit further includes a fifth node control circuit, and the fifth node control circuit includes a sixth node control transistor;
  • the sixth node control transistor includes a third active pattern, and the third active pattern extends in a first direction.
  • the scan driving circuit further includes a fourth voltage signal line, the fourth voltage signal line is used to provide a first voltage; the first tank circuit includes an output capacitor;
  • the orthographic projection of the second plate of the output capacitor on the substrate is within the orthographic projection of the first plate of the output capacitor on the substrate;
  • the orthographic projection of the second plate of the output capacitor on the substrate partially overlaps the orthographic projection of the fourth voltage signal line on the substrate;
  • the width of the second plate of the output capacitor in the second direction is smaller than the first predetermined width, and the length of the second plate of the output capacitor in the first direction is greater than the first predetermined length;
  • the fourth voltage signal line extends along the first direction.
  • the first predetermined width is 20 microns
  • the first predetermined length is 22 microns.
  • the first tank circuit includes an output capacitor;
  • the at least one shift register unit further includes a fifth node control circuit, and the fifth node control circuit includes a fifth node control transistor and a sixth node control transistor ;
  • the fifth node control transistor and the sixth node control transistor are located between the third voltage signal line and the fourth voltage signal line;
  • the first electrode of the sixth node control transistor is coupled to the fourth voltage signal line, and the second electrode of the sixth node control transistor is coupled to the second electrode of the fifth node control transistor;
  • the first electrode of the fifth node control transistor is coupled to the gate of the sixth node control transistor
  • the orthographic projection of the second plate of the output capacitor on the substrate is within the orthographic projection of the first plate of the output capacitor on the substrate; the second plate of the output capacitor is on the substrate.
  • the orthographic projection of the fourth voltage signal line partially overlaps the orthographic projection of the fourth voltage signal line on the substrate;
  • the first plate of the output capacitor is coupled to the gate of the fifth node control transistor
  • the third voltage signal line and the fourth voltage signal line extend along a first direction.
  • the scan driving circuit further includes a first clock signal line and a second clock signal line that are arranged on the fourth voltage signal line away from the display area;
  • the second plate of the output capacitor is coupled to the first clock signal line
  • the gate of the sixth node control transistor is coupled to the second clock signal line
  • Both the first clock signal line and the second clock signal line extend in a first direction.
  • the scan driving circuit further includes a third voltage signal line, a fourth voltage signal line, a first clock signal line, and a second clock signal line;
  • the output circuit includes an output transistor and an output reset transistor;
  • the first An anti-leakage circuit includes a first control transistor;
  • the at least one shift register unit also includes a signal output line, a second control transistor, an input transistor, a first node control transistor, a second node control transistor, a third node control transistor, A fourth node control transistor, a fifth node control transistor, a sixth node control transistor, and a reset control transistor;
  • the reset control transistor, the output transistor, and the output reset transistor are arranged between the first voltage signal line and the second voltage signal line;
  • the first control transistor, the second control transistor, the input transistor, the first node control transistor, the second node control transistor, the third node control transistor, and the fourth node control transistor Located between the first voltage signal line and the third voltage signal line;
  • the fifth node control transistor and the sixth node control transistor are located between the third voltage signal line and the fourth voltage signal line;
  • the signal output line includes a first output line part and a second output line part
  • the first output line part is located between the output circuit and the second voltage signal line;
  • the first output line part is coupled to the second output line part, the first output line part extends in a first direction, and the second output line part extends in a second direction.
  • the second direction intersects;
  • the second output line partially extends to the display area.
  • the first energy storage circuit includes an output capacitor and an output reset capacitor;
  • the at least one shift register unit further includes a first capacitor;
  • the orthographic projection of the second plate of the first capacitor on the substrate partially overlaps the orthographic projection of the first voltage signal line and the substrate, or the first capacitor is located at the first voltage Between the signal line and the fourth node control transistor;
  • the orthographic projection of the second electrode plate of the first capacitor on the substrate is between the orthographic projection of the first electrode plate of the first capacitor on the substrate;
  • the orthographic projection of the second plate of the output reset capacitor on the substrate is within the orthographic projection of the first plate of the output reset capacitor on the substrate;
  • the orthographic projection of the second plate of the output reset capacitor on the substrate partially overlaps the orthographic projection of the second voltage signal line on the substrate;
  • the orthographic projection of the second plate of the output capacitor on the substrate is within the orthographic projection of the first plate of the output capacitor on the substrate;
  • the orthographic projection of the second plate of the output capacitor on the substrate partially overlaps the orthographic projection of the fourth voltage signal line on the substrate.
  • an embodiment of the present disclosure also provides a method for manufacturing a display substrate, the method for manufacturing the display substrate includes manufacturing a first voltage signal line, a second voltage signal line, and a scan driving circuit on a base;
  • the scan driving circuit includes a plurality of shift register units, and at least one shift register unit of the plurality of shift register units includes an output circuit, a first storage circuit, and a first leakage prevention circuit, and the output circuits are respectively Is coupled to the first voltage signal line and the second voltage signal line, the first tank circuit is respectively coupled to the output circuit and the second voltage signal line, the first anti-leakage circuit Coupled with the output circuit;
  • the manufacturing method of the display substrate further includes:
  • the first voltage signal line is used to provide a first voltage
  • the second voltage signal line is used to provide a second voltage
  • an embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate.
  • FIG. 1 is a structural diagram of at least one embodiment of at least one shift register unit in a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a structural diagram of at least one embodiment of the shift register unit
  • 3 is a structural diagram of at least one embodiment of the shift register unit
  • FIG. 5 is a structural diagram of at least one embodiment of the shift register unit
  • Fig. 6 is a circuit diagram of a specific embodiment of the shift register unit
  • FIG. 7 is a schematic diagram showing the gate, the first electrode, and the second electrode of each transistor on the basis of FIG. 6, and the first electrode plate and the second electrode plate of each capacitor;
  • FIG. 8 is a working timing diagram of the specific embodiment of the shift register unit shown in FIG. 6;
  • FIG. 9 is a schematic diagram of area division of a display substrate according to at least one embodiment of the present disclosure.
  • 10A is a schematic diagram of the connection relationship between the scan driving circuit and the pixel circuit included in the display substrate according to at least one embodiment of the present disclosure
  • 10B is a schematic diagram of a layout of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of another layout of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of an active layer in a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a first gate metal layer in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 14 is a schematic diagram of a second gate metal layer in a display substrate provided by at least one embodiment of the present disclosure.
  • 15 is a schematic diagram of a via used in a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram of the source and drain metal layers in the display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate includes a scan driving circuit disposed on a substrate, and the scan driving circuit includes a plurality of shift register units.
  • At least one embodiment of at least one shift register unit in the display substrate may include a signal output line E0, an output circuit O1, a first energy storage circuit 11, and a first anti-leakage circuit. Circuit 12;
  • the output circuit O1 is used to control the signal output line E0 to be connected to the first voltage V1 under the control of the potential of the first node N1, and to control the signal output line to be connected to the first voltage V1 under the control of the potential of the second node N2
  • the first energy storage circuit 11 is respectively coupled to the first node N1 and the second node N2 for storing electric energy
  • the first anti-leakage circuit 12 is coupled to the first node N1, and is used to control the absolute value of the change in the potential of the first node N1 to be smaller than the first node N1 when the potential of the first node N1 changes.
  • the predetermined amount of voltage change is used to control the absolute value of the change in the potential of the first node N1 to be smaller than the first node N1 when the potential of the first node N1 changes. The predetermined amount of voltage change.
  • the first anti-leakage circuit 12 can be used to control the first node N1 when the potential of the first node N1 changes.
  • the absolute value of the change in the potential of is smaller than the first predetermined change in voltage, so as to prevent the potential change of the first node N1 from being too large to cause leakage of the output transistor included in the output circuit O1, resulting in an output error.
  • the first predetermined voltage change amount may be 1V, but is not limited to this.
  • the first voltage may be a low voltage VL, but is not limited to this.
  • the first leakage prevention circuit may include a first control transistor
  • the gate of the first control transistor is coupled to the first control voltage terminal, the first electrode of the first control transistor is coupled to the first node, and the second electrode of the first control transistor is coupled to the third Node coupling
  • the first control voltage terminal is used to provide a first control voltage so as to be able to control the first control transistor to turn on.
  • the first control voltage may be a low voltage VL, but it is not limited.
  • At least one embodiment of the shift register unit may further include a second node control circuit 13 , The second energy storage circuit 14 and the second anti-leakage circuit 15;
  • the second node control circuit 13 is respectively coupled to the first clock signal line CB, the fourth node N4, the second node N2, and the third node N3, and is used for the first clock signal and the third node N3 provided on the first clock signal line CB. Under the control of the potential of the fourth node N4, the potential of the second node N2 is controlled, and under the control of the potential of the third node N3, the second node N2 is controlled to be connected to the second voltage;
  • the second energy storage circuit 14 is coupled to the fourth node N4 for storing electric energy
  • the second anti-leakage circuit 15 is coupled to the fourth node N4, and is used to control the absolute value of the change in the potential of the fourth node N4 to be smaller than the second when the potential of the fourth node N4 changes.
  • the predetermined amount of voltage change is coupled to the fourth node N4, and is used to control the absolute value of the change in the potential of the fourth node N4 to be smaller than the second when the potential of the fourth node N4 changes. The predetermined amount of voltage change.
  • the second predetermined voltage change amount may be 1V, but is not limited to this.
  • the second voltage may be a high voltage Vh, but is not limited to this.
  • the embodiment of the shift register unit as shown in FIG. 2 adopts the second leakage prevention circuit 15, so that when the potential of the fourth node N4 changes, the absolute value of the change in the potential of the fourth node N4 can be controlled to be less than
  • the first predetermined voltage change amount is to avoid that the potential change amplitude of the fourth node N4 is too large to cause leakage of the transistor coupled to the gate of the shift register unit and the fourth node N4.
  • the second anti-leakage circuit may include a second control transistor
  • the gate of the second control transistor is coupled to the second control voltage terminal, the first electrode of the second control transistor is coupled to the fourth node, and the second electrode of the second control transistor is coupled to the fifth node. Node coupling
  • the second control voltage terminal is used to provide a second control voltage so as to be able to control the second control transistor to turn on.
  • the second control voltage may be a low voltage VL, but is not limited to this.
  • the shift register unit has a one-to-one correspondence with a row of pixel circuits located in the display area;
  • the shift register unit is coupled to the light emission control terminal of the row pixel circuit, and is used to provide a light emission control signal for the light emission control terminal of the row pixel circuit.
  • a first-level shift register unit is used to provide a single-row pixel circuit with a light-emitting control signal, which can realize PWM (pulse width modulation) fine dimming under low grayscale display conditions, and achieve a better display screen. And effect, reduce the low grayscale Mura (unevenness) of the screen.
  • the output circuit may include an output transistor and an output reset transistor
  • the gate of the output transistor is coupled to the first node, the first electrode of the output transistor is connected to a first voltage, and the second electrode of the output transistor is coupled to the signal output line;
  • the gate of the output reset transistor is coupled to the second node, the first electrode of the output reset transistor is connected to a second voltage, and the second electrode of the output reset transistor is coupled to the signal output line;
  • the first tank circuit may include an output reset capacitor and an output capacitor
  • the first plate of the output capacitor is coupled to the first node, and the second plate of the output capacitor is coupled to the first clock signal line;
  • the first plate of the output reset capacitor is coupled to the second node, and the second plate of the output reset capacitor is connected to a second voltage.
  • At least one embodiment of the shift register unit may further include a reset control circuit 16;
  • the reset control circuit 16 is respectively coupled to the first node N1 and the second node N2 for controlling the second node N2 to connect to the second voltage under the control of the potential of the first node N1.
  • the shift register unit adopts the multiplexing control circuit 16 to be able to control the second node N2 to connect to the second node N2 when the output transistor included in the output circuit is controlled by the first node N1 to be turned on Two voltages to control the output reset transistor included in the output circuit to turn off.
  • the reset control circuit may include a reset control transistor
  • the gate of the reset control transistor is coupled to the first node, the first electrode of the reset control transistor is connected to a second voltage, and the second electrode of the reset control transistor is coupled to the second node.
  • At least one embodiment of the shift register unit may further include a third node control circuit 17;
  • the third node control circuit 17 is respectively coupled to the input terminal E1, the second clock signal line CK, the third node N3, the fifth node N5, and the first clock signal line CB, and is used to provide data on the second clock signal line CK. Under the control of the second clock signal, the input terminal E1 is controlled to communicate with the third node N3, and the potential of the fifth node N5 and the first clock signal provided by the first clock signal line CB are controlled Next, controlling the third node N3 to connect to the second voltage;
  • the first clock signal line CB is used to provide the first clock signal
  • the second clock signal line CK is used to provide the second clock signal.
  • the shift register unit may further include a third node control circuit 17 for controlling the potential of the third node N3.
  • the third node control circuit may include an input transistor, a first node control transistor, and a second node control transistor, where:
  • a gate of the input transistor is coupled to a second clock signal line, a first electrode of the input transistor is coupled to the input terminal, and a second electrode of the input transistor is coupled to the third node;
  • the gate of the second node control transistor is coupled to the fifth node, and the first electrode of the second node control transistor is connected to a second voltage;
  • the gate of the first node control transistor is coupled to the first clock signal line, the first electrode of the first node control transistor is coupled to the second electrode of the second node control transistor, and the first node The second electrode of a node control transistor is coupled to the third node.
  • At least one embodiment of the shift register unit may further include a fifth node control Circuit 18;
  • the fifth node control circuit 18 is respectively coupled to the second clock signal line CK, the fifth node N5, and the third node N3 for controlling the fifth node N5 to connect to the first voltage under the control of the second clock signal , And under the control of the potential of the third node N3, controlling the communication between the fifth node N5 and the second clock signal line CK;
  • the second clock signal line CK is used to provide the second clock signal.
  • the shift register unit may use the fifth node control circuit 18 to control the potential of the fifth node N5.
  • the second node control circuit may include a third node control transistor and a fourth node control transistor; the second tank circuit includes a first capacitor;
  • the gate of the third node control transistor is coupled to the fourth node, and the first electrode of the third node control transistor is coupled to the first clock signal line;
  • the gate of the fourth node control transistor is coupled to the first clock signal line, the first electrode of the fourth node control transistor is coupled to the second electrode of the third node control transistor, and the first The second electrode of the four-node control transistor is coupled to the second node;
  • the first plate of the first capacitor is coupled to the fourth node, and the second plate of the first capacitor is coupled to the second electrode of the third node control transistor.
  • the fifth node control circuit may include a fifth node control transistor and a sixth node control transistor;
  • the gate of the fifth node control transistor is coupled to the third node, the first electrode of the fifth node control transistor is coupled to the second clock signal line, and the fifth node controls the second clock signal line of the transistor. Two electrodes are coupled to the fifth node;
  • the gate of the sixth node control transistor is coupled to the second clock signal line, the first electrode of the sixth node control transistor is connected to a first voltage, and the second electrode of the sixth node control transistor is connected to the The fifth node is coupled.
  • a specific embodiment of the shift register unit may include a signal output line E0, an output circuit O1, a first tank circuit 11, a first anti-leakage circuit 12, a second node control circuit 13, and a second node control circuit.
  • the first anti-leakage circuit 12 includes a first control transistor T12;
  • the gate of the first control transistor T12 is connected to a low voltage VL, the first electrode of the first control transistor T12 is coupled to the first node N1, and the second electrode of the first control transistor T12 is connected to the first node N1.
  • the second anti-leakage circuit 15 includes a second control transistor T11;
  • the gate of the second control transistor T11 is connected to a low voltage VL, the first electrode of the second control transistor T11 is coupled to the fourth node N4, and the second electrode of the second control transistor T11 is connected to the fourth node N4.
  • the output circuit O1 includes an output transistor T10 and an output reset transistor T9;
  • the gate of the output transistor T10 is coupled to the first node N1, the first electrode of the output transistor T10 is connected to a low voltage VL, and the second electrode of the output transistor T10 is coupled to the signal output line E0 catch;
  • the gate of the output reset transistor T9 is coupled to the second node N2, the first electrode of the output reset transistor T9 is connected to a high voltage Vh, and the second electrode of the output reset transistor T9 is connected to the signal output Line E0 is coupled;
  • the first tank circuit 11 includes an output reset capacitor C3 and an output capacitor C2;
  • the first plate of the output capacitor C2 is coupled to the first node N1, and the second plate of the output capacitor C2 is coupled to the first clock signal line CB;
  • the first plate of the output reset capacitor C3 is coupled to the second node N2, and the second plate of the output reset capacitor C3 is connected to a high voltage Vh;
  • the reset control circuit 16 includes a reset control transistor T8;
  • the gate of the reset control transistor T8 is coupled to the first node N1, the first electrode of the reset control transistor T8 is connected to the high voltage Vh, and the second electrode of the reset control transistor T8 is connected to the second node N1.
  • Node N2 is coupled;
  • the third node control circuit 17 includes an input transistor T1, a first node control transistor T4, and a second node control transistor T5, wherein,
  • the gate of the input transistor T1 is coupled to the second clock signal line CK, the first electrode of the input transistor T1 is coupled to the input terminal E1, and the second electrode of the input transistor T1 is coupled to the third clock signal line CK.
  • Node N3 is coupled;
  • the gate of the second node control transistor T5 is coupled to the fifth node N5, and the first electrode of the second node control transistor T5 is connected to a high voltage Vh;
  • the gate of the first node control transistor T4 is coupled to the first clock signal line CB, and the first electrode of the first node control transistor T4 is coupled to the second electrode of the second node control transistor T5 , The second electrode of the first node control transistor T4 is coupled to the third node N3;
  • the second node control circuit 13 includes a third node control transistor T6 and a fourth node control transistor T7; the second tank circuit 14 includes a first capacitor C1;
  • the gate of the third node control transistor T6 is coupled to the fourth node N4, and the first electrode of the third node control transistor T6 is coupled to the first clock signal line CB;
  • the gate of the fourth node control transistor T7 is coupled to the first clock signal line CB, and the first electrode of the fourth node control transistor T7 is coupled to the second electrode of the third node control transistor T6 , The second electrode of the fourth node control transistor T7 is coupled to the second node N2;
  • the first plate of the first capacitor C1 is coupled to the fourth node N4, and the second plate of the first capacitor C1 is coupled to the second electrode of the third node control transistor T6;
  • the fifth node control circuit 18 includes a fifth node control transistor T2 and a sixth node control transistor T3;
  • the gate of the fifth node control transistor T2 is coupled to the third node N3, the first electrode of the fifth node control transistor T2 is coupled to the second clock signal line CK, and the fifth node The second electrode of the control transistor T2 is coupled to the fifth node N5;
  • the gate of the sixth node control transistor T3 is coupled to the second clock signal line CK, the first electrode of the sixth node control transistor T3 is connected to the low voltage VL, and the sixth node controls the transistor T3
  • the second electrode is coupled to the fifth node N5.
  • the first control voltage terminal and the second control voltage terminal provide a low voltage VL, the first voltage is a low voltage VL, and the second voltage is a high voltage Vh, but not This is limited.
  • all the transistors are p-type transistors, but not limited to this.
  • the embodiment of the shift register unit shown in FIG. 6 may be the shift register unit in the light emission control scan driving circuit, but it is not limited to this.
  • Fig. 7 shows the first electrode of each transistor, the second electrode of each transistor, the gate of each transistor, the first plate of each capacitor, and the second plate of each capacitor on the basis of Fig. 6.
  • the gate labeled G1 is the gate of T1
  • the first electrode labeled S1 is the first electrode of T1
  • the second electrode labeled D1 is the second electrode of T1
  • the gate labeled G2 is the gate of T2, labeled S2
  • G4 is the gate of T4, S4 is the first electrode of T4, and the second electrode of T4 is D4
  • the gate of G5 is T5, and the gate of S5 is T5
  • the first electrode, labeled D5 is the second electrode of T5
  • labeled G6 is the gate of T6, labeled S6 is the first electrode of T6, and labeled D6 is the second electrode of T6;
  • labeled G7 Is the grid of T7, the first electrode of T7 is labele
  • the first electrode of the transistor may be a source, and the second electrode of the transistor may be a drain; or, the first electrode of the transistor may be a drain, and the second electrode of the transistor may be a source.
  • E1 and CK provide high level
  • CB provides low level
  • T1, T2 and T3 are off
  • the potential of N5 remains low
  • T4, T5 and T6 are on
  • the potential of N3 is high.
  • the potential of the first electrode of the fourth node control transistor T7 changes from high level to low level, T7 is turned on, T8 is turned off, the potential of N2 is low, T9 is turned on, and E0 outputs a high level; T12 is turned on , T10 ends;
  • E1 and CB all provide high level
  • CK provides low level
  • T1 and T3 are open
  • the electric potential of N3 is high
  • the electric potential of N5 is low
  • T2 and T4 are cut off
  • T5 and T6 is turned on
  • the potential of the first electrode of the fourth node control transistor T7 is changed from the low level to the high level in the previous time period
  • T7 is turned off
  • the potential of N2 is maintained at a low level due to the discharge of C3, and T9 is turned on
  • T12 is on
  • T8 and T10 are off
  • both E1 and CB provide low level
  • CK provides high level
  • T1 and T3 are off
  • the potential of N3 is high
  • T2 is off
  • the potential of N5 is maintained at low level
  • T11, T4 , T5 and T6 are turned on
  • the potential of the first electrode of the fourth node control transistor T7 jumps to a low level
  • T7 is turned on
  • the potential of N2 is low
  • T9 is turned on
  • E0 outputs a high level
  • T12 is turned on, End of T8 and T10;
  • E1 and CK provide low level
  • CB provides high level
  • T1, T2, T3, T11 and T12 are all turned on
  • the potential of N3 and N5 are both low
  • T4 is turned off.
  • T5 and T6 are turned on, the potential of the first electrode of the fourth node control transistor T7 becomes high, T7 is turned off, T8 is turned on, the potential of N2 becomes high, T9 is turned off, T10 is turned on, and E0 outputs low power. flat;
  • both E1 and CB provide a low level
  • CK provides a high level
  • T1 and T3 are off
  • the potential of N3 is maintained at a low level
  • T2 is turned on
  • the potential of N5 is at a high level
  • T11, T12 , T4 and T5 are turned on
  • T6 is turned off
  • the potential of the first electrode of the fourth node control transistor T7 is high
  • T7 and T8 are turned on
  • the potential of N2 is high
  • T9 is turned off
  • T10 is turned on
  • the output of E0 is low.
  • both E1 and CK provide low level
  • CB provides high level
  • T1, T2, T3, T11, T12 and T5 are all turned on
  • the potential of N3 and N5 are low
  • T4 is turned off
  • T5 and T6 are turned on
  • the fourth node controls the potential of the first electrode of the transistor T7 to be high
  • T7 is turned off
  • T8 is turned on
  • node N4 is high
  • T9 is turned off
  • T10 is turned on
  • the output of E0 is low ;
  • E1 and CB provide low level
  • CK provides high level
  • T1 and T3 are off
  • the potential of N3 is maintained at low level
  • T2 is turned on
  • the potential of N5 is high
  • T4 is turned on.
  • T5 and T6 are turned off
  • the potential of the first electrode of the fourth node control transistor T7 is maintained at a high level
  • T11, T12, T7 and T8 are turned on
  • the potential of N2 is at a high level
  • T9 is turned off
  • T10 is turned on
  • E0 is output Low level
  • T8 continues to be turned on, T9 is turned off, T1 periodically charges C2, the potential of N3 remains low, and T10 continues to turn on, so that E0 outputs a low level until the next frame of input signal The pulse enters.
  • the scan driving circuit includes multiple stages of the above-mentioned shift register units.
  • the scan driving circuit is usually designed to be arranged on both sides of the pixel circuit in the display area.
  • the scan driving circuit includes a lot of capacitors, thin film transistors, and signal lines, which takes up a lot of space. Therefore, it is necessary to reasonably design the placement position of the device and the common signal wiring to reduce the space occupied by the scan driving circuit and facilitate the narrowing of the display frame.
  • the label J1 is the display substrate
  • the label A0 is the display area
  • the label B1 is the first edge area
  • the label B2 is the second edge area.
  • the display area A0 of the display substrate J1 may be provided with a plurality of light-emitting control lines, a plurality of gate lines, and a plurality of data lines, and a plurality of sub-pixels defined by the intersection of the plurality of gate lines and the plurality of data lines ;
  • a scan driving circuit may be provided in the first edge area B1 and/or the second edge area B2, and the scan driving circuit includes a plurality of shift register units;
  • the multiple shift register units included in the scan driving circuit correspond to the multiple light-emitting control lines one-to-one, and the signal output line of each shift register unit is coupled to the corresponding light-emitting control line for corresponding The light-emitting control line provides light-emitting control signals.
  • one of the light-emitting control lines is coupled to the light-emitting control end of the pixel circuit of the corresponding row.
  • the display substrate further includes a plurality of rows of pixel circuits arranged on the base; the pixel circuit includes a light-emitting control terminal;
  • the shift register unit included in the scan driving circuit corresponds to the row pixel circuit one-to-one
  • the signal output line of the shift register unit is coupled to the light emission control end of the corresponding row of pixel circuits, and is used to provide light emission control signals for the light emission control end of the corresponding row of pixel circuits.
  • the pixel circuit may be disposed in the display area of the display substrate, and the scan driving circuit may be disposed in the edge area of the display substrate.
  • Y1 is a scan drive circuit
  • Y11 is a first stage shift register unit included in the scan drive circuit Y1
  • Y12 is a second stage included in the scan drive circuit Y1 Shift register unit
  • Y1N-1 is the N-1th stage shift register unit included in the scan drive circuit Y1
  • Y1N is the Nth stage shift register unit included in the scan drive circuit Y1
  • N is an integer greater than 3;
  • the pixel circuit labeled R1 is the first row of pixel circuits
  • the pixel circuit labeled R2 is the second row of pixel circuits
  • the pixel circuit labeled RN-1 is row N-1
  • the pixel circuit labeled RN is row N Pixel circuit
  • Y11 corresponds to R1
  • Y12 corresponds to R2
  • Y1N-1 corresponds to RN-1
  • Y1N corresponds to RN;
  • Y11 provides R1 with the first row of light-emitting control signals
  • Y12 for R2 with the second row of light-emitting control signals
  • Y1N-1 provides R1N-1 with the N-1th row of light-emitting control signals
  • Y1N provides R1N with the Nth row of light-emitting control signals.
  • the display substrate may further include a gate driving circuit, the gate driving circuit includes a multi-stage gate driving unit, and the gate driving unit and the pixel row are also in one-to-one correspondence, Used to provide corresponding gate drive signals for corresponding rows of pixels;
  • Y2 is the gate drive circuit
  • S21 is the first row of gate drive units included in the gate drive circuit
  • S22 is the second row of gates included in the gate drive circuit.
  • the driving unit, marked S2N-1 is the gate driving unit of the N-1th row included in the gate driving circuit
  • marked S2N is the gate driving unit of the Nth row included in the gate driving circuit.
  • each transistor, each capacitor, and each signal line in the shift register unit can be adjusted to reduce the occupied area of the shift register unit, thereby reducing the frame width of the display substrate.
  • At least one embodiment of the shift register unit includes an output transistor T10, an output reset transistor T9, an output reset capacitor C3, an output capacitor C2, a reset control transistor T8, an input transistor T1, a second A node control transistor T4, a second node control transistor T5, a third node control transistor T6, a fourth node control transistor T7, a first capacitor C1, a fifth node control transistor T2, and a sixth node control transistor T3.
  • S4 is multiplexed as D5
  • D6 is multiplexed as S7
  • D7 is multiplexed as D8;
  • E01 is the first output line part included in the signal output line
  • E021 is the first second output line part included in the signal output line
  • E022 is the first output line part included in the signal output line.
  • the second second output line part labeled E020, is the second output line part included in the signal output line of the adjacent upper stage shift register unit.
  • E01 is coupled to E021 and E022, respectively, E01 extends in the first direction, and E021 and E022 extend in the second direction.
  • the first voltage signal line VGL1 is used to provide a low voltage VL
  • the second voltage signal line VGH is used to provide a high voltage Vh
  • the third voltage signal line VGH2 is used to provide a high voltage Vh.
  • the four-voltage signal line VGL2 is used to provide low voltage VL;
  • the shift register unit of the above structure is arranged in the edge area of the display substrate, along the direction away from the display area of the display substrate, the second voltage signal line VGH1, the first voltage signal line VGL1, and the third voltage
  • the signal line VGH2 and the fourth voltage signal line VGL2 are arranged in sequence, and the second voltage signal line VGH1, the first voltage signal line VGL1, the third voltage signal line VGH2 and the fourth voltage signal line VGL2 all extend along the first direction;
  • a first clock signal line CB and a second clock signal line CK are provided on the side of the fourth voltage signal line VGL2 away from the third voltage signal line VGH2; the second clock signal line CK and The first clock signal line CB and the start voltage signal line ESTV are sequentially arranged along a direction away from the display area; the first clock signal line CB and the second clock signal line CK both extend along the first direction;
  • the output transistor T10 and the output reset transistor T9 included in the output circuit, and the reset control transistor T8 included in the reset control circuit are arranged between the first voltage signal line VGL1 and the second voltage signal line VGH1; along the first direction, the output The reset transistor T9 and the output transistor T10 are arranged in sequence;
  • T1, T4, T5, T6, T7, T11, and T12 may be arranged between the first voltage signal line VGL1 and the third voltage signal line VGH2;
  • T2 and T3 may be arranged between the third voltage signal line VGH2 and the fourth voltage signal line VGL2;
  • the orthographic projection of the second plate C3b of the output reset capacitor C3 on the substrate overlaps with the orthographic projection of the second voltage signal line VGH1 on the substrate.
  • the orthographic projection of the second plate C3b of the output reset capacitor C3 on the substrate is The first plate C3a of the output reset capacitor C3 is within the orthographic projection on the substrate;
  • the orthographic projection of the second plate C2b of the output capacitor C2 on the substrate partially overlaps the orthographic projection of the fourth voltage signal line VGL2 on the substrate.
  • the orthographic projection of the second plate C2b of the output capacitor C2 on the substrate is on the output capacitor
  • the first plate C2a of C2 is within the orthographic projection on the substrate;
  • the orthographic projection of the first electrode plate C1a of C1 on the substrate partially overlaps the orthographic projection of the first voltage signal line VGL1 on the substrate, and the orthographic projection of the second electrode plate C1b of C1 on the substrate is on the first electrode plate C1a of C1 Within the orthographic projection on the substrate;
  • the signal output line includes a first output line part E01 and a second output line part E02;
  • the first output line part E01 and the second output line part E02 are coupled to each other;
  • the first output line part E01 extends in a first direction, and the first output line part E01 is located between the second voltage signal line VGH1 and the output circuit O1;
  • the second output line portion E02 extends in a second direction, and the second output line portion E02 extends to the display area of the display substrate to provide light emission control signals for the light emission control terminals of the corresponding row of pixel circuits;
  • T1, T4 and T5 are arranged in sequence along the first direction
  • T7, T6 and T12 are arranged in sequence along the first direction
  • C1 and T11 are arranged in sequence along the first direction
  • T1, T7 and C1 are arranged in sequence along the second direction;
  • T3 and T2 are arranged in sequence along the first direction, and the active pattern of T2 is arranged in a U-shaped structure, so that T2 is formed as a double gate structure.
  • the first direction intersects the second direction.
  • the first direction may be perpendicular to the second direction, but it is not limited thereto.
  • the angle at which the second direction intersects with the first direction can be set according to actual needs.
  • the second direction is perpendicular to the first direction.
  • the position of the first clock signal line CB and the position of the second clock signal line CK can be reversed, but it is not limited to this.
  • the first direction may be a vertical direction from top to bottom, and the second direction may be a horizontal direction from left to right, but is not limited to this.
  • the width of the signal line mainly affects the resistance, and a wider signal line has less resistance, which is beneficial to signal stability.
  • the first voltage signal line VGL1, the second voltage signal line VGH1, the third voltage signal line VGH2, and the fourth voltage signal line VGL2 provide a direct current voltage, which is less affected by the line width.
  • the first clock signal line CB and the second clock signal line CK provide clock signals. When the potential of the clock signal is converted from a high voltage to a low voltage, the low resistance of the clock signal line makes the potential of the clock signal faster. A low voltage is reached. Therefore, in at least one embodiment of the present disclosure, the line width of the first clock signal line CB and the line width of the second clock signal line can be set to be wider, but not limited to this.
  • the first electrode S9 of the output reset transistor T9 is coupled to the second voltage signal line VGH1
  • the first electrode S10 of the output transistor T10 is coupled to the first voltage signal line VGL1
  • the second electrode D10 of the output transistor T10 and the second electrode D9 of the output reset transistor T9 are both coupled to the first output line part E01 of the signal output lines included in the at least one shift register unit;
  • the gate G8 of the reset control transistor T8 is coupled to the gate G10 of the output transistor T10, the first electrode S8 of the reset control transistor T8 is coupled to the first electrode S9 of the output reset transistor T9, and the reset The second electrode D8 of the control transistor T8 is coupled to the gate G8 of the output reset transistor T9, so T8, T9, T10, and E01 are all set between VGL1 and VGH1, and the active pattern of T9 is set along the first The width in the two directions is set to be smaller than the width of the active pattern of T19 in the second direction, and the space
  • the shift register unit shown in FIG. 11 may be an n-th stage shift register unit included in the scan driving circuit, and n is a positive integer.
  • the active layer of T1, the active layer of T4, and the active layer of T5 are formed by a continuous second semiconductor layer, and the second semiconductor layer extends along the first direction. Therefore, the space in the second direction occupied by T1, T4 and T5 can be reduced, which is conducive to the realization of a narrow frame;
  • the active layer of T7 and the active layer of T6 are formed by a continuous third semiconductor layer, and the third semiconductor layer is formed along the first Extend in one direction, so as to reduce the space in the second direction occupied by T7 and T6, which is beneficial to realize a narrow frame;
  • the second electrode D1 of T1 is multiplexed as the second electrode of T4, and the first electrode S1 of T4 is multiplexed as the second electrode of T5;
  • the first electrode S1 of T7 is multiplexed as the second electrode of T6;
  • C1, T6, and T7 are moved up to use the extra longitudinal space to set up T11 and T12 for noise reduction;
  • the active pattern of T3 is set to extend along the first direction, so as to save the space occupied by T3 in the second direction;
  • the active pattern of T2 is set to a U-shaped structure, so that T2 is formed as a double-gate structure;
  • the purpose of the double-gate structure design is: in the second stage P2, the scan driving circuit
  • the included shift register unit outputs the high voltage signal Vgh, T10 should be completely turned off, and the high level connected to the gate of T10 is input by the source of T5. Therefore, in the second phase P2, it is necessary to ensure that T5 is turned on, that is, the potential of the fifth node N5 needs to be made low; and in the second phase P2, the potential of the gate of T2 is high, to ensure that T2 does not leak.
  • the potential of the two-node N2 rises, so T2 is set to adopt a double-gate design, which makes it easier to turn off T2.
  • the active pattern of T2 In actual production exposure, if the active pattern of T2 is set to a U-shape without missing corners, metal will be deposited after exposure, which will make the U-shaped active pattern a V-shape. Therefore, in actual products, taking into account the actual production exposure process, a small part of the U-shaped active pattern is dug in two right-angle parts to compensate, and the actual pattern is made to be U-shaped as much as possible, without affecting the aspect ratio of T2. .
  • the pole plate of C3 is set to overlap with VGH1
  • the pole plate of C2 is set to overlap with VGL2 to reduce the second direction occupied by the shift register unit.
  • the orthographic projection of the C1 plate on the substrate is set to overlap with the orthographic projection of VGL1 on the substrate to reduce the shift register unit in the second direction. Space is conducive to achieving a narrow frame.
  • the display substrate includes a scan driving circuit disposed on the base, the scan driving circuit includes a plurality of shift register units, and among the plurality of shift register units At least one shift register unit is the aforementioned shift register unit; the scan driving circuit further includes a first voltage signal line VGL1 and a second voltage signal line VGH1;
  • the first voltage signal line VGL1 is located on a side of the second voltage signal line VGL2 away from the display area;
  • the at least one shift register unit includes an output circuit O1, a first tank circuit, and a first leakage prevention circuit 12;
  • the output circuit O1 is respectively coupled to the first voltage signal line VGL1 and the second voltage signal line VGH1, and the first tank circuit is respectively coupled to the output circuit O1 and the second voltage signal line VGH1 Coupled, the first anti-leakage circuit 12 is coupled to the output circuit O1;
  • the output circuit O1 is arranged between the first voltage signal line VGL1 and the second voltage signal line VGH1;
  • the orthographic projection of the first tank circuit on the substrate partially overlaps the orthographic projection of the second voltage signal line VGH1 on the substrate;
  • the first anti-leakage circuit 12 is arranged on a side of the first voltage signal line VGL1 away from the second voltage signal line VGH1;
  • the first voltage signal line VGL1 is used to provide a first voltage
  • the second voltage signal line VGH2 is used to provide a second voltage
  • the first voltage signal line VGL1 and the second voltage signal line VGH1 may extend along a first direction.
  • the first tank circuit may include an output reset capacitor C3 and an output capacitor C2.
  • the display substrate Since the output circuit O1 is respectively coupled to the first voltage signal line VGL1 and the second voltage signal line VGH1, the display substrate according to at least one embodiment of the present disclosure has the output circuit O1 disposed on the first voltage signal line VGL1 and the second voltage signal line VGL1. Between the signal lines VGH1, the length of the connection line between the output circuit O1 and the first voltage signal line VGL1 can be shortened, and the length of the connection line between the output circuit O1 and the second voltage signal line VGH1 can be shortened, Therefore, the output circuit O1, the first voltage signal line VGL1, and the second voltage signal line VGH1 can be rationally arranged.
  • the orthographic projection of the first tank circuit on the substrate is set to partially overlap with the orthographic projection of the second voltage signal line VGH1 on the substrate, In order to reduce the width of the shift register unit in the second direction, it is beneficial to realize a narrow frame and facilitate the coupling of the first tank circuit and the second voltage signal line VGH1.
  • the at least one shift register unit may include a first anti-leakage circuit 12 to prevent leakage of the output transistor included in the output circuit O1.
  • the first anti-leakage circuit 12 is arranged on a side of the first voltage signal line VGL1 away from the second voltage signal line VGH1, so that the first anti-leakage circuit 12 can be easily coupled to the first voltage signal line VGL1 catch.
  • the second voltage signal line VGH1 may be located on the side of the output circuit O1 close to the display area, and the first voltage signal line VGL1 may be located on the side of the output circuit O1 away from the display area;
  • the first voltage signal line VGL1 and the second voltage signal line VGH1 extend in a first direction.
  • the scan driving circuit further includes a third voltage signal line VGH2 and a fourth voltage signal line VGL2, and the fourth voltage signal line VGL2 is used to provide a first voltage.
  • the third voltage signal line VGH2 is used to provide a second voltage; the third voltage signal line VGH2 is located on the side of the first voltage signal line VGL1 away from the display area, and the fourth voltage signal line VGL2 is located at the The third voltage signal line VGH2 is far away from the side of the display area;
  • the orthographic projection of the first tank circuit on the substrate partially overlaps the orthographic projection of the fourth voltage signal line VGL2 on the substrate;
  • the first anti-leakage circuit 12 is located between the first voltage signal line VGL1 and the third voltage signal line VGH2.
  • the first tank circuit may include an output reset capacitor C3 and an output capacitor C2.
  • the orthographic projection of the first tank circuit on the substrate is set to partially overlap with the orthographic projection of the fourth voltage signal line VGL2 on the substrate, so that Reducing the width of the shift register unit in the second direction facilitates the realization of a narrow frame.
  • the first voltage signal line VGL1, the second voltage signal line VGH1, the third voltage signal line VGH2, and the fourth voltage signal line VGL2 all extend along the first direction.
  • the at least one shift register unit further includes a reset control circuit 16; the reset control circuit is coupled to the output circuit O1;
  • the reset control circuit 16 is provided between the first voltage signal line VGL1 and the second voltage signal line VGH1.
  • the display substrate Since the reset control circuit 16 is coupled to the output circuit O1, the display substrate according to at least one embodiment of the present disclosure has both the output circuit O1 and the reset control circuit 16 disposed on the first voltage signal line VGL1 and the second voltage. Between the signal lines VGH1, the reset control circuit 16 can be easily coupled to the output circuit O1, so that the output circuit O1, the reset control circuit 16, the first voltage signal line VGL1, and the second voltage signal line VGH1 can be rationally arranged.
  • the reset control circuit 16 may include a reset control transistor T8.
  • the at least one shift register unit may further include a second node control circuit, a second energy storage circuit, and a second anti-leakage circuit;
  • the second node control circuit is coupled to a second tank circuit; the second anti-leakage circuit is respectively coupled to the first anti-leakage circuit and the first voltage signal line;
  • the second node control circuit is arranged on a side of the first voltage signal line away from the second voltage signal line;
  • the orthographic projection of the second tank circuit on the substrate partially overlaps the orthographic projection of the first voltage signal line on the substrate;
  • the second anti-leakage circuit is located on a side of the first voltage signal line away from the second voltage signal line.
  • the second anti-leakage circuit is respectively coupled to the first voltage signal line and the first anti-leakage circuit, so that the second anti-leakage circuit and the first anti-leakage circuit are connected to each other.
  • the circuits are all arranged on the side of the first voltage signal line away from the second voltage signal line, which facilitates the coupling of the first anti-leakage circuit and the second anti-leakage circuit, and also facilitates the second anti-leakage circuit
  • the circuit is coupled to the first voltage signal line.
  • the orthographic projection of the second tank circuit on the substrate partially overlaps the orthographic projection of the first voltage signal line on the substrate to narrow the shift register unit
  • the occupied space in the second direction facilitates the realization of a narrow frame.
  • the second node control circuit is arranged on the side of the first voltage signal line away from the second voltage signal line, so as to facilitate the second node control circuit and the second storage. Can circuit coupling.
  • the second anti-leakage circuit may include a second control transistor T11, the second tank circuit may include a first capacitor C1, and the second node control circuit It may include a third node control transistor T6 and a fourth node control transistor T7.
  • the at least one shift register unit may further include a third node control circuit; the third node control circuit is located on a side of the first voltage signal line away from the second voltage signal line.
  • the third node control circuit may include an input transistor T1, a first node control transistor T4, and a second node control transistor T5.
  • the scan driving circuit may further include a third voltage signal line VGH2; the third voltage signal line VGH2 is located on a side of the first voltage signal line VGL1 away from the display area; the third node The control circuit is coupled to the third voltage signal line VGH2;
  • the third node control circuit is located between the first voltage signal line VGL1 and the third voltage signal line VGH2, so that the third node control circuit is coupled to the third voltage signal line VGH2.
  • the at least one shift register unit further includes a fifth node control circuit;
  • the scan driving circuit further includes a third voltage signal line VGH2 and a fourth voltage signal line VGL2;
  • the third voltage signal line VGH2 is located on the side of the first voltage signal line VGL1 away from the display area, and the fourth voltage signal line VGL2 is located on the side of the third voltage signal line away from the display area;
  • the fifth node control circuit is respectively coupled to the fourth voltage signal line VGL2 and the first tank circuit;
  • the fifth node control circuit is located between the third voltage signal line VGH2 and the fourth voltage signal line VGL2.
  • the fifth node control circuit may include a fifth node control transistor T2 and a sixth node control transistor T3, and the first tank circuit may include an output reset capacitor C3 and an output Capacitance C2.
  • At least one embodiment of the present disclosure places a fifth node control circuit between the third voltage signal line VGH2 and the fourth voltage signal line VGL2, so as to facilitate the five-node control circuit They are respectively coupled to the fourth voltage signal line VGL2 and the output capacitor C2 included in the first tank circuit.
  • the scan driving circuit further includes a first clock signal line CB and a second clock signal line CK which are arranged on the fourth voltage signal line VGL2 away from the display area;
  • the first tank circuit is coupled to the first clock signal line CB;
  • Both the first clock signal line CB and the second clock signal line CK extend in a first direction.
  • the first tank circuit may include an output reset capacitor C3 and an output capacitor C2.
  • the second voltage signal line, the first voltage signal line, the third voltage signal line, the fourth voltage signal line, and the The second clock signal line and the first clock signal line are arranged in sequence; or,
  • the second voltage signal line, the first voltage signal line, the third voltage signal line, the fourth voltage signal line, the first clock signal line, and the The second clock signal lines are arranged in sequence.
  • the display substrate may further include multiple rows of pixel circuits arranged in the display area on the substrate; the pixel circuits may include a light-emitting control terminal; the shift register unit may further include a signal output line;
  • the shift register unit and the row pixel circuit have a one-to-one correspondence
  • the signal output line of the shift register unit is coupled to the light emission control end of the corresponding row of pixel circuits, and is used to provide light emission control signals for the light emission control end of the corresponding row of pixel circuits.
  • At least one embodiment of the present disclosure adopts a one-stage shift register unit to provide a light-emitting control signal for a single-row pixel circuit, which can realize PWM (Pulse Width Modulation) fine dimming under low grayscale display conditions, and achieve better display images and effects. Reduce the low gray level Mura (unevenness) of the screen.
  • the signal output line may include a first output line part E01 and a second output line part E02;
  • the first output line part E01 is located between the output circuit O1 and the second voltage signal line VGH1;
  • the first output line part E01 is coupled to the second output line part E02, the first output line part E01 extends in a first direction, and the second output line part E02 extends in a second direction.
  • the first direction intersects the second direction;
  • the second output line portion E02 extends to the display area to provide light emission control signals for a row of pixel circuits located in the display area.
  • the output circuit may include an output transistor and an output reset transistor
  • the output reset transistor and the output transistor are arranged along a first direction;
  • the first electrode of the output reset transistor is coupled to the second voltage signal line, and the first electrode of the output transistor is coupled to the first voltage signal line;
  • Both the second electrode of the output transistor and the second electrode of the output reset transistor are coupled to a signal output line included in the at least one shift register unit.
  • the width of the active layer of the output reset transistor in the second direction may be smaller than the width of the active layer of the output transistor in the second direction
  • the first direction intersects the second direction.
  • At least one embodiment of the present disclosure can set the reset control circuit by setting the width of the active layer of the output reset transistor in the second direction to be smaller than the width of the active layer of the output transistor in the second direction.
  • the space saved in the second direction is used to reduce the width of the shift register unit in the second direction, which is beneficial to realize a narrow frame.
  • the at least one shift register unit further includes a reset control circuit, and the reset control circuit includes a reset control transistor;
  • the gate of the reset control transistor is coupled to the gate of the output transistor, the first electrode of the reset control transistor is coupled to the first electrode of the output reset transistor, and the second electrode of the reset control transistor It is coupled to the gate of the output reset transistor.
  • the output circuit O1 may include an output transistor T10 and an output reset transistor T9;
  • the reset control circuit 16 may include a reset control transistor T8;
  • the output reset transistor T9 and the output transistor T10 are arranged in order from top to bottom;
  • the first electrode S9 of the output reset transistor T9 is coupled to the second voltage signal line VGH1, and the first electrode S10 of the output transistor T10 is coupled to the first voltage signal line VGL1;
  • the second electrode D10 of the output transistor T10 and the second electrode D9 of the output reset transistor T9 are both coupled to the first output line part E01 included in the signal output line;
  • the gate G8 of the reset control transistor T8 is coupled to the gate G8 of the output transistor T10, and the first electrode S8 of the reset control transistor T8 is coupled to the first electrode S9 of the output reset transistor G9, so The second electrode D8 of the reset control transistor T8 is coupled to the gate G9 of the output reset transistor T9.
  • the output reset transistor T9 is used to provide an invalid light emission control signal
  • the output transistor T10 is used to provide an effective light emission control signal
  • the effective light emission control signal may be a voltage signal capable of turning on the light emission control transistor in the pixel circuit (the gate of the light emission control transistor is coupled to the light emission control line),
  • the invalid light emission control signal may be a voltage signal capable of turning off the light emission control transistor.
  • the display area of the display substrate includes a plurality of sub-pixels; at least one of the plurality of sub-pixels includes a pixel driving circuit; the pixel driving circuit includes a transistor, a gate line, a light-emitting control line, and a data line; the scanning
  • the multiple shift register units included in the drive circuit correspond to multiple light-emitting control lines one-to-one, and the signal output line of each shift register unit is coupled to a corresponding light-emitting control line for providing a corresponding light-emitting control line.
  • Luminous control signal a corresponding light-emitting control line for providing a corresponding light-emitting control line.
  • the active layer of the output transistor and the active layer of the output reset transistor are formed by a continuous first semiconductor layer
  • the first semiconductor layer and the signal output line are arranged along a first direction.
  • the active layer of the output transistor and the active layer of the output reset transistor may be formed by a continuous first semiconductor layer, but it is not limited to this.
  • the active layer of the output transistor and the active layer of the output reset transistor may be formed by a continuous first semiconductor layer
  • the active layer of the output reset transistor includes at least two first conductive portions and at least one first channel portion arranged opposite to each other in a first direction; each of the first channel portions is arranged on two adjacent first channel portions. Between a conductive part;
  • the active layer of the output transistor may include at least two second conductive portions and at least one second channel portion arranged opposite to each other along the first direction; each of the second channel portions is arranged on two adjacent Between the second conductive parts;
  • the first conductive part of the active layer of the output reset transistor that is closest to the active layer of the output transistor can be multiplexed as the second conductive part of the output transistor, which can further reduce the size of the output transistor and the output transistor.
  • the layout space of the output reset transistor is beneficial to realize the narrow frame of the display substrate.
  • the active layer of the output reset transistor T9 and the active layer of the output transistor T10 may be formed by a continuous first semiconductor layer 10;
  • the active layer of the output reset transistor T9 includes a first first conductive portion 111, a second first conductive portion 112, and a third first conductive portion 113 that are arranged oppositely along the first direction.
  • the output reset transistor also includes a first first channel portion 121, a second first channel portion 122, and a third first channel portion 123;
  • the first first channel portion 121 is disposed between the first first conductive portion 111 and the second first conductive portion 112, and the second first channel portion 122 is disposed between Between the second first conductive portion 112 and the third first conductive portion 113; the third first channel portion 123 is disposed between the third first conductive portion 113 and the fourth Between the first conductive parts;
  • the active layer of the output transistor T10 further includes a first second conductive portion 131, a second second conductive portion 132, and a third second conductive portion 133 arranged opposite to each other along the first direction.
  • the output transistor T10 The active layer also includes a first second channel portion 141 and a second second channel portion 142;
  • the first second conductive part 131 is multiplexed into a fourth first conductive part
  • the first second channel portion 141 is disposed between the first second conductive portion 131 and the second second conductive portion 132, and the second second channel portion 142 is disposed on the second Between the second conductive portion 132 and the third second conductive portion 133.
  • the conductive parts on both sides of the channel part of each transistor may correspond to the first electrode and the second electrode of the transistor, or may be connected to the transistor's
  • the first electrode is coupled to the second electrode of the transistor, so that T9 and T10 can be electrically connected through the third first conductive portion 113.
  • the first semiconductor material layer may be formed first, and then after the gate G9 of the output reset transistor T9 and the gate G10 of the output transistor T10 are formed, the output reset transistor T9 may be formed.
  • the gate G9 of the output transistor T10 and the gate G10 of the output transistor T10 are masks, and the portions of the first semiconductor material layer that are not covered by the gates of the transistors are doped so that the first semiconductor material layer is not covered by the transistors
  • the portion covered by the gate of the first semiconductor material layer is formed as the conductive portion, and the portion covered by each transistor in the first semiconductor material layer is formed as the channel portion.
  • the output reset transistor T9 and the output transistor T10 in the shift register unit can be arranged along the first direction.
  • the area occupied by the shift register unit in the second direction makes the display substrate more in line with the development demand of narrow frame.
  • the gate of the output reset transistor may include at least one output reset gate pattern, the first electrode of the output reset transistor includes at least one first electrode pattern, and the second electrode of the output reset transistor includes at least one Second electrode pattern;
  • the output reset gate pattern is located between the adjacent first electrode pattern and the second electrode pattern;
  • the second electrode pattern, the output reset gate pattern, and the first electrode pattern all extend along a second direction;
  • the first direction intersects the second direction.
  • the gate of the output transistor may include at least two output gate patterns arranged in a first direction, the first electrode of the output transistor includes at least one third electrode pattern, and the second electrode of the output transistor Including at least one fourth electrode pattern;
  • the output reset gate pattern is located between the adjacent third electrode pattern and the fourth electrode pattern;
  • the fourth electrode pattern, the output gate pattern, and the third electrode pattern all extend along the second direction;
  • the first direction intersects the second direction
  • the fourth electrode pattern of the output transistors closest to the gate of the output reset transistor is multiplexed as the second electrode pattern of the output reset transistor.
  • the number of output reset gate patterns, the number of first electrode patterns, the number of second electrode patterns, the number of output gate patterns, and the number of third electrode patterns And the number of the fourth electrode patterns can be set according to actual needs.
  • the number of output gate patterns may be two
  • the number of output reset gate patterns may be three
  • the number of first electrode patterns may be two.
  • the number of the second electrode pattern can be two
  • the number of the third electrode pattern can be one
  • the number of the fourth electrode pattern can be two, but it is not limited to this.
  • the closest one of the output transistors can be
  • the fourth electrode pattern of the gate of the output reset transistor is multiplexed as the second electrode pattern of the output reset transistor, which can further reduce the layout space of the output transistor and the output reset transistor, which is beneficial to realize the narrow frame of the display substrate .
  • the gate G9 of the output reset transistor T9 may include: a first output reset gate pattern G91, a second output reset gate pattern G92, and a third output reset Gate pattern G93;
  • the gate G10 of the output transistor T10 may include: a first output gate pattern G101 and a second output gate pattern G102;
  • the graphics G102 are arranged in sequence along the first direction;
  • the graphics G102 all extend along the second direction, and the second direction intersects the first direction;
  • the first output reset gate pattern G91, the second output reset gate pattern G92, and the third output reset gate pattern G93 are coupled to each other, and the first output gate pattern G101 and the second output gate pattern G101 are coupled to each other.
  • the output gate patterns G102 are coupled to each other;
  • the first electrode S9 of the output reset transistor T9 includes a first first electrode pattern S91 and a second first electrode pattern S92;
  • the second electrode D9 of the output reset transistor T9 includes a first second electrode pattern D91;
  • S91, D91, and S92 are sequentially arranged along the first direction, and S91, D91, and S92 all extend along the second direction, and S91 and S92 are both coupled to the second voltage signal line VGH2;
  • the first fourth electrode pattern D101 is multiplexed as the second second electrode pattern included in the second electrode D9 of the output reset transistor T9; the second electrode D10 of the output transistor T10 includes the first fourth electrode pattern D101 and the second fourth electrode pattern D102;
  • D101, S10 and D102 are arranged in sequence along the first direction, and D101, S10 and D102 all extend along the second direction;
  • S10 is coupled to the first voltage signal line VGL1;
  • the orthographic projection of G91 on the substrate is set between the orthographic projection of S91 on the substrate and the orthographic projection of D91 on the substrate.
  • the orthographic projection of G92 on the substrate Set between the orthographic projection of D91 on the substrate and the orthographic projection of S92 on the substrate, and the orthographic projection of G93 on the substrate is set between the orthographic projection of S92 on the substrate and the orthographic projection of D101 on the substrate;
  • the orthographic projection of G101 on the substrate is set between the orthographic projection of D101 on the substrate and the orthographic projection of S10 on the substrate
  • the orthographic projection of G102 on the substrate is set between the orthographic projection of S10 on the substrate and the orthographic projection of D102 on the substrate. Between the orthographic projections on the substrate.
  • the shift register unit when at least one shift register unit included in the scan driving circuit is in operation, when T10 is turned on, the shift register unit continuously outputs a low voltage signal, in order to keep the gate of T10 connected The voltage signal is stable, and the gate G10 of T10 should be avoided to overlap with the clock signal line.
  • the active layer of the output reset transistor may include at least two first conductive parts and at least one first channel part arranged oppositely along the first direction; each of the first channel parts is arranged Between two adjacent first conductive parts;
  • the first channel portion corresponds to the output reset gate pattern one-to-one, and the orthographic projection of each first channel portion on the substrate is located in the corresponding output reset gate pattern.
  • a part of the first conductive portion in the output reset transistor corresponds to the first electrode pattern one-to-one, and the orthographic projection of the first electrode pattern on the substrate is in the same position as the corresponding first conductive portion.
  • the other part of the output reset transistor, the first conductive part corresponds to the second electrode pattern one-to-one, and the orthographic projection of the second electrode pattern on the substrate corresponds to the first conductive part
  • the orthographic projection on the substrate has a second overlap area, and the second electrode pattern is coupled to the corresponding first conductive portion through at least one second via provided in the second overlap area.
  • the active layer of the output transistor may include at least two second conductive parts and at least one second channel part arranged oppositely along the first direction; each of the second channel parts is arranged at Between two adjacent second conductive parts;
  • the second channel portion corresponds to the output gate pattern one-to-one, and the orthographic projection of each second channel portion on the substrate is located on the corresponding output gate pattern on the substrate.
  • a part of the second conductive portion in the output transistor corresponds to the third electrode pattern one-to-one, and the orthographic projection of the third electrode pattern on the substrate corresponds to the second conductive portion at the corresponding position.
  • the other part of the second conductive part in the output transistor corresponds to the fourth electrode pattern on a one-to-one basis.
  • the orthographic projection of the fourth electrode pattern on the substrate is aligned with the corresponding second conductive part.
  • the orthographic projection on the substrate has a fourth overlap area, and the fourth electrode pattern is coupled to the corresponding second conductive portion through at least one fourth via provided in the fourth overlap area.
  • the first first channel portion 121 corresponds to the first output reset gate pattern G91
  • the second first channel portion 122 corresponds to the second output reset gate pattern G91
  • the pole pattern G92 corresponds
  • the third first channel portion 123 corresponds to the third output reset gate pattern G93;
  • the orthographic projection of the first first channel portion 121 on the substrate is located inside the orthographic projection of G91 on the substrate;
  • the orthographic projection of the second first channel portion 122 on the substrate is located inside the orthographic projection of G92 on the substrate;
  • the orthographic projection of the third first channel part 123 on the substrate is located inside the orthographic projection of G93 on the substrate;
  • the first first conductive portion 111 corresponds to the first first electrode pattern S91
  • the second first conductive portion 112 corresponds to the first second electrode pattern D91
  • the third first conductive portion 113 corresponds to the second
  • the first electrode pattern S92 corresponds;
  • the orthographic projection of S91 on the substrate and the orthographic projection of the first first conductive part 111 on the substrate have a first first overlap area, and S91 passes through at least one first overlap area disposed in the first first overlap area.
  • the via hole H1 is coupled to the first first conductive portion 111;
  • the orthographic projection of D91 on the substrate and the orthographic projection of the second first conductive portion 112 on the substrate have a first second overlap area, and D91 passes through at least one second overlap area disposed in the first second overlap area.
  • the via hole H2 is coupled to the second first conductive portion 112;
  • the orthographic projection of S92 on the substrate and the orthographic projection of the third first conductive part 113 on the substrate have a second first overlap area, and S92 is arranged in at least one first overlap area in the second first overlap area.
  • a via hole H1 is coupled to the third first conductive portion 113;
  • the first second channel portion 141 corresponds to the first output gate pattern G101, and the second second channel portion 142 corresponds to the second output gate pattern G102;
  • the orthographic projection of the first second channel part 141 on the substrate is located inside the orthographic projection of G101 on the substrate;
  • the orthographic projection of the second second channel portion 142 on the substrate is located inside the orthographic projection of G102 on the substrate;
  • D101 is multiplexed as the second second electrode pattern; the third first conductive part 113 is multiplexed as the first second conductive part;
  • the first second conductive portion 131 corresponds to the first fourth electrode pattern D101;
  • the second second conductive portion 132 corresponds to the first electrode S10 of the output transistor, and the third second conductive portion 133 corresponds to the second fourth electrode pattern D102;
  • the orthographic projection of D101 on the substrate and the orthographic projection of the first second conductive portion 131 on the substrate have a first fourth overlapping area, and D102 passes through at least one of the first fourth overlapping areas provided in the first fourth overlapping area.
  • the four via holes H4 are coupled to the first second conductive portion 131;
  • the orthographic projection of S10 on the substrate and the orthographic projection of the second second conductive part 132 on the substrate have a third overlap area, and S10 passes through at least one third via H3 provided in the third overlap area and the second
  • the second conductive portion 132 is coupled;
  • the orthographic projection of D102 on the substrate and the orthographic projection of the third second conductive portion 133 on the substrate have a second and fourth overlapping area, and D102 is disposed on the second At least one fourth via H4 in the fourth overlapping area is coupled to the third second conductive portion 133.
  • the number of first vias, the number of second vias, the number of third vias, and the number of fourth vias can be set according to actual needs.
  • the first semiconductor layer 10 is used to form the active layer of the output reset transistor T9 and the active layer of the output transistor T10, which not only makes the space occupied by T9 and T10 in the second direction smaller, but also
  • the size of the active layer of the output reset transistor T9 and the active layer of the output transistor T10 in the first direction can be increased to ensure the channel width of T9 and the channel width of T10, so as to ensure the working performance of T9 and In the case of T10 performance, reduce the frame width of the display substrate.
  • the orthographic projection of the first output line part E01 in the signal output line on the substrate is the orthographic projection of the first semiconductor layer 10 on the substrate and the second voltage signal
  • the line VGH1 is between the orthographic projections on the substrate to facilitate the coupling of the second electrode of the output transistor and the second electrode of the output reset transistor with the signal output line.
  • FIG. 12 is a schematic diagram of the active layer in FIG. 11,
  • FIG. 13 is a schematic diagram of the first gate metal layer in FIG. 11, and
  • FIG. 14 is a schematic diagram of the second gate metal layer in FIG. Schematic diagram.
  • FIG. 15 is a schematic diagram of vias made after the active layer, the first gate metal layer and the second gate metal layer are sequentially arranged
  • FIG. 16 is a schematic diagram of the source and drain metal layers in FIG. 11.
  • an active layer, a first gate metal layer, a second gate metal layer, a via hole, and a source-drain metal layer are sequentially arranged on the base to form a display substrate.
  • the at least one shift register unit may also include a plurality of transistors; the conductive parts on both sides of the channel part of each transistor may be separately It corresponds to the first electrode and the second electrode of the transistor, or can be respectively coupled to the first electrode of the transistor and the second electrode of the transistor.
  • the reset control transistor T8 may be located between the output reset transistor T9 and the first voltage signal line VGL1, and the output reset transistor T9 is active
  • the width of the layer in the second direction may be smaller than the width of the active layer of the output transistor T10 in the second direction;
  • the first direction intersects the second direction
  • the reset control transistor T8 includes a first active pattern A1, and the first active pattern A1 extends along a first direction.
  • the first active pattern A1 includes a first reset control conductive portion A11, a reset control channel portion A10, and a second reset control conductive portion A12 that are sequentially arranged along the first direction;
  • the first reset control conductive portion A11 serves as the first electrode S8 of T8, and the second reset control conductive portion A12 serves as the second electrode D8 of T8.
  • the at least one shift register unit may further include an output reset capacitor
  • the orthographic projection of the second plate of the output reset capacitor on the substrate is within the orthographic projection of the first plate of the output reset capacitor on the substrate;
  • the orthographic projection of the second plate of the output reset capacitor on the substrate partially overlaps the orthographic projection of the second voltage signal line on the substrate;
  • the first plate of the output reset capacitor is coupled to the gate of the output reset transistor in the output circuit
  • the second plate of the output reset capacitor is coupled to the second voltage signal line through a plate connection via.
  • the orthographic projection of the second plate of the output reset capacitor on the substrate is set to overlap with the orthographic projection of the second voltage signal line on the substrate to reduce displacement.
  • the width of the register unit in the second direction facilitates the realization of a narrow frame and facilitates the coupling of the second plate of the output reset capacitor with the second voltage signal line.
  • the at least one shift register unit may include an output reset transistor T9, an output transistor T10, a reset control transistor T8, and an output reset capacitor C3;
  • the gate G9 of T9 is coupled to the first plate C3a of C3, the first electrode S9 of T9 is coupled to the second voltage signal line VGH2, and the second electrode D9 of T9 is coupled to the first output line portion E01 catch;
  • the gate G10 of T10 is coupled to the first electrode S12 of T12, the first electrode S10 of T10 is coupled to the first voltage signal line VGL1, and the second electrode D10 of T10 is coupled to the first output line portion E01 ;
  • the gate G8 of T8 is coupled to the gate G10 of T10,
  • the first electrode G9 of T9 is coupled to the first conductive connection portion L1;
  • the second electrode D8 of T8 is coupled to the second conductive connection portion L2 through the first connection via H01, and there is a fifth overlap area between the second conductive connection portion L2 and the first conductive connection portion L1.
  • the second conductive connection portion L2 is coupled to the first conductive connection portion L1 through a fifth via H5 provided in the fifth overlapping area;
  • the first electrode S8 of T8 is coupled to the second first electrode pattern S92 included in the first electrode S9 of the output reset transistor T9 through the second connection via H02, and S92 is coupled to the second voltage signal line VGH1 , So that the first electrode S8 of T8 is coupled to the second voltage signal line VGH1;
  • the first plate C3a of C3 is coupled to the gate G9 of T9;
  • the second plate C3b of C3 is coupled to the second voltage signal line VGH1 through the plate connection via H30.
  • the first leakage prevention circuit may include a first control transistor; the output circuit may include an output transistor;
  • the first control transistor is located on a side of the first voltage signal line away from the display area;
  • the first electrode of the first control transistor is coupled to the gate of the output transistor.
  • the at least one shift register unit may include a first anti-leakage circuit and a second anti-leakage circuit, the first anti-leakage circuit includes a first control transistor, and the second anti-leakage circuit includes a second anti-leakage circuit.
  • the first control transistor and the second control transistor are located on a side of the first voltage signal line away from the display area;
  • the gate of the first control transistor and the gate of the second control transistor are coupled to each other;
  • the gate of the second control transistor is coupled to an electrode conductive connection part, and there is between an orthographic projection of the electrode conductive connection part on the substrate and an orthographic projection of the first voltage signal line on the substrate An electrode overlap area, where the electrode conductive connection portion is coupled to the first voltage signal line through an electrode connection via provided in the electrode overlap area;
  • the first electrode of the first control transistor is coupled to the gate of the output transistor.
  • the at least one shift register unit may include a first anti-leakage circuit and a second anti-leakage circuit to prevent leakage of the output transistor and prevent leakage of the transistor whose gate is coupled to the fourth node
  • the gate of the first control transistor included in the first anti-leakage circuit and the gate of the second control transistor included in the second anti-leakage circuit are coupled to each other, and the gate of the second control transistor and the first A voltage signal line is coupled, and the first control transistor and the second control transistor are arranged close to the first voltage signal line to facilitate coupling between the gate of the second control transistor and the first voltage signal line And facilitate the coupling between the gate of the first control transistor and the gate of the second control transistor.
  • the at least one shift register unit may include a first leakage prevention circuit and a second leakage prevention circuit, the first leakage prevention circuit includes a first control transistor T12, and the second leakage prevention circuit
  • the leakage circuit includes a second control transistor T11;
  • the output circuit O1 includes an output transistor T10;
  • the first control transistor T12 and the second control transistor T11 are located on the side of the first voltage signal line VGL1 away from the display area;
  • the gate G12 of the first control transistor T12 and the gate G11 of the second control transistor T11 are coupled to each other;
  • the gate G11 of the second control transistor T11 is coupled to an electrode conductive connection portion L01, and the orthographic projection of the electrode conductive connection portion L01 on the substrate is similar to that of the first voltage signal line VGL1 on the substrate.
  • the first electrode S12 of the first control transistor T12 is coupled to the third conductive connection portion L3 through the third connection via H03, the gate G10 of T10 is coupled to the fourth conductive connection portion L4, and the third conductive connection There is a sixth overlapping area between the portion L3 and the fourth conductive connecting portion L4, and the third conductive connecting portion L3 is connected to the fourth conductive connecting portion through a sixth via H6 provided in the sixth overlapping area.
  • L4 is coupled, so that the first electrode S12 of T12 is coupled to the gate G10 of T10.
  • the first control transistor T12 includes a fourth active pattern A4;
  • the fourth active pattern A4 includes a first control conductive portion A411, a first control channel portion A42, and a second control conductive portion A412 sequentially arranged along the second direction;
  • A411 is used as the second electrode D12 of T12, and A412 is used as the first electrode S12 of T12;
  • the second control transistor T11 includes a fifth active pattern A5;
  • the fifth active pattern A5 includes a third control conductive portion A511, a second control channel portion A52, and a fourth control conductive portion A512 sequentially arranged along the first direction;
  • A511 is used as the first electrode S11 of T11, and A512 is used as the second electrode D11 of T11;
  • T11 and T12 are arranged on the side of the first voltage signal line VGL1 away from the display area.
  • D102 is coupled to the fifth conductive connection portion L5, and the fifth conductive connection portion L5 is coupled to the sixth conductive connection portion L6 through the fourth connection via H04.
  • the connecting portion L6 is included in the second gate metal layer;
  • the sixth conductive connection portion L6 is coupled to a carry signal line E11 through a fifth connection via H05.
  • the carry signal line E11 can provide an input signal for the n+1th stage shift register unit.
  • the carry signal line E11 It can be included in the source and drain metal layers, but is not limited to this.
  • the scan driving circuit may further include a third voltage signal line; the third voltage signal line is used to provide a second voltage; the at least one shift register unit further includes a third node Control circuit; the third node control circuit includes an input transistor, a first node control transistor, and a second node control transistor;
  • the active layer of the input transistor, the active layer of the first node control transistor, and the active layer of the second node control transistor are formed by a continuous second semiconductor layer;
  • the second semiconductor layer extends along the first direction
  • the active layer of the input transistor includes a first third conductive portion, a third channel portion, and a second third conductive portion sequentially arranged along a first direction;
  • the second third conductive part is multiplexed into the first fourth conductive part
  • the active layer of the first node control transistor includes a first fourth conductive portion, a fourth channel portion, and a second fourth conductive portion sequentially arranged along a first direction;
  • the second fourth conductive part is multiplexed into the first fifth conductive part
  • the active layer of the second node control transistor includes a first fifth conductive portion, a fifth channel portion, and a second fifth conductive portion sequentially arranged along the first direction;
  • the first electrode of the input transistor is coupled to the input terminal, and the first electrode of the second node control transistor is coupled to the third voltage signal line.
  • the second voltage may be a high voltage Vh, but is not limited to this.
  • the active layer of the input transistor, the active layer of the first node control transistor, and the active layer of the third node control transistor are formed by a continuous second semiconductor layer , And the second semiconductor layer extends along the first direction, so that the space occupied by the input transistor, the first node control transistor, and the second node control transistor in the second direction can be reduced, which is beneficial to realize a narrow frame.
  • the second third conductive portion is multiplexed as the first fourth conductive portion
  • the second fourth conductive portion is multiplexed as the first fifth conductive portion , In order to narrow the horizontal width of the shift register unit while reducing the vertical height of the shift register unit.
  • the scan driving circuit may further include a third voltage signal line VGH2; the third voltage signal line VGH2 is used to provide a high voltage Vh; the at least one shift register unit includes an input transistor T1, the first node control transistor T4 and the second node control transistor T5;
  • the active layer of the input transistor T1, the active layer of the first node control transistor T4, and the active layer of the second node control transistor T5 are formed by a continuous second semiconductor layer 20;
  • the second semiconductor layer 20 extends along the first direction
  • the active layer of the input transistor T1 includes a first third conductive portion 231, a third channel portion 23, and a second third conductive portion 232 sequentially arranged along the first direction;
  • the second third conductive part 232 is multiplexed into the first fourth conductive part
  • the T4 active layer of the first node control transistor includes a first fourth conductive portion, a fourth channel portion 24, and a second fourth conductive portion 242 sequentially arranged along the first direction;
  • the second fourth conductive part 242 is multiplexed into the first fifth conductive part
  • the active layer of the second node control transistor T5 includes a first fifth conductive portion, a fifth channel portion 25, and a second fifth conductive portion 252 sequentially arranged along the first direction;
  • the first electrode S1 of the input transistor T1 is coupled to the input terminal E1 through the sixth connection via H06, and the first electrode S5 of the second node control transistor T5 is connected to the third voltage signal line through the seventh connection via H07 VGH2 is coupled.
  • the first third conductive portion 231 is used as the first electrode S1 of T1
  • the second third conductive portion 232 is used as the second electrode D1 of T1
  • the second fourth conductive portion 242 is used as the first electrode S4 of the first node control transistor T4
  • the second fifth conductive portion 252 is used as the first electrode of the second node control transistor T5
  • the second electrode D1 of T1 is multiplexed as the second electrode of T4
  • the first electrode S4 of D4 and T4 is multiplexed into the second electrode D5 of T5.
  • the input transistor, the first node control transistor, and the second node control transistor are located between the third voltage signal line and the first voltage signal line;
  • the third voltage signal line extends along a first direction, and the third voltage signal line is located on a side of the first voltage signal line away from the display area.
  • the third voltage signal line VGH2 extends along the first direction, the third voltage signal line VGH2 is located on the side of the first voltage signal line VGL1 away from the display area, and T1, T4, and T5 are provided at VGH2 and Between VGL1.
  • the at least one shift register unit may further include a second tank circuit and a second node control circuit; the second tank circuit includes a first capacitor, and the second node control circuit includes a third A node control transistor and a fourth node control transistor;
  • the active layer of the fourth node control transistor and the active layer of the third node control transistor are formed by a continuous third semiconductor layer; the third semiconductor layer extends along the first direction;
  • the active layer of the fourth node control transistor includes a first sixth conductive portion, a sixth channel portion, and a second sixth conductive portion sequentially arranged along the first direction;
  • the second sixth conductive part is multiplexed into the first seventh conductive part
  • the active layer of the third node control transistor includes a first seventh conductive portion, a seventh channel portion, and a second seventh conductive portion sequentially arranged along the first direction;
  • the gate of the fourth node control transistor is coupled to the gate of the first node control transistor, and the second electrode of the fourth node control transistor is coupled to the gate of the output reset transistor;
  • the gate of the third node control transistor is coupled to the first plate of the first capacitor, and the first electrode of the third node control transistor is coupled to the gate of the first node control transistor;
  • the second sixth conductive portion is used as the second electrode of the third node control transistor and the first electrode of the fourth node control transistor;
  • the first electrode of the fourth node control transistor is coupled to the second plate of the first capacitor.
  • the active layer of the third node control transistor and the active layer of the fourth node control transistor are formed by a continuous third semiconductor layer; Extending in one direction can reduce the space occupied by the third node control transistor and the fourth node control transistor in the second direction, which is beneficial to realize a narrow frame.
  • the second sixth conductive portion is multiplexed into the first seventh conductive portion, so as to narrow the lateral width of the shift register unit while reducing the shift register. The vertical height of the unit.
  • the at least one shift register unit may further include a first capacitor C1, a third node control transistor T6, and a fourth node control transistor T7;
  • the active layer of the fourth node control transistor T7 and the active layer of the third node control transistor T3 are formed by a continuous third semiconductor layer 30; the third semiconductor layer 30 extends in the first direction;
  • the active layer of the fourth node control transistor T7 includes a first sixth conductive portion 361, a sixth channel portion 36, and a second sixth conductive portion 362 sequentially arranged along the first direction;
  • the second sixth conductive part 362 is multiplexed into the first seventh conductive part
  • the active layer of the third node control transistor T6 includes a first seventh conductive portion, a seventh channel portion 37, and a second seventh conductive portion 372 sequentially arranged along the first direction;
  • the first sixth conductive portion 361 is used as the second electrode D7 of T7, and the second seventh conductive portion 372 is used as the first electrode S6 of T6;
  • the gate G7 of the fourth node control transistor T7 is coupled to the gate G4 of the first node control transistor T4, and the second electrode D7 of the fourth node control transistor T7 is coupled to the gate G7 of the output reset transistor T9 ;
  • the gate G6 of the third node control transistor T6 is coupled to the first plate C1a of the first capacitor C1, and the first electrode S6 of the third node control transistor T6 and the gate of the first node control transistor T4 G4 coupling;
  • the second sixth conductive portion 362 serves as the second electrode D6 of the third node control transistor T6 and the first electrode S7 of the fourth node control transistor T7;
  • the first electrode S7 of the fourth node control transistor T7 is coupled to the second plate C1b of the first capacitor C1.
  • T6 and T7 can be set between VGH2 and VGL1.
  • the second electrode D7 of T7 is coupled to the seventh conductive connection portion L7 through the eighth connection via H08, and the seventh conductive connection portion L7 is connected to the seventh conductive connection portion L7 through the ninth connection via H09.
  • the first conductive connection portion L1 is coupled;
  • the first electrode S7 of T7 is coupled to the eighth conductive connection portion L8 through the tenth connection via H010, and there is a seventh overlap between the eighth conductive connection portion L8 and the second plate C1b of the first capacitor C1 Area, the eighth conductive connecting portion L8 is coupled to the second plate C1b of the first capacitor C1 through a seventh via hole H7 provided in the seventh overlapping area,
  • the gate G7 of T7 is coupled to the gate G4 of T4 through the ninth conductive connection portion L9; the first electrode S6 of T6 is coupled to the tenth conductive connection portion L10 through the through hole H60; the tenth conductive connection portion L10 There is an eighth overlapping area with the ninth conductive connecting portion L9, and the tenth conductive connecting portion L10 is coupled to the ninth conductive connecting portion L9 through an eighth via H8 provided in the eighth overlapping area. Connected so that the first electrode S6 of T6 is coupled to the gate G4 of T4.
  • the orthographic projection of the second electrode plate of the first capacitor on the substrate is within the orthographic projection of the first electrode plate of the first capacitor on the substrate;
  • the orthographic projection of the second plate of the first capacitor on the substrate partially overlaps the orthographic projection of the first voltage signal line on the substrate;
  • the third node control transistor and the fourth node control transistor are located on the side of the first capacitor away from the display area.
  • At least one embodiment of the present disclosure partially overlaps the orthographic projection of the second plate of the first capacitor on the substrate with the orthographic projection of the first voltage signal line on the substrate to narrow the shift register unit occupation
  • the space in the second direction is conducive to achieving a narrow frame.
  • the orthographic projection of the second electrode plate C1b of the first capacitor C1 on the substrate is within the orthographic projection of the first electrode plate C1a of the first capacitor C1 on the substrate;
  • the orthographic projection of the second plate C1b of the first capacitor C1 on the substrate partially overlaps the orthographic projection of the first voltage signal line VGL1 on the substrate;
  • the third node control transistor T6 and the fourth node control transistor T7 are located on the side of the first capacitor C1 away from the display area;
  • T11, and T12 are arranged in sequence along the first direction, and the space below C1 is used to set T11 and T12 to reduce the occupied horizontal width.
  • the first electrode plate C1a of C1 is coupled to the eleventh conductive connection portion L11 through the eleventh connection via H011, and the first electrode S11 of T11 is connected to the eleventh conductive connection portion L11 through the twelfth connection via H012.
  • the eleventh conductive connecting portion L11 is coupled, so that the first electrode S11 of T11 is coupled to the first electrode plate C1a of C1;
  • the second electrode D11 of T11 is coupled to the twelfth conductive connection portion L12 through the thirteenth connection via H013, and the twelfth conductive connection portion L12 is coupled to the thirteenth conductive connection portion L13 through the fourteenth connection via H014 Coupling, the thirteenth conductive connecting portion L13 is coupled to the gate G5 of T5, so that the second electrode D11 of T11 is coupled to the gate G5 of T5;
  • the second electrode D12 of T12 is coupled to the fourteenth conductive connection portion L14 through the fifteenth connection via H015, and the second electrode D1 of T1 is coupled to the fourteenth conductive connection portion L14 through the sixteenth connection via H016 So that the second electrode D1 of T1 is coupled to the second electrode D12 of T12.
  • the scan driving circuit may further include a third voltage signal line, and the third voltage signal line is used to provide a second voltage;
  • the at least one shift register unit includes a first anti-leakage circuit, a second anti-leakage circuit, an input transistor, a first node control transistor, a second node control transistor, a third node control transistor, and a fourth node control transistor;
  • the first anti-leakage circuit includes a first control transistor, and the second anti-leakage circuit includes a second control transistor;
  • the first control transistor, the second control transistor, the input transistor, the first node control transistor, the second node control transistor, the third node control transistor, and the fourth node control transistor Located between the third voltage signal line and the first voltage signal line;
  • the third voltage signal line extends along a first direction, and the third voltage signal line is located on a side of the first voltage signal line away from the display area.
  • a first control transistor, the second control transistor, the input transistor, the first node control transistor, the second node control transistor, the third node control transistor, and The fourth node control transistor may be located between the third voltage signal line and the first voltage signal line, and the third voltage signal line may be located on a side of the first voltage signal line away from the display area.
  • the at least one shift register unit may further include a fifth node control circuit, and the fifth node control circuit includes a fifth node control transistor;
  • the fifth node control transistor includes a second active pattern, and the second active pattern is a U-shaped structure
  • the second active pattern includes a first fifth node control channel portion, a second fifth node control channel portion, and a first first fifth node control channel portion coupled to the first fifth node control channel portion.
  • the gate of the fifth node control transistor includes a first gate pattern and a second gate pattern that are coupled to each other;
  • the first gate pattern corresponds to the first fifth node control channel portion, and the second gate pattern corresponds to the second fifth node control channel portion;
  • the first fifth node control conductive portion serves as the second electrode of the fifth node control transistor, and the second fifth node control conductive portion serves as the first electrode of the fifth node control transistor.
  • the at least one shift register unit may further include a fifth node control transistor T2;
  • the fifth node control transistor T2 includes a second active pattern A2, and the second active pattern A2 is a U-shaped structure;
  • the second active pattern A2 includes a first fifth node control channel portion A211, a second fifth node control channel portion A212, and a second fifth node control channel portion A211 coupled to the first fifth node control channel portion A211.
  • the gate G2 of the fifth node control transistor T2 includes a first gate pattern G21 and a second gate pattern G22 that are coupled to each other;
  • the first gate pattern G21 corresponds to the first fifth node control channel portion A211, and the second gate pattern G22 corresponds to the second fifth node control channel portion A212;
  • the first fifth node control conductive portion A221 serves as the second electrode D2 of the fifth node control transistor T2, and the second fifth node control conductive portion A222 serves as the fifth node control transistor T2 The first electrode S2.
  • the active pattern of the fifth node control transistor T2 is arranged in a U-shaped structure, so that T2 is formed as a double gate structure.
  • the purpose of the double-gate structure design is: in the second stage P2, when the shift register unit included in the scan drive circuit outputs a high voltage signal, T10 should be completely closed, and the high level of the gate of T10 is connected to the source of T5. enter. Therefore, in the second phase P2, it is necessary to ensure that T5 is turned on, that is, the potential of the fifth node N5 needs to be made low; and in the second phase P2, the potential of the gate of T2 is high, to ensure that T2 does not leak.
  • the potential of the five-node N5 is increased, so T2 is set to adopt a double-gate design, which makes it easier to turn off T2.
  • the active pattern of T2 In actual production exposure, if the active pattern of T2 is set to a U-shape without missing corners, metal will be deposited after exposure, which will make the U-shaped active pattern a V-shape. Therefore, in actual products, taking into account the actual production exposure process, a small part of the U-shaped active pattern is dug in two right-angle parts to compensate, and the actual pattern is made to be U-shaped as much as possible, without affecting the aspect ratio of T2. .
  • the first electrode S2 of T2 is coupled to the fifteenth conductive connection portion L15 through the seventeenth connection via H017, and the gate G1 of T1 is coupled to the sixteenth conductive connection portion L16, There is a ninth overlapping area between the fifteenth conductive connecting portion L15 and the sixteenth conductive connecting portion L16, and the fifteenth conductive connecting portion L15 passes through the ninth via H9 and the ninth via H9 disposed in the ninth overlapping area.
  • the sixteenth conductive connecting portion L16 is coupled, so that the first electrode S2 of T2 is coupled to the gate G1 of T1;
  • the sixteenth conductive connection portion L16 is also coupled to the gate G3 of T3, so that the first electrode S2 of T2 is coupled to the gate G3 of T3;
  • the second electrode D2 of T2 is coupled to the seventeenth conductive connection portion L17 through the eighteenth connection via H018, the gate G5 of T5 is coupled to the eighteenth conductive connection portion L18, and the seventeenth conductive connection portion L17 is coupled to the seventh conductive connection portion L18.
  • the second electrode D3 of T3 is coupled to the seventeenth conductive connection portion L17 through the nineteenth connection via H019, so that the second electrode D3 of T3 is coupled to the second electrode D2 of T2;
  • the gate G2 of T2 is coupled to the first plate C2a of the output capacitor C2.
  • the at least one shift register unit may further include a fifth node control circuit, and the fifth node control circuit includes a sixth node control transistor;
  • the sixth node control transistor includes a third active pattern, and the third active pattern extends in a first direction.
  • the at least one shift register unit may further include a sixth node control transistor, the sixth node control transistor and the fifth node control transistor are arranged along the first direction, and the sixth node control transistor includes The third active pattern extends along the first direction to narrow the width in the second direction occupied by the shift register unit.
  • the at least one shift register unit may further include a sixth node control transistor T2;
  • the sixth node control transistor T2 includes a third active pattern A3, and the third active pattern A3 extends along a first direction;
  • the third active pattern A3 includes a first eighth conductive portion A31, an eighth channel portion A30, and a second eighth conductive portion A32;
  • A31 is used as the first electrode S3 of T3, and A32 is used as the second electrode D3 of T3;
  • the sixteenth conductive connection portion L16 is also coupled to the gate G3 of T3, so that the first electrode S2 of T2 is coupled to the gate G3 of T3;
  • the second electrode D3 of T3 is coupled to the seventeenth conductive connection portion L17 through the nineteenth connection via H019, so that the second electrode D3 of T3 is coupled to the second electrode D2 of T2;
  • the first electrode S3 of T3 is coupled to the nineteenth conductive connection portion L19 through the twentieth connection via H020, and the nineteenth conductive connection portion L19 is coupled to the fourth voltage signal line VGL2, so that the first The electrode S3 is coupled to the fourth voltage signal line VGL2;
  • the fourth voltage signal line VGL2 may provide a first voltage, and the first voltage may be a low voltage VL, but is not limited to this.
  • T2 and T3 are arranged between VGH2 and VGL2, and both VGH2 and VGL2 extend in the first direction.
  • the scan driving circuit may further include a fourth voltage signal line, and the fourth voltage signal line is used to provide a first voltage;
  • the first tank circuit may include an output capacitor;
  • the orthographic projection of the second plate of the output capacitor on the substrate is within the orthographic projection of the first plate of the output capacitor on the substrate;
  • the orthographic projection of the second plate of the output capacitor on the substrate partially overlaps the orthographic projection of the fourth voltage signal line on the substrate;
  • the width of the second plate of the output capacitor in the second direction is smaller than the first predetermined width, and the length of the second plate of the output capacitor in the first direction is greater than the first predetermined length;
  • the fourth voltage signal line extends along the first direction.
  • At least one embodiment of the present disclosure is provided with a fourth voltage signal line on the side of the third voltage signal line away from the display area, and the plate of the output capacitor is arranged to overlap the fourth voltage signal line to narrow the shift register.
  • the first predetermined width is 20 microns, and the first predetermined length is 22 microns, but not limited to this.
  • the scan driving circuit may further include a third voltage signal line and a fourth voltage signal line, the fourth voltage signal line is used to provide a first voltage; the third voltage signal line Used to provide a second voltage; the third voltage signal line is located on the side of the first voltage signal line away from the display area, and the third voltage signal line is located on the side of the third voltage signal line away from the display area ;
  • the first tank circuit includes an output capacitor; the at least one shift register unit further includes a fifth node control circuit, and the fifth node control circuit includes a fifth node control transistor and a sixth node control transistor;
  • the fifth node control transistor and the sixth node control transistor are located between the third voltage signal line and the fourth voltage signal line;
  • the first electrode of the sixth node control transistor is coupled to the fourth voltage signal line, and the second electrode of the sixth node control transistor is coupled to the second electrode of the fifth node control transistor;
  • the first electrode of the fifth node control transistor is coupled to the gate of the sixth node control transistor
  • the orthographic projection of the second plate of the output capacitor on the substrate is within the orthographic projection of the first plate of the output capacitor on the substrate; the second plate of the output capacitor is on the substrate.
  • the orthographic projection of the fourth voltage signal line partially overlaps the orthographic projection of the fourth voltage signal line on the substrate;
  • the first plate of the output capacitor is coupled to the gate of the fifth node control transistor
  • the third voltage signal line and the fourth voltage signal line extend along a first direction.
  • the fifth node control transistor and the sixth node control transistor may be arranged between the third voltage signal line and the fourth voltage signal line, and the orthographic projection of the second plate of the output capacitor on the substrate and the The orthographic projection of the fourth voltage signal line on the substrate partially overlaps.
  • the scan driving circuit may further include a first clock signal line and a second clock signal line that are arranged on the fourth voltage signal line away from the display area;
  • the second plate of the output capacitor is coupled to the first clock signal line
  • the gate of the sixth node control transistor is coupled to the second clock signal line
  • Both the first clock signal line and the second clock signal line extend in a first direction.
  • the scan driving circuit may further include a first clock signal line CB and a second clock signal line CK that are arranged on the fourth voltage signal line VGL2 away from the display area;
  • the first clock signal line CB and the second clock signal line CK may both extend in the first direction;
  • the gate of T3 is coupled to the twentieth conductive connection portion L20, and there is an eleventh overlap area between the twentieth conductive connection portion L20 and the second clock signal line CK, and the twentieth conductive connection portion L20 is coupled to the second clock signal line CK through an eleventh via H11 provided in the eleventh overlap region;
  • the gate of T4 is coupled to the twenty-first conductive connection portion L21, there is a twelfth overlap area between the twenty-first conductive connection portion L21 and the first clock signal line CB, and the twenty-first conductive connection
  • the portion L21 is coupled to the first clock signal line CB through a twelfth via H12 provided in the twelfth overlapping area;
  • the gate G2 of T2 is coupled to the first plate C2a of C2;
  • the second plate C2b of C2 is coupled to the twenty-second conductive connection portion L22.
  • the twenty-second conductive connection portion L22 is coupled to the first clock signal line CB through a thirteenth via H13 provided in the thirteenth overlapping area.
  • the second electrode D12 of T12 is coupled to the fourteenth conductive connection portion L14 through the fifteenth connection via H015, and the gate G2 of T2 is coupled to the twenty-third conductive connection portion
  • the twenty-third conductive connection portion L23 is coupled to the fourteenth conductive connection portion L14 through the twenty-first connection via H021, so that the gate G2 of T2 is coupled to the second electrode D12 of T12 Coupling.
  • VGL2, CK, and CB are arranged in order along the direction away from the display area, but in actual operation, VGL2, CB, and CK may be arranged in order along the direction away from the display area.
  • the first second electrode pattern D91 in the second electrode D9 of the output reset transistor T9 is coupled to the first output line conductive connection portion L91;
  • first output line overlap portion between the first output line conductive connection portion L91 and the first output line portion E01, and L91 passes through the first output line via H91 provided in the first output line overlap portion to communicate with the first output line via H91.
  • the output line part E01 is coupled, so that D91 and E01 are coupled;
  • D101 and D102 are both coupled to the second output line conductive connection part L101.
  • the second output line via H101 of the overlapping portion is coupled to the first output line portion E01, so that D101 and D102 are respectively coupled to E01.
  • the scan driving circuit may further include a third voltage signal line, a fourth voltage signal line, a first clock signal line, and a second clock signal line; the third voltage signal line, the The fourth voltage signal line, the first clock signal line, and the second clock signal line all extend in a first direction;
  • the second voltage signal line, the first voltage signal line, the third voltage signal line, the fourth voltage signal line, the second clock signal line, and the The first clock signal lines are arranged in sequence; or,
  • the second voltage signal line, the first voltage signal line, the third voltage signal line, the fourth voltage signal line, the first clock signal line, and the The second clock signal lines are arranged in sequence.
  • the specific positions of the first clock signal line, the second clock signal line, and the fourth voltage signal line can be set according to actual needs.
  • the first clock signal line, the The second clock signal line and the first search voltage signal line are both arranged at the edge of the display substrate, that is, the orthographic projection of the fourth voltage signal line on the substrate, the first clock signal line
  • the orthographic projection on the substrate and the orthographic projection of the second clock signal line on the substrate are both located where the orthographic projection of the shift register unit on the substrate is far from the display area of the display substrate
  • the shift register unit is laid out, it is possible to prevent the transistors in the shift register unit from interacting with the first clock signal line, the second clock signal line, and the fourth voltage signal line. Excessive overlap is generated, which is more conducive to improving the working performance of the shift register unit.
  • the display substrate by arranging the first clock signal line, the second clock signal line, and the fourth voltage signal line to extend along the first direction, it is more advantageous for the display substrate to achieve a narrow frame.
  • the phases of the first clock signal output by the first clock signal line and the second clock signal output by the second clock signal line may be opposite, but not limited to this.
  • the scan driving circuit includes a first voltage signal line VGL1, a second voltage signal line VGH1, a third voltage signal line VGH2, and a fourth voltage signal line VGH2.
  • the output circuit O1 includes an output transistor T10 and an output reset transistor T9;
  • the first leakage prevention circuit 12 includes a first control transistor T12;
  • the at least one shift register unit further includes a signal output line, a second control transistor T11, an input transistor T1, a first node control transistor T4, a second node control transistor T5, a third node control transistor T6, and a fourth node control transistor T7 ,
  • the reset control transistor T8, the output transistor T10, and the output reset transistor G9 are arranged between the first voltage signal line VGL1 and the second voltage signal line VGH1;
  • the first control transistor T12, the second control transistor T11, the input transistor T1, the first node control transistor T4, the second node control transistor T5, the third node control transistor T6, and the The fourth node control transistor T7 is located between the first voltage signal line VGL1 and the third voltage signal line VGH2;
  • the fifth node control transistor T2 and the sixth node control transistor T3 are located between the third voltage signal line VGH2 and the fourth voltage signal line VGL2;
  • the signal output line includes a first output line part E01 and a second output line part E02;
  • the first output line part E01 is located between the output circuit O1 and the second voltage signal line VGH1;
  • the first output line part E01 is coupled to the second output line part E02, the first output line part E01 extends in a first direction, and the second output line part E02 extends in a second direction.
  • the first direction intersects the second direction;
  • the second output line part E02 extends to the display area.
  • T8, T9, and T10 can be set between VGH1 and VGL1, T1, T4, T5, T6, T7, T11, and T12 can be set between VGL1 and VGH2, and T2 and T3 can be set between VGH2 and VGL2, T9 and T10 are arranged in sequence along the first direction, T8 is arranged between G9 and VGL1, T1, T4 and T5 are arranged in sequence along the first direction, T7 and T6 are arranged in sequence along the first direction, T11 and T12 is arranged below T6, T2 and T3 are arranged between VGH2 and VGL2, and T3 and T2 are arranged along the first direction.
  • the first energy storage circuit includes an output capacitor and an output reset capacitor;
  • the at least one shift register unit may also include a first capacitor;
  • the orthographic projection of the second plate of the first capacitor on the substrate partially overlaps the orthographic projection of the first voltage signal line and the substrate, or the first capacitor is located at the first voltage Between the signal line and the fourth node control transistor;
  • the orthographic projection of the second electrode plate of the first capacitor on the substrate is between the orthographic projection of the first electrode plate of the first capacitor on the substrate;
  • the orthographic projection of the second plate of the output reset capacitor on the substrate is within the orthographic projection of the first plate of the output reset capacitor on the substrate;
  • the orthographic projection of the second plate of the output reset capacitor on the substrate partially overlaps the orthographic projection of the second voltage signal line on the substrate;
  • the orthographic projection of the second plate of the output capacitor on the substrate is within the orthographic projection of the first plate of the output capacitor on the substrate;
  • the orthographic projection of the second plate of the output capacitor on the substrate partially overlaps the orthographic projection of the fourth voltage signal line on the substrate.
  • the at least one shift register unit may further include a first capacitor, an output capacitor, and an output reset capacitor, and the orthographic projection of the second plate of the first capacitor on the substrate and
  • the first voltage signal line partially overlaps the orthographic projection on the substrate, and the orthographic projection of the second electrode plate of the output reset capacitor on the substrate is similar to that of the second voltage signal line on the substrate.
  • the orthographic projection part overlaps, and the orthographic projection of the second electrode plate of the output capacitor on the substrate overlaps the orthographic projection of the fourth voltage signal line on the substrate, so as to narrow the first occupancy of the shift register unit. Width in two directions.
  • the at least one shift register unit may further include a first capacitor C1, an output capacitor C2, and an output reset capacitor C3;
  • the orthographic projection of the second plate C1b of the first capacitor C1 on the substrate partially overlaps the orthographic projection of the first voltage signal line VGL1 and the substrate;
  • the orthographic projection of the second electrode plate C1b of the first capacitor C1 on the substrate is between the orthographic projection of the first electrode plate C1a of the first capacitor C1 on the substrate;
  • the orthographic projection of the second electrode plate C3b of the output reset capacitor C3 on the substrate is within the orthographic projection of the first electrode plate C3a of the output reset capacitor C3 on the substrate;
  • the orthographic projection of the second plate C3b of the output reset capacitor C3 on the substrate partially overlaps the orthographic projection of the second voltage signal line VGH1 on the substrate;
  • the orthographic projection of the second electrode plate C2b of the output capacitor C2 on the substrate is within the orthographic projection of the first electrode plate C2a of the output capacitor C2 on the substrate;
  • the orthographic projection of the second plate C2b of the output capacitor C2 on the substrate partially overlaps the orthographic projection of the fourth voltage signal line VGL2 on the substrate.
  • the overlapping area of the plate of C2 and VGL2 is larger, and the overlapping area of the plate of C3 and VGH1 is also larger, in order to fully save the plate of C2 and the plate of C3 The space occupied.
  • the third voltage signal line, the fourth voltage signal line, the first clock signal line, and the second clock signal line all extend in a first direction;
  • the second voltage signal line, the first voltage signal line, the third voltage signal line, the fourth voltage signal line, the second clock signal line, and the The first clock signal lines are arranged in sequence; or,
  • the second voltage signal line, the first voltage signal line, the third voltage signal line, the fourth voltage signal line, the first clock signal line, and the The second clock signal lines are arranged in sequence.
  • a first gate insulating layer may also be provided between the semiconductor layer shown in FIG. 12 and the first gate metal layer shown in FIG. 13;
  • a second gate insulating layer may also be provided between the first gate metal layer and the second gate metal layer shown in FIG. 14; between the second gate metal layer shown in FIG. 14 and the second gate metal layer shown in FIG.
  • An insulating layer may also be included between the source and drain metal layers.
  • a semiconductor material layer is first provided on the base, and the semiconductor material layer is patterned to form the active layer of each transistor; as shown in FIG. 12, A first semiconductor layer 10, a second semiconductor layer 20, a third semiconductor layer 30, a first active pattern A1 included in the reset control transistor T8, and a second active pattern included in the fifth node control transistor T2 are formed A2 and a third active pattern A3 included in the sixth node control transistor T2;
  • a first gate metal layer is fabricated, and a patterning process is performed on the first gate metal layer.
  • the transistors included in the shift register unit are formed The gate of the output reset capacitor C3, the first plate of the first capacitor C1, and the first plate of the output capacitor C2;
  • each transistor doping the part of the active layer that is not covered by the gate, so that the part of the active layer that is not covered by the gate is formed as a conductive part,
  • the portion of the active layer covered by the gate is formed as a channel portion;
  • the conductive portion is used as a first electrode or a second electrode; or, the conductive portion is coupled to the first electrode or the second electrode ;
  • a second gate metal layer is provided on the side of the second gate insulating layer facing away from the first gate metal layer, and a patterning process is performed on the second gate metal layer. As shown in FIG. 14, a signal output line and output are formed.
  • a plurality of via holes are provided on the substrate provided with the active layer, the first gate insulating layer, the first gate metal layer, the second gate insulating layer, the second gate metal layer and the insulating layer;
  • a source-drain metal layer is provided on the side of the insulating layer opposite to the second gate metal layer, and the source-drain metal layer is patterned, as shown in FIG. 16, to form a first voltage signal line VGL1 and a second voltage The signal line VGH1, the third voltage signal line VGH2, the fourth voltage signal line VGL2, the first clock signal line CB, the second clock signal line CB, the input terminal E1, the second electrode of the output reset transistor T9, the output The first electrode of the reset transistor T9, the second electrode of the output transistor T10, and the first electrode of the output transistor T10.
  • the method for fabricating a display substrate includes fabricating a first voltage signal line, a second voltage signal line, and a scan driving circuit on a substrate;
  • the scan driving circuit includes a plurality of shift register units, and At least one shift register unit of the plurality of shift register units includes an output circuit, a first storage circuit, and a first leakage prevention circuit.
  • the output circuit is connected to the first voltage signal line and the second voltage signal, respectively.
  • the first voltage signal line is used to provide a first voltage
  • the second voltage signal line is used to provide a second voltage
  • At least one embodiment of the present disclosure since the output circuit is respectively coupled to the first voltage signal line and the second voltage signal line, at least one embodiment of the present disclosure configures the output circuit on the first voltage signal line and the second voltage signal line. Between the lines, the length of the connection line between the output circuit and the first voltage signal line can be shortened, and the length of the connection line between the output circuit and the second voltage signal line can be shortened, so that the output circuit can be reasonably laid out , The first voltage signal line and the second voltage signal line.
  • the orthographic projection of the first tank circuit on the substrate is set to partially overlap with the orthographic projection of the second voltage signal line on the substrate, so as to reduce shift register units.
  • the width in the second direction facilitates the realization of a narrow frame and facilitates the coupling of the first tank circuit and the second voltage signal line.
  • the at least one shift register unit may include a first anti-leakage circuit to prevent leakage of an output transistor included in the output circuit. At least one embodiment of the present disclosure provides the first anti-leakage circuit On the side of the first voltage signal line away from the second voltage signal line, the first anti-leakage circuit can be easily coupled to the first voltage signal line.
  • the display device includes the above-mentioned display substrate.
  • the display device provided by at least one embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

提供一种显示基板、制作方法和显示装置。显示基板包括扫描驱动电路，至少一个移位寄存器单元包括输出电路(O1)、第一储能电路(11)和第一防漏电电路(12)；扫描驱动电路还包括第一电压信号线(V1)和第二电压信号线(V2)；第一电压信号线(V1)位于第二电压信号线(V2)远离显示区域的一侧；输出电路(O1)分别与第一电压信号线(V1)和第二电压信号线(V2)耦接，第一储能电路(11)分别与输出电路(O1)与第二电压信号线(V2)耦接，第一防漏电电路(12)与输出电路(O1)耦接；输出电路(O1)设置于第一电压信号线(V1)和第二电压信号线(V2)之间；第一储能电路(11)在基底上的正投影与第二电压信号线(V2)在基底上的正投影部分重叠；第一防漏电电路(12)设置于第一电压信号线(V1)远离第二电压信号线(V2)的一侧。

Description

显示基板、制作方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、制作方法和显示装置。
背景技术
有源矩阵有机发光二极管(英文：Active-Matrix Organic Light-Emitting Diode，以下简称：AMOLED)显示面板以其低功耗、低制作成本、广色域等优点被广泛的应用在各个领域。
AMOLED显示面板包括位于显示区域的像素电路和位于边缘区域的扫描驱动电路，所述像素电路包括阵列分布的多个子像素电路，所述扫描驱动电路包括多个移位寄存器单元，每个移位寄存器单元用于为对应的子像素电路提供发光控制信号。相关的移位寄存器单元在工作时，会出现由于节点的电位变化幅度太大而导致的栅极与所述节点电连接的晶体管产生漏电，而导致移位寄存器单元输出错误。
发明内容
本公开的主要目的在于提供一种显示基板、制作方法和显示装置。
在一个方面中，本公开实施例提供一种显示基板，包括设置于基底上的扫描驱动电路，所述扫描驱动电路包括多个移位寄存器单元，所述多个移位寄存器单元中的至少一个移位寄存器单元包括输出电路、第一储能电路和第一防漏电电路；所述扫描驱动电路还包括第一电压信号线和第二电压信号线；所述第一电压信号线用于提供第一电压，所述第二电压信号线用于提供第二电压；
所述第一电压信号线位于所述第二电压信号线远离显示区域的一侧；
所述输出电路分别与所述第一电压信号线和所述第二电压信号线耦接，所述第一储能电路分别与所述输出电路与所述第二电压信号线耦接，所述第一防漏电电路分别与所述输出电路和所述第一电压信号线耦接；
所述输出电路设置于所述第一电压信号线和所述第二电压信号线之间；
所述第一储能电路在所述基底上的正投影与所述第二电压信号线在所述基底上的正投影部分重叠；
所述第一防漏电电路设置于所述第一电压信号线远离所述第二电压信号线的一侧。
可选的，所述扫描驱动电路还包括第三电压信号线和第四电压信号线，所述第四电压信号线用于提供第一电压；所述第三电压信号线用于提供第二电压；所述第三电压信号线位于所述第一电压信号线远离显示区域的一侧，所述第四电压信号线位于所述第三电压信号线远离显示区域的一侧；
所述第一储能电路在所述基底上的正投影与所述第四电压信号线在所述基底上的正投影部分重叠；
所述第一防漏电电路位于所述第一电压信号线与所述第三电压信号线之间。
可选的，所述第一电压信号线、所述第二电压信号线、所述第三电压信号线和所述第四电压信号线都沿第一方向延伸。
可选的，所述至少一个移位寄存器单元还包括复位控制电路；所述复位控制电路与所述输出电路耦接；
所述复位控制电路设置于所述第一电压信号线和所述第二电压信号线之间。
可选的，所述至少一个移位寄存器单元还包括第二节点控制电路、第二储能电路和第二防漏电电路；
所述第二节点控制电路与第二储能电路耦接；所述第二防漏电电路分别与第一防漏电电路和所述第一电压信号线耦接；
所述第二节点控制电路设置于所述第一电压信号线远离所述第二电压信号线的一侧；
所述第二储能电路在所述基底上的正投影与所述第一电压信号线在所述基底上的正投影部分重叠；
所述第二防漏电电路位于所述第一电压信号线远离所述第二电压信号线的一侧。
可选的，所述至少一个移位寄存器单元还包括第三节点控制电路；所述第三节点控制电路位于第一电压信号线远离所述第二电压信号线的一侧。
可选的，所述扫描驱动电路还包括第三电压信号线；所述第三电压信号线位于所述第一电压信号线远离显示区域的一侧；所述第三节点控制电路与所述第三电压信号线耦接；
所述第三节点控制电路位于所述第一电压信号线与所述第三电压信号线之间。
可选的，所述至少一个移位寄存器单元还包括第五节点控制电路；所述扫描驱动电路还包括第三电压信号线和第四电压信号线；所述第三电压信号线位于所述第一电压信号线远离显示区域的一侧，所述第四电压信号线位于所述第三电压信号线远离显示区域的一侧；
所述第五节点控制电路分别与所述第四电压信号线和所述第一储能电路耦接；
所述第五节点控制电路位于所述第三电压信号线与所述第四电压信号线之间。
可选的，所述扫描驱动电路还包括设置于所述第四电压信号线远离显示区域的第一时钟信号线和第二时钟信号线；
所述第一储能电路与所述第一时钟信号线耦接；
所述第一时钟信号线和所述第二时钟信号线都沿第一方向延伸。
可选的，沿着远离显示区域的方向，所述第二电压信号线、所述第一电压信号线、所述第三电压信号线、所述第四电压信号线、所述第二时钟信号线和所述第一时钟信号线依次排列；或者，
沿着远离显示区域的方向，所述第二电压信号线、所述第一电压信号线、所述第三电压信号线、所述第四电压信号线、所述第一时钟信号线和所述第二时钟信号线依次排列。
可选的，所述显示基板还包括设置于所述基底上的显示区域内的多行像素电路；所述像素电路包括发光控制端；所述移位寄存器单元还包括信号输出线；
所述移位寄存器单元与所述行像素电路一一对应；
所述移位寄存器单元的信号输出线与相应行像素电路的发光控制端耦接，用于为所述相应行像素电路的发光控制端提供发光控制信号。
可选的，所述信号输出线包括第一输出线部分和第二输出线部分；
所述第一输出线部分位于所述输出电路与所述第二电压信号线之间；
所述第一输出线部分与所述第二输出线部分耦接，所述第一输出线部分沿第一方向延伸，所述第二输出线部分沿第二方向延伸，所述第一方向与所述第二方向相交；
所述第二输出线部分延伸至显示区域，以为位于显示区域中的一行像素电路提供发光控制信号。
可选的，所述输出电路包括输出晶体管和输出复位晶体管；
所述输出复位晶体管和所述输出晶体管沿着第一方向排列；
所述输出复位晶体管的第一电极与所述第二电压信号线耦接，所述输出晶体管的第一电极与所述第一电压信号线耦接；
所述输出晶体管的第二电极和所述输出复位晶体管的第二电极都与所述至少一个移位寄存器单元包括的信号输出线耦接。
可选的，所述输出复位晶体管的有源层沿第二方向上的宽度小于所述输出晶体管的有源层沿第二方向上的宽度；
所述第一方向与所述第二方向相交。
可选的，所述至少一个移位寄存器单元还包括复位控制电路；所述复位控制电路包括复位控制晶体管；所述输出电路包括输出晶体管和输出复位晶体管；
所述复位控制晶体管的栅极与所述输出晶体管的栅极耦接，所述复位控制晶体管的第一电极与所述输出复位晶体管的第一电极耦接，所述复位控制晶体管的第二电极与所述输出复位晶体管的栅极耦接。
可选的，所述复位控制晶体管位于所述输出复位晶体管与所述第一电压信号线之间；
所述复位控制晶体管包括第一有源图形，所述第一有源图形沿第一方向延伸。
可选的，所述第一储能电路包括输出复位电容；所述输出电路包括输出 复位晶体管；
所述输出复位电容的第二极板在所述基底上的正投影在所述输出复位电容的第一极板在所述基底上的正投影之内；
所述输出复位电容的第二极板在所述基底上的正投影与所述第二电压信号线在所述基底上的正投影部分重叠；
所述输出复位电容的第一极板与所述输出复位晶体管的栅极耦接；
所述输出复位电容的第二极板通过极板连接过孔与所述第二电压信号线耦接。
可选的，所述第一防漏电电路包括第一控制晶体管；所述输出电路包括输出晶体管；
所述第一控制晶体管位于所述第一电压信号线远离显示区域的一侧；
所述第一控制晶体管的第一电极与输出晶体管的栅极耦接。
可选的，所述至少一个移位寄存器单元还包括第二防漏电电路；所述第二防漏电电路包括第二控制晶体管，所述第一防漏电电路包括第一控制晶体管；
所述第二控制晶体管位于所述第一电压信号线远离显示区域的一侧；所述第一控制晶体管的栅极和第二控制晶体管的栅极相互耦接；
所述第二控制晶体管的栅极与电极导电连接部耦接，所述电极导电连接部在所述基底上的正投影与所述第一电压信号线在所述基底上的正投影之间存在电极重叠区域，所述电极导电连接部通过设置于所述电极重叠区域的电极连接过孔与所述第一电压信号线耦接。
可选的，所述扫描驱动电路还包括第三电压信号线；所述第三电压信号线用于提供第二电压；所述至少一个移位寄存器单元还包括第三节点控制电路；所述第三节点控制电路包括输入晶体管、第一节点控制晶体管和第二节点控制晶体管；
所述输入晶体管的有源层、所述第一节点控制晶体管的有源层和所述第二节点控制晶体管的有源层由一个连续的第二半导体层形成；
所述第二半导体层沿第一方向延伸；
所述输入晶体管的有源层包括沿第一方向依次设置的第一个第三导电部 分、第三沟道部分和第二个第三导电部分；
所述第二个第三导电部分复用为第一个第四导电部分；
所述第一节点控制晶体管的有源层包括沿第一方向依次设置的第一个第四导电部分、第四沟道部分和第二个第四导电部分；
所述第二个第四导电部分复用为第一个第五导电部分；
所述第二节点控制晶体管的有源层包括沿第一方向依次设置的第一个第五导电部分、第五沟道部分和第二个第五导电部分；
所述输入晶体管的第一电极与输入端耦接，所述第二节点控制晶体管的第一电极与第三电压信号线耦接。
可选的，所述输入晶体管、所述第一节点控制晶体管和所述第二节点控制晶体管位于所述第三电压信号线和所述第一电压信号线之间；
所述第三电压信号线沿第一方向延伸，所述第三电压信号线位于所述第一电压信号线远离显示区域的一侧。
可选的，所述至少一个移位寄存器单元还包括第二储能电路和第二节点控制电路；所述第二储能电路包括第一电容，所述第二节点控制电路包括第三节点控制晶体管和第四节点控制晶体管；
所述第四节点控制晶体管的有源层和所述第三节点控制晶体管的有源层由一个连续的第三半导体层形成；所述第三半导体层沿第一方向延伸；
所述第四节点控制晶体管的有源层包括沿第一方向依次设置的第一个第六导电部分、第六沟道部分和第二个第六导电部分；
所述第二个第六导电部分复用为第一个第七导电部分；
所述第三节点控制晶体管的有源层包括沿第一方向依次设置的第一个第七导电部分、第七沟道部分和第二个第七导电部分；
所述第四节点控制晶体管的栅极与第一节点控制晶体管的栅极耦接，所述第四节点控制晶体管的第二电极与输出复位晶体管的栅极耦接；
所述第三节点控制晶体管的栅极与所述第一电容的第一极板耦接，所述第三节点控制晶体管的第一电极与第一节点控制晶体管的栅极耦接；
所述第二个第六导电部分用作所述第三节点控制晶体管的第二电极以及所述第四节点控制晶体管的第一电极；
所述第四节点控制晶体管的第一电极与所述第一电容的第二极板耦接。
可选的，所述第一电容的第二极板在基底上的正投影在所述第一电容的第一极板在所述基底上的正投影内；
所述第一电容的第二极板在所述基底上的正投影与所述第一电压信号线在所述基底上的正投影部分重叠；
所述第三节点控制晶体管和所述第四节点控制晶体管位于所述第一电容远离显示区域的一侧。
可选的，所述至少一个移位寄存器单元还包括第五节点控制电路，所述第五节点控制电路包括第五节点控制晶体管；
所述第五节点控制晶体管包括第二有源图形，所述第二有源图形为U形结构；
所述第二有源图形包括第一个第五节点控制沟道部分、第二个第五节点控制沟道部分、与所述第一个第五节点控制沟道部分耦接的第一个第五节点控制导电部分，以及，与所述第二个第五节点控制沟道部分耦接的第二个第五节点控制导电部分；
所述第五节点控制晶体管的栅极包括相互耦接的第一栅极图形和第二栅极图形；
所述第一栅极图形与所述第一个第五节点控制沟道部分对应，所述第二栅极图形与所述第二个第五节点控制沟道部分对应；
所述第一个第五节点控制导电部分用作所述第五节点控制晶体管的第二电极，所述第二个第五节点控制导电部分用作所述第五节点控制晶体管的第一电极。
可选的，所述至少一个移位寄存器单元还包括第五节点控制电路，所述第五节点控制电路包括第六节点控制晶体管；
所述第六节点控制晶体管包括第三有源图形，所述第三有源图形沿第一方向延伸。
可选的，所述扫描驱动电路还包括第四电压信号线，所述第四电压信号线用于提供第一电压；所述第一储能电路包括输出电容；
所述输出电容的第二极板在所述基底上的正投影在所述输出电容的第一 极板在所述基底上的正投影之内；
所述输出电容的第二极板在基底上的正投影与所述第四电压信号线在所述基底上的正投影部分重叠；
所述输出电容的第二极板在第二方向上的宽度小于第一预定宽度，所述输出电容的第二极板在第一方向上的长度大于第一预定长度；
所述第四电压信号线沿第一方向延伸。
可选的，所述第一预定宽度为20微米，所述第一预定长度为22微米。
可选的，所述第一储能电路包括输出电容；所述至少一个移位寄存器单元还包括第五节点控制电路，所述第五节点控制电路包括第五节点控制晶体管和第六节点控制晶体管；
所述第五节点控制晶体管和所述第六节点控制晶体管位于所述第三电压信号线与所述第四电压信号线之间；
所述第六节点控制晶体管的第一电极与所述第四电压信号线耦接，所述第六节点控制晶体管的第二电极与所述第五节点控制晶体管的第二电极耦接；
所述第五节点控制晶体管的第一电极与所述第六节点控制晶体管的栅极耦接；
所述输出电容的第二极板在所述基底上的正投影在所述输出电容的第一极板在所述基底上的正投影之内；所述输出电容的第二极板在基底上的正投影与所述第四电压信号线在所述基底上的正投影部分重叠；
所述输出电容的第一极板与所述第五节点控制晶体管的栅极耦接；
所述第三电压信号线与所述第四电压信号线沿第一方向延伸。
可选的，所述扫描驱动电路还包括设置于所述第四电压信号线远离显示区域的第一时钟信号线和第二时钟信号线；
所述输出电容的第二极板与所述第一时钟信号线耦接；
所述第六节点控制晶体管的栅极与所述第二时钟信号线耦接；
所述第一时钟信号线和所述第二时钟信号线都沿第一方向延伸。
可选的，所述扫描驱动电路还包括第三电压信号线、第四电压信号线、第一时钟信号线和第二时钟信号线；所述输出电路包括输出晶体管和输出复位晶体管；所述第一防漏电电路包括第一控制晶体管；所述至少一个移位寄 存器单元还包括信号输出线、第二控制晶体管、输入晶体管、第一节点控制晶体管、第二节点控制晶体管、第三节点控制晶体管、第四节点控制晶体管、第五节点控制晶体管、第六节点控制晶体管和复位控制晶体管；
所述复位控制晶体管、所述输出晶体管和所述输出复位晶体管设置于所述第一电压信号线与所述第二电压信号线之间；
所述第一控制晶体管、所述第二控制晶体管、所述输入晶体管、所述第一节点控制晶体管、所述第二节点控制晶体管、所述第三节点控制晶体管和所述第四节点控制晶体管位于所述第一电压信号线与所述第三电压信号线之间；
所述第五节点控制晶体管和所述第六节点控制晶体管位于所述第三电压信号线与所述第四电压信号线之间；
所述信号输出线包括第一输出线部分和第二输出线部分；
所述第一输出线部分位于所述输出电路与所述第二电压信号线之间；
所述第一输出线部分与所述第二输出线部分耦接，所述第一输出线部分沿第一方向延伸，所述第二输出线部分沿第二方向延伸，所述第一方向与所述第二方向相交；
所述第二输出线部分延伸至显示区域。
可选的，所述第一储能电路包括输出电容和输出复位电容；所述至少一个移位寄存器单元还包括第一电容；
所述第一电容的第二极板在所述基底上的正投影与所述第一电压信号线与所述基底上的正投影部分重叠，或者，所述第一电容位于所述第一电压信号线与所述第四节点控制晶体管之间；
所述第一电容的第二极板在所述基底上的正投影在所述第一电容的第一极板在所述基底上的正投影之间；
所述输出复位电容的第二极板在所述基底上的正投影在所述输出复位电容的第一极板在所述基底上的正投影之内；
所述输出复位电容的第二极板在所述基底上的正投影与所述第二电压信号线在所述基底上的正投影部分重叠；
所述输出电容的第二极板在所述基底上的正投影在所述输出电容的第一 极板在所述基底上的正投影之内；
所述输出电容的第二极板在基底上的正投影与所述第四电压信号线在所述基底上的正投影部分重叠。
在第二个方面中，本公开实施例还提供了一种显示基板的制作方法，所述显示基板的制作方法包括在基底上制作第一电压信号线、第二电压信号线和扫描驱动电路；所述扫描驱动电路包括多个移位寄存器单元，所述多个移位寄存器单元中的至少一个移位寄存器单元包括输出电路、第一储能电路和第一防漏电电路，所述输出电路分别与所述第一电压信号线和所述第二电压信号线耦接，所述第一储能电路分别与所述输出电路与所述第二电压信号线耦接，所述第一防漏电电路与所述输出电路耦接；所述显示基板的制作方法还包括：
将所述第一电压信号线设置于所述第二电压信号线远离显示区域的一侧；
在所述第一电压信号线和所述第二电压信号线之间设置所述输出电路；
将所述第一储能电路在所述基底上的正投影设置为与所述第二电压信号线在所述基底上的正投影部分重叠；
在所述第一电压信号线远离所述第二电压信号线的一侧设置所述第一防漏电电路；
所述第一电压信号线用于提供第一电压，所述第二电压信号线用于提供第二电压。
在第三个方面中，本公开实施例还提供了一种显示装置，包括上述的显示基板。
附图说明
图1是本公开实施例所述的显示基板中的至少一个移位寄存器单元的至少一实施例结构图；
图2是所述移位寄存器单元的至少一实施例的结构图；
图3是所述移位寄存器单元的至少一实施例结构图；
图4是所述移位寄存器单元的至少一实施例的结构图；
图5是所述移位寄存器单元的至少一实施例的结构图；
图6是所述移位寄存器单元的一具体实施例的电路图；
图7是在图6的基础上标示出各晶体管的栅极、第一电极和第二电极，并标示出各电容的第一极板和第二极板的示意图；
图8是图6所示的移位寄存器单元的具体实施例的工作时序图；
图9是本公开至少一实施例所述的显示基板的区域划分示意图；
图10A是本公开至少一实施例所述的显示基板包括的扫描驱动电路与像素电路之间的连接关系示意图；
图10B是本公开至少一实施例提供的显示基板的一种布局示意图；
图11是本公开至少一实施例提供的显示基板的另一种布局示意图；
图12是本公开至少一实施例提供的显示基板中的有源层的示意图；
图13是本公开至少一实施例提供的显示基板中的第一栅金属层的示意图；
图14是本公开至少一实施例提供的显示基板中的第二栅金属层的示意图；
图15是本公开至少一实施例提供的显示基板中采用的过孔的示意图；
图16是本公开至少一实施例提供的显示基板中的源漏金属层的示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开至少一实施例所述的显示基板包括设置于基底上的扫描驱动电路，所述扫描驱动电路包括多个移位寄存器单元。
如图1所示，本公开实施例所述的显示基板中的至少一个移位寄存器单元的至少一实施例可以包括信号输出线E0、输出电路O1、第一储能电路11和第一防漏电电路12；
所述输出电路O1用于在第一节点N1的电位的控制下，控制信号输出线E0接入第一电压V1，并在第二节点N2的电位的控制下，控制所述信号输出线接入第二电压V2；
所述第一储能电路11分别与所述第一节点N1和所述第二节点N2耦接，用于储存电能；
所述第一防漏电电路12与所述第一节点N1耦接，用于当所述第一节点N1的电位变化时，控制所述第一节点N1的电位的变化量的绝对值小于第一预定电压变化量。
在本公开实施例中，所述移位寄存器单元的至少一实施例在工作时，通过采用第一防漏电电路12，能够在当第一节点N1的电位变化时，控制所述第一节点N1的电位的变化量的绝对值小于第一预定电压变化量，以避免第一节点N1的电位变化幅度太大而导致输出电路O1包括的输出晶体管产生漏电而导致输出错误的情况发生。
可选的，所述第一预定电压变化量可以为1V，但不以此为限。
在具体实施时，所述第一电压可以为低电压VL，但不以此为限。
可选的，所述第一防漏电电路可以包括第一控制晶体管；
所述第一控制晶体管的栅极与第一控制电压端耦接，所述第一控制晶体管的第一电极与所述第一节点耦接，所述第一控制晶体管的第二电极与第三节点耦接；
所述第一控制电压端用于提供第一控制电压，以能够控制所述第一控制晶体管打开。
在本公开至少一实施例中，所述第一控制电压可以为低电压VL，但不以为限。
在具体实施时，在图1所示的移位寄存器单元的至少一实施例的基础上，如图2所示，所述移位寄存器单元的至少一实施例还可以包括第二节点控制电路13、第二储能电路14和第二防漏电电路15；
所述第二节点控制电路13分别与第一时钟信号线CB、第四节点N4、第二节点N2和第三节点N3耦接，用于在第一时钟信号线CB提供的第一时钟信号和第四节点N4的电位的控制下，控制所述第二节点N2的电位，并用于在第三节点N3的电位的控制下，控制所述第二节点N2接入第二电压；
所述第二储能电路14与所述第四节点N4耦接，用于储存电能；
所述第二防漏电电路15与所述第四节点N4耦接，用于当所述第四节点 N4的电位变化时，控制所述第四节点N4的电位的变化量的绝对值小于第二预定电压变化量。
可选的，所述的第二预定电压变化量可以为1V，但不以此为限。
在具体实施时，所述第二电压可以为高电压Vh，但不以此为限。
如图2所示的移位寄存器单元的实施例通过采用第二防漏电电路15，能够在当第四节点N4的电位变化时，控制所述第四节点N4的电位的变化量的绝对值小于第一预定电压变化量，以避免第四节点N4的电位变化幅度太大而导致所述移位寄存器单元包括的栅极与所述第四节点N4耦接的晶体管产生漏电。
可选的，所述第二防漏电电路可以包括第二控制晶体管；
所述第二控制晶体管的栅极与第二控制电压端耦接，所述第二控制晶体管的第一电极与所述第四节点耦接，所述第二控制晶体管的第二电极与第五节点耦接；
所述第二控制电压端用于提供第二控制电压，以能够控制所述第二控制晶体管打开。
在本公开至少一实施例中，所述第二控制电压可以为低电压VL，但不以此为限。
在优选情况下，所述移位寄存器单元与位于显示区域中的一行像素电路一一对应；
所述移位寄存器单元与所述行像素电路的发光控制端耦接，用于为所述行像素电路的发光控制端提供发光控制信号。
在本公开至少一实施例中，采用一级移位寄存器单元为单行像素电路提供发光控制信号，可以实现低灰阶显示条件下的PWM(脉宽调制)精细调光，实现更优的显示画面和效果，降低屏幕的低灰阶Mura(不均匀)。
在本公开至少一实施例中，所述输出电路可以包括输出晶体管和输出复位晶体管；
所述输出晶体管的栅极与所述第一节点耦接，所述输出晶体管的第一电极接入第一电压，所述输出晶体管的第二电极与所述信号输出线耦接；
所述输出复位晶体管的栅极与所述第二节点耦接，所述输出复位晶体管 的第一电极接入第二电压，所述输出复位晶体管的第二电极与所述信号输出线耦接；
所述第一储能电路可以包括输出复位电容和输出电容；
所述输出电容的第一极板与所述第一节点耦接，所述输出电容的第二极板与第一时钟信号线耦接；
所述输出复位电容的第一极板与所述第二节点耦接，所述输出复位电容的第二极板接入第二电压。
在具体实施时，如图3所示，在图2所示的移位寄存器单元的实施例的基础上，所述移位寄存器单元的至少一实施例还可以包括复位控制电路16；
所述复位控制电路16分别与第一节点N1和第二节点N2耦接，用于在第一节点N1的电位的控制下，控制所述第二节点N2接入第二电压。
在本公开至少一实施例中，所述移位寄存器单元通过采用复用控制电路16，以能够在第一节点N1的电位控制输出电路包括的输出晶体管打开时，控制第二节点N2接入第二电压，以控制输出电路包括的输出复位晶体管关断。
可选的，所述复位控制电路可以包括复位控制晶体管；
所述复位控制晶体管的栅极与所述第一节点耦接，所述复位控制晶体管的第一电极接入第二电压，所述复位控制晶体管的第二电极与所述第二节点耦接。
在具体实施时，如图4所示，在图3所示的移位寄存器单元的实施例的基础上，所述移位寄存器单元的至少一实施例还可以包括第三节点控制电路17；
所述第三节点控制电路17分别与输入端E1、第二时钟信号线CK、第三节点N3、第五节点N5和第一时钟信号线CB耦接，用于在第二时钟信号线CK提供的第二时钟信号的控制下，控制所述输入端E1与所述第三节点N3之间连通，在所述第五节点N5的电位和第一时钟信号线CB提供的第一时钟信号的控制下，控制所述第三节点N3接入第二电压；
所述第一时钟信号线CB用于提供所述第一时钟信号，所述第二时钟信号线CK用于提供所述第二时钟信号。
在本公开至少一实施例中，所述移位寄存器单元还可以包括第三节点控制电路17，用于控制第三节点N3的电位。
可选的，所述第三节点控制电路可以包括输入晶体管、第一节点控制晶体管和第二节点控制晶体管，其中，
所述输入晶体管的栅极与第二时钟信号线耦接，所述输入晶体管的第一电极与所述输入端耦接，所述输入晶体管的第二电极与所述第三节点耦接；
所述第二节点控制晶体管的栅极与所述第五节点耦接，所述第二节点控制晶体管的第一电极接入第二电压；
所述第一节点控制晶体管的栅极与所述第一时钟信号线耦接，所述第一节点控制晶体管的第一电极与所述第二节点控制晶体管的第二电极耦接，所述第一节点控制晶体管的第二电极与所述第三节点耦接。
在本公开至少一实施例中，如图5所示，在图4所示的移位寄存器单元的实施例的基础上，所述移位寄存器单元的至少一实施例还可以包括第五节点控制电路18；
所述第五节点控制电路18分别与第二时钟信号线CK、第五节点N5和第三节点N3耦接，用于在第二时钟信号的控制下，控制第五节点N5接入第一电压，并在第三节点N3的电位的控制下，控制所述第五节点N5与第二时钟信号线CK之间连通；
所述第二时钟信号线CK用于提供所述第二时钟信号。
在本公开至少一实施例中，所述移位寄存器单元可以采用第五节点控制电路18，以控制第五节点N5的电位。
可选的，所述第二节点控制电路可以包括第三节点控制晶体管和第四节点控制晶体管；所述第二储能电路包括第一电容；
所述第三节点控制晶体管的栅极与所述第四节点耦接，所述第三节点控制晶体管的第一电极与所述第一时钟信号线耦接；
所述第四节点控制晶体管的栅极与所述第一时钟信号线耦接，所述第四节点控制晶体管的第一电极与所述第三节点控制晶体管的第二电极耦接，所述第四节点控制晶体管的第二电极与所述第二节点耦接；
所述第一电容的第一极板与第四节点耦接，所述第一电容的第二极板与 所述第三节点控制晶体管的第二电极耦接。
可选的，所述第五节点控制电路可以包括第五节点控制晶体管和第六节点控制晶体管；
所述第五节点控制晶体管的栅极与所述第三节点耦接，所述第五节点控制晶体管的第一电极与所述第二时钟信号线耦接，所述第五节点控制晶体管的第二电极与所述第五节点耦接；
所述第六节点控制晶体管的栅极与所述第二时钟信号线耦接，所述第六节点控制晶体管的第一电极接入第一电压，所述第六节点控制晶体管的第二电极与所述第五节点耦接。
如图6所示，所述移位寄存器单元的一具体实施例可以包括信号输出线E0、输出电路O1、第一储能电路11、第一防漏电电路12、第二节点控制电路13、第二储能电路14、第二防漏电电路15、复位控制电路16、第三节点控制电路17和第五节点控制电路18；
所述第一防漏电电路12包括第一控制晶体管T12；
所述第一控制晶体管T12的栅极接入低电压VL，所述第一控制晶体管T12的第一电极与所述第一节点N1耦接，所述第一控制晶体管T12的第二电极与第三节点N3耦接；
所述第二防漏电电路15包括第二控制晶体管T11；
所述第二控制晶体管T11的栅极接入低电压VL，所述第二控制晶体管T11的第一电极与所述第四节点N4耦接，所述第二控制晶体管T11的第二电极与第五节点N5耦接；
所述输出电路O1包括输出晶体管T10和输出复位晶体管T9；
所述输出晶体管T10的栅极与所述第一节点N1耦接，所述输出晶体管T10的第一电极接入低电压VL，所述输出晶体管T10的第二电极与所述信号输出线E0耦接；
所述输出复位晶体管T9的栅极与所述第二节点N2耦接，所述输出复位晶体管T9的第一电极接入高电压Vh，所述输出复位晶体管T9的第二电极与所述信号输出线E0耦接；
所述第一储能电路11包括输出复位电容C3和输出电容C2；
所述输出电容C2的第一极板与所述第一节点N1耦接，所述输出电容C2的第二极板与第一时钟信号线CB耦接；
所述输出复位电容C3的第一极板与所述第二节点N2耦接，所述输出复位电容C3的第二极板接入高电压Vh；
所述复位控制电路16包括复位控制晶体管T8；
所述复位控制晶体管T8的栅极与所述第一节点N1耦接，所述复位控制晶体管T8的第一电极接入高电压Vh，所述复位控制晶体管T8的第二电极与所述第二节点N2耦接；
所述第三节点控制电路17包括输入晶体管T1、第一节点控制晶体管T4和第二节点控制晶体管T5，其中，
所述输入晶体管T1的栅极与第二时钟信号线CK耦接，所述输入晶体管T1的第一电极与所述输入端E1耦接，所述输入晶体管T1的第二电极与所述第三节点N3耦接；
所述第二节点控制晶体管T5的栅极与所述第五节点N5耦接，所述第二节点控制晶体管T5的第一电极接入高电压Vh；
所述第一节点控制晶体管T4的栅极与所述第一时钟信号线CB耦接，所述第一节点控制晶体管T4的第一电极与所述第二节点控制晶体管T5的第二电极耦接，所述第一节点控制晶体管T4的第二电极与所述第三节点N3耦接；
所述第二节点控制电路13包括第三节点控制晶体管T6和第四节点控制晶体管T7；所述第二储能电路14包括第一电容C1；
所述第三节点控制晶体管T6的栅极与所述第四节点N4耦接，所述第三节点控制晶体管T6的第一电极与所述第一时钟信号线CB耦接；
所述第四节点控制晶体管T7的栅极与所述第一时钟信号线CB耦接，所述第四节点控制晶体管T7的第一电极与所述第三节点控制晶体管T6的第二电极耦接，所述第四节点控制晶体管T7的第二电极与所述第二节点N2耦接；
所述第一电容C1的第一极板与第四节点N4耦接，所述第一电容C1的第二极板与所述第三节点控制晶体管T6的第二电极耦接；
所述第五节点控制电路18包括第五节点控制晶体管T2和第六节点控制晶体管T3；
所述第五节点控制晶体管T2的栅极与所述第三节点N3耦接，所述第五节点控制晶体管T2的第一电极与所述第二时钟信号线CK耦接，所述第五节点控制晶体管T2的第二电极与所述第五节点N5耦接；
所述第六节点控制晶体管T3的栅极与所述第二时钟信号线CK耦接，所述第六节点控制晶体管T3的第一电极接入低电压VL，所述第六节点控制晶体管T3的第二电极与所述第五节点N5耦接。
在图6所示的移位寄存器单元的实施例中，第一控制电压端和第二控制电压端提供低电压VL，第一电压为低电压VL，第二电压为高电压Vh，但不以此为限。
在图6所示的移位寄存器单元的实施例中，所有的晶体管都为p型晶体管，但不以此为限。
在本公开实施例中，图6所示的移位寄存器单元的实施例可以为发光控制扫描驱动电路中的移位寄存器单元，但不以此为限。
图7在图6的基础上示出了各晶体管的第一电极、各晶体管的第二电极、各晶体管的栅极、各电容的第一极板和各电容的第二极板。
在图7中，标号为G1的为T1的栅极，标号为S1的为T1的第一电极，标号为D1的为T1的第二电极；标号为G2的为T2的栅极，标号为S2的为T2的第一电极，标号为D2的为T2的第二电极；标号为G3的为T3的栅极，标号为S3的为T3的第一电极，标号为D3的为T3的第二电极；标号为G4的为T4的栅极，标号为S4的为T4的第一电极，标号为D4的为T4的第二电极；标号为G5的为T5的栅极，标号为S5的为T5的第一电极，标号为D5的为T5的第二电极；标号为G6的为T6的栅极，标号为S6的为T6的第一电极，标号为D6的为T6的第二电极；标号为G7的为T7的栅极，标号为S7的为T7的第一电极，标号为D7的为T7的第二电极；标号为G8的为T8的栅极，标号为S8的为T8的第一电极，标号为D8的为T8的第二电极；标号为G9的为T9的栅极，标号为S9的为T9的第一电极，标号为D9的为T9的第二电极；标号为G10的为T10的栅极，标号为S10的为T10的第一电极，标号为D10的为T10的第二电极；标号为G11的为T11的栅极，标号为S11的为T11的第一电极，标号为D11的为T11的第二电极；标号为G12的为 T12的栅极，标号为S12的为T12的第一电极，标号为D12的为T12的第二电极；标号为C1a的为C1的第一极板，标号为C1b的为C1的第二极板；标号为C2a的为C2的第一极板，标号为C2b的为C2的第二极板；标号为C3a的为C3的第一极板，标号为C3b的为C3的第二极板。
在本公开至少一实施例中，晶体管的第一电极可以为源极，晶体管的第二电极可以为漏极；或者，晶体管的第一电极可以为漏极，晶体管的第二电极可以为源极。
如图8所示，本公开如图6所示的移位寄存器单元的至少一实施例在工作时，
在第一时间段P1，E1提供高电平，CK提供低电平，T1、T3、T11和T12打开，N3的电位为高电平，T2截止，N5的电位为低电平，T4、T8和T10截止，T5和T6打开；此时所述第四节点控制晶体管T7的第一电极的电位为高电平，CB为高电平，T7截止；由于电容两端电压不会突变，所以N2的电位维持为上一帧的高电平，T9截止，E0输出的发光控制信号的电位维持为上一帧的低电平；
在第二时间段P2，E1和CK提供高电平，CB提供低电平，T1、T2和T3截止，N5的电位保持低电平，T4、T5和T6打开，N3的电位为高电平，所述第四节点控制晶体管T7的第一电极的电位由高电平变为低电平，T7打开，T8截止，N2的电位为低电平，T9打开，E0输出高电平；T12打开，T10截止；
在第三时间段P3，E1和CB都提供高电平，CK提供低电平，T1和T3打开，N3的电位为高电平，N5的电位为低电平，T2和T4截止，T5和T6打开，所述第四节点控制晶体管T7的第一电极的电位由上一时间段的低电平转变为高电平，T7截止，N2的电位由于C3放电而维持为低电平，T9打开，E0输出高电平；T12打开，T8和T10截止；
在第四时间段P4，E1和CB都提供低电平，CK提供高电平，T1和T3截止，N3的电位为高电平，T2截止，N5的电位维持为低电平，T11、T4、T5和T6打开，所述第四节点控制晶体管T7的第一电极的电位跳变为低电平，T7打开，N2的电位为低电平，T9打开，E0输出高电平，T12打开，T8和 T10截止；
在第五时间段P5，E1和CK都提供低电平，CB提供高电平，T1、T2、T3、T11和T12都打开，N3的电位和N5的电位都为低电平，T4截止，T5、T6打开，所述第四节点控制晶体管T7的第一电极的电位变为高电平，T7截止，T8打开，N2的电位变为高电平，T9截止，T10打开，E0输出低电平；
在第六时间段P6，E1和CB都提供低电平，CK提供高电平，T1和T3截止，N3的电位维持为低电平，T2打开，N5的电位为高电平，T11、T12、T4和T5打开，T6截止，所述第四节点控制晶体管T7的第一电极的电位为高电平，T7和T8打开，N2的电位为高电平，T9截止、T10打开，E0输出低电平；
在第七时间段P7，E1和CK都提供低电平，CB提供高电平，T1、T2、T3、T11、T12和T5都打开，N3的电位和N5的电位为低电平，T4截止，T5和T6打开，所述第四节点控制晶体管T7的第一电极的电位为高电平，T7截止，T8打开，N4节点为高电平，T9截止、T10打开，E0输出为低电平；
在第八时间段P8，E1和CB都提供低电平，CK提供高电平，T1和T3截止，N3的电位维持为低电平，T2打开，N5的电位为高电平，T4打开，T5和T6截止，所述第四节点控制晶体管T7的第一电极的电位维持为高电平，T11、T12、T7和T8打开，N2的电位为高电平，T9截止，T10打开，E0输出低电平；
在第七时间段P7之后，T8持续开启，T9截止，T1周期性地给C2充电，N3的电位保持为低电平，T10持续开启，以使得E0输出低电平，直到下一帧输入信号脉冲进入。
在本公开至少一实施例中，所述扫描驱动电路包括多级上述的移位寄存器单元。
在具体实施时，所述扫描驱动电路通常被设计排列在位于显示区中的像素电路两侧，所述扫描驱动电路内部包括了非常多的电容、薄膜晶体管和信号线，非常占据空间结构。因此，需要合理设计器件的摆放位置及共用信号走线，缩减扫描驱动电路占用的空间，方便显示器的边框窄化。
如图9所示，标号为J1的为显示基板，标号为A0的为显示区域，标号 为B1的为第一边缘区域，标号为B2的为第二边缘区域。
在所述显示基板J1的显示区域A0可以设置有多条发光控制线、多条栅线和多条数据线，以及由所述多条栅线和所述多条数据线交叉限定的多个子像素；
在第一边缘区域B1和/或第二边缘区域B2可以设置有扫描驱动电路，所述扫描驱动电路包括多个移位寄存器单元；
所述扫描驱动电路包括的多个移位寄存器单元与所述多条发光控制线一一对应，每个所述移位寄存器单元的信号输出线与对应的发光控制线耦接，用于为对应的发光控制线提供发光控制信号。
在具体实施时，一所述发光控制线与相应行像素电路的发光控制端耦接。
可选的，所述显示基板还包括设置于所述基底上的多行像素电路；所述像素电路包括发光控制端；
所述扫描驱动电路包括的所述移位寄存器单元与所述行像素电路一一对应
所述移位寄存器单元的信号输出线与相应行像素电路的发光控制端耦接，用于为所述相应行像素电路的发光控制端提供发光控制信号。
在本公开至少一实施例中，所述像素电路可以设置于显示基板的显示区域，所述扫描驱动电路可以设置于显示基板的边缘区域。
如图10A所示，标号为Y1的为扫描驱动电路，标号为Y11的为扫描驱动电路Y1包括的第一级移位寄存器单元，标号为Y12的为所述扫描驱动电路Y1包括的第二级移位寄存器单元，标号为Y1N-1的为所述扫描驱动电路Y1包括的第N-1级移位寄存器单元，标号为Y1N的为所述扫描驱动电路Y1包括的第N级移位寄存器单元，N为大于3的整数；
在图10A中，标号为R1的为第一行像素电路，标号为R2的为第二行像素电路，标号为RN-1的为第N-1行像素电路，标号为RN的为第N行像素电路；
Y11与R1相对应，Y12与R2相对应，Y1N-1与RN-1相对应，Y1N与RN相对应；
Y11为R1提供第一行发光控制信号，Y12为R2提供第二行发光控制信 号，Y1N-1为R1N-1提供第N-1行发光控制信号，Y1N为R1N提供第N行发光控制信号。
如图10A所示，在边缘区域，所述显示基板还可以包括栅极驱动电路，所述栅极驱动电路包括多级栅极驱动单元，所述栅极驱动单元与像素行也一一对应，用于为相应行像素提供相应的栅极驱动信号；
在图10A中，标号为Y2的为栅极驱动电路，标号为S21的为栅极驱动电路包括的第一行栅极驱动单元，标号为S22的为栅极驱动电路包括的第二行栅极驱动单元，标号为S2N-1的为栅极驱动电路包括的第N-1行栅极驱动单元，标号为S2N的为栅极驱动电路包括的第N行栅极驱动单元。
在具体实施时，可以通过调整移位寄存器单元中各晶体管、各电容和各信号线的布局方式，缩小移位寄存器单元的占用面积，从而缩小显示基板的边框宽度。
在图10B所示的布局方式中，所述移位寄存器单元的至少一实施例包括输出晶体管T10、输出复位晶体管T9、输出复位电容C3、输出电容C2、复位控制晶体管T8、输入晶体管T1、第一节点控制晶体管T4、第二节点控制晶体管T5、第三节点控制晶体管T6、第四节点控制晶体管T7、第一电容C1、第五节点控制晶体管T2和第六节点控制晶体管T3。
在图10B中，S4复用为D5，D6复用为S7，D7复用为D8；
在图10B中，标示为VGL1的为第一电压信号线，标号为VGH1的为第二电压信号线，标号为VGL2的为第四电压信号线；在图10B所示的布局方式中，采用了三根电压信号线，T9和T10设置于VGL1和VGH1之间，C1、C2、T1、T2、T3、T4、T5、T6、T7和T8设置于VGL1和VGL2之间；
在图10B中，标号为E01的为信号输出线包括的第一输出线部分，标号为E021的为信号输出线包括的第一个第二输出线部分，标号为E022的为信号输出线包括的第二个第二输出线部分，标号为E020为相邻上一级移位寄存器单元的信号输出线包括的第二输出线部分。
在图10B所示的布局方式中，E01分别与E021和E022耦接，E01沿第一方向延伸，E021和E022沿第二方向延伸。
在图11所示的布局方式中，第一电压信号线VGL1用于提供低电压VL， 第二电压信号线VGH用于提供高电压Vh，第三电压信号线VGH2用于提供高电压Vh，第四电压信号线VGL2用于提供低电压VL；
如图11所示，将上述结构的移位寄存单元布局在显示基板的边缘区域，沿着远离显示基板的显示区域的方向，第二电压信号线VGH1、第一电压信号线VGL1、第三电压信号线VGH2和第四电压信号线VGL2依次排列，第二电压信号线VGH1、第一电压信号线VGL1、第三电压信号线VGH2和第四电压信号线VGL2都沿第一方向延伸；
并且，进一步的，在所述第四电压信号线VGL2远离所述第三电压信号线VGH2的一侧，设置有第一时钟信号线CB和第二时钟信号线CK；第二时钟信号线CK和第一时钟信号线CB和起始电压信号线ESTV沿着远离所述显示区域的方向依次排列；第一时钟信号线CB和第二时钟信号线CK都沿着第一方向延伸；
输出电路包括的输出晶体管T10和输出复位晶体管T9，以及复位控制电路包括的复位控制晶体管T8设置于第一电压信号线VGL1和第二电压信号线VGH1之间；沿着第一方向，所述输出复位晶体管T9和所述输出晶体管T10依次排列；
T1、T4、T5、T6、T7、T11和T12可以设置于第一电压信号线VGL1与第三电压信号线VGH2之间；
T2和T3可以设置于第三电压信号线VGH2与第四电压信号线VGL2之间；
输出复位电容C3的第二极板C3b在基底上的正投影，与第二电压信号线VGH1在基底上的正投影部分重叠，输出复位电容C3的第二极板C3b在基底上的正投影在输出复位电容C3的第一极板C3a在基底上的正投影之内；
输出电容C2的第二极板C2b在基底上的正投影，与第四电压信号线VGL2在基底上的正投影部分重叠，输出电容C2的第二极板C2b在基底上的正投影在输出电容C2的第一极板C2a在基底上的正投影之内；
C1的第一极板C1a在基底上的正投影与第一电压信号线VGL1在基底上的正投影部分重叠，C1的第二极板C1b在基底上的正投影在C1的第一极板C1a在基底上的正投影之内；
信号输出线包括第一输出线部分E01和第二输出线部分E02；
所述第一输出线部分E01与所述第二输出线部分E02相互耦接；
所述第一输出线部分E01沿第一方向延伸，第一输出线部分E01位于第二电压信号线VGH1与输出电路O1之间；
所述第二输出线部分E02沿第二方向延伸，所述第二输出线部分E02延伸至显示基板的显示区域，以为相应行像素电路的发光控制端提供发光控制信号；
T1、T4和T5沿第一方向依次排列，T7、T6和T12沿第一方向依次排列，C1和T11沿第一方向依次排列；
T1、T7和C1沿第二方向依次排列；
T3和T2沿第一方向依次排列，T2的有源图形设置为U形结构，以使得T2形成为双栅结构。
在本公开至少一实施例中，所述第一方向与所述第二方向相交，例如，所述第一方向可以与所述第二方向垂直，但不以此为限。
具体的，所述第二方向与所述第一方向相交的夹角可以根据实际需要设置，示例性的，所述第二方向与所述第一方向垂直。
在本公开至少一实施例中，第一时钟信号线CB的位置和所述第二时钟信号线CK的位置可以对调，但不以此为限。
例如，在如图11所示的布局方式中，第一方向可以为从上至下的垂直方向，第二方向可以为从左至右的水平方向，但不以此为限。
在实际操作时，信号线宽度主要会对电阻产生影响，较宽的信号线电阻小，有利于信号稳定。其中，第一电压信号线VGL1、第二电压信号线VGH1、第三电压信号线VGH2和第四电压信号线VGL2提供的是直流电压，受线宽影响较小。而第一时钟信号线CB和第二时钟信号线CK提供的是时钟信号，当该时钟信号的电位由高电压转换为低电压时，电阻小的时钟信号线更容易使得该时钟信号的电位迅速达到低电压，因此，在本公开至少一实施例中，可以将所述第一时钟信号线CB的线宽和所述二时钟信号线的线宽设置为较宽，但不以此为限。
在本公开图11所示的布局方式中，由于输出复位晶体管T9的第一电极 S9与第二电压信号线VGH1耦接，输出晶体管T10的第一电极S10与第一电压信号线VGL1耦接，所述输出晶体管T10的第二电极D10和所述输出复位晶体管T9的第二电极D9都与所述至少一个移位寄存器单元包括的信号输出线中的第一输出线部分E01耦接；所述复位控制晶体管T8的栅极G8与所述输出晶体管T10的栅极G10耦接，所述复位控制晶体管T8的第一电极S8与所述输出复位晶体管T9的第一电极S9耦接，所述复位控制晶体管T8的第二电极D8与所述输出复位晶体管T9的栅极G8耦接，因此将T8、T9、T10和E01都设置于VGL1和VGH1之间，并将T9的有源图形的沿第二方向的宽度设置为小于T19的有源图形的沿第二方向的宽度，利用T9与VGL1之间的空间设置T8，并将T8的有源图形设置为沿第一方向延伸，从而可以收窄移位寄存单元的第二方向上的宽度。
在本公开至少一实施例中，图11所示的移位寄存器单元可以为扫描驱动电路包括的第n级移位寄存器单元，n为正整数。
在本公开图11所示的布局方式中，T1的有源层、T4的有源层和T5的有源层由一个连续的第二半导体层形成，所述第二半导体层沿第一方向延伸，从而能够减少T1、T4和T5占用的第二方向上的空间，利于实现窄边框；T7的有源层和T6的有源层由一个连续的第三半导体层形成，第三半导体层沿第一方向延伸，从而能够减少T7和T6占用的第二方向上的空间，利于实现窄边框；
在本公开图11所示的布局方式中，T1的第二电极D1复用为T4的第二电极，T4的第一电极S1复用为T5的第二电极；
在本公开图11所示的布局方式中，T7的第一电极S1复用为T6的第二电极；
在本公开图11所示的布局方式中，将C1、T6和T7上移，以利用多出来的纵向的空间设置用于降噪的T11和T12；
在本公开图11所示的布局方式中，将T3的有源图形设置为沿第一方向延伸，以节省T3在第二方向上占用的空间；
在本公开图11所示的布局方式中，将T2的有源图形设置为U形结构，以使得T2形成为双栅结构；双栅结构设计的目的在于：在第二阶段P2，扫 描驱动电路包括的移位寄存器单元输出高电压信号Vgh时，T10应完全关闭，而T10的栅极接入的高电平由T5的源极输入。因此，在第二阶段P2，应务必保证T5打开，即需要使得第五节点N5的电位为低电压；而在第二阶段P2，T2栅极的电位为高电压，为保证T2不漏电造成第二节点N2电位升高，因此将T2设置为采用双栅设计，使得T2更容易关断。
由于在实际生产曝光中，如果将T2的有源图形设置为不带缺角的U字形，会在曝光后沉积金属，会使得该U字形的有源图形为V字形。因此，在实际产品中，考虑到实际生产曝光过程，U字形的有源图形内侧在两个直角部分挖了一小部分进行补偿，尽量使实际图案为U字形，不对T2的宽长比产生影响。
并且，在本公开图11所示的布局方式中，将C3的极板设置为与VGH1交叠，将C2的极板设置为与VGL2交叠，以减少移位寄存器单元占用的第二方向上的空间，利于实现窄边框；
在在本公开图11所示的布局方式中，将C1的极板在基底上的正投影设置为与VGL1在基底上的正投影部分重叠，以减少移位寄存器单元占用的第二方向上的空间，利于实现窄边框。
如图11所示，本公开至少一实施例所述的显示基板包括设置于基底上的扫描驱动电路，所述扫描驱动电路包括多个移位寄存器单元，所述多个移位寄存器单元中的至少一个移位寄存器单元为上述的移位寄存器单元；所述扫描驱动电路还包括第一电压信号线VGL1和第二电压信号线VGH1；
所述第一电压信号线VGL1位于所述第二电压信号线VGL2远离显示区域的一侧；
所述至少一个移位寄存器单元包括输出电路O1、第一储能电路和第一防漏电电路12；
所述输出电路O1分别与所述第一电压信号线VGL1和所述第二电压信号线VGH1耦接，所述第一储能电路分别与所述输出电路O1与所述第二电压信号线VGH1耦接，所述第一防漏电电路12与所述输出电路O1耦接；
所述输出电路O1设置于所述第一电压信号线VGL1和所述第二电压信号线VGH1之间；
所述第一储能电路在基底上的正投影与所述第二电压信号线VGH1在所述基底上的正投影部分重叠；
所述第一防漏电电路12设置于所述第一电压信号线VGL1远离所述第二电压信号线VGH1的一侧；
所述第一电压信号线VGL1用于提供第一电压，所述第二电压信号线VGH2用于提供第二电压。
在具体实施时，所述第一电压信号线VGL1和所述第二电压信号线VGH1可以沿着第一方向延伸。
如图6、图11-图16所示，所述第一储能电路可以包括输出复位电容C3和输出电容C2。
由于输出电路O1分别与第一电压信号线VGL1和第二电压信号线VGH1耦接，因此本公开至少一实施例所述的显示基板将输出电路O1设置于第一电压信号线VGL1和第二电压信号线VGH1之间，以能够减短输出电路O1与第一电压信号线VGL1之间的连接线的长度，并能够减短输出电路O1与第二电压信号线VGH1之间的连接线的长度，从而能够合理布局输出电路O1、第一电压信号线VGL1和第二电压信号线VGH1。
并本公开至少一实施例所述的显示基板将所述第一储能电路在所述基底上的正投影设置为与所述第二电压信号线VGH1在所述基底上的正投影部分重叠，以减少移位寄存器单元在第二方向上的宽度，利于实现窄边框，并方便第一储能电路与第二电压信号线VGH1耦接。
在本公开至少一实施例所述的显示基板中，所述至少一个移位寄存器单元可以包括第一防漏电电路12，以防止输出电路O1包括的输出晶体管漏电，本公开至少一实施例将所述第一防漏电电路12设置于所述第一电压信号线VGL1远离所述第二电压信号线VGH1的一侧，使得所述第一防漏电电路12可以方便的与第一电压信号线VGL1耦接。在具体实施时，所述第二电压信号线VGH1可以位于所述输出电路O1靠近显示区域的一侧，所述第一电压信号线VGL1可以位于所述输出电路O1远离显示区域的一侧；
所述第一电压信号线VGL1和所述第二电压信号线VGH1沿第一方向延伸。
在本公开至少一实施例中，如图11所示，所述扫描驱动电路还包括第三电压信号线VGH2和第四电压信号线VGL2，所述第四电压信号线VGL2用于提供第一电压；所述第三电压信号线VGH2用于提供第二电压；所述第三电压信号线VGH2位于所述第一电压信号线VGL1远离显示区域的一侧，所述第四电压信号线VGL2位于所述第三电压信号线VGH2远离显示区域的一侧；
所述第一储能电路在所述基底上的正投影与所述第四电压信号线VGL2在所述基底上的正投影部分重叠；
所述第一防漏电电路12位于所述第一电压信号线VGL1与所述第三电压信号线VGH2之间。
如图6、图11-图16所示，所述第一储能电路可以包括输出复位电容C3和输出电容C2。
本公开至少一实施例所述的显示基板将所述第一储能电路在所述基底上的正投影设置为与所述第四电压信号线VGL2在所述基底上的正投影部分重叠，以减少移位寄存器单元在第二方向上的宽度，利于实现窄边框。
在具体实施时，所述第一电压信号线VGL1、所述第二电压信号线VGH1、所述第三电压信号线VGH2和所述第四电压信号线VGL2都沿第一方向延伸。
在本公开至少一实施例中，如图11所示，所述至少一个移位寄存器单元还包括复位控制电路16；所述复位控制电路与所述输出电路O1耦接；
所述复位控制电路16设置于所述第一电压信号线VGL1和所述第二电压信号线VGH1之间。
由于所述复位控制电路16与所述输出电路O1耦接，因此本公开至少一实施例所述的显示基板将输出电路O1和复位控制电路16都设置于第一电压信号线VGL1和第二电压信号线VGH1之间，以能够方便复位控制电路16与输出电路O1耦接，从而能够合理布局输出电路O1、复位控制电路16、第一电压信号线VGL1和第二电压信号线VGH1。
如图6、图11-图16所示，所述复位控制电路16可以包括复位控制晶体管T8。
在具体实施时，所述至少一个移位寄存器单元还可以包括第二节点控制 电路、第二储能电路和第二防漏电电路；
所述第二节点控制电路与第二储能电路耦接；所述第二防漏电电路分别与第一防漏电电路和所述第一电压信号线耦接；
所述第二节点控制电路设置于所述第一电压信号线远离所述第二电压信号线的一侧；
所述第二储能电路在所述基底上的正投影与所述第一电压信号线在所述基底上的正投影部分重叠；
所述第二防漏电电路位于所述第一电压信号线远离所述第二电压信号线的一侧。
在本公开至少一实施例中，所述第二防漏电电路分别与第一电压信号线和所述第一防漏电电路耦接，因此将所述第二防漏电电路和所述第一防漏电电路都设置于所述第一电压信号线远离所述第二电压信号线的一侧，方便所述第一防漏电电路与所述第二防漏电电路耦接，也方便所述第二防漏电电路与所述第一电压信号线耦接。
在本公开至少一实施例中，所述第二储能电路在所述基底上的正投影与所述第一电压信号线在所述基底上的正投影部分重叠，以缩窄移位寄存器单元占用的第二方向上的空间，利于实现窄边框。
在本公开至少一实施例中，将所述第二节点控制电路设置于所述第一电压信号线远离所述第二电压信号线的一侧，便于所述第二节点控制电路与第二储能电路耦接。
如图6、图11-图16所示，所述第二防漏电电路可以包括第二控制晶体管T11，所述第二储能电路可以包括第一电容C1，所述所述第二节点控制电路可以包括第三节点控制晶体管T6和第四节点控制晶体管T7。
在具体实施时，所述至少一个移位寄存器单元还可以包括第三节点控制电路；所述第三节点控制电路位于第一电压信号线远离所述第二电压信号线的一侧。
如图6、图11-图16所示，所述第三节点控制电路可以包括输入晶体管T1、第一节点控制晶体管T4和第二节点控制晶体管T5。
如图11所示，所述扫描驱动电路还可以包括第三电压信号线VGH2；所 述第三电压信号线VGH2位于所述第一电压信号线VGL1远离显示区域的一侧；所述第三节点控制电路与所述第三电压信号线VGH2耦接；
所述第三节点控制电路位于所述第一电压信号线VGL1与所述第三电压信号线VGH2之间，以便于所述第三节点控制电路与所述第三电压信号线VGH2耦接。
在本公开至少一实施例中，如图11所示，所述至少一个移位寄存器单元还包括第五节点控制电路；所述扫描驱动电路还包括第三电压信号线VGH2和第四电压信号线VGL2；所述第三电压信号线VGH2位于所述第一电压信号线VGL1远离显示区域的一侧，所述第四电压信号线VGL2位于所述第三电压信号线远离显示区域的一侧；
所述第五节点控制电路分别与所述第四电压信号线VGL2和所述第一储能电路耦接；
所述第五节点控制电路位于所述第三电压信号线VGH2与所述第四电压信号线VGL2之间。
如图6、图11-图16所示，所述第五节点控制电路可以包括第五节点控制晶体管T2和第六节点控制晶体管T3，所述第一储能电路可以包括输出复位电容C3和输出电容C2。
如图11-图16所示，本公开至少一实施例将第五节点控制电路位于所述第三电压信号线VGH2与所述第四电压信号线VGL2之间，以便于所述五节点控制电路分别与所述第四电压信号线VGL2和所述第一储能电路包括的输出电容C2耦接。
如图11所示，所述扫描驱动电路还包括设置于所述第四电压信号线VGL2远离显示区域的第一时钟信号线CB和第二时钟信号线CK；
所述第一储能电路与所述第一时钟信号线CB耦接；
所述第一时钟信号线CB和所述第二时钟信号线CK都沿第一方向延伸。
如图6、图11-图16所示，所述第一储能电路可以包括输出复位电容C3和输出电容C2，所述输出电容C2的第二极板C2b与所述第一时钟信号线CB耦接。
如图11-图16所示，沿着远离显示区域的方向，所述第二电压信号线、 所述第一电压信号线、所述第三电压信号线、所述第四电压信号线、所述第二时钟信号线和所述第一时钟信号线依次排列；或者，
沿着远离显示区域的方向，所述第二电压信号线、所述第一电压信号线、所述第三电压信号线、所述第四电压信号线、所述第一时钟信号线和所述第二时钟信号线依次排列。
在具体实施时，所述显示基板还可以包括设置于所述基底上的显示区域内的多行像素电路；所述像素电路可以包括发光控制端；所述移位寄存器单元还包括信号输出线；
所述移位寄存器单元与所述行像素电路一一对应；
所述移位寄存器单元的信号输出线与相应行像素电路的发光控制端耦接，用于为所述相应行像素电路的发光控制端提供发光控制信号。
本公开至少一实施例采用一级移位寄存器单元为单行像素电路提供发光控制信号，可以实现低灰阶显示条件下的PWM(脉宽调制)精细调光，实现更优的显示画面和效果，降低屏幕的低灰阶Mura(不均匀)。如图11所示，所述信号输出线可以包括第一输出线部分E01和第二输出线部分E02；
所述第一输出线部分E01位于所述输出电路O1与所述第二电压信号线VGH1之间；
所述第一输出线部分E01与所述第二输出线部分E02耦接，所述第一输出线部分E01沿第一方向延伸，所述第二输出线部分E02沿第二方向延伸，所述第一方向与所述第二方向相交；
所述第二输出线部分E02延伸至显示区域，以为位于显示区域中的一行像素电路提供发光控制信号。
可选的，所述输出电路可以包括输出晶体管和输出复位晶体管；
所述输出复位晶体管和所述输出晶体管沿着第一方向排列；
所述输出复位晶体管的第一电极与所述第二电压信号线耦接，所述输出晶体管的第一电极与所述第一电压信号线耦接；
所述输出晶体管的第二电极和所述输出复位晶体管的第二电极都与所述至少一个移位寄存器单元包括的信号输出线耦接。
在本公开至少一实施例中，所述输出复位晶体管的有源层沿第二方向上 的宽度可以小于所述输出晶体管的有源层沿第二方向上的宽度；
所述第一方向与所述第二方向相交。
本公开至少一实施例通过将所述输出复位晶体管的有源层沿第二方向上的宽度设置为小于所述输出晶体管的有源层沿第二方向上的宽度，以能够将复位控制电路设置于节省出来的第二方向上的空间，以减少移位寄存器单元在第二方向上的宽度，利于实现窄边框。
可选的，所述至少一个移位寄存器单元还包括复位控制电路，所述复位控制电路包括复位控制晶体管；
所述复位控制晶体管的栅极与所述输出晶体管的栅极耦接，所述复位控制晶体管的第一电极与所述输出复位晶体管的第一电极耦接，所述复位控制晶体管的第二电极与所述输出复位晶体管的栅极耦接。
如图7和图11所示，所述输出电路O1可以包括输出晶体管T10和输出复位晶体管T9；所述复位控制电路16可以包括复位控制晶体管T8；
所述输出复位晶体管T9和所述输出晶体管T10从上至下依次排列；
所述输出复位晶体管T9的第一电极S9与所述第二电压信号线VGH1耦接，所述输出晶体管T10的第一电极S10与所述第一电压信号线VGL1耦接；
所述输出晶体管T10的第二电极D10和所述输出复位晶体管T9的第二电极D9都与所述信号输出线包括的第一输出线部分E01耦接；
所述复位控制晶体管T8的栅极G8与所述输出晶体管T10的栅极G8耦接，所述复位控制晶体管T8的第一电极S8与所述输出复位晶体管G9的第一电极S9耦接，所述复位控制晶体管T8的第二电极D8与所述输出复位晶体管T9的栅极G9耦接。
在本公开至少一实施例中，输出复位晶体管T9用于提供无效的发光控制信号，输出晶体管T10用于提供有效的发光控制信号。
在本公开至少一实施例中，所述有效的发光控制信号可以为能够使得像素电路中的发光控制晶体管打开的电压信号(所述发光控制晶体管的栅极与所述发光控制线耦接)，所述无效的发光控制信号可以为能够使得所述发光控制晶体管关断的电压信号。
具体的，所述显示基板的显示区域包括多个子像素；所述多个子像素中 的至少一个包括像素驱动电路；所述像素驱动电路包括晶体管、栅线、发光控制线和数据线；所述扫描驱动电路包括的多个移位寄存器单元与多条发光控制线一一对应，每个所述移位寄存器单元的信号输出线与对应的发光控制线耦接，用于为对应的发光控制线提供发光控制信号。
在本公开至少一实施例中，所述输出晶体管的有源层和所述输出复位晶体管的有源层由一个连续的第一半导体层形成；
所述第一半导体层与所述信号输出线沿第一方向排列。
在具体实施时，所述输出晶体管的有源层和所述输出复位晶体管的有源层可以由一个连续的第一半导体层形成，但不以此为限。
在本公开至少一实施例中，所述输出晶体管的有源层和所述输出复位晶体管的有源层可以由一个连续的第一半导体层形成；
所述输出复位晶体管的有源层包括沿第一方向相对设置的至少两个第一导电部分，以及至少一个第一沟道部分；每一所述第一沟道部分设置于两相邻的第一导电部分之间；
所述输出晶体管的有源层可以包括沿第一方向相对设置的至少两个第二导电部分，以及至少一个第二沟道部分；每一所述第二沟道部分设置于两相邻的所述第二导电部分之间；
所述输出复位晶体管的有源层中与所述输出晶体管的有源层距离最近的第一导电部分可以复用为所述输出晶体管中的第二导电部分，这样能够进一步缩小所述输出晶体管和输出复位晶体管的布局空间，有利于实现所述显示基板的窄边框化。
如图12所示，所述输出复位晶体管T9的有源层和所述输出晶体管T10的有源层可以由一个连续的第一半导体层10形成；
所述输出复位晶体管T9的有源层包括沿第一方向相对设置的第一个第一导电部分111、第二个第一导电部分112和第三个第一导电部分113，所述输出复位晶体管T9的有源层还包括第一个第一沟道部分121、第二个第一沟道部分122和第三个第一沟道部分123；
所述第一个第一沟道部分121设置于所述第一个第一导电部分111和所述第二个第一导电部分112之间，所述第二个第一沟道部分122设置于所述 第二个第一导电部分112和所述第三个第一导电部分113之间；所述第三个第一沟道部分123设置于所述第三个第一导电部分113与第四个第一导电部分之间；
所述输出晶体管T10的有源层还包括沿第一方向相对设置的第一个第二导电部分131、第二个第二导电部分132和第三个第二导电部分133，所述输出晶体管T10的有源层还包括第一个第二沟道部分141和第二个第二沟道部分142；
所述第一个第二导电部分131复用为第四个第一导电部分；
所述第一个第二沟道部分141设置于第一个第二导电部分131与第二个第二导电部分132之间，所述第二个第二沟道部分142设置于所述第二个第二导电部分132和第三个第二导电部分133之间。
在所述输出复位晶体管T9和所述输出晶体管T10中，每个晶体管的沟道部分两侧的导电部分，可以分别对应作为该晶体管的第一电极和第二电极，或者可以分别与该晶体管的第一电极和该晶体管的第二电极耦接，从而使得T9和T10可以通过第三个第一导电部分113实现电连接。
在制作所述第一半导体层10时，示例性的，可以先形成第一半导体材料层，然后在形成输出复位晶体管T9的栅极G9和输出晶体管T10的栅极G10之后，以输出复位晶体管T9的栅极G9和输出晶体管T10的栅极G10为掩膜，对第一半导体材料层中未被各晶体管的栅极覆盖的部分进行掺杂，使得所述第一半导体材料层中未被各晶体管的栅极覆盖的部分形成为所述导电部分，所述第一半导体材料层中被各晶体管覆盖的部分形成为所述沟道部分。
根据上述显示基板的具体结构可知，本公开至少一实施例所述的显示基板中，移位寄存器单元中的所述输出复位晶体管T9和输出晶体管T10能够沿着所述第一方向排列，缩小了移位寄存器单元在第二方向上占用的面积，从而使得所述显示基板更符合窄边框化的发展需求。
具体的，所述输出复位晶体管的栅极可以包括至少一个输出复位栅极图形，所述输出复位晶体管的第一电极包括至少一个第一电极图形，所述输出复位晶体管的第二电极包括至少一个第二电极图形；
所述输出复位栅极图形位于相邻的所述第一电极图形和所述第二电极图 形之间；
所述第二电极图形、所述输出复位栅极图形和所述第一电极图形都沿着第二方向延伸；
所述第一方向与所述第二方向相交。
具体的，所述输出晶体管的栅极可以包括至少两个沿第一方向排列的输出栅极图形，所述输出晶体管的第一电极包括至少一个第三电极图形，所述输出晶体管的第二电极包括至少一个第四电极图形；
所述输出复位栅极图形位于相邻的所述第三电极图形和所述第四电极图形之间；
所述第四电极图形、所述输出栅极图形和所述第三电极图形都沿着第二方向延伸；
所述第一方向与所述第二方向相交；
所述输出晶体管中最靠近所述输出复位晶体管的栅极的所述第四电极图形复用为所述输出复位晶体管的第二电极图形。
在具体实施时，所述输出复位栅极图形的数量、所述第一电极图形的数量、所述第二电极图形的数量、所述输出栅极图形的数量、所述第三电极图形的数量和所述第四电极图形的数量可以根据实际需要设置。示例性的，如图13和图16所示，所述输出栅极图形的数量可以为两个，所述输出复位栅极图形的数量可以为三个，第一电极图形的数量可以为两个，第二电极图形的数量可以为两个，第三电极图形的数量可以为一个，第四电极图形的数量可以为两个，但不以此为限。
并且，由于所述输出晶体管的第二电极和输出复位晶体管的第二电极都与信号输出线耦接，因此，在布局输出晶体管和输出复位晶体管时，可以将所述输出晶体管中最靠近所述输出复位晶体管的栅极的所述第四电极图形复用为所述输出复位晶体管的第二电极图形，这样能够进一步缩小输出晶体管和输出复位晶体管的布局空间，有利于实现显示基板的窄边框化。
如图11和图13所示，在一些实施例中，所述输出复位晶体管T9的栅极G9可以包括：第一输出复位栅极图形G91、第二输出复位栅极图形G92和第三输出复位栅极图形G93；
所述输出晶体管T10的栅极G10可以包括：第一输出栅极图形G101和第二输出栅极图形G102；
所述第一输出复位栅极图形G91、所述第二输出复位栅极图形G92、所述第三输出复位栅极图形G93、所述第一输出栅极图形G101和所述第二输出栅极图形G102沿第一方向依次排列；
所述第一输出复位栅极图形G91、所述第二输出复位栅极图形G92、所述第三输出复位栅极图形G93、所述第一输出栅极图形G101和所述第二输出栅极图形G102都沿第二方向延伸，第二方向与第一方向相交；
所述第一输出复位栅极图形G91、所述第二输出复位栅极图形G92和所述第三输出复位栅极图形G93相互耦接，所述第一输出栅极图形G101和所述第二输出栅极图形G102相互耦接；
如图16所示，所述输出复位晶体管T9的第一电极S9包括第一个第一电极图形S91和第二个第一电极图形S92；
所述输出复位晶体管T9的第二电极D9包括第一个第二电极图形D91；
S91、D91和S92沿第一方向依次排列，并且，S91、D91和S92都沿第二方向延伸，S91和S92都与第二电压信号线VGH2耦接；
第一个第四电极图形D101复用为所述输出复位晶体管T9的第二电极D9包括的第二个第二电极图形；所述输出晶体管T10的第二电极D10包括第一个第四电极图形D101和第二个第四电极图形D102；
D101、S10和D102沿第一方向依次排列，D101、S10和D102都沿第二方向延伸；
S10与第一电压信号线VGL1耦接；
如图11、图13、图16所示，G91在所述基底上的正投影设置于S91在基底上的正投影与D91在基底上的正投影之间，G92在所述基底上的正投影设置于D91在基底上的正投影与S92在基底上的正投影之间，G93在所述基底上的正投影设置于S92在基底上的正投影与D101在基底上的正投影之间；
G101在所述基底上的正投影设置于D101在基底上的正投影与S10在基底上的正投影之间，G102在所述基底上的正投影设置于S10在基底上的正投影与D102在基底上的正投影之间。
在本公开至少一实施例中，扫描驱动电路包括的至少一个移位寄存器单元在工作时，当T10开启时，所述移位寄存器单元持续输出低电压信号，为了保持T10的栅极接入的电压信号稳定，应避免T10的栅极G10与时钟信号线交叠。
在具体实施时，所述输出复位晶体管的有源层可以包括沿第一方向相对设置的至少两个第一导电部分，以及至少一个第一沟道部分；每一所述第一沟道部分设置于两相邻的所述第一导电部分之间；
所述第一沟道部分与所述输出复位栅极图形一一对应，每个所述第一沟道部分在所述基底上的正投影，均位于对应的所述输出复位栅极图形在所述基底上的正投影的内部；
所述输出复位晶体管中的一部分所述第一导电部分与所述第一电极图形一一对应，所述第一电极图形在所述基底上的正投影，与对应的所述第一导电部分在所述基底上的正投影存在第一重叠区域，所述第一电极图形通过设置在所述第一重叠区域的至少一个第一过孔与对应的所述第一导电部分耦接；
所述输出复位晶体管中的另一部分所述第一导电部分与所述第二电极图形一一对应，所述第二电极图形在所述基底上的正投影，与对应的所述第一导电部分在所述基底上的正投影存在第二重叠区域，所述第二电极图形通过设置在所述第二重叠区域的至少一个第二过孔与对应的所述第一导电部分耦接。
在具体实施时，所述输出晶体管的有源层可以包括沿第一方向相对设置的至少两个第二导电部分，以及至少一个第二沟道部分；每一所述第二沟道部分设置于两相邻的所述第二导电部分之间；
所述第二沟道部分与所述输出栅极图形一一对应，每个所述第二沟道部分在所述基底上的正投影，均位于对应的所述输出栅极图形在所述基底上的正投影的内部；
所述输出晶体管中的一部分所述第二导电部分与所述第三电极图形一一对应，所述第三电极图形在所述基底上的正投影，与对应的所述第二导电部分在所述基底上的正投影存在第三重叠区域，所述第三电极图形通过设置在所述第三重叠区域的至少一个第三过孔与对应的所述第二导电部分耦接；
所述输出晶体管中的另一部分所述第二导电部分与所述第四电极图形一一对应，所述第四电极图形在所述基底上的正投影，与对应的所述第二导电部分在所述基底上的正投影存在第四重叠区域，所述第四电极图形通过设置在所述第四重叠区域的至少一个第四过孔与对应的所述第二导电部分耦接。
如图12、图13、图15和图16所示，第一个第一沟道部分121与第一输出复位栅极图形G91对应，第二个第一沟道部分122与第二输出复位栅极图形G92对应，第三个第一沟道部分123与第三输出复位栅极图形G93对应；
第一个第一沟道部分121在基底上的正投影，位于G91在基底上的正投影的内部；
第二个第一沟道部分122在基底上的正投影，位于G92在基底上的正投影的内部；
第三个第一沟道部分123在基底上的正投影，位于G93在基底上的正投影的内部；
第一个第一导电部分111与第一个第一电极图形S91对应，第二个第一导电部分112与第一个第二电极图形D91对应，第三个第一导电部分113与第二个第一电极图形S92对应；
S91在基底上的正投影，与第一个第一导电部分111在基底上的正投影存在第一个第一重叠区域，S91通过设置于所述第一个第一重叠区域的至少一个第一过孔H1与第一个第一导电部分111耦接；
D91在基底上的正投影，与第二个第一导电部分112在基底上的正投影存在第一个第二重叠区域，D91通过设置于所述第一第二重叠区域中的至少一个第二过孔H2与第二个第一导电部分112耦接；
S92在基底上的正投影，与第三个第一导电部分113在基底上的正投影存在第二个第一重叠区域，S92通过设置于所述第二个第一重叠区域中的至少一个第一过孔H1与第三个第一导电部分113耦接；
第一个第二沟道部分141与第一输出栅极图形G101对应，第二个第二沟道部分142与第二输出栅极图形G102对应；
第一个第二沟道部分141在基底上的正投影，位于G101在基底上的正投影的内部；
第二个第二沟道部分142在基底上的正投影，位于G102在基底上的正投影的内部；
D101复用为第二个第二电极图形；第三个第一导电部分113复用为第一个第二导电部分；
第一个第二导电部分131与第一个第四电极图形D101对应；
第二个第二导电部分132与输出晶体管的第一电极S10对应，第三个第二导电部分133与第二个第四电极图形D102对应；
D101在基底上的正投影，与第一个第二导电部分131在基底上的正投影存在第一个第四重叠区域，D102通过设置于所述第一个第四重叠区域中的至少一个第四过孔H4与第一个第二导电部分131耦接；
S10在基底上的正投影，与第二个第二导电部分132在基底上的正投影存在第三重叠区域，S10通过设置于所述第三重叠区域的至少一个第三过孔H3与第二个第二导电部分132耦接；D102在基底上的正投影，与第三个第二导电部分133在基底上的正投影存在第二个第四重叠区域，D102通过设置于所述第二个第四重叠区域中的至少一个第四过孔H4与第三个第二导电部分133耦接。
在本公开至少一实施例中，第一过孔的数量、第二过孔的数量、第三过孔的数量和第四过孔的数量可以根据实际需要设置。
上述实施例提供的显示基板中，利用第一半导体层10形成输出复位晶体管T9的有源层和输出晶体管T10的有源层，不仅使得T9和T10在第二方向上占用的空间较小，而且可以通过增加输出复位晶体管T9的有源层和输出晶体管T10的有源层在第一方向上的尺寸，来保证T9的沟道宽度和T10的沟道宽度，从而实现在保证T9的工作性能和T10的工作性能的情况下，缩小显示基板的边框宽度。
如图11、图12和图14所示，信号输出线中的第一输出线部分E01在基底上的正投影在所述第一半导体层10在所述基底上的正投影与第二电压信号线VGH1在所述基底上的正投影之间，以方便输出晶体管的第二电极和输出复位晶体管的第二电极与所述信号输出线耦接。
在本公开至少一实施例中，图12是图11中的有源层的示意图，图13是 图11中的第一栅金属层的示意图，图14是图11中的第二栅金属层的示意图，图15是依次设置了有源层、第一栅金属层和第二栅金属层之后制作的过孔的示意图，图16是图11中的源漏金属层的示意图。
在具体实施时，在基底上依次设置有源层、第一栅金属层、第二栅金属层、过孔和源漏金属层，以形成显示基板。
在本公开至少一实施例中，所述至少一个移位寄存器单元除了包括输出晶体管和输出复位晶体管之外，还可以包括多个晶体管；每个晶体管的沟道部分两侧的导电部分，可以分别对应作为该晶体管的第一电极和第二电极，或者可以分别与该晶体管的第一电极和该晶体管的第二电极耦接。
在本公开至少一实施例中，如图12所示，所述复位控制晶体管T8可以位于所述输出复位晶体管T9与所述第一电压信号线VGL1之间，所述输出复位晶体管T9的有源层沿第二方向上的宽度可以小于所述输出晶体管T10的有源层沿第二方向上的宽度；
所述第一方向与所述第二方向相交；
所述复位控制晶体管T8包括第一有源图形A1，所述第一有源图形A1沿第一方向延伸。
如图12所示，所述第一有源图形A1包括沿第一方向依次排列的第一复位控制导电部分A11、复位控制沟道部分A10和第二复位控制导电部分A12；
所述第一复位控制导电部分A11用作T8的第一电极S8，所述第二复位控制导电部分A12用作T8的第二电极D8。
在图12中，通过将所述输出复位晶体管T9的有源层沿第二方向上的宽度W1设置为小于所述输出晶体管T10的有源层沿第二方向上的宽度W2，并将T8设置于T9与VGL1之间，以将T8设置于节省出来的第二方向上的空间，并将第一有源图形A1沿第一方向延伸，以减少移位寄存器单元在第二方向上的宽度，利于实现窄边框。
可选的，所述至少一个移位寄存器单元还可以包括输出复位电容；
所述输出复位电容的第二极板在所述基底上的正投影在所述输出复位电容的第一极板在所述基底上的正投影之内；
所述输出复位电容的第二极板在所述基底上的正投影与所述第二电压信 号线在所述基底上的正投影部分重叠；
所述输出复位电容的第一极板与输出电路中的输出复位晶体管的栅极耦接；
所述输出复位电容的第二极板通过极板连接过孔与所述第二电压信号线耦接。
本公开至少一实施例通过所述输出复位电容的第二极板在所述基底上的正投影设置为与所述第二电压信号线在所述基底上的正投影部分重叠，以减少移位寄存器单元在第二方向上的宽度，利于实现窄边框，并方便输出复位电容的第二极板与第二电压信号线耦接。
如图11-图16所示，所述至少一个移位寄存器单元可以包括输出复位晶体管T9、输出晶体管T10、复位控制晶体管T8和输出复位电容C3；
T9的栅极G9与C3的第一极板C3a耦接，T9的第一电极S9与所述第二电压信号线VGH2耦接，T9的第二电极D9与所述第一输出线部分E01耦接；
T10的栅极G10与T12的第一电极S12耦接，T10的第一电极S10与所述第一电压信号线VGL1耦接，T10的第二电极D10与所述第一输出线部分E01耦接；
T8的栅极G8与T10的栅极G10耦接，
T9的第一电极G9与第一导电连接部L1耦接；
T8的第二电极D8通过第一连接过孔H01与第二导电连接部L2耦接，所述第二导电连接部L2与所述第一导电连接部L1之间存在第五重叠区域，所述第二导电连接部L2通过设置于所述第五重叠区域中的第五过孔H5与所述第一导电连接部L1耦接；
T8的第一电极S8通过第二连接过孔H02与所述输出复位晶体管T9的第一电极S9包括的第二个第一电极图形S92耦接，S92与所述第二电压信号线VGH1耦接，以使得T8的第一电极S8与第二电压信号线VGH1耦接；
C3的第一极板C3a与T9的栅极G9耦接；
C3的第二极板C3b通过极板连接过孔H30与第二电压信号线VGH1耦接。
在本公开至少一实施例中，所述第一防漏电电路可以包括第一控制晶体管；所述输出电路可以包括输出晶体管；
所述第一控制晶体管位于所述第一电压信号线远离显示区域的一侧；
所述第一控制晶体管的第一电极与输出晶体管的栅极耦接。
在具体实施时，所述至少一个移位寄存器单元可以包括第一防漏电电路和第二防漏电电路，所述第一防漏电电路包括第一控制晶体管，所述第二防漏电电路包括第二控制晶体管；所述输出电路包括输出晶体管；
所述第一控制晶体管和所述第二控制晶体管位于所述第一电压信号线远离显示区域的一侧；
所述第一控制晶体管的栅极和第二控制晶体管的栅极相互耦接；
所述第二控制晶体管的栅极与电极导电连接部耦接，所述电极导电连接部在所述基底上的正投影与所述第一电压信号线在所述基底上的正投影之间存在电极重叠区域，所述电极导电连接部通过设置于所述电极重叠区域的电极连接过孔与所述第一电压信号线耦接；
所述第一控制晶体管的第一电极与输出晶体管的栅极耦接。
在本公开至少一实施例中，所述至少一个移位寄存器单元可以包括第一防漏电电路和第二防漏电电路，以防止输出晶体管漏电，并防止栅极与第四节点耦接的晶体管漏电；第一防漏电电路包括的第一控制晶体管的栅极和第二防漏电电路包括的第二控制晶体管的栅极相互耦接，并所述第二控制晶体管的栅极与所述所述第一电压信号线耦接，将所述第一控制晶体管和所述第二控制晶体管设置为靠近第一电压信号线，以方便第二控制晶体管的栅极与所述第一电压信号线之间耦接，并方便第一控制晶体管的栅极与第二控制晶体管的栅极耦接。
如图11至图16所示，所述至少一个移位寄存器单元可以包括第一防漏电电路和第二防漏电电路，所述第一防漏电电路包括第一控制晶体管T12，所述第二防漏电电路包括第二控制晶体管T11；所述输出电路O1包括输出晶体管T10；
所述第一控制晶体管T12和所述第二控制晶体管T11位于所述第一电压信号线VGL1远离显示区域的一侧；
所述第一控制晶体管T12的栅极G12和第二控制晶体管T11的栅极G11相互耦接；
所述第二控制晶体管T11的栅极G11与电极导电连接部L01耦接，所述电极导电连接部L01在所述基底上的正投影与所述第一电压信号线VGL1在所述基底上的正投影之间存在电极重叠区域，所述电极导电连接部L01通过设置于所述电极重叠区域的电极连接过孔H0与所述第一电压信号线VGL1耦接；
所述第一控制晶体管T12的第一电极S12通过第三连接过孔H03与第三导电连接部L3耦接，T10的栅极G10与第四导电连接部L4耦接，所述第三导电连接部L3与所述第四导电连接部L4之间存在第六重叠区域，所述第三导电连接部L3通过设置于所述第六重叠区域的第六过孔H6与所述第四导电连接部L4耦接，以使得T12的第一电极S12与T10的栅极G10耦接。
如图11-图16所示，所述第一控制晶体管T12包括第四有源图形A4；
所述第四有源图形A4包括沿第二方向依次排列的第一控制导电部分A411、第一控制沟道部分A42和第二控制导电部分A412；
A411用作T12的第二电极D12，A412用作T12的第一电极S12；
所述第二控制晶体管T11包括第五有源图形A5；
所述第五有源图形A5包括沿第一方向依次排列的第三控制导电部分A511、第二控制沟道部分A52和第四控制导电部分A512；
A511用作T11的第一电极S11，A512用作T11的第二电极D11；
T11和T12设置于所述第一电压信号线VGL1远离显示区域的一侧。
如图11-图16所示，D102与第五导电连接部L5耦接，所述第五导电连接部L5通过第四连接过孔H04与第六导电连接部L6耦接，所述第六导电连接部L6包含于第二栅金属层；
所述第六导电连接部L6通过第五连接过孔H05与进位信号线E11耦接，所述进位信号线E11可以为第n+1级移位寄存器单元提供输入信号，所述进位信号线E11可以包含于源漏金属层，但不以此为限。
在本公开至少一实施例中，所述扫描驱动电路还可以包括第三电压信号线；所述第三电压信号线用于提供第二电压；所述至少一个移位寄存器单元 还包括第三节点控制电路；所述第三节点控制电路包括输入晶体管、第一节点控制晶体管和第二节点控制晶体管；
所述输入晶体管的有源层、所述第一节点控制晶体管的有源层和所述第二节点控制晶体管的有源层由一个连续的第二半导体层形成；
所述第二半导体层沿第一方向延伸；
所述输入晶体管的有源层包括沿第一方向依次设置的第一个第三导电部分、第三沟道部分和第二个第三导电部分；
所述第二个第三导电部分复用为第一个第四导电部分；
所述第一节点控制晶体管的有源层包括沿第一方向依次设置的第一个第四导电部分、第四沟道部分和第二个第四导电部分；
所述第二个第四导电部分复用为第一个第五导电部分；
所述第二节点控制晶体管的有源层包括沿第一方向依次设置的第一个第五导电部分、第五沟道部分和第二个第五导电部分；
所述输入晶体管的第一电极与输入端耦接，所述第二节点控制晶体管的第一电极与第三电压信号线耦接。
在具体实施时，所述第二电压可以为高电压Vh，但不以此为限。
在本公开至少一实施例中，所述输入晶体管的有源层、所述第一节点控制晶体管的有源层和所述第三节点控制晶体管的有源层由一个连续的第二半导体层形成，并所述第二半导体层沿第一方向延伸，从而可以缩小所述输入晶体管、第一节点控制晶体管和第二节点控制晶体管在第二方向上占用的空间，利于实现窄边框。并且，在本公开至少一实施例中，所述第二个第三导电部分复用为第一个第四导电部分，所述第二个第四导电部分复用为第一个第五导电部分，以在收窄移位寄存器单元的横向宽度的同时，减小移位寄存器单元的纵向高度。
如图11-图16所示，所述扫描驱动电路还可以包括第三电压信号线VGH2；所述第三电压信号线VGH2用于提供高电压Vh；所述至少一个移位寄存器单元包括输入晶体管T1、第一节点控制晶体管T4和第二节点控制晶体管T5；
所述输入晶体管T1的有源层、所述第一节点控制晶体管T4的有源层和所述第二节点控制晶体管T5的有源层由一个连续的第二半导体层20形成；
所述第二半导体层20沿第一方向延伸；
所述输入晶体管T1的有源层包括沿第一方向依次设置的第一个第三导电部分231、第三沟道部分23和第二个第三导电部分232；
所述第二个第三导电部分232复用为第一个第四导电部分；
所述第一节点控制晶体管的T4有源层包括沿第一方向依次设置的第一个第四导电部分、第四沟道部分24和第二个第四导电部分242；
所述第二个第四导电部分242复用为第一个第五导电部分；
所述第二节点控制晶体管T5的有源层包括沿第一方向依次设置的第一个第五导电部分、第五沟道部分25和第二个第五导电部分252；
所述输入晶体管T1的第一电极S1通过第六连接过孔H06与输入端E1耦接，所述第二节点控制晶体管T5的第一电极S5通过第七连接过孔H07与第三电压信号线VGH2耦接。
在本公开至少一实施例中，第一个第三导电部分231用作T1的第一电极S1，第二个第三导电部分232用作T1的第二电极D1，第二个第四导电部分242用作第一节点控制晶体管T4的第一电极S4，第二个第五导电部分252用作第二节点控制晶体管T5的第一电极；T1的第二电极D1复用为T4的第二电极D4，T4的第一电极S4复用为T5的第二电极D5。
可选的，所述输入晶体管、所述第一节点控制晶体管和所述第二节点控制晶体管位于所述第三电压信号线和所述第一电压信号线之间；
所述第三电压信号线沿第一方向延伸，所述第三电压信号线位于所述第一电压信号线远离显示区域的一侧。
如图11-图16所示，第三电压信号线VGH2沿第一方向延伸，第三电压信号线VGH2位于第一电压信号线VGL1远离显示区域的一侧，T1、T4和T5设置于VGH2和VGL1之间。
在具体实施时，所述至少一个移位寄存器单元还可以包括第二储能电路和第二节点控制电路；所述第二储能电路包括第一电容，所述第二节点控制电路包括第三节点控制晶体管和第四节点控制晶体管；
所述第四节点控制晶体管的有源层和所述第三节点控制晶体管的有源层由一个连续的第三半导体层形成；所述第三半导体层沿第一方向延伸；
所述第四节点控制晶体管的有源层包括沿第一方向依次设置的第一个第六导电部分、第六沟道部分和第二个第六导电部分；
所述第二个第六导电部分复用为第一个第七导电部分；
所述第三节点控制晶体管的有源层包括沿第一方向依次设置的第一个第七导电部分、第七沟道部分和第二个第七导电部分；
所述第四节点控制晶体管的栅极与第一节点控制晶体管的栅极耦接，所述第四节点控制晶体管的第二电极与输出复位晶体管的栅极耦接；
所述第三节点控制晶体管的栅极与所述第一电容的第一极板耦接，所述第三节点控制晶体管的第一电极与第一节点控制晶体管的栅极耦接；
所述第二个第六导电部分用作所述第三节点控制晶体管的第二电极以及所述第四节点控制晶体管的第一电极；
所述第四节点控制晶体管的第一电极与所述第一电容的第二极板耦接。
在本公开至少一实施例中，所述第三节点控制晶体管的有源层和所述第四节点控制晶体管的有源层由一个连续的第三半导体层形成；所述第三半导体层沿第一方向延伸，从而可以缩小第三节点控制晶体管和第四节点控制晶体管在第二方向上占用的空间，利于实现窄边框。并且，在本公开至少一实施例中，所述第二个第六导电部分复用为第一个第七导电部分，以在收窄移位寄存器单元的横向宽度的同时，减小移位寄存器单元的纵向高度。
如图11-图16所示，所述至少一个移位寄存器单元还可以包括第一电容C1、第三节点控制晶体管T6和第四节点控制晶体管T7；
所述第四节点控制晶体管T7的有源层和所述第三节点控制晶体管T3的有源层由一个连续的第三半导体层30形成；所述第三半导体层30沿第一方向延伸；
所述第四节点控制晶体管T7的有源层包括沿第一方向依次设置的第一个第六导电部分361、第六沟道部分36和第二个第六导电部分362；
所述第二个第六导电部分362复用为第一个第七导电部分；
所述第三节点控制晶体管T6的有源层包括沿第一方向依次设置的第一个第七导电部分、第七沟道部分37和第二个第七导电部分372；
第一个第六导电部分361用作T7的第二电极D7，第二个第七导电部分 372用作T6的第一电极S6；
所述第四节点控制晶体管T7的栅极G7与第一节点控制晶体管T4的栅极G4耦接，所述第四节点控制晶体管T7的第二电极D7与输出复位晶体管T9的栅极G7耦接；
所述第三节点控制晶体管T6的栅极G6与所述第一电容C1的第一极板C1a耦接，所述第三节点控制晶体管T6的第一电极S6与第一节点控制晶体管T4的栅极G4耦接；
所述第二个第六导电部分362用作所述第三节点控制晶体管T6的第二电极D6以及所述第四节点控制晶体管T7的第一电极S7；
所述第四节点控制晶体管T7的第一电极S7与所述第一电容C1的第二极板C1b耦接。
如图11-图16所示，T6和T7可以设置于VGH2与VGL1之间。
并如图11-图16所示，T7的第二电极D7通过第八连接过孔H08与第七导电连接部L7耦接，所述第七导电连接部L7通过第九连接过孔H09与所述第一导电连接部L1耦接；
T7的第一电极S7通过第十连接过孔H010与第八导电连接部L8耦接，所述第八导电连接部L8与所述第一电容C1的第二极板C1b之间存在第七重叠区域，所述第八导电连接部L8通过设置于所述第七重叠区域的第七过孔H7与所述第一电容C1的第二极板C1b耦接，
T7的栅极G7通过第九导电连接部L9与T4的栅极G4耦接；T6的第一电极S6通过连通过孔H60与第十导电连接部L10耦接；所述第十导电连接部L10与所述第九导电连接部L9之间存在第八重叠区域，所述第十导电连接部L10通过设置于所述第八重叠区域的第八过孔H8与所述第九导电连接部L9耦接，以使得T6的第一电极S6与T4的栅极G4耦接。
在本公开至少一实施例中，所述第一电容的第二极板在基底上的正投影在所述第一电容的第一极板在所述基底上的正投影内；
所述第一电容的第二极板在所述基底上的正投影与所述第一电压信号线在所述基底上的正投影部分重叠；
所述第三节点控制晶体管和所述第四节点控制晶体管位于所述第一电容 远离显示区域的一侧。
本公开至少一实施例将第一电容的第二极板在所述基底上的正投影与所述第一电压信号线在所述基底上的正投影部分重叠，以缩窄移位寄存器单元占用的第二方向上的空间，利于实现窄边框。
如图11-图16所示，所述第一电容C1的第二极板C1b在基底上的正投影在所述第一电容C1的第一极板C1a在所述基底上的正投影内；
所述第一电容C1的第二极板C1b在所述基底上的正投影与所述第一电压信号线VGL1在所述基底上的正投影部分重叠；
所述第三节点控制晶体管T6和所述第四节点控制晶体管T7位于所述第一电容C1远离显示区域的一侧；
C1、T11和T12沿着第一方向依次排列，利用C1下方的空间设置T11和T12，以减少占用的横向宽度。
如图11-图16所示，C1的第一极板C1a通过第十一连接过孔H011与第十一导电连接部L11耦接，T11的第一电极S11通过第十二连接过孔H012与所述第十一导电连接部L11耦接，以使得T11的第一电极S11与C1的第一极板C1a耦接；
T11的第二电极D11通过第十三连接过孔H013与第十二导电连接部L12耦接，所述第十二导电连接部L12通过第十四连接过孔H014与第十三导电连接部L13耦接，所述第十三导电连接部L13与T5的栅极G5耦接，以使得T11的第二电极D11与T5的栅极G5耦接；
T12的第二电极D12通过第十五连接过孔H015与第十四导电连接部L14耦接，T1的第二电极D1通过第十六连接过孔H016与所述第十四导电连接部L14耦接，以使得T1的第二电极D1与T12的第二电极D12耦接。
在具体实施时，所述扫描驱动电路还可以包括第三电压信号线，所述第三电压信号线用于提供第二电压；
所述至少一个移位寄存器单元包括第一防漏电电路、第二防漏电电路、输入晶体管、第一节点控制晶体管、第二节点控制晶体管、第三节点控制晶体管和第四节点控制晶体管；
所述第一防漏电电路包括第一控制晶体管，所述第二防漏电电路包括第 二控制晶体管；
所述第一控制晶体管、所述第二控制晶体管、所述输入晶体管、所述第一节点控制晶体管、所述第二节点控制晶体管、所述第三节点控制晶体管和所述第四节点控制晶体管位于所述第三电压信号线和所述第一电压信号线之间；
所述第三电压信号线沿第一方向延伸，所述第三电压信号线位于所述第一电压信号线远离显示区域的一侧。
在本公开至少一实施例中，第一控制晶体管、所述第二控制晶体管、所述输入晶体管、所述第一节点控制晶体管、所述第二节点控制晶体管、所述第三节点控制晶体管和所述第四节点控制晶体管可以位于所述第三电压信号线和所述第一电压信号线之间，并第三电压信号线可以位于所述第一电压信号线远离显示区域的一侧。
可选的，所述至少一个移位寄存器单元还可以包括第五节点控制电路，所述第五节点控制电路包括第五节点控制晶体管；
所述第五节点控制晶体管包括第二有源图形，所述第二有源图形为U形结构；
所述第二有源图形包括第一个第五节点控制沟道部分、第二个第五节点控制沟道部分、与所述第一个第五节点控制沟道部分耦接的第一个第五节点控制导电部分，以及，与所述第二个第五节点控制沟道部分耦接的第二个第五节点控制导电部分；
所述第五节点控制晶体管的栅极包括相互耦接的第一栅极图形和第二栅极图形；
所述第一栅极图形与所述第一个第五节点控制沟道部分对应，所述第二栅极图形与所述第二个第五节点控制沟道部分对应；
所述第一个第五节点控制导电部分用作所述第五节点控制晶体管的第二电极，所述第二个第五节点控制导电部分用作所述第五节点控制晶体管的第一电极。
如图11-图16所示，所述至少一个移位寄存器单元还可以包括第五节点控制晶体管T2；
所述第五节点控制晶体管T2包括第二有源图形A2，所述第二有源图形A2为U形结构；
所述第二有源图形A2包括第一个第五节点控制沟道部分A211、第二个第五节点控制沟道部分A212、与所述第一个第五节点控制沟道部分A211耦接的第一个第五节点控制导电部分A221，以及，与所述第二个第五节点控制沟道部分A212耦接的第二个第五节点控制导电部分A222；
所述第五节点控制晶体管T2的栅极G2包括相互耦接的第一栅极图形G21和第二栅极图形G22；
所述第一栅极图形G21与所述第一个第五节点控制沟道部分A211对应，所述第二栅极图形G22与所述第二个第五节点控制沟道部分A212对应；
所述第一个第五节点控制导电部分A221用作所述第五节点控制晶体管T2的第二电极D2，所述第二个第五节点控制导电部分A222用作所述第五节点控制晶体管T2的第一电极S2。
如图11和图12所示，所述第五节点控制晶体管T2的有源图形设置为U形结构，以使得T2形成为双栅结构。双栅结构设计的目的在于：在第二阶段P2，扫描驱动电路包括的移位寄存器单元输出高电压信号时，T10应完全关闭，而T10的栅极接入的高电平由T5的源极输入。因此，在第二阶段P2，应务必保证T5打开，即需要使得第五节点N5的电位为低电压；而在第二阶段P2，T2栅极的电位为高电压，为保证T2不漏电造成第五节点N5电位升高，因此将T2设置为采用双栅设计，使得T2更容易关断。
由于在实际生产曝光中，如果将T2的有源图形设置为不带缺角的U字形，会在曝光后沉积金属，会使得该U字形的有源图形为V字形。因此，在实际产品中，考虑到实际生产曝光过程，U字形的有源图形内侧在两个直角部分挖了一小部分进行补偿，尽量使实际图案为U字形，不对T2的宽长比产生影响。
如图11-图16所示，T2的第一电极S2通过第十七连接过孔H017与第十五导电连接部L15耦接，T1的栅极G1与第十六导电连接部L16耦接，所述第十五导电连接部L15与第十六导电连接部L16之间存在第九重叠区域，所述第十五导电连接部L15通过设置于所述第九重叠区域的第九过孔H9与所 述第十六导电连接部L16耦接，以使得T2的第一电极S2与T1的栅极G1耦接；
所述第十六导电连接部L16还与T3的栅极G3耦接，以使得T2的第一电极S2与T3的栅极G3耦接；
T2的第二电极D2通过第十八连接过孔H018与第十七导电连接部L17耦接，T5的栅极G5与第十八导电连接部L18耦接，第十七导电连接部L17与第十八导电连接部L18之间存在第十重叠区域，所述第十七导电连接部L17通过设置于所述第十重叠区域的第十过孔H10与所述第十八导电连接部L18耦接，以使得T2的第二电极D2与T5的栅极G5耦接；
T3的第二电极D3通过第十九连接过孔H019与所述第十七导电连接部L17耦接，以使得T3的第二电极D3与T2的第二电极D2耦接；
T2的栅极G2与输出电容C2的第一极板C2a耦接。
可选的，所述至少一个移位寄存器单元还可以包括第五节点控制电路，所述第五节点控制电路包括第六节点控制晶体管；
所述第六节点控制晶体管包括第三有源图形，所述第三有源图形沿第一方向延伸。
在本公开至少一实施例中，所述至少一个移位寄存器单元还可以包括第六节点控制晶体管，第六节点控制晶体管和第五节点控制晶体管沿第一方向排列，第六节点控制晶体管包括的第三有源图形沿第一方向延伸，以缩窄移位寄存器单元占用的第二方向上的宽度。
如图11-图16所示，所述至少一个移位寄存器单元还可以包括第六节点控制晶体管T2；
所述第六节点控制晶体管T2包括第三有源图形A3，所述第三有源图形A3沿第一方向延伸；
所述第三有源图形A3包括第一个第八导电部分A31、第八沟道部分A30和第二个第八导电部分A32；
A31用作T3的第一电极S3，A32用作T3的第二电极D3；
所述第十六导电连接部L16还与T3的栅极G3耦接，以使得T2的第一电极S2与T3的栅极G3耦接；
T3的第二电极D3通过第十九连接过孔H019与所述第十七导电连接部L17耦接，以使得T3的第二电极D3与T2的第二电极D2耦接；
T3的第一电极S3通过第二十连接过孔H020与第十九导电连接部L19耦接，所述第十九导电连接部L19与第四电压信号线VGL2耦接，以使得T3的第一电极S3与第四电压信号线VGL2耦接；
所述第四电压信号线VGL2可以提供第一电压，所述第一电压可以为低电压VL，但不以此为限。
如图11所示，T2和T3设置于VGH2和VGL2之间，VGH2和VGL2都沿第一方向延伸。
在具体实施时，所述扫描驱动电路还可以包括第四电压信号线，所述第四电压信号线用于提供第一电压；所述第一储能电路可以包括输出电容；
所述输出电容的第二极板在所述基底上的正投影在所述输出电容的第一极板在所述基底上的正投影之内；
所述输出电容的第二极板在基底上的正投影与所述第四电压信号线在所述基底上的正投影部分重叠；
所述输出电容的第二极板在第二方向上的宽度小于第一预定宽度，所述输出电容的第二极板在第一方向上的长度大于第一预定长度；
所述第四电压信号线沿第一方向延伸。
本公开至少一实施例在第三电压信号线远离显示区域的一侧设置第四电压信号线，并通过将输出电容的极板设置为与第四电压信号线交叠，以缩窄移位寄存
器单元占用的第二方向上的宽度，并将输出电容的第二极板在第二方向上的宽度设置为小于第一预定宽度，将输出电容的第二极板在第一方向上的长度设置为大于第一预定长度，以在收窄横向宽度的同时保证输出电容的第二极板的面积。
可选的，所述第一预定宽度为20微米，所述第一预定长度为22微米，但不以此为限。
在本公开至少一实施例中，所述扫描驱动电路还可以包括第三电压信号线和第四电压信号线，所述第四电压信号线用于提供第一电压；所述第三电 压信号线用于提供第二电压；所述第三电压信号线位于所述第一电压信号线远离显示区域的一侧，所述第三电压信号线位于所述第三电压信号线远离显示区域的一侧；
所述第一储能电路包括输出电容；所述至少一个移位寄存器单元还包括第五节点控制电路，所述第五节点控制电路包括第五节点控制晶体管和第六节点控制晶体管；
所述第五节点控制晶体管和所述第六节点控制晶体管位于所述第三电压信号线与所述第四电压信号线之间；
所述第六节点控制晶体管的第一电极与所述第四电压信号线耦接，所述第六节点控制晶体管的第二电极与所述第五节点控制晶体管的第二电极耦接；
所述第五节点控制晶体管的第一电极与所述第六节点控制晶体管的栅极耦接；
所述输出电容的第二极板在所述基底上的正投影在所述输出电容的第一极板在所述基底上的正投影之内；所述输出电容的第二极板在基底上的正投影与所述第四电压信号线在所述基底上的正投影部分重叠；
所述输出电容的第一极板与所述第五节点控制晶体管的栅极耦接；
所述第三电压信号线与所述第四电压信号线沿第一方向延伸。
在具体实施时，第五节点控制晶体管和第六节点控制晶体管可以设置于第三电压信号线和第四电压信号线之间，所述输出电容的第二极板在基底上的正投影与所述第四电压信号线在所述基底上的正投影部分重叠。
可选的，所述扫描驱动电路还可以包括设置于所述第四电压信号线远离显示区域的第一时钟信号线和第二时钟信号线；
所述输出电容的第二极板与所述第一时钟信号线耦接；
所述第六节点控制晶体管的栅极与所述第二时钟信号线耦接；
所述第一时钟信号线和所述第二时钟信号线都沿第一方向延伸。
如图11-图16所示，所述扫描驱动电路还可以包括设置于所述第四电压信号线VGL2远离显示区域的第一时钟信号线CB和第二时钟信号线CK；
第一时钟信号线CB和第二时钟信号线CK可以都沿第一方向延伸；
T3的栅极与第二十导电连接部L20耦接，所述第二十导电连接部L20 与所述第二时钟信号线CK之间存在第十一重叠区域，所述第二十导电连接部L20通过设置于所述第十一重叠区域的第十一过孔H11与所述第二时钟信号线CK耦接；
T4的栅极与第二十一导电连接部L21耦接，第二十一导电连接部L21与所述第一时钟信号线CB之间存在第十二重叠区域，所述第二十一导电连接部L21通过设置于所述第十二重叠区域的第十二过孔H12与所述第一时钟信号线CB耦接；
T2的栅极G2与C2的第一极板C2a耦接；
C2的第二极板C2b与第二十二导电连接部L22耦接，所述第二十二导电连接部L22与所述第一时钟信号线CB之间存在第十三重叠区域，所述第二十二导电连接部L22通过设置于所述第十三重叠区域的第十三过孔H13与所述第一时钟信号线CB耦接。
如图7、图11-图16所示，T12的第二电极D12通过第十五连接过孔H015与第十四导电连接部L14耦接，T2的栅极G2与第二十三导电连接部L23耦接，所述第二十三导电连接部L23通过第二十一连接过孔H021与所述第十四导电连接部L14耦接，以使得T2的栅极G2与T12的第二电极D12耦接。
在图11所示的布局方式中，沿着远离显示区域的方向，VGL2、CK和CB依次排列，但是在实际操作时，也可以沿着远离显示区域的方向，VGL2、CB和CK依次排列。
如图7、图11-图16所示，所述输出复位晶体管T9的第二电极D9中的第一个第二电极图形D91与第一输出线导电连接部L91耦接；
所述第一输出线导电连接部L91与第一输出线部分E01之间存在第一输出线重叠部分，L91通过设置于第一输出线重叠部分的第一输出线过孔H91与所述第一输出线部分E01耦接，以使得D91与E01耦接；
D101和D102都与第二输出线导电连接部L101耦接，第二输出线导电连接部L101与与第一输出线部分E01之间存在第二输出线重叠部分，L101通过设置于第二输出线重叠部分的第二输出线过孔H101与所述第一输出线部分E01耦接，以使得D101和D102分别与E01耦接。
在本公开至少一实施例中，所述扫描驱动电路还可以包括第三电压信号 线、第四电压信号线、第一时钟信号线和第二时钟信号线；所述第三电压信号线、所述第四电压信号线、所述第一时钟信号线和所述第二时钟信号线都沿第一方向延伸；
沿着远离显示区域的方向，所述第二电压信号线、所述第一电压信号线、所述第三电压信号线、所述第四电压信号线、所述第二时钟信号线和所述第一时钟信号线依次排列；或者，
沿着远离显示区域的方向，所述第二电压信号线、所述第一电压信号线、所述第三电压信号线、所述第四电压信号线、所述第一时钟信号线和所述第二时钟信号线依次排列。
具体地，所述第一时钟信号线、所述第二时钟信号线和所述第四电压信号线的具体位置可根据实际需要设置，示例性的，可将所述第一时钟信号线、所述第二时钟信号线和所述第搜电压信号线均设置在所述显示基板的边缘处，即使得所述第四电压信号线在所述基底上的正投影、所述第一时钟信号线在所述基底上的正投影和所述第二时钟信号线在所述基底上的正投影，都位于所述移位寄存器单元在所述基底上的正投影远离所述显示基板的显示区域的一侧，这样在布局所述移位寄存器单元时，能够避免所述移位寄存器单元中的各晶体管与所述第一时钟信号线、所述第二时钟信号线和所述第四电压信号线产生过多的交叠，从而更有利于提升所述移位寄存器单元的工作性能。
另外，通过设置所述第一时钟信号线、所述第二时钟信号线和所述第四电压信号线均沿所述第一方向延伸，更有利于所述显示基板实现窄边框化。
在具体实施时，所述第一时钟信号线输出的第一时钟信号和所述第二时钟信号线输出的第二时钟信号的相位可以相反，但不以此为限。
在本公开至少一实施例中，如图7、图11-图16所示，所述扫描驱动电路包括第一电压信号线VGL1、第二电压信号线VGH1、第三电压信号线VGH2、第四电压信号线VGL2、第一时钟信号线CB和第二时钟信号线CK；所述输出电路O1包括输出晶体管T10和输出复位晶体管T9；所述第一防漏电电路12包括第一控制晶体管T12；所述至少一个移位寄存器单元还包括信号输出线、第二控制晶体管T11、输入晶体管T1、第一节点控制晶体管T4、第二节点控制晶体管T5、第三节点控制晶体管T6、第四节点控制晶体管T7、 第五节点控制晶体管T2、第六节点控制晶体管T3和复位控制晶体管T8；
所述复位控制晶体管T8、所述输出晶体管T10和所述输出复位晶体管G9设置于所述第一电压信号线VGL1与所述第二电压信号线VGH1之间；
所述第一控制晶体管T12、所述第二控制晶体管T11、所述输入晶体管T1、所述第一节点控制晶体管T4、所述第二节点控制晶体管T5、所述第三节点控制晶体管T6和所述第四节点控制晶体管T7位于所述第一电压信号线VGL1与所述第三电压信号线VGH2之间；
所述第五节点控制晶体管T2和所述第六节点控制晶体管T3位于所述第三电压信号线VGH2与所述第四电压信号线VGL2之间；
所述信号输出线包括第一输出线部分E01和第二输出线部分E02；
所述第一输出线部分E01位于所述输出电路O1与所述第二电压信号线VGH1之间；
所述第一输出线部分E01与所述第二输出线部分E02耦接，所述第一输出线部分E01沿第一方向延伸，所述第二输出线部分E02沿第二方向延伸，所述第一方向与所述第二方向相交；
所述第二输出线部分E02延伸至显示区域。
在本公开至少一实施例中，T8、T9和T10可以设置于VGH1与VGL1之间，T1、T4、T5、T6、T7、T11和T12可以设置于VGL1和VGH2之间，T2和T3可以设置于VGH2和VGL2之间，T9和T10沿第一方向依次排列，T8设置于G9与VGL1之间，T1、T4和T5沿第一方向依次排列，T7和T6沿第一方向依次排列，T11和T12设置于T6下方，T2和T3设置于VGH2和VGL2之间，T3和T2沿第一方向排列。
可选的，所述第一储能电路包括输出电容和输出复位电容；所述至少一个移位寄存器单元还可以包括第一电容；
所述第一电容的第二极板在所述基底上的正投影与所述第一电压信号线与所述基底上的正投影部分重叠，或者，所述第一电容位于所述第一电压信号线与所述第四节点控制晶体管之间；
所述第一电容的第二极板在所述基底上的正投影在所述第一电容的第一极板在所述基底上的正投影之间；
所述输出复位电容的第二极板在所述基底上的正投影在所述输出复位电容的第一极板在所述基底上的正投影之内；
所述输出复位电容的第二极板在所述基底上的正投影与所述第二电压信号线在所述基底上的正投影部分重叠；
所述输出电容的第二极板在所述基底上的正投影在所述输出电容的第一极板在所述基底上的正投影之内；
所述输出电容的第二极板在基底上的正投影与所述第四电压信号线在所述基底上的正投影部分重叠。
在本公开至少一实施例中，所述至少一个移位寄存器单元还可以包括第一电容、输出电容和输出复位电容，所述第一电容的第二极板在所述基底上的正投影与所述第一电压信号线与所述基底上的正投影部分重叠，所述输出复位电容的第二极板在所述基底上的正投影与所述第二电压信号线在所述基底上的正投影部分重叠，所述输出电容的第二极板在基底上的正投影与所述第四电压信号线在所述基底上的正投影部分重叠，以能够收窄移位寄存器单元占用的第二方向的宽度。
如图6、图7、图11-图16所示，所述至少一个移位寄存器单元还可以包括第一电容C1、输出电容C2和输出复位电容C3；
所述第一电容C1的第二极板C1b在所述基底上的正投影与所述第一电压信号线VGL1与所述基底上的正投影部分重叠；
所述第一电容C1的第二极板C1b在所述基底上的正投影在所述第一电容C1的第一极板C1a在所述基底上的正投影之间；
所述输出复位电容C3的第二极板C3b在所述基底上的正投影在所述输出复位电容C3的第一极板C3a在所述基底上的正投影之内；
所述输出复位电容C3的第二极板C3b在所述基底上的正投影与所述第二电压信号线VGH1在所述基底上的正投影部分重叠；
所述输出电容C2的第二极板C2b在所述基底上的正投影在所述输出电容C2的第一极板C2a在所述基底上的正投影之内；
所述输出电容C2的第二极板C2b在基底上的正投影与所述第四电压信号线VGL2在所述基底上的正投影部分重叠。
在图11所示的布局方式中，C2的极板与VGL2的重叠区域面积较大，并C3的极板与VGH1的重叠区域也较大，以能充分节省C2的极板和C3的极板占用的空间。
在具体实施时，所述第三电压信号线、所述第四电压信号线、所述第一时钟信号线和所述第二时钟信号线都沿第一方向延伸；
沿着远离显示区域的方向，所述第二电压信号线、所述第一电压信号线、所述第三电压信号线、所述第四电压信号线、所述第二时钟信号线和所述第一时钟信号线依次排列；或者，
沿着远离显示区域的方向，所述第二电压信号线、所述第一电压信号线、所述第三电压信号线、所述第四电压信号线、所述第一时钟信号线和所述第二时钟信号线依次排列。
在本公开至少一实施例中，在如图12所示的半导体层和如图13所示的第一栅金属层之间，还可以设置有第一栅绝缘层；在如图13所示的第一栅金属层和如图14所示的的第二栅金属层之间，还可以设置有第二栅绝缘层；在如图14所示的第二栅金属层和如图15所示的源漏金属层之间还可以包括一层绝缘层。
并在制作本公开至少一实施例所述的显示基板时，首先在基底上设置半导体材料层，对所述半导体材料层进行构图工艺，以形成各晶体管的有源层；如图12所示，形成了第一半导体层10、第二半导体层20、第三半导体层30、所述复位控制晶体管T8包括的第一有源图形A1、所述第五节点控制晶体管T2包括的第二有源图形A2和所述第六节点控制晶体管T2包括的第三有源图形A3；
在所述有源层背向所述基底的一面制作第一栅绝缘层；
在所述第一栅绝缘层背向所述有源层的一面，制作第一栅金属层，对第一栅金属层进行构图工艺，如图13所示，形成移位寄存器单元包括的各晶体管的栅极、输出复位电容C3的第一极板、第一电容C1的第一极板和输出电容C2的第一极板；
以所述各晶体管的栅极为掩膜，对有源层中未被所述栅极覆盖的部分进行掺杂，使得所述有源层中未被所述栅极覆盖的部分形成为导电部分，所述 有源层中被所述栅极覆盖的部分形成为沟道部分；所述导电部分用作第一电极或第二电极；或者，所述导电部分与第一电极或第二电极耦接；
在所述第一栅金属层背向所述第一栅金属层的一面设置第二栅绝缘层；
在所述第二栅绝缘层背向所述第一栅金属层的一面设置第二栅金属层，对所述第二栅金属层进行构图工艺，如图14所示，形成信号输出线、输出复位电容C3的第二极板、第一电容C1的第二极板和输出电容C2的第二极板；
在所述第二栅金属层背向所述第二栅绝缘层的一面设置绝缘层；
如图15所示，在设置了有源层、第一栅绝缘层、第一栅金属层、第二栅绝缘层、第二栅金属层和绝缘层的基底上，设置多个过孔；
在所述绝缘层背向所述第二栅金属层的一面设置源漏金属层，对所述源漏金属层进行构图工艺，如图16所示，形成第一电压信号线VGL1、第二电压信号线VGH1、第三电压信号线VGH2、第四电压信号线VGL2、第一时钟信号线CB、第二时钟信号线CB、输入端E1、所述输出复位晶体管T9的第二电极、所述输出复位晶体管T9的第一电极、所述输出晶体管T10的第二电极，以及，所述输出晶体管T10的第一电极。
本公开至少一实施例所述的显示基板的制作方法包括在基底上制作第一电压信号线、第二电压信号线和扫描驱动电路；所述扫描驱动电路包括多个移位寄存器单元，所述多个移位寄存器单元中的至少一个移位寄存器单元包括输出电路、第一储能电路和第一防漏电电路，所述输出电路分别与所述第一电压信号线和所述第二电压信号线耦接，所述第一储能电路分别与所述输出电路与所述第二电压信号线耦接，所述第一防漏电电路与所述输出电路耦接；所述显示基板的制作方法还包括：
将所述第一电压信号线设置于所述第二电压信号线远离显示区域的一侧；
在所述第一电压信号线和所述第二电压信号线之间设置所述输出电路；
将所述第一储能电路在所述基底上的正投影设置为与所述第二电压信号线在所述基底上的正投影部分重叠；
在所述第一电压信号线远离所述第二电压信号线的一侧设置所述第一防漏电电路；
所述第一电压信号线用于提供第一电压，所述第二电压信号线用于提供 第二电压。
在本公开至少一实施例中，由于输出电路分别与第一电压信号线和第二电压信号线耦接，因此本公开至少一实施例将输出电路设置于第一电压信号线和第二电压信号线之间，以能够减短输出电路与第一电压信号线之间的连接线的长度，并能够减短输出电路与第二电压信号线之间的连接线的长度，从而能够合理布局输出电路、第一电压信号线和第二电压信号线。
并本公开至少一实施例将所述第一储能电路在所述基底上的正投影设置为与所述第二电压信号线在所述基底上的正投影部分重叠，以减少移位寄存器单元在第二方向上的宽度，利于实现窄边框，并方便第一储能电路与第二电压信号线耦接。
在本公开至少一实施例中，所述至少一个移位寄存器单元可以包括第一防漏电电路，以防止输出电路包括的输出晶体管漏电，本公开至少一实施例将所述第一防漏电电路设置于所述第一电压信号线远离所述第二电压信号线的一侧，使得所述第一防漏电电路可以方便的与第一电压信号线耦接。
本公开至少一实施例所述的显示装置包括上述的显示基板。
本公开至少一实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (33)

  1. 一种显示基板，包括设置于基底上的扫描驱动电路，所述扫描驱动电路包括多个移位寄存器单元，所述多个移位寄存器单元中的至少一个移位寄存器单元包括输出电路、第一储能电路和第一防漏电电路；所述扫描驱动电路还包括第一电压信号线和第二电压信号线；所述第一电压信号线用于提供第一电压，所述第二电压信号线用于提供第二电压；
    所述第一电压信号线位于所述第二电压信号线远离显示区域的一侧；
    所述输出电路分别与所述第一电压信号线和所述第二电压信号线耦接，所述第一储能电路分别与所述输出电路与所述第二电压信号线耦接，所述第一防漏电电路分别与所述输出电路和所述第一电压信号线耦接；
    所述输出电路设置于所述第一电压信号线和所述第二电压信号线之间；
    所述第一储能电路在所述基底上的正投影与所述第二电压信号线在所述基底上的正投影部分重叠；
    所述第一防漏电电路设置于所述第一电压信号线远离所述第二电压信号线的一侧。
  2. 如权利要求1所述的显示基板，其中，所述扫描驱动电路还包括第三电压信号线和第四电压信号线，所述第四电压信号线用于提供第一电压；所述第三电压信号线用于提供第二电压；所述第三电压信号线位于所述第一电压信号线远离显示区域的一侧，所述第四电压信号线位于所述第三电压信号线远离显示区域的一侧；
    所述第一储能电路在所述基底上的正投影与所述第四电压信号线在所述基底上的正投影部分重叠；
    所述第一防漏电电路位于所述第一电压信号线与所述第三电压信号线之间。
  3. 如权利要求2所述的显示基板，其中，所述第一电压信号线、所述第二电压信号线、所述第三电压信号线和所述第四电压信号线都沿第一方向延伸。
  4. 如权利要求1所述的显示基板，其中，所述至少一个移位寄存器单元 还包括复位控制电路；所述复位控制电路与所述输出电路耦接；
    所述复位控制电路设置于所述第一电压信号线和所述第二电压信号线之间。
  5. 如权利要求1所述的显示基板，其中，所述至少一个移位寄存器单元还包括第二节点控制电路、第二储能电路和第二防漏电电路；
    所述第二节点控制电路与第二储能电路耦接；所述第二防漏电电路分别与第一防漏电电路和所述第一电压信号线耦接；
    所述第二节点控制电路设置于所述第一电压信号线远离所述第二电压信号线的一侧；
    所述第二储能电路在所述基底上的正投影与所述第一电压信号线在所述基底上的正投影部分重叠；
    所述第二防漏电电路位于所述第一电压信号线远离所述第二电压信号线的一侧。
  6. 如权利要求1所述的显示基板，其中，所述至少一个移位寄存器单元还包括第三节点控制电路；所述第三节点控制电路位于第一电压信号线远离所述第二电压信号线的一侧。
  7. 如权利要求6所述的显示基板，其中，所述扫描驱动电路还包括第三电压信号线；所述第三电压信号线位于所述第一电压信号线远离显示区域的一侧；所述第三节点控制电路与所述第三电压信号线耦接；
    所述第三节点控制电路位于所述第一电压信号线与所述第三电压信号线之间。
  8. 如权利要求1所述的显示基板，其中，所述至少一个移位寄存器单元还包括第五节点控制电路；所述扫描驱动电路还包括第三电压信号线和第四电压信号线；所述第三电压信号线位于所述第一电压信号线远离显示区域的一侧，所述第四电压信号线位于所述第三电压信号线远离显示区域的一侧；
    所述第五节点控制电路分别与所述第四电压信号线和所述第一储能电路耦接；
    所述第五节点控制电路位于所述第三电压信号线与所述第四电压信号线之间。
  9. 如权利要求3所述的显示基板，其中，所述扫描驱动电路还包括设置于所述第四电压信号线远离显示区域的第一时钟信号线和第二时钟信号线；
    所述第一储能电路与所述第一时钟信号线耦接；
    所述第一时钟信号线和所述第二时钟信号线都沿第一方向延伸。
  10. 如权利要求9所述的显示基板，其中，沿着远离显示区域的方向，所述第二电压信号线、所述第一电压信号线、所述第三电压信号线、所述第四电压信号线、所述第二时钟信号线和所述第一时钟信号线依次排列；或者，沿着远离显示区域的方向，所述第二电压信号线、所述第一电压信号线、所述第三电压信号线、所述第四电压信号线、所述第一时钟信号线和所述第二时钟信号线依次排列。
  11. 如权利要求1所述的显示基板，其中，所述显示基板还包括设置于所述基底上的显示区域内的多行像素电路；所述像素电路包括发光控制端；所述移位寄存器单元还包括信号输出线；
    所述移位寄存器单元与所述行像素电路一一对应；
    所述移位寄存器单元的信号输出线与相应行像素电路的发光控制端耦接，用于为所述相应行像素电路的发光控制端提供发光控制信号。
  12. 如权利要求11所述的显示基板，其中，所述信号输出线包括第一输出线部分和第二输出线部分；
    所述第一输出线部分位于所述输出电路与所述第二电压信号线之间；
    所述第一输出线部分与所述第二输出线部分耦接，所述第一输出线部分沿第一方向延伸，所述第二输出线部分沿第二方向延伸，所述第一方向与所述第二方向相交；
    所述第二输出线部分延伸至显示区域，以为位于显示区域中的一行像素电路提供发光控制信号。
  13. 如权利要求1所述的显示基板，其中，所述输出电路包括输出晶体管和输出复位晶体管；
    所述输出复位晶体管和所述输出晶体管沿着第一方向排列；
    所述输出复位晶体管的第一电极与所述第二电压信号线耦接，所述输出晶体管的第一电极与所述第一电压信号线耦接；
    所述输出晶体管的第二电极和所述输出复位晶体管的第二电极都与所述至少一个移位寄存器单元包括的信号输出线耦接。
  14. 如权利要求13所述的显示基板，其中，所述输出复位晶体管的有源层沿第二方向上的宽度小于所述输出晶体管的有源层沿第二方向上的宽度；
    所述第一方向与所述第二方向相交。
  15. 如权利要求1所述的显示基板，其中，所述至少一个移位寄存器单元还包括复位控制电路；所述复位控制电路包括复位控制晶体管；所述输出电路包括输出晶体管和输出复位晶体管；
    所述复位控制晶体管的栅极与所述输出晶体管的栅极耦接，所述复位控制晶体管的第一电极与所述输出复位晶体管的第一电极耦接，所述复位控制晶体管的第二电极与所述输出复位晶体管的栅极耦接。
  16. 如权利要求15所述的显示基板，其中，所述复位控制晶体管位于所述输出复位晶体管与所述第一电压信号线之间；
    所述复位控制晶体管包括第一有源图形，所述第一有源图形沿第一方向延伸。
  17. 如权利要求1所述的显示基板，其中，所述第一储能电路包括输出复位电容；所述输出电路包括输出复位晶体管；
    所述输出复位电容的第二极板在所述基底上的正投影在所述输出复位电容的第一极板在所述基底上的正投影之内；
    所述输出复位电容的第二极板在所述基底上的正投影与所述第二电压信号线在所述基底上的正投影部分重叠；
    所述输出复位电容的第一极板与所述输出复位晶体管的栅极耦接；
    所述输出复位电容的第二极板通过极板连接过孔与所述第二电压信号线耦接。
  18. 如权利要求1所述的显示基板，其中，所述第一防漏电电路包括第一控制晶体管；所述输出电路包括输出晶体管；
    所述第一控制晶体管位于所述第一电压信号线远离显示区域的一侧；
    所述第一控制晶体管的第一电极与输出晶体管的栅极耦接。
  19. 如权利要求1所述的显示基板，其中，所述至少一个移位寄存器单 元还包括第二防漏电电路；所述第二防漏电电路包括第二控制晶体管，所述第一防漏电电路包括第一控制晶体管；
    所述第二控制晶体管位于所述第一电压信号线远离显示区域的一侧；所述第一控制晶体管的栅极和第二控制晶体管的栅极相互耦接；
    所述第二控制晶体管的栅极与电极导电连接部耦接，所述电极导电连接部在所述基底上的正投影与所述第一电压信号线在所述基底上的正投影之间存在电极重叠区域，所述电极导电连接部通过设置于所述电极重叠区域的电极连接过孔与所述第一电压信号线耦接。
  20. 如权利要求1所述的显示基板，其中，所述扫描驱动电路还包括第三电压信号线；所述第三电压信号线用于提供第二电压；所述至少一个移位寄存器单元还包括第三节点控制电路；所述第三节点控制电路包括输入晶体管、第一节点控制晶体管和第二节点控制晶体管；
    所述输入晶体管的有源层、所述第一节点控制晶体管的有源层和所述第二节点控制晶体管的有源层由一个连续的第二半导体层形成；
    所述第二半导体层沿第一方向延伸；
    所述输入晶体管的有源层包括沿第一方向依次设置的第一个第三导电部分、第三沟道部分和第二个第三导电部分；
    所述第二个第三导电部分复用为第一个第四导电部分；
    所述第一节点控制晶体管的有源层包括沿第一方向依次设置的第一个第四导电部分、第四沟道部分和第二个第四导电部分；
    所述第二个第四导电部分复用为第一个第五导电部分；
    所述第二节点控制晶体管的有源层包括沿第一方向依次设置的第一个第五导电部分、第五沟道部分和第二个第五导电部分；
    所述输入晶体管的第一电极与输入端耦接，所述第二节点控制晶体管的第一电极与第三电压信号线耦接。
  21. 如权利要求20所述的显示基板，其中，所述输入晶体管、所述第一节点控制晶体管和所述第二节点控制晶体管位于所述第三电压信号线和所述第一电压信号线之间；
    所述第三电压信号线沿第一方向延伸，所述第三电压信号线位于所述第 一电压信号线远离显示区域的一侧。
  22. 如权利要求1所述的显示基板，其中，所述至少一个移位寄存器单元还包括第二储能电路和第二节点控制电路；所述第二储能电路包括第一电容，所述第二节点控制电路包括第三节点控制晶体管和第四节点控制晶体管；
    所述第四节点控制晶体管的有源层和所述第三节点控制晶体管的有源层由一个连续的第三半导体层形成；所述第三半导体层沿第一方向延伸；
    所述第四节点控制晶体管的有源层包括沿第一方向依次设置的第一个第六导电部分、第六沟道部分和第二个第六导电部分；
    所述第二个第六导电部分复用为第一个第七导电部分；
    所述第三节点控制晶体管的有源层包括沿第一方向依次设置的第一个第七导电部分、第七沟道部分和第二个第七导电部分；
    所述第四节点控制晶体管的栅极与第一节点控制晶体管的栅极耦接，所述第四节点控制晶体管的第二电极与输出复位晶体管的栅极耦接；
    所述第三节点控制晶体管的栅极与所述第一电容的第一极板耦接，所述第三节点控制晶体管的第一电极与第一节点控制晶体管的栅极耦接；
    所述第二个第六导电部分用作所述第三节点控制晶体管的第二电极以及所述第四节点控制晶体管的第一电极；
    所述第四节点控制晶体管的第一电极与所述第一电容的第二极板耦接。
  23. 如权利要求22所述的显示基板，其中，所述第一电容的第二极板在基底上的正投影在所述第一电容的第一极板在所述基底上的正投影内；
    所述第一电容的第二极板在所述基底上的正投影与所述第一电压信号线在所述基底上的正投影部分重叠；
    所述第三节点控制晶体管和所述第四节点控制晶体管位于所述第一电容远离显示区域的一侧。
  24. 如权利要求1所述的显示基板，其中，所述至少一个移位寄存器单元还包括第五节点控制电路，所述第五节点控制电路包括第五节点控制晶体管；
    所述第五节点控制晶体管包括第二有源图形，所述第二有源图形为U形结构；
    所述第二有源图形包括第一个第五节点控制沟道部分、第二个第五节点控制沟道部分、与所述第一个第五节点控制沟道部分耦接的第一个第五节点控制导电部分，以及，与所述第二个第五节点控制沟道部分耦接的第二个第五节点控制导电部分；
    所述第五节点控制晶体管的栅极包括相互耦接的第一栅极图形和第二栅极图形；
    所述第一栅极图形与所述第一个第五节点控制沟道部分对应，所述第二栅极图形与所述第二个第五节点控制沟道部分对应；
    所述第一个第五节点控制导电部分用作所述第五节点控制晶体管的第二电极，所述第二个第五节点控制导电部分用作所述第五节点控制晶体管的第一电极。
  25. 如权利要求1所述的显示基板，其中，所述至少一个移位寄存器单元还包括第五节点控制电路，所述第五节点控制电路包括第六节点控制晶体管；
    所述第六节点控制晶体管包括第三有源图形，所述第三有源图形沿第一方向延伸。
  26. 如权利要求1所述的显示基板，其中，所述扫描驱动电路还包括第四电压信号线，所述第四电压信号线用于提供第一电压；所述第一储能电路包括输出电容；
    所述输出电容的第二极板在所述基底上的正投影在所述输出电容的第一极板在所述基底上的正投影之内；
    所述输出电容的第二极板在基底上的正投影与所述第四电压信号线在所述基底上的正投影部分重叠；
    所述输出电容的第二极板在第二方向上的宽度小于第一预定宽度，所述输出电容的第二极板在第一方向上的长度大于第一预定长度；
    所述第四电压信号线沿第一方向延伸。
  27. 如权利要求26所述的显示基板，其中，所述第一预定宽度为20微米，所述第一预定长度为22微米。
  28. 如权利要求2所述的显示基板，其中，
    所述第一储能电路包括输出电容；所述至少一个移位寄存器单元还包括第五节点控制电路，所述第五节点控制电路包括第五节点控制晶体管和第六节点控制晶体管；
    所述第五节点控制晶体管和所述第六节点控制晶体管位于所述第三电压信号线与所述第四电压信号线之间；
    所述第六节点控制晶体管的第一电极与所述第四电压信号线耦接，所述第六节点控制晶体管的第二电极与所述第五节点控制晶体管的第二电极耦接；
    所述第五节点控制晶体管的第一电极与所述第六节点控制晶体管的栅极耦接；
    所述输出电容的第二极板在所述基底上的正投影在所述输出电容的第一极板在所述基底上的正投影之内；所述输出电容的第二极板在基底上的正投影与所述第四电压信号线在所述基底上的正投影部分重叠；
    所述输出电容的第一极板与所述第五节点控制晶体管的栅极耦接；
    所述第三电压信号线与所述第四电压信号线沿第一方向延伸。
  29. 如权利要求28所述的显示基板，其中，所述扫描驱动电路还包括设置于所述第四电压信号线远离显示区域的第一时钟信号线和第二时钟信号线；
    所述输出电容的第二极板与所述第一时钟信号线耦接；
    所述第六节点控制晶体管的栅极与所述第二时钟信号线耦接；
    所述第一时钟信号线和所述第二时钟信号线都沿第一方向延伸。
  30. 如权利要求1所述的显示基板，其中，所述扫描驱动电路还包括第三电压信号线、第四电压信号线、第一时钟信号线和第二时钟信号线；所述输出电路包括输出晶体管和输出复位晶体管；所述第一防漏电电路包括第一控制晶体管；所述至少一个移位寄存器单元还包括信号输出线、第二控制晶体管、输入晶体管、第一节点控制晶体管、第二节点控制晶体管、第三节点控制晶体管、第四节点控制晶体管、第五节点控制晶体管、第六节点控制晶体管和复位控制晶体管；
    所述复位控制晶体管、所述输出晶体管和所述输出复位晶体管设置于所述第一电压信号线与所述第二电压信号线之间；
    所述第一控制晶体管、所述第二控制晶体管、所述输入晶体管、所述第 一节点控制晶体管、所述第二节点控制晶体管、所述第三节点控制晶体管和所述第四节点控制晶体管位于所述第一电压信号线与所述第三电压信号线之间；
    所述第五节点控制晶体管和所述第六节点控制晶体管位于所述第三电压信号线与所述第四电压信号线之间；
    所述信号输出线包括第一输出线部分和第二输出线部分；
    所述第一输出线部分位于所述输出电路与所述第二电压信号线之间；
    所述第一输出线部分与所述第二输出线部分耦接，所述第一输出线部分沿第一方向延伸，所述第二输出线部分沿第二方向延伸，所述第一方向与所述第二方向相交；
    所述第二输出线部分延伸至显示区域。
  31. 如权利要求30所述的显示基板，其中，所述第一储能电路包括输出电容和输出复位电容；所述至少一个移位寄存器单元还包括第一电容；
    所述第一电容的第二极板在所述基底上的正投影与所述第一电压信号线与所述基底上的正投影部分重叠，或者，所述第一电容位于所述第一电压信号线与所述第四节点控制晶体管之间；
    所述第一电容的第二极板在所述基底上的正投影在所述第一电容的第一极板在所述基底上的正投影之间；
    所述输出复位电容的第二极板在所述基底上的正投影在所述输出复位电容的第一极板在所述基底上的正投影之内；
    所述输出复位电容的第二极板在所述基底上的正投影与所述第二电压信号线在所述基底上的正投影部分重叠；
    所述输出电容的第二极板在所述基底上的正投影在所述输出电容的第一极板在所述基底上的正投影之内；
    所述输出电容的第二极板在基底上的正投影与所述第四电压信号线在所述基底上的正投影部分重叠。
  32. 一种显示基板的制作方法，包括在基底上制作第一电压信号线、第二电压信号线和扫描驱动电路；所述扫描驱动电路包括多个移位寄存器单元，所述多个移位寄存器单元中的至少一个移位寄存器单元包括输出电路、第一 储能电路和第一防漏电电路，所述输出电路分别与所述第一电压信号线和所述第二电压信号线耦接，所述第一储能电路分别与所述输出电路与所述第二电压信号线耦接，所述第一防漏电电路与所述输出电路耦接；所述显示基板的制作方法还包括：
    将所述第一电压信号线设置于所述第二电压信号线远离显示区域的一侧；
    在所述第一电压信号线和所述第二电压信号线之间设置所述输出电路；
    将所述第一储能电路在所述基底上的正投影设置为与所述第二电压信号线在所述基底上的正投影部分重叠；
    在所述第一电压信号线远离所述第二电压信号线的一侧设置所述第一防漏电电路；
    所述第一电压信号线用于提供第一电压，所述第二电压信号线用于提供第二电压。
  33. 一种显示装置，包括如权利要求1至31中任一权利要求所述的显示基板。
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