WO2021184158A1 - 显示基板、制作方法和显示装置 - Google Patents

显示基板、制作方法和显示装置 Download PDF

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Publication number
WO2021184158A1
WO2021184158A1 PCT/CN2020/079482 CN2020079482W WO2021184158A1 WO 2021184158 A1 WO2021184158 A1 WO 2021184158A1 CN 2020079482 W CN2020079482 W CN 2020079482W WO 2021184158 A1 WO2021184158 A1 WO 2021184158A1
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WIPO (PCT)
Prior art keywords
transistor
signal line
voltage signal
electrode
output
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Application number
PCT/CN2020/079482
Other languages
English (en)
French (fr)
Inventor
代洁
于鹏飞
张顺
白露
王思雨
王梦奇
张昊
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/256,563 priority Critical patent/US11699397B2/en
Priority to EP20897676.1A priority patent/EP4123904A4/en
Priority to CN202080000254.7A priority patent/CN114223135A/zh
Priority to JP2021565803A priority patent/JP2023528096A/ja
Priority to PCT/CN2020/079482 priority patent/WO2021184158A1/zh
Publication of WO2021184158A1 publication Critical patent/WO2021184158A1/zh
Priority to US18/297,294 priority patent/US20230245623A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a manufacturing method, and a display device.
  • AMOLED Active Matrix Organic Light-Emitting Diode
  • the AMOLED display panel includes a pixel circuit located in the display area and a scan driving circuit located in the edge area.
  • the pixel circuit includes a plurality of sub-pixel circuits distributed in an array.
  • the scan driving circuit includes a plurality of shift register units. The unit is used to provide a light-emitting control signal for the corresponding sub-pixel circuit. Since the scan driving circuit is arranged in the edge area of the AMOLED display panel, the arrangement of the scan driving circuit determines the frame width of the AMOLED display panel.
  • an embodiment of the present disclosure provides a display substrate, including a scan driving circuit and a display area disposed on the substrate, the scan driving circuit includes a plurality of shift register units, and the scan driving circuit further includes a A voltage signal line, a second voltage signal line, a first clock signal line, and a second clock signal line; the first voltage signal line, the second voltage signal line, the first clock signal line, and the first The two clock signal lines extend along the first direction; the display area includes at least one driving transistor, and the driving transistor is configured to drive a light-emitting element for display;
  • At least one of the plurality of shift register units includes an output circuit and a signal output line; the output circuit is connected to the first voltage signal line, the second voltage signal line, and the signal output line, respectively Line coupling; the signal output line extends along a second direction, and the first direction intersects the second direction;
  • the transistor included in the output circuit is disposed between the first voltage signal line and the second voltage signal line.
  • the first voltage signal line provides a first voltage to the output circuit
  • the second voltage signal line provides a second voltage to the output circuit
  • the first voltage is higher than the second voltage
  • the signal output line is located between output circuits in adjacent shift register units.
  • the first voltage signal line is located on a side of the second voltage signal line away from the display area.
  • the output circuit includes an output transistor and an output reset transistor
  • the output reset transistor and the output transistor are arranged along a first direction;
  • the first electrode of the output reset transistor is coupled to the first voltage signal line, and the first electrode of the output transistor is coupled to the second voltage signal line;
  • Both the second electrode of the output transistor and the second electrode of the output reset transistor are coupled to the signal output line.
  • the active layer of the output transistor and the active layer of the output reset transistor are formed by a continuous first semiconductor layer
  • the first semiconductor layer and the signal output line are arranged along a first direction.
  • the gate of the output reset transistor includes at least one output reset gate pattern
  • the first electrode of the output reset transistor includes at least one first electrode pattern
  • the second electrode of the output reset transistor includes at least one Second electrode pattern
  • the output reset gate pattern is located between the adjacent first electrode pattern and the second electrode pattern;
  • the second electrode pattern, the output reset gate pattern, and the first electrode pattern all extend along a second direction;
  • the first direction intersects the second direction.
  • the gate of the output transistor includes at least one output gate pattern
  • the first electrode of the output transistor includes at least one third electrode pattern
  • the second electrode of the output transistor includes at least one fourth electrode pattern ;
  • the output gate pattern is located between the adjacent third electrode pattern and the fourth electrode pattern;
  • the fourth electrode pattern, the output gate pattern, and the third electrode pattern all extend along the second direction;
  • the first direction intersects the second direction
  • the second electrode pattern closest to the gate of the output transistor in the output reset transistor is multiplexed as a fourth electrode pattern of the output transistor.
  • the active layer of the output reset transistor includes at least two first conductive parts and at least one first channel part arranged opposite to each other in a first direction; each of the first channel parts is arranged on two Between adjacent first conductive parts;
  • the first channel portion corresponds to the output reset gate pattern one-to-one, and the orthographic projection of each first channel portion on the substrate is located in the corresponding output reset gate pattern.
  • a part of the first conductive part in the output reset transistor corresponds to the first electrode pattern one-to-one, and the orthographic projection of the first electrode pattern on the substrate is in the same position as the corresponding first conductive part.
  • the other part of the output reset transistor, the first conductive part corresponds to the second electrode pattern one-to-one, and the orthographic projection of the second electrode pattern on the substrate corresponds to the first conductive part
  • the orthographic projection on the substrate has a second overlap area, and the second electrode pattern is coupled to the corresponding first conductive portion through at least one second via provided in the second overlap area.
  • the active layer of the output transistor includes at least two second conductive parts and at least one second channel part arranged oppositely along the first direction; each of the second channel parts is arranged in two phases. Between adjacent second conductive parts;
  • the second channel portion corresponds to the output gate pattern one-to-one, and the orthographic projection of each second channel portion on the substrate is located on the corresponding output gate pattern on the substrate.
  • a part of the second conductive part in the output transistor corresponds to the third electrode pattern one-to-one, and the orthographic projection of the third electrode pattern on the substrate corresponds to the second conductive part at the same position.
  • the other part of the second conductive part in the output transistor corresponds to the fourth electrode pattern on a one-to-one basis.
  • the orthographic projection of the fourth electrode pattern on the substrate is aligned with the corresponding second conductive part.
  • the orthographic projection on the substrate has a fourth overlap area, and the fourth electrode pattern is coupled to the corresponding second conductive portion through at least one fourth via provided in the fourth overlap area.
  • the number of the first voltage signal line is one;
  • the output circuit includes an output reset transistor; the at least one shift register unit also includes an output capacitor, a first transistor, and a second capacitor connecting transistor;
  • the first electrode of the output reset transistor, the first plate of the output capacitor, the first electrode of the first transistor, and the first electrode of the second capacitor connecting transistor are all connected to the first voltage signal line Coupling.
  • the display substrate further includes a third voltage signal line, and the first voltage signal line is located between the second voltage signal line and the third voltage signal line.
  • the first electrode of the second capacitor connection transistor is coupled to the signal line conductive connection part through the fifth connection via, and the signal line conductive connection part is coupled to the first voltage signal line, so that The first electrode of the second capacitor connecting transistor is coupled to the first voltage signal line;
  • the signal line conductive connection portion and the first voltage signal line are included in a source-drain metal layer, and the first electrode of the second capacitor connection transistor is included in an active layer.
  • the at least one shift register unit further includes a first capacitor
  • the orthographic projection of the conductive connecting portion of the signal line on the substrate partially overlaps the orthographic projection of the first electrode plate of the first capacitor on the substrate.
  • the orthographic projection of the first plate of the output capacitor on the substrate has a signal line overlapping area with the orthographic projection of the first voltage signal line on the substrate.
  • a pole plate is coupled to the first voltage signal line through at least one signal line via provided in the signal line overlapping area.
  • the at least one shift register unit further includes a first node control transistor and a second capacitor;
  • the gate of the first node control transistor is coupled to the second plate of the second capacitor
  • the orthographic projection of the first electrode plate of the second capacitor on the substrate is within the orthographic projection of the second electrode plate of the second capacitor on the substrate;
  • the first plate of the second capacitor is L-shaped
  • the first plate of the second capacitor includes a second horizontal plate portion
  • the orthographic projection of the gate of the first node control transistor on the substrate and the orthographic projection of the second horizontal plate portion on the substrate are arranged in a first direction.
  • the scan driving circuit further includes a third voltage signal line; the third voltage signal line extends along a first direction; the third voltage signal line is located at the first voltage signal line away from the second voltage signal line One side of the voltage signal line; the first node control transistor is located between the third voltage signal line and the first voltage signal line;
  • the first electrode plate of the second capacitor further includes a second vertical electrode plate portion coupled with the second horizontal electrode plate portion; the orthographic projection of the second vertical electrode plate portion on the substrate and The orthographic projection of the third voltage signal line on the substrate partially overlaps.
  • the first clock signal line is located on a side of the third voltage signal line away from the first voltage signal line;
  • the output circuit includes an output transistor; the at least one shift register unit further includes a second conductive connection portion provided between the gate of the output transistor and the second plate of the second capacitor; the first Two conductive connection parts are respectively coupled to the gate of the output transistor and the second plate of the second capacitor;
  • the at least one shift register unit further includes a third conductive connection part coupled with the second plate of the second capacitor;
  • the first node control transistor includes a second active pattern; the second active pattern is U-shaped;
  • the second active pattern includes a first first node control channel portion, a second first node control channel portion, and a first first node control channel portion coupled to the first first node control channel portion.
  • the gate of the first node control transistor includes a first gate pattern and a second gate pattern that are coupled to each other;
  • the first gate pattern corresponds to the first first node control channel portion, and the second gate pattern corresponds to the second first node control channel portion;
  • the first first node control conductive portion corresponds to the second electrode of the first node control transistor, and the second first node control conductive portion corresponds to the first electrode of the first node control transistor.
  • the at least one shift register unit further includes a second node control transistor; the at least one shift register unit includes a second capacitor connection transistor;
  • the second electrode of the second node control transistor and the second electrode of the first node control transistor are coupled through a fourth conductive connection part;
  • the at least one shift register unit further includes a fifth conductive connection portion coupled to the gate of the second capacitor connection transistor; the orthographic projection of the fifth conductive connection portion on the substrate is consistent with the fourth There is a seventh overlapping area between the orthographic projections of the conductive connecting portion on the substrate;
  • the fifth conductive connecting portion is coupled to the fourth conductive connecting portion through a seventh via hole provided in the seventh overlapping area.
  • the scan driving circuit further includes a third voltage signal line; the third voltage signal line is located on a side of the first voltage signal line away from the second voltage signal line;
  • the first electrode of the first node control transistor is coupled to the sixth conductive connection portion; the gate of the second node control transistor is coupled to the seventh conductive connection portion;
  • the first electrode of the second node control transistor is coupled to the third voltage signal line.
  • the gate of the second node control transistor is further coupled to an eighth conductive connection part; the orthographic projection of the eighth conductive connection part on the substrate and the second clock signal line are in the There is a ninth overlap area before the orthographic projection on the substrate, and the eighth conductive connecting portion is coupled to the second clock signal line through a ninth via hole disposed in the ninth overlap area.
  • the scan driving circuit further includes a third voltage signal line; the third voltage signal line extends along the first direction;
  • the second clock signal line is arranged between the first clock signal line and the third voltage signal line; or, the first clock signal line is arranged between the second clock signal line and the third voltage signal Between the lines.
  • the at least one shift register unit further includes an input transistor
  • the first electrode of the input transistor is coupled to the input signal terminal
  • the second electrode of the input transistor is coupled to the ninth conductive connecting portion, and the orthographic projection of the ninth conductive connecting portion on the substrate is opposite to the orthographic projection of the second electrode plate of the second capacitor on the substrate.
  • the at least one shift register unit further includes a third node control transistor, a second capacitor connection transistor, and an input transistor;
  • the gate of the third node control transistor is coupled to the first clock signal line
  • the active layer of the input transistor, the active layer of the third node control transistor, and the active layer of the second capacitor connection transistor are formed by a continuous third semiconductor layer;
  • the active layer of the input transistor includes a first fifth conductive portion, a fifth channel portion, and a second fifth conductive portion sequentially arranged along a first direction;
  • the second fifth conductive part is multiplexed into the first sixth conductive part
  • the active layer of the third node control transistor includes a first sixth conductive portion, a sixth channel portion, and a second sixth conductive portion sequentially arranged along the first direction;
  • the second sixth conductive part is multiplexed into the first seventh conductive part
  • the active layer of the second capacitor connection transistor includes a first seventh conductive portion, a seventh channel portion, and a second seventh conductive portion sequentially arranged along the first direction.
  • the scan driving circuit further includes a third voltage signal line
  • the third voltage signal line extends along the first direction
  • the orthographic projection of the third voltage signal line on the substrate, the orthographic projection of the first clock signal line on the substrate, and the orthographic projection of the second clock signal line on the substrate are all located
  • the orthographic projection of the shift register unit on the base is away from the side of the display area of the display substrate.
  • the scan driving circuit further includes a third voltage signal line;
  • the at least one shift register unit further includes an output capacitor, a first capacitor, a second capacitor, a first transistor, a second transistor, and a first capacitor connection A transistor, a second capacitor connecting transistor, a first node control transistor, a second node control transistor, an input transistor, and a third node control transistor;
  • the second electrode of the first transistor is coupled to the second plate of the output capacitor, the first electrode of the first transistor is coupled to the first voltage signal line, and the gate of the first transistor is Coupled to the second electrode of the third node control transistor;
  • the first electrode of the second transistor is coupled to the first plate of the first capacitor, the second electrode of the second transistor is coupled to the second electrode of the first capacitor connected to the transistor, and the second transistor The gate of is coupled to the gate of the third node control transistor;
  • the gate of the first capacitor-connecting transistor and the gate of the second capacitor-connecting transistor are respectively coupled to the second plate of the first capacitor; the first capacitor is connected to the second electrode of the transistor and the second electrode of the first capacitor.
  • the first plate of the first capacitor is coupled; the first electrode of the first capacitor connected to the transistor is coupled to the gate of the second transistor;
  • the first electrode of the second capacitor connection transistor is coupled to the first voltage signal line; the gate of the second capacitor connection transistor is coupled to the second electrode of the second node control transistor; the first The second electrode of the two capacitor connection transistor is coupled to the first electrode of the third node control transistor;
  • the first electrode of the first node control transistor is coupled to the gate of the second node control transistor; the gate of the first node control transistor is coupled to the second plate of the second capacitor;
  • the second electrode of the second node control transistor is coupled to the second electrode of the first node control transistor; the gate of the second node control transistor is coupled to the second clock signal line; the first The first electrode of the two-node control transistor is coupled to the third voltage signal line;
  • the gate of the input transistor is coupled to the gate of the second node control transistor; the first electrode of the input transistor is coupled to the input signal terminal; the second electrode of the input transistor is coupled to the second capacitor ⁇ second plate coupling;
  • the gate of the third node control transistor is coupled to the first clock signal line
  • the first plate of the output capacitor is coupled to the first voltage signal line, and the second plate of the output capacitor is coupled to the gate of the output reset transistor;
  • the second plate of the second capacitor is coupled to the gate of the output transistor, and the first plate of the second capacitor is coupled to the first clock signal line;
  • Both the second electrode of the output transistor and the second electrode of the output reset transistor are coupled to the signal output line.
  • the first clock signal line, the second clock signal line, and the third voltage signal line are arranged in sequence along a direction close to the display area; or, along a direction close to the display area,
  • the second clock signal line, the first clock signal line, and the third voltage signal line are arranged in order.
  • the first plate of the first capacitor includes a first horizontal plate portion and a first vertical plate portion;
  • the output transistor and the output reset transistor are arranged between the first voltage signal line and the second voltage signal line; along the first direction, the output reset transistor, the output transistor, and the The signal output lines are arranged in sequence;
  • the third voltage signal line is arranged on a side of the first voltage signal line away from the second voltage signal line; the first capacitor, the first transistor, the second transistor, the first capacitor connected to the transistor, The second capacitor connection transistor, the first node control transistor, the second node control transistor, the input transistor and the third node control transistor are all arranged between the first voltage signal line and the third voltage signal line;
  • the first transistor, the second transistor, and the first vertical plate portion are sequentially arranged along a first direction, the input transistor, the third node control transistor, the second capacitor connecting transistor, and The first horizontal plate portions are arranged in sequence along a first direction, and the second node control transistors and the first node control transistors are arranged in sequence along the first direction;
  • the orthographic projection of the gate of the first capacitor connecting transistor on the substrate is arranged on the substrate and the orthographic projection of the second electrode plate of the first capacitor on the substrate and the first voltage signal line on the substrate Between the orthographic projections;
  • the orthographic projection of the gate of the second transistor on the substrate is set at the third node and the orthographic projection of the gate of the control transistor on the substrate is in relation to the orthographic projection of the first voltage signal line on the substrate.
  • the orthographic projection of the gate of the first node control transistor on the substrate is arranged on the orthographic projection of the third voltage signal line on the substrate and the first plate of the first capacitor is on the substrate Between the orthographic projections;
  • the minimum distance between the orthographic projection of the gate of the first node control transistor on the substrate and the orthographic projection of the third voltage signal line on the substrate in the second direction is greater than the second capacitor connection.
  • the orthographic projection of the first electrode plate of the output capacitor on the substrate has a signal line overlapping area with the orthographic projection of the first voltage signal line on the substrate;
  • the orthographic projection of the diode and the substrate partially overlaps the orthographic projection of the first voltage signal line on the substrate;
  • the orthographic projection of the first electrode plate of the second capacitor on the substrate is within the orthographic projection of the second electrode plate of the second capacitor on the substrate; the first electrode plate of the second capacitor L-shaped;
  • the first plate of the second capacitor includes a second horizontal plate portion and a second vertical plate portion
  • the gate of the first node control transistor and the second horizontal plate portion are arranged along a first direction;
  • the orthographic projection of the second vertical plate portion on the substrate partially overlaps the orthographic projection of the third voltage signal line on the substrate.
  • the display substrate further includes a plurality of rows of pixel circuits arranged on the base; the pixel circuit includes a light-emitting control terminal;
  • the shift register unit included in the scan driving circuit corresponds to the row pixel circuit one-to-one
  • the signal output line of the shift register unit is coupled to the light emission control end of the corresponding row of pixel circuits, and is used to provide light emission control signals for the light emission control end of the corresponding row of pixel circuits.
  • an embodiment of the present disclosure also provides a method for manufacturing a display substrate.
  • the method for manufacturing the display substrate includes manufacturing a scan driving circuit on a base, and manufacturing at least one driver in a display area included in the display substrate.
  • Transistor the driving transistor is configured to drive a light-emitting element for display;
  • the scan driving circuit includes a plurality of shift register units, a first voltage signal line, a second voltage signal line, a first clock signal line, and a second clock signal line, and at least one of the plurality of shift register units shifts
  • the bit register unit includes an output circuit and a signal output line;
  • the manufacturing method of the display substrate further includes:
  • the first voltage signal line, the second voltage signal line, the first clock signal line, and the second clock signal line are arranged to extend along the first direction, and the signal output line is arranged to extend along the first direction. Extend in two directions;
  • the first direction and the second direction intersect.
  • the manufacturing method of the display substrate described in at least one embodiment of the present disclosure further includes:
  • the signal output line is arranged between output circuits in adjacent shift register units.
  • the first voltage signal line is located on a side of the second voltage signal line away from the display area.
  • the output circuit includes an output transistor and an output reset transistor, and the step of manufacturing the transistor included in the output circuit specifically includes:
  • a first gate metal layer is fabricated, and a patterning process is performed on the first gate metal layer to form the gate of the output transistor and the output reset transistor ⁇ Grid;
  • the portion of the first semiconductor layer that is not covered by the gate is doped so that the first semiconductor layer is not covered by the gate.
  • the part covered by the gate is formed as a conductive part, and the part covered by the gate in the first semiconductor layer is formed as a channel part.
  • the manufacturing method of the display substrate further includes: disposing a second gate metal layer on the side of the first gate metal layer facing away from the first semiconductor layer, and patterning the second gate metal layer Process to form a signal output line extending in the second direction;
  • the orthographic projection of the first semiconductor layer on the substrate and the orthographic projection of the signal output line on the substrate are arranged along a first direction, and the first direction intersects the second direction.
  • the steps of making the first voltage signal line, the second voltage signal line, the first clock signal line, and the second clock signal line specifically include:
  • a source-drain metal layer is formed on the side of the second gate metal layer facing away from the first gate metal layer, and a patterning process is performed on the source-drain metal layer to form the first voltage signal line and the second voltage signal line.
  • the voltage signal line, the first clock signal line, and the second clock signal line are formed on the side of the second gate metal layer facing away from the first gate metal layer, and a patterning process is performed on the source-drain metal layer to form the first voltage signal line and the second voltage signal line.
  • the number of the first voltage signal line is one;
  • the output circuit includes an output reset transistor;
  • the at least one shift register unit further includes an output capacitor, a first plate, and a second capacitor connecting transistor;
  • the manufacturing method of the display substrate further includes:
  • the first electrode of the output reset transistor, the first plate of the output capacitor, the first electrode of the first transistor, and the first electrode of the second capacitor connecting transistor are set to be all connected to the first electrode.
  • the voltage signal line is coupled.
  • an embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate.
  • FIG. 1 is a circuit diagram of at least one embodiment of at least one shift register unit included in a display substrate according to an embodiment of the present disclosure
  • FIG. 2A is a working timing diagram of at least one embodiment of the shift register unit shown in FIG. 1
  • 2B is a schematic diagram of the area division of the display substrate according to at least one embodiment of the present disclosure.
  • 2C is a schematic diagram of the connection relationship between the scan driving circuit and the pixel circuit included in the display substrate according to at least one embodiment of the present disclosure
  • 2D is a schematic diagram of a layout of a shift register unit provided by at least one embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of another layout of a shift register unit provided by at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of an active layer in a shift register unit provided by at least one embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of the first gate metal layer in the shift register unit provided by at least one embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of the second gate metal layer in the shift register unit provided by at least one embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a via used in a shift register unit provided by at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of the source and drain metal layers in the shift register unit provided by at least one embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of the division of the plates of the capacitor on the basis of FIG. 6;
  • 10A is the orthographic projection of the first voltage signal line VGH on the substrate and the orthographic projection of the first third conductive portion 211 used as the first electrode S8 of the first transistor T8 in the second semiconductor layer on the substrate Schematic diagram of the distance between;
  • 10B is the orthographic projection of the first voltage signal line VGH on the substrate and the orthographic projection of the second third conductive portion 212 used as the second electrode D8 of the first transistor T8 included in the second semiconductor layer on the substrate Schematic diagram of the distance between;
  • 10C is a schematic diagram of the distance between the orthographic projection of the grid G5 of T5 on the substrate, the orthographic projection of the grid G6 of T6 on the substrate, and the orthographic projection of the first voltage signal line VGH on the substrate.
  • the present disclosure provides a display substrate.
  • the display substrate includes a scan driving circuit located in an edge area of the display substrate.
  • the scan driving circuit includes a first voltage signal line VGH, a second voltage signal line VGL1, and a second voltage signal line VGL1.
  • the scan driving circuit further includes a plurality of shift register units;
  • At least one embodiment of at least one shift register unit of the plurality of shift register units includes an output reset transistor T9, an output transistor T10, an output capacitor C3, a first capacitor C1, and a second capacitor C2.
  • the first transistor T8 the second transistor T7, the first capacitor connection transistor T6, the second capacitor connection transistor T5, the first node control transistor T2, the second node control transistor T3, the input transistor T1 and the third node control transistor T4;
  • the gate G9 of the output reset transistor T9 is coupled to the second plate C3b of the output capacitor C3, and the first electrode S9 of the output reset transistor T9 is connected to a high voltage signal Vgh;
  • the gate G10 of the output transistor T10 is coupled to the second plate C2b of the second capacitor C2, and the first electrode S10 of the output transistor T10 is connected to a low voltage signal Vgl;
  • the second electrode D9 of the output reset transistor T9 and the second electrode D10 of the output transistor T10 are both coupled to the signal output line EOUT;
  • the second electrode D8 of the first transistor T8 is coupled to the second plate C3b of the output capacitor C3, the first electrode S8 of the first transistor T8 is connected to the high voltage signal Vgh, and the first The gate G8 of the transistor T8 is coupled to the second electrode D4 of the third node control transistor T4;
  • the second electrode D7 of the second transistor T7 is coupled to the first plate C1a of the first capacitor C1, and the first electrode S7 of the second transistor T7 is connected to the second plate C3b of the output capacitor C3. Coupled, the gate G7 of the second transistor T7 is coupled to the gate G4 of the third node control transistor T4;
  • the gate G6 of the first capacitor connecting transistor T6 and the gate G5 of the second capacitor connecting transistor T5 are respectively coupled to the second plate C1b of the first capacitor C1; the first capacitor is connected to the transistor T6
  • the second electrode D6 of the first capacitor is coupled to the first plate C1a of the first capacitor C1; the first electrode S6 of the first capacitor connecting transistor T6 is coupled to the gate G7 of the second transistor T7;
  • the first electrode S5 of the second capacitor connecting transistor T5 is coupled to the first voltage signal line VGH; the second capacitor connecting the gate G5 of the transistor T5 and the second electrode of the second node control transistor T3 D3 is coupled; the second electrode D5 of the second capacitor connection transistor T5 is coupled to the first electrode S4 of the third node control transistor T4;
  • the first electrode S2 of the first node control transistor T2 is coupled to the gate G3 of the second node control transistor T3; the gate G2 of the first node control transistor T2 and the second capacitor C2 are The diode C2b is coupled;
  • the second electrode D3 of the second node control transistor T3 is coupled to the second electrode D2 of the first node control transistor T2; the gate G3 of the second node control transistor T3 is connected to the second clock signal line CK is coupled; the first electrode S3 of the second node control transistor T3 is connected to the low voltage signal Vgl;
  • the gate G1 of the input transistor T1 is coupled to the gate G3 of the second node control transistor T3; the first electrode S1 of the input transistor T1 is coupled to the input signal terminal E1; the first electrode of the input transistor T1 is coupled to the input signal terminal E1.
  • the two electrodes D1 are coupled to the second plate C2b of the second capacitor C2;
  • the gate G4 of the third node control transistor T4 is coupled to the first clock signal line CB;
  • the first plate C3a of the output capacitor C3 is connected to the high voltage signal Vgh, and the second plate C3b of the output capacitor C3 is coupled to the gate G9 of the output reset transistor T9;
  • the second plate C2b of the second capacitor C2 is coupled to the gate G10 of the output transistor T10, and the first plate C2a of the second capacitor C2 is coupled to the first clock signal line CB.
  • all the transistors are p-type transistors, but not limited to this.
  • At least one embodiment of the shift register unit shown in FIG. 1 may be a light emission control scan driving circuit, but it is not limited thereto.
  • the first electrode of the transistor may be a source, and the second electrode of the transistor may be a drain; or, the first electrode of the transistor may be a drain, and the second electrode of the transistor may be a source.
  • the node labeled N1 is the first node
  • the node labeled N2 is the second node
  • the node labeled N3 is the third node
  • the node labeled N4 is the fourth node.
  • CK inputs a low level
  • T1 and T3 are turned on, and the turned-on T1 transmits the high-level input signal provided by E1 to the first node N1, so that the potential of the first node N1 becomes high T2, T8, and T10 are turned off; in addition, the turned-on T3 transmits Vgl to the second node N2, so that the level of the second node N2 becomes low, so T5 and T6 are turned on.
  • T7 is turned off; in addition, due to the energy storage effect of C3, the potential of the fourth node N4 can be maintained at a high level, so that T9 is turned off; in the first stage P1, because T9 and T10 are both End, EOUT keeps outputting low level;
  • CB inputs a low level, T4 and T7 are turned on; because the first clock signal CK is input high, T1 and T3 are turned off; due to the energy storage effect of the first capacitor C1, the second node N2 Can continue to maintain the low level of the previous stage, T5 and T6 are turned on, and Vgh is transmitted to the first node N1 through the turned on T5 and T4, so that the potential of the first node N1 continues to maintain the high power of the previous stage T2, T8, and T10 are turned off; in addition, the low level provided by CB is transmitted to the fourth node N4 through the turned-on T6 and T7, so that the potential of the fourth node N4 becomes low, so T9 is turned on ON, EOUT outputs high voltage signal Vgh;
  • CK inputs a low level, T1 and T3 are turned on; CB provides a high level, so T4 and T7 are turned off; due to the energy storage effect of C3, the potential of the fourth node N4 can maintain the previous stage Low level, so that T9 remains on, and EOUT outputs a high voltage signal Vgh;
  • CK inputs a high level, T1 and T3 are turned off; CB inputs a low level, T4 and T7 are turned on; due to the energy storage effect of the second capacitor C2, the potential of the first node N1 remains at the previous stage High level, which turns off T2, T8, and T10. Due to the energy storage effect of the first capacitor C1, the potential of the second node N2 continues to maintain the low level of the previous stage, so that T5 and T6 are turned on.
  • the low-voltage signal input by CB is transmitted to the fourth node N4 through the turned-on T6 and T7, so that the level of the fourth node N4 becomes low, T9 is turned on, and the turned-on T9 turns the high voltage Vgh Output, EOUT outputs high voltage signal Vgh;
  • CK inputs a low voltage signal
  • T1 and T3 are turned on
  • CB inputs a high voltage signal
  • T4 and T7 are turned off.
  • the turned-on T1 transmits the low-level input signal provided by E1 to the first node N1, so that the potential of the first node N1 becomes low, so T2, T8, and T10 are turned on; the turned-on T2 will be low
  • the level of the second clock signal is transmitted to the second node N2, so that the potential of the second node N2 can be further lowered, so the potential of the second node N2 continues to maintain the low level of the previous stage, so that T5 and T6 are turned on
  • the turned-on T8 transmits Vgh to the fourth node N4, so that the potential of the fourth node N4 becomes a high voltage, so T9 is turned off; the turned-on T10 outputs Vgl, and EOUT outputs the low-voltage signal Vgl.
  • the label J1 is the display substrate
  • the label A0 is the display area
  • the label B1 is the first edge area
  • the label B2 is the second edge area.
  • the display area A0 of the display substrate J1 may be provided with a plurality of light-emitting control lines, a plurality of gate lines, and a plurality of data lines, and a plurality of sub-pixels defined by the intersection of the plurality of gate lines and the plurality of data lines ;
  • a scan driving circuit may be provided in the first edge area B1 and/or the second edge area B2, and the scan driving circuit includes a plurality of shift register units;
  • the multiple shift register units included in the scan driving circuit correspond to the multiple light-emitting control lines one-to-one, and the signal output line of each shift register unit is coupled to the corresponding light-emitting control line for corresponding The light-emitting control line provides light-emitting control signals.
  • one of the light-emitting control lines is coupled to the light-emitting control end of the pixel circuit of the corresponding row.
  • the display substrate further includes a plurality of rows of pixel circuits arranged on the base; the pixel circuit includes a light-emitting control terminal;
  • the shift register unit included in the scan driving circuit corresponds to the row pixel circuit one-to-one
  • the signal output line of the shift register unit is coupled to the light emission control end of the corresponding row of pixel circuits, and is used to provide light emission control signals for the light emission control end of the corresponding row of pixel circuits.
  • the pixel circuit may be disposed in the effective display area of the display substrate, and the scan driving circuit may be disposed in the edge area of the display substrate.
  • Y1 is a scan driving circuit
  • S11 is the first stage shift register unit included in the scan driving circuit S1
  • S12 is the first shift register unit included in the scan driving circuit S1.
  • a two-stage shift register unit the one marked S1N-1 is the N-1th stage shift register unit included in the scan drive circuit S1
  • the one marked S1N is the Nth stage shift included in the scan drive circuit S1 Register unit, N is an integer greater than 3;
  • the pixel circuit labeled R1 is the first row of pixel circuits
  • the pixel circuit labeled R2 is the second row of pixel circuits
  • the pixel circuit labeled RN-1 is row N-1
  • the pixel circuit labeled RN is row N Pixel circuit
  • S11 corresponds to R1
  • S12 corresponds to R2
  • S1N-1 corresponds to RN-1
  • S1N corresponds to RN;
  • S11 provides R1 with the first row of light-emitting control signals, S12 for R2 with the second row of light-emitting control signals, S1N-1 provides R1N-1 with the N-1th row of light-emitting control signals, and S1N provides R1N with the Nth row of light-emitting control signals.
  • the display substrate may further include a gate driving circuit, and the gate driving circuit includes a multi-stage gate driving unit, and the gate driving unit and the pixel row are also in one-to-one correspondence. Used to provide corresponding gate drive signals for corresponding rows of pixels;
  • Y2 is the gate drive circuit
  • S21 is the first row of gate drive units included in the gate drive circuit
  • S22 is the second row of gates included in the gate drive circuit.
  • the driving unit, marked S2N-1 is the gate driving unit in the N-1th row included in the gate driving circuit
  • marked S2N is the gate driving unit in the Nth row included in the gate driving circuit.
  • the first voltage signal line VGH provides a high voltage signal Vgh
  • the second voltage signal line VGL1 and the third voltage signal line VGL2 provide a low voltage signal Vgl
  • the fourth voltage signal line VGH0 provides a high voltage signal Vgh
  • ESTV, VGH0, VGL2, VGH, VGL1, CK and CB are arranged in a direction away from the display area; ESTV, VGH0, VGL2, VGH, VGL1, CK and CB extend in the first direction;
  • T8 and T10 are arranged between VGL2 and VGH0, T9 and T10 are arranged along the first direction; T8 is arranged between T9 and VGL2;
  • T6, T7, C1, T1, T4 and T5 are set between VGH and VGL2;
  • C1 is set between VGL2 and T6;
  • T4 is set between VGL2 and T6;
  • T7 and T6 are arranged in sequence along the first direction, and T1, T4 and T5 are arranged in sequence along the first direction;
  • T2 and T3 are arranged between VGL1 and VGH, and T3 and T2 are arranged in sequence along the first direction;
  • the orthographic projection of C3 on the substrate partially overlaps the orthographic projection of VGH0 on the substrate, and the orthographic projection of C2 on the substrate partially overlaps the orthographic projection of VGL1 on the substrate.
  • D1 is multiplexed into D4, S4 is multiplexed into D5, and D6 is multiplexed into D7.
  • the gate labeled G1 is the gate of T1
  • the gate labeled S1 is the first electrode of T1
  • the gate labeled D1 is the second electrode of T1
  • the gate labeled G2 is the gate of T2
  • the first electrode labeled S2 is the first electrode of T2
  • the second electrode labeled D2 is the second electrode of T2
  • the gate labeled G3 is the gate of T3
  • the grid of T5 is G5, and the grid is S5
  • One electrode, labeled D8 is the second electrode of T8; labeled G9 is the gate of T9, labeled S9 is the first electrode of T9, labeled D9 is the second electrode of T9; labeled G10 It is the gate of T10, the first electrode labeled S10 is the first electrode of T10, and the second electrode labeled D10 is the second electrode of T10.
  • the use of two signal lines that provide high-voltage signals leads to messy connection of the signal lines, which does not make full use of the T10 and the first in the n-th stage shift register unit.
  • the space between the output reset transistors in the n+1 stage shift register unit is set to EOUT, and C1 does not fully utilize the space between the gate of T5 and the second conductive connection part, and C2 does not fully utilize the space between T2 and the adjacent next.
  • the space between the stage shift register units causes the lateral width of the shift register units to be large, which is not conducive to the development of a narrow frame of the display substrate.
  • the shift register unit shown in FIG. 2D may be an n-th stage shift register unit included in the scan driving circuit, and n is a positive integer.
  • the inventors of the present disclosure have discovered through research that the layout of the transistors in the shift register unit can be adjusted to reduce the occupied area of the shift register unit, thereby reducing the frame width of the display substrate.
  • the first voltage signal line VGH provides a high voltage signal Vgh
  • the second voltage signal line VGL1 and the third voltage signal line VGL2 provide a low voltage signal Vgl; at least one embodiment of the present disclosure reduces one Provide a signal line for the high-voltage signal Vgh, and set VGH between VGL1 and VGL2 to facilitate layout.
  • the fourth voltage signal line VGH0 is removed, and only the first voltage signal line VGH, the second voltage signal line VGL1, and the third voltage signal line VGL2 are used, and VGH Set between VGL1 and VGL2.
  • the first electrode S9 of the output reset transistor T9 is coupled to the first voltage signal line VGH
  • the first electrode S10 of the output transistor T10 is coupled to the second voltage signal line VGL1
  • the first electrode S10 of the output transistor T10 is coupled to the second voltage signal line VGL1.
  • the first electrode S8 of a transistor T8 is coupled to the first voltage signal line VGH
  • the first electrode S5 of the second capacitor connection transistor T5 is coupled to the first voltage signal line VGH
  • the first electrode S3 of the control transistor T3 is coupled to the third voltage signal line VGL2, and the first plate C3a of the output capacitor C3 is coupled to the first voltage signal line VGH.
  • the second voltage signal line VGL1, the first voltage signal line VGH, and the The three voltage signal lines VGL2 are arranged in sequence; the second voltage signal line VGL1, the first voltage signal line VGH and the third voltage signal line VGL2 all extend along the first direction;
  • a first clock signal line CB, a second clock signal line CK and a starting voltage signal line ESTV are provided on the side of the third voltage signal line VGL2 away from the first voltage signal line VGH;
  • the first clock signal line CB, the second clock signal line CK, and the start voltage signal line ESTV are arranged in sequence along the second direction away from the display area;
  • the first clock signal line CB, the second clock signal line CK, and the start The voltage signal lines ESTV all extend along the first direction;
  • the output reset transistor T9 and the output transistor T10 are arranged between the first voltage signal line VGH and the second voltage signal line VGL1; along the first direction, the output reset transistor T9, the output transistor The transistor T10 and the signal output line EOUT are arranged in sequence;
  • the first capacitor C1, the first transistor T8, the second transistor T7, the first capacitor connecting transistor T6, the second capacitor connecting transistor T5, the first node control transistor T2, the second node control transistor T3, and the input transistor T1 And the third node control transistor T4 are both arranged between the first voltage signal line VGH and the third voltage signal line VGL2;
  • the first transistor T8, the second transistor T7, and the first capacitor C1 are sequentially arranged along a first direction, the input transistor T1, the third node control transistor T4, and the second capacitor connection transistor T5 and the first capacitor C1 are arranged in sequence along the first direction, and the second node control transistor T3 and the first node control transistor T2 are arranged in sequence along the first direction;
  • the second transistor T7 and the third node control transistor T4 are sequentially arranged along the second direction;
  • the first capacitor connection transistor T6 and the second capacitor connection transistor T5 are arranged in sequence along the second direction;
  • the first transistor T8, the input transistor T1, and the second node control transistor T3 are arranged along a second direction;
  • the active pattern of the first node control transistor T2 is arranged in a U-shaped structure, so that T2 is formed as a double gate structure.
  • the input signal terminal of the first-stage shift register unit included in the scan driving circuit is coupled to the start signal line ESTV, and the input signal terminal is connected to the first electrode of the input transistor T1. S1 coupled terminal.
  • the first direction intersects the second direction.
  • the first direction may be perpendicular to the second direction, but it is not limited thereto.
  • the angle at which the second direction intersects with the first direction can be set according to actual needs.
  • the second direction is perpendicular to the first direction.
  • the position of the first clock signal line CB and the position of the second clock signal line CK can be reversed, but this is limited.
  • the first direction may be a vertical direction from top to bottom, and the second direction may be a horizontal direction from right to left, but it is not limited to this.
  • the width of the signal line mainly affects the resistance, and a wider signal line has less resistance, which is beneficial to signal stability.
  • the first voltage signal line VGH, the second voltage signal line VGL1, and the third voltage signal line VGL2 provide a direct current voltage, which is less affected by the line width.
  • the first clock signal line CB and the second clock signal line CK provide clock signals. When the potential of the clock signal is converted from a high voltage to a low voltage, the low resistance of the clock signal line makes the potential of the clock signal faster. A low voltage is reached. Therefore, in at least one embodiment of the present disclosure, the line width of the first clock signal line CB and the line width of the second clock signal line are set to be wider.
  • the orthographic projection of the first plate C3a of the output capacitor C3 on the substrate has a signal line overlap area with the orthographic projection of the first voltage signal line VGH on the substrate;
  • the orthographic projection of the second plate C3b of the output capacitor C3 and the substrate on the substrate partially overlaps the orthographic projection of the first voltage signal line VGH on the substrate;
  • the orthographic projection of the first electrode plate C2a of the second capacitor C2 on the substrate is within the orthographic projection of the second electrode plate C2b of the second capacitor C2 on the substrate; the second capacitor C2
  • the first plate C2a is L-shaped;
  • the lateral part of the first plate of C2 is arranged between T2 in the n-th stage shift register unit and the second node control transistor in the n+1-th stage shift register unit, making full use of the n-th T2 in the stage shift register unit and the second node in the n+1th stage shift register unit control the space between the transistors, and the lateral part of the first plate of C1 is located at the gate of T5 and the second conductive connection Between the portions L2, the space between the gate of T5 and the second conductive connection portion L2 is fully utilized.
  • the output reset transistor T9 is coupled to the first voltage signal line VGH, and the output transistor T10 is coupled to the second voltage signal line VGL1, the output reset transistor T9 and the output transistor T10 are coupled to each other.
  • the shift register unit shown in FIG. 3 may be an n-th stage shift register unit included in the scan driving circuit, and n is a positive integer.
  • T8 is arranged on the side of the first voltage signal line VGH away from the second voltage signal line VGL1, and T8 is arranged close to the adjacent upper stage shift register unit, so as to utilize the nth stage of shifting.
  • T7, T6 and C1 are all set in the space between T8 in the nth stage shift register unit and the first transistor included in the n+1 stage shift register unit, making full use of the nth stage The space between T8 in the shift register unit and the first transistor included in the n+1-th stage shift register unit.
  • the gate G5 of T5 is coupled to the second plate C1b of C1
  • the second electrode D6 of T6 is coupled to the first plate C1a of the first capacitor C1
  • the position of T5 and the position of T6 are It should be close to VGH and shorten the distance between T5 and T6 to adjust the shape of C1.
  • at least one embodiment of the present disclosure configures the electrode plate of the first capacitor C1 to be L-shaped.
  • C2 makes full use of the extra space between T2 in the n-th stage shift register unit and the second node control transistor in the n+1-th stage shift register unit to reduce the capacitance of the second capacitor C2
  • the pole plate is set in an L shape.
  • the display substrate includes a scan driving circuit and a display area disposed on the substrate, the scan driving circuit includes a plurality of shift register units; the scan driving circuit It also includes a first voltage signal line VGH, a second voltage signal line VGL1, a first clock signal line CB, and a second clock signal line CK; the first voltage signal line VGH, the second voltage signal line VGL1, and the The first clock signal line CB and the second clock signal line CK extend along a first direction; the display area includes at least one driving transistor configured to drive a light-emitting element for display;
  • At least one shift register unit of the plurality of shift register units includes an output circuit O1 and a signal output line EOUT;
  • the output circuit O1 is connected to the first voltage signal line VGH and the second voltage signal line VGL1, respectively Coupled to the signal output line EOUT;
  • the signal output line EOUT extends along a second direction, and the first direction intersects the second direction;
  • the transistor included in the output circuit O1 is disposed between the first voltage signal line VGH and the second voltage signal line VGL1.
  • the output circuit O1 is disposed between the first voltage signal line VGH and the second voltage signal line VGL1, so that in terms of the spatial structure, the first voltage signal line VGH is disposed on the output circuit O1 A side away from the display area, and no other signal lines and other components included in transistors are arranged between the first voltage signal line VGH and the output circuit O1, and the second voltage signal line VGL1 is arranged on the output circuit O1 close to the display area On the other side, the second voltage signal line VGL1 and the output circuit O1 are not provided with other signal lines and other components included in the transistor.
  • the distance between the first voltage signal line VGH and the output circuit O1 can be narrowed and reduced
  • the distance between the second voltage signal line VGL1 and the output circuit O1 is narrowed, so that the lateral width of the shift register unit is reduced.
  • the first voltage signal line VGH is located on a side of the second voltage signal line VGL1 away from the display area.
  • the first voltage signal line VGH provides a first voltage to the output circuit O1
  • the second voltage signal line VGL1 provides a second voltage to the output circuit O1
  • the first voltage signal line VGL1 provides a second voltage to the output circuit O1.
  • a voltage is higher than the second voltage.
  • the first voltage may be a high voltage Vgh
  • the second voltage may be a low voltage Vgl, but not limited to this.
  • the output circuit may include an output transistor and an output reset transistor
  • the output reset transistor and the output transistor are arranged along a first direction;
  • the first electrode of the output reset transistor is coupled to the first voltage signal line, and the first electrode of the output transistor is coupled to the second voltage signal line.
  • the output circuit O1 includes an output reset transistor T9 and an output transistor T10;
  • the output reset transistor T9 and the output transistor T10 are arranged in order from top to bottom.
  • the first electrode S9 of the output reset transistor T9 is coupled to the first voltage signal line VGH.
  • the electrode S10 is coupled to the second voltage signal line VGL1.
  • the second electrode of the output transistor and the second electrode of the output reset transistor are both coupled to the signal output line;
  • the signal output line is located between output circuits in adjacent shift register units.
  • the output transistor and the output reset transistor are both coupled to the signal output line, then the output transistor and the output reset transistor should be closer to the signal output line.
  • the signal output line is moved down to between the output circuits in adjacent shift register units to narrow the lateral width of the shift register units.
  • the output reset transistor T9 is used to provide an invalid light emission control signal
  • the output transistor T10 is used to provide an effective light emission control signal
  • the effective light emission control signal may be a voltage signal capable of turning on the light emission control transistor in the pixel circuit (the gate of the light emission control transistor is coupled to the light emission control line),
  • the invalid light emission control signal may be a voltage signal capable of turning off the light emission control transistor.
  • the display area of the display substrate includes a plurality of sub-pixels; at least one of the plurality of sub-pixels includes a pixel driving circuit; the pixel driving circuit includes a driving transistor, a gate line, a light-emitting control line, and a data line, so The driving transistor is configured to drive a light-emitting element for display; a plurality of shift register units included in the scan driving circuit correspond to a plurality of light-emitting control lines, and the signal output line of each shift register unit corresponds to The light-emitting control line is coupled to provide a light-emitting control signal for the corresponding light-emitting control line.
  • the active layer of the output transistor and the active layer of the output reset transistor are formed by a continuous first semiconductor layer
  • the first semiconductor layer and the signal output line are arranged along a first direction.
  • the active layer of the output transistor and the active layer of the output reset transistor may be formed by a continuous first semiconductor layer, but it is not limited to this.
  • the active layer of the output transistor and the active layer of the output reset transistor may be formed of a continuous first semiconductor layer
  • the active layer of the output reset transistor includes at least two first conductive portions and at least one first channel portion arranged opposite to each other in a first direction; each of the first channel portions is arranged on two adjacent first channel portions. Between a conductive part;
  • the active layer of the output transistor may include at least two second conductive portions and at least one second channel portion arranged opposite to each other along the first direction; each of the second channel portions is arranged on two adjacent Between the second conductive parts;
  • the first conductive part of the active layer of the output reset transistor that is closest to the active layer of the output transistor can be multiplexed as the second conductive part of the output transistor, which can further reduce the size of the output transistor and the output transistor.
  • the layout space of the output reset transistor is beneficial to realize the narrow frame of the display substrate.
  • the active layer of the output reset transistor T9 and the active layer of the output transistor T10 may be formed by a continuous first semiconductor layer 10;
  • the active layer of the output reset transistor T9 includes a first first conductive portion 111, a second first conductive portion 112, and a third first conductive portion 113 that are arranged oppositely along the first direction.
  • the output reset transistor also includes a first first channel portion 121 and a second first channel portion 122;
  • the first first channel portion 121 is disposed between the first first conductive portion 111 and the second first conductive portion 112, and the second first channel portion 122 is disposed between Between the second first conductive portion 112 and the third first conductive portion 113;
  • the first conductive part 113 is multiplexed as the first second conductive part included in the active layer of the output transistor T10;
  • the active layer of the output transistor T10 further includes a second second conductive portion 132 and a third second conductive portion 133 arranged opposite to each other along the first direction, and the active layer of the output transistor T10 further includes a first The second channel portion 141 and the second second channel portion 142;
  • the first second channel portion 141 is disposed between the first second conductive portion and the second second conductive portion 132, and the second second channel portion 142 is disposed between the second Between the second conductive portion 132 and the third second conductive portion 133.
  • the conductive parts on both sides of the channel part of each transistor may correspond to the first electrode and the second electrode of the transistor, or may be connected to the transistor's
  • the first electrode is coupled to the second electrode of the transistor, so that T9 and T10 can be electrically connected through the third first conductive portion 113.
  • the first semiconductor material layer may be formed first, and then after the gate G9 of the output reset transistor T9 and the gate G10 of the output transistor T10 are formed, the output reset transistor T9 may be formed.
  • the gate G9 of the output transistor T10 and the gate G10 of the output transistor T10 are masks, and the portions of the first semiconductor material layer that are not covered by the gates of the transistors are doped so that the first semiconductor material layer is not covered by the transistors
  • the portion covered by the gate of the first semiconductor material layer is formed as the conductive portion, and the portion covered by each transistor in the first semiconductor material layer is formed as the channel portion.
  • the output reset transistor T9 and the output transistor T10 in the shift register unit can be arranged along the first direction.
  • the area occupied by the shift register unit in the second direction makes the display substrate more in line with the development demand of narrow frame.
  • the gate of the output reset transistor may include at least one output reset gate pattern, the first electrode of the output reset transistor includes at least one first electrode pattern, and the second electrode of the output reset transistor includes at least one Second electrode pattern;
  • the output reset gate pattern is located between the adjacent first electrode pattern and the second electrode pattern;
  • the second electrode pattern, the output reset gate pattern, and the first electrode pattern all extend along a second direction;
  • the first direction intersects the second direction.
  • the gate of the output transistor may include at least two output gate patterns arranged in a first direction, the first electrode of the output transistor includes at least one third electrode pattern, and the second electrode of the output transistor Including at least one fourth electrode pattern;
  • the output gate pattern is located between the adjacent third electrode pattern and the fourth electrode pattern;
  • the fourth electrode pattern, the output gate pattern, and the third electrode pattern all extend along the second direction;
  • the first direction intersects the second direction
  • the second electrode pattern closest to the gate of the output transistor in the output reset transistor is multiplexed as a fourth electrode pattern of the output transistor.
  • the number of output reset gate patterns, the number of first electrode patterns, the number of second electrode patterns, the number of output gate patterns, and the number of third electrode patterns And the number of the fourth electrode patterns can be set according to actual needs.
  • the number of output gate patterns and the number of output reset gate patterns may be two, and the number of first electrode patterns and the number of third electrode patterns may be It is one, and the number of the second electrode patterns and the number of the fourth electrode patterns may be two.
  • the second electrode of the output transistor and the second electrode of the output reset transistor are both coupled to the signal output line, when the output transistor and the output reset transistor are laid out, the closest one of the output reset transistors can be placed.
  • the second electrode pattern of the gate of the output transistor is multiplexed into the fourth electrode pattern of the output transistor, which can further reduce the layout space of the output transistor and the output reset transistor, which is beneficial to realize a narrow frame of the display substrate.
  • the gate G9 of the output reset transistor T9 may include: a first output reset gate pattern G91 and a second output reset gate pattern G92;
  • the gate G10 of the output transistor T10 may include: a first output gate pattern G101 and a second output gate pattern G102;
  • a first output reset gate pattern G91, a second output reset gate pattern G92, the first output gate pattern G101, and the second output gate pattern G102 are arranged in sequence along a first direction;
  • the first output reset gate pattern G91, the second output reset gate pattern G92, the first output gate pattern G101, and the second output gate pattern G102 all extend in the second direction, and the second direction is the same as the first Direction intersect
  • the first output reset gate pattern G91 and the second output reset gate pattern G92 are coupled to each other, and the first output gate pattern G101 and the second output gate pattern G102 are coupled to each other;
  • the second electrode D9 of the output reset transistor T9 includes a first second electrode pattern D91 and a second second electrode pattern D92;
  • D91, S9, and D92 are sequentially arranged along the first direction, and D91, S9, and D92 all extend along the second direction, and S9 is coupled to the first voltage signal line VGH;
  • D92 is multiplexed as the first fourth electrode pattern in the second electrode D10 of the output transistor T10;
  • the second electrode D10 of the output transistor T10 further includes a second fourth electrode pattern D102;
  • D92, S10 and D102 are arranged in sequence along the first direction; S10 is coupled to the second voltage signal line VGL1;
  • the orthographic projection of G91 on the substrate is set between the orthographic projection of D91 on the substrate and the orthographic projection of S9 on the substrate.
  • the orthographic projection of G92 on the substrate Set between the orthographic projection of S9 on the substrate and the orthographic projection of D92 on the substrate, the orthographic projection of G101 on the substrate is between the orthographic projection of D92 on the substrate and the orthographic projection of S10 on the substrate, and the orthographic projection of G102 on the substrate
  • the orthographic projection on the substrate is between the orthographic projection of S10 on the substrate and the orthographic projection of D102 on the substrate.
  • the shift register unit when at least one shift register unit included in the scan driving circuit is in operation, when T10 is turned on, the shift register unit continuously outputs a low voltage signal, in order to keep the gate of T10 connected
  • the voltage signal is stable, and the gate G10 of T10 should be avoided to overlap with the clock signal line.
  • G10 is set to overlap with the second voltage signal line VGL1 (VGL1 is the DC voltage signal line), and the gate G10 of T10 is connected
  • VGL1 is the DC voltage signal line
  • the active layer of the output reset transistor may include at least two first conductive parts and at least one first channel part arranged oppositely along the first direction; each of the first channel parts is arranged Between two adjacent first conductive parts;
  • the first channel portion corresponds to the output reset gate pattern one-to-one, and the orthographic projection of each first channel portion on the substrate is located in the corresponding output reset gate pattern.
  • a part of the first conductive part in the output reset transistor corresponds to the first electrode pattern one-to-one, and the orthographic projection of the first electrode pattern on the substrate is in the same position as the corresponding first conductive part.
  • the other part of the output reset transistor, the first conductive part corresponds to the second electrode pattern one-to-one, and the orthographic projection of the second electrode pattern on the substrate corresponds to the first conductive part
  • the orthographic projection on the substrate has a second overlap area, and the second electrode pattern is coupled to the corresponding first conductive portion through at least one second via provided in the second overlap area.
  • the active layer of the output transistor may include at least two second conductive parts and at least one second channel part arranged oppositely along the first direction; each of the second channel parts is arranged at Between two adjacent second conductive parts;
  • the second channel portion corresponds to the output gate pattern one-to-one, and the orthographic projection of each second channel portion on the substrate is located on the corresponding output gate pattern on the substrate.
  • a part of the second conductive part in the output transistor corresponds to the third electrode pattern one-to-one, and the orthographic projection of the third electrode pattern on the substrate corresponds to the second conductive part at the same position.
  • the other part of the second conductive part in the output transistor corresponds to the fourth electrode pattern on a one-to-one basis.
  • the orthographic projection of the fourth electrode pattern on the substrate is aligned with the corresponding second conductive part.
  • the orthographic projection on the substrate has a fourth overlap area, and the fourth electrode pattern is coupled to the corresponding second conductive portion through at least one fourth via provided in the fourth overlap area.
  • the first first channel portion 121 corresponds to the first output reset gate pattern G91
  • the second first channel portion 122 corresponds to the second output reset gate pattern G91.
  • polar pattern G92 corresponds to polar pattern G92
  • the orthographic projection of the first first channel portion 121 on the substrate is located inside the orthographic projection of G91 on the substrate;
  • the orthographic projection of the second first channel portion 122 on the substrate is located inside the orthographic projection of G92 on the substrate;
  • the first first conductive portion 111 corresponds to the first second electrode pattern D91
  • the second first conductive portion 112 corresponds to the first electrode S9 of the output reset transistor
  • the third first conductive portion 113 corresponds to the second
  • the second electrode pattern D92 corresponds;
  • the orthographic projection of S9 on the substrate and the orthographic projection of the second first conductive part 112 on the substrate have a first overlap area.
  • S9 passes through at least one first via H1 and a second A first conductive portion 112 is coupled;
  • the orthographic projection of D91 on the substrate and the orthographic projection of the first first conductive part 111 on the substrate have a first second overlap area, and D91 passes through at least one second overlap area disposed in the first second overlap area.
  • the via hole H2 is coupled to the first first conductive portion 111;
  • the orthographic projection of D92 on the substrate and the orthographic projection of the third first conductive part 113 on the substrate have a second second overlap area, and D92 passes through at least one of the second overlap areas provided in the second overlap area.
  • the two via holes H2 are coupled to the third first conductive portion 113;
  • the first second channel portion 141 corresponds to the first output gate pattern G101, and the second second channel portion 142 corresponds to the second output gate pattern G102;
  • the orthographic projection of the first second channel part 141 on the substrate is located inside the orthographic projection of G101 on the substrate;
  • the orthographic projection of the second second channel portion 142 on the substrate is located inside the orthographic projection of G102 on the substrate;
  • D92 is multiplexed as the first fourth electrode pattern; the third first conductive part 113 is multiplexed as the first second conductive part;
  • the first second conductive part corresponds to the first fourth electrode pattern
  • the second second conductive portion 132 corresponds to the first electrode S10 of the output transistor, and the third second conductive portion 133 corresponds to the second fourth electrode pattern D102;
  • the orthographic projection of S10 on the substrate and the orthographic projection of the second second conductive part 132 on the substrate have a third overlap area, and S10 passes through at least one third via H3 provided in the third overlap area and the second A second conductive portion 132 is coupled;
  • the orthographic projection of D102 on the substrate and the orthographic projection of the third second conductive portion 133 on the substrate have a fourth overlap area, and D102 passes through at least one fourth via H4 arranged in the fourth overlap area and the first
  • the three second conductive parts 133 are coupled.
  • the number of first vias, the number of second vias, the number of third vias, and the number of fourth vias can be set according to actual needs.
  • the first semiconductor layer 10 is used to form the active layer of the output reset transistor T9 and the active layer of the output transistor T10, which not only makes the space occupied by T9 and T10 in the second direction smaller, but also
  • the size of the active layer of the output reset transistor T9 and the active layer of the output transistor T10 in the first direction can be increased to ensure the channel width of T9 and the channel width of T10, so as to ensure the working performance of T9 and In the case of T10 performance, reduce the frame width of the display substrate.
  • FIG. 4 is a schematic diagram of the active layer in FIG. 3
  • FIG. 5 is a schematic diagram of the first gate metal layer in FIG. 3
  • FIG. 6 is a schematic diagram of the second gate metal layer in FIG. Schematic diagram
  • FIG. 7 is a schematic diagram of vias made after the active layer, the first gate metal layer and the second gate metal layer are sequentially arranged
  • FIG. 8 is a schematic diagram of the source and drain metal layers in FIG. 3.
  • an active layer, a first gate metal layer, a second gate metal layer, a via hole, and a source-drain metal layer are sequentially arranged on the base to form a display substrate.
  • the at least one shift register unit may also include a plurality of transistors; the conductive parts on both sides of the channel part of each transistor may be separately It corresponds to the first electrode and the second electrode of the transistor, or can be respectively coupled to the first electrode of the transistor and the second electrode of the transistor.
  • the number of the first voltage signal line VGH may be one;
  • the output circuit includes an output reset transistor T9; the at least one shift register unit also includes an output capacitor C3, a first transistor T8, and a second capacitor connection transistor T5;
  • the first electrode of the output reset transistor T9, the first plate of the output capacitor C3, the first electrode of the first transistor T8, and the first electrode of the second capacitor connecting transistor T5 are all connected to the first electrode of the second capacitor connecting transistor T5.
  • a voltage signal line VGH is coupled, so that each transistor included in the shift register unit is coupled to the same first voltage signal line VGH, reducing the number of signal lines used.
  • the first voltage signal line VGH can simultaneously connect the first electrode of the transistor T5 and the first electrode of the first transistor T8 for the second capacitor. Provide a first voltage signal, and enable the first voltage signal line VGH to charge the first plate of the output capacitor C3.
  • the display substrate further includes a third voltage signal line VGL2, and the first voltage signal line VGH is located between the second voltage signal line VGL1 and the third voltage signal line VGL3.
  • the first electrode S5 of the second capacitor connection transistor T5 is coupled to the signal line conductive connection portion L40 through the fifth connection via H85, and the signal line is conductive
  • the connecting portion L40 is coupled to the first voltage signal line VGH, so that the first electrode S5 of the second capacitor connection transistor T5 is coupled to the first voltage signal line VGH;
  • the signal line conductive connection portion L40 and the first voltage signal line VGH are included in the source and drain metal layer, and the first electrode S5 of the second capacitor connection transistor T5 is included in the active layer.
  • the at least one shift register unit further includes a first capacitor C1;
  • the orthographic projection of the signal line conductive connection portion L40 on the substrate partially overlaps the orthographic projection of the first electrode plate C1a of the first capacitor C1 on the substrate.
  • the orthographic projection of the first plate C3a of the output capacitor C3 on the substrate is identical to the orthographic projection of the first voltage signal line VGH on the substrate.
  • the first plate C3a of the output capacitor C3 is coupled to the first voltage signal line VGH through at least one signal line via H01 provided in the signal line overlapping area.
  • the at least one shift register unit may further include an output capacitor C3 and a first transistor T8;
  • the orthographic projection of the first plate C3a of the output capacitor C3 on the substrate is identical to the orthographic projection of the first voltage signal line VGH on the substrate.
  • the first plate C3a of the output capacitor C3 is coupled to the first voltage signal line VGH through at least one signal line via H01 provided in the signal line overlapping area;
  • the first transistor T8 is located on a side of the first voltage signal line VGH away from the output reset transistor T9;
  • the at least one shift register unit further includes a plate conductive connection portion 71 coupled to the second electrode D8 of the first transistor T8;
  • the second electrode D8 of the first transistor T8 is coupled to the electrode plate conductive connection portion 71 through a first connection via H81;
  • the orthographic projection of the electrode plate conductive connection portion 71 on the substrate is similar to that of the second electrode plate C3b of the output capacitor C3 on the substrate
  • the plate conductive connecting portion 71 is coupled to the second plate C3b of the output capacitor C3 through at least one plate via H02 provided in the plate overlapping area;
  • the first electrode S8 of the first transistor T8 is coupled to the first voltage signal line VGH.
  • the first electrode S8 of the first transistor T8 is coupled to the first voltage signal line VGH through a second connection via H82.
  • T8 is moved to the side of the first voltage signal line VGH far away from the second voltage signal line VGL1, and the orthographic projection of the plate of the output capacitor C3 on the substrate is set to be the same as the first voltage signal line VGH.
  • the orthographic projection of the signal line VGH on the substrate is partially overlapped to reduce the distance between the first electrode S8 of the first transistor T8 and the first voltage signal line VGH, and reduce the second electrode D8 of the first transistor T8 and the output capacitor.
  • the distance between the second plate C3b of C3 allows T8 to be easily coupled to the first voltage signal line VGH and the second plate C3b of the output capacitor C3, so that the space is compact and the layout is more reasonable.
  • the maximum distance in the second direction between the orthographic projection of the first electrode S8 of the first transistor T8 on the substrate and the orthographic projection of the first voltage signal line VGH on the substrate is smaller than the first A predetermined distance
  • the maximum distance in the second direction between the orthographic projection of the second electrode D8 of the first transistor T8 on the substrate and the orthographic projection of the second electrode plate C3b of the output capacitor C3 on the substrate is smaller than the first Two predetermined distances, so that the first transistor T8 is close to the first voltage signal line VGH and the output capacitor C3, shortens the lateral width of the shift register unit, and facilitates the realization of a narrow frame.
  • the first predetermined distance and the second predetermined distance may be selected according to actual conditions, for example, the first predetermined distance may be greater than or equal to 20um (micrometers) and less than or equal to 30um , The second predetermined distance may be greater than or equal to 25um (micrometer) and less than or equal to 35um.
  • S8 and D8 are disposed on the active layer.
  • the first third conductive portion 211 is used as the first electrode S8 of the first transistor T8.
  • the second third conductive portion 212 serves as the second electrode D8 of the first transistor T8.
  • the maximum value in the second direction between the orthographic projection of the first electrode S8 of the first transistor T8 on the substrate and the orthographic projection of the first voltage signal line VGH on the substrate refers to: between any point on the edge line of the orthographic projection of the first electrode S8 of the first transistor T8 on the substrate and the edge line of the orthographic projection of the first voltage signal line VGH on the substrate , The maximum distance along the second direction;
  • the maximum distance in the second direction between the orthographic projection of the second electrode D8 of the first transistor T8 on the substrate and the orthographic projection of the second electrode plate C3b of the output capacitor C3 on the substrate refers to:
  • the second electrode D8 of the first transistor T8 is between any point on the edge line of the orthographic projection on the substrate and between the edge line of the second electrode plate C3b of the output capacitor C3 on the orthographic projection on the substrate, along the first The maximum distance in both directions.
  • X1 is the edge line of the orthographic projection of the first electrode S8 of the first transistor T8 on the substrate
  • X2 is the first voltage signal line VGH on the substrate
  • the edge line of the orthographic projection of the X3 is the edge line of the orthographic projection of the second electrode D8 of the first transistor T8 on the substrate
  • the X4 is the second plate C3b of the output capacitor C3. The edge line of the orthographic projection on the substrate.
  • d1 is the difference between the orthographic projection of the first electrode S8 of the first transistor T8 on the substrate and the orthographic projection of the first voltage signal line VGH on the substrate in the second direction. Maximum distance.
  • the second electrode D8 of the first transistor T8 is between the orthographic projection of the second electrode D8 of the first transistor T8 on the substrate and the orthographic projection of the second electrode plate C3b of the output capacitor C3 on the substrate. The maximum distance in the direction.
  • the gate G9 of the output reset transistor T9 includes a first output reset gate pattern G91 and a second output reset gate pattern G92 and a second plate C3b of the output capacitor C3. Coupling
  • the orthographic projection of the first plate C3a of the output capacitor C3 on the substrate and the orthographic projection of the second plate C3b of the output capacitor C3 on the substrate are at least partially overlapping.
  • the display substrate may further include a third voltage signal line; the third voltage signal line is located on a side of the first transistor away from the first voltage signal line;
  • the third voltage signal line extends along the first direction.
  • the third voltage signal line may be a low voltage signal line, and the low voltage provided by the third voltage signal line may be the same as the low voltage provided by the first voltage signal line, but not limit.
  • the first transistor may be arranged between the first voltage signal line and the third voltage signal line.
  • the at least one shift register unit may further include a second transistor T7;
  • the active layer of the first transistor T8 and the active layer of the second transistor T7 are formed by a continuous second semiconductor layer 20; the second semiconductor layer 20 extends along the first direction ;
  • the active layer of the first transistor T8 includes a first third conductive portion 211, a third channel portion 221, and a second third conductive portion 212 sequentially arranged along the first direction;
  • the second third conductive part 212 is multiplexed into the first fourth conductive part
  • the active layer of the second transistor T7 includes the first fourth conductive portion, the fourth channel portion 241, and the second fourth conductive portion 232 sequentially arranged along the first direction;
  • the second electrode D8 of the first transistor T8 is multiplexed as the first electrode S7 of the second transistor T7.
  • the first third conductive portion 211 is used as the first electrode S8 of the first transistor T8, and the second third conductive portion 212 is used as the first transistor T8
  • the second electrode D8 of T8; the second fourth conductive portion 232 serves as the second electrode D7 of the second transistor T7.
  • T7 is disposed between T8 and C1, and the second electrode S8 of T8 is multiplexed as the second electrode of T7 to narrow the lateral width of the shift register unit while reducing The vertical height of the shift register unit.
  • the at least one shift register unit may further include a first capacitor, and a transistor coupled to the second plate of the first capacitor;
  • the first capacitor and the transistor coupled to the second plate of the first capacitor are both arranged on a side of the first voltage signal line away from the second voltage signal line;
  • the maximum distance in the second direction between the orthographic projection of the gate of the transistor coupled to the second plate of the first capacitor on the substrate and the orthographic projection of the first voltage signal line on the substrate Less than the third predetermined distance.
  • the position of the transistor coupled to the second plate of the first capacitor is It is better to be close to the first voltage signal line.
  • At least one embodiment of the present disclosure connects the orthographic projection of the gate of the transistor coupled to the second plate of the first capacitor on the substrate to the first voltage signal line The maximum distance in the second direction between the orthographic projections on the substrate is set to be smaller than the third predetermined distance to narrow the lateral width of the shift register unit.
  • the third predetermined distance may be selected according to actual conditions, for example, the third predetermined distance is greater than or equal to 30 um (micrometers) and less than or equal to 40 um.
  • between the orthographic projection of the gate of the transistor coupled to the second plate of the first capacitor on the substrate and the orthographic projection of the first voltage signal line on the substrate is between The maximum distance in the second direction refers to any point on the edge line of the orthographic projection of the gate of the transistor coupled to the second plate of the first capacitor on the substrate, and the first voltage signal line on the substrate The maximum distance between the edge lines of the orthographic projection along the second direction.
  • the transistor coupled to the second plate C1b of the first capacitor C1 may include a first capacitor connection transistor T6 and a second capacitor connection transistor T5;
  • the gate G6 of the first capacitor connecting transistor T6 and the gate G5 of the second capacitor connecting transistor T5 are respectively coupled to the second plate C1b of the first capacitor C1 ;
  • the at least one shift register unit further includes a first conductive connection portion L1 coupled to the second electrode D6 of the first capacitor connection transistor T6, and the first There is a fifth overlap area between the orthographic projection of the conductive connecting portion L1 on the substrate and the orthographic projection of the first electrode plate C1a of the first capacitor C1 on the substrate, and the first conductive connecting portion L1 passes At least one fifth via hole H5 provided in the fifth overlapping area is coupled to the first electrode plate C1a of the first capacitor C1.
  • the second electrode S6 of the first capacitor connection transistor T6 is coupled to the first conductive connection portion L1 through a third connection via H83.
  • the first conductive connecting portion L1 may be L-shaped, but not limited to this.
  • FIG. 10C only the orthographic projection of the gate G5 of T5, the gate G6 of T6, the second plate C1b of C1, and the fifth conductive connection portion L5 on the substrate are shown, and the first voltage signal line VGH Orthographic projection on the substrate;
  • X2 is the edge line of the orthographic projection of the first voltage signal line VGH on the substrate
  • X5 is the edge line of the orthographic projection of G5 on the substrate
  • X6 is the edge line of the orthographic projection on the substrate. The edge line of the orthographic projection on the substrate;
  • d3 is the maximum distance in the second direction between the orthographic projection of the gate G5 of T5 on the substrate and the orthographic projection of the VGH on the substrate;
  • the label d4 is the maximum distance in the second direction between the orthographic projection of the grid G6 of T6 on the substrate and the orthographic projection of the VGH on the substrate.
  • the at least one shift register unit may further include a second transistor T7;
  • the at least one shift register unit further includes a gate connection conductive portion 51 coupled to the gate G7 of the second transistor T7, and, The first electrode connecting conductive portion 52 to which the first electrode S6 of the first capacitor connecting transistor T6 is coupled;
  • connection overlap area between the gate connecting conductive part and the first electrode connecting conductive part 52;
  • the gate connection conductive portion 51 is coupled to the first electrode connection conductive portion 52 through the electrode connection via H05 provided in the connection overlap area, so that the gate G7 of the second transistor T7 is connected to the
  • the first capacitor connection transistor T6 is coupled to the first electrode S6.
  • the first electrode S6 of the first capacitor connection transistor T6 is coupled to the first electrode connection conductive portion 52 through a fourth connection via H84;
  • the second electrode D7 of the second transistor T7 is coupled to the first conductive connection portion L1.
  • the first electrode S5 of the second capacitor connection transistor T5 may be coupled to the first voltage signal line VGH;
  • the maximum distance d32 is smaller than the maximum distance d31 in the second direction between the orthographic projection of the gate of the second capacitor connection transistor T5 on the substrate and the orthographic projection of the first voltage signal line VGH on the substrate. That is, T5 is arranged on the side of T6 away from the first voltage signal line VGH.
  • the first electrode S5 of the second capacitor connection transistor T5 is connected to the conductive connection portion of the signal line through the fifth connection via H85.
  • L40 is coupled, and the signal line conductive connection portion L40 is coupled to the first voltage signal line VGH, so that the first electrode S5 of the second capacitor connection transistor T5 is coupled to the first voltage signal line VGH .
  • the signal line conductive connection portion L40 may be L-shaped.
  • the orthographic projection of the signal line conductive connection portion L40 on the substrate partially overlaps the orthographic projection of the first electrode plate C1a of the first capacitor C1 on the substrate.
  • the longest distance in the second direction between the gate G6 of the first capacitor connecting transistor T6 and the gate G5 of the second capacitor connecting transistor T5 is less than the fourth Predetermined distance
  • the orthographic projection of the first electrode plate C1a of the first capacitor C1 on the substrate is within the orthographic projection of the second electrode plate C1b of the first capacitor C1 on the substrate;
  • the first electrode plate C1a of the first capacitor C1 is L-shaped.
  • T5 and T6 are set to be relatively close to each other to adjust the shape of the electrode plate of C1, and the first electrode plate C1a of C1 is set to an L shape, which makes full use of the gate and the gate of T5.
  • the wiring space between the second conductive connecting portions makes the layout more reasonable, effectively narrows the horizontal width of the shift register unit, and reduces the vertical height of the shift register unit.
  • the fourth predetermined distance may be selected according to actual conditions, for example, the fourth predetermined distance is greater than or equal to 20 um (micrometers) and less than or equal to 30 um.
  • the longest distance in the second direction between the gate G6 of the first capacitor connection transistor T6 and the gate G5 of the second capacitor connection transistor T5 refers to: G5 The maximum distance between any point on the edge line of G6 and the edge line of G6 in the second direction, as shown in FIG. The maximum distance.
  • the shift register unit may include a first transistor T8 and a second transistor T7;
  • the first electrode plate C1a of the first capacitor C1 includes a first horizontal electrode plate portion C1a1 and a first vertical electrode plate portion C1a2;
  • the orthographic projection of the gate G5 of the second capacitor connecting transistor T5 on the substrate and the orthographic projection of the first horizontal plate portion C1a1 on the substrate are along the first Direction arrangement
  • the orthographic projection of the gate G8 of the first transistor T8 on the substrate, the orthographic projection of the gate G7 of the second transistor T7 on the substrate, and the first vertical plate portion C1a2 on the substrate Orthographic projections are arranged along the first direction;
  • the first electrode S7 of the second transistor T7 is coupled to the second plate C3b of the output capacitor C3.
  • the space between T5 and T6 and the space between the gate of T5 and the second conductive connection part are used to set C1, and the pole plate of C1 is set to be L-shaped for reasonable layout .
  • the second electrode D7 of the second transistor T7 is coupled to the first conductive connection portion L1 through the sixth connection via H86, so that the second electrode D7 of the second transistor T7 The electrode D7 is coupled to the second electrode D6 of the first capacitor connection transistor T6.
  • the at least one shift register unit may further include a first node control transistor T2 and a second capacitor C2;
  • the first gate pattern G21 and the second gate pattern G22 included in the gate of the first node control transistor T2 are respectively coupled to the second plate C2b of the second capacitor C2;
  • the orthographic projection of the first plate C2a of the second capacitor C2 on the substrate is on the substrate.
  • the first plate C2a of the second capacitor C2 is L-shaped
  • the first electrode plate C2a of the second capacitor C2 includes a second horizontal electrode plate portion C2a1;
  • the first node controls the orthographic projection of the gate G2 of the transistor T2 on the substrate, and the orthographic projection of the second horizontal plate portion C2a1 on the substrate is arranged in a first direction.
  • the plate of C2 is set to be L-shaped, and the transistor is controlled between T2 in the n-th stage shift register unit and the second node in the n+1-th stage shift register unit.
  • the horizontal plate portion included in the plate of C2 is placed in the space to narrow the lateral width of the shift register unit.
  • the scan driving circuit further includes a third voltage signal line VGL2; the third voltage signal line VGL2 extends along the first direction;
  • the first node control transistor T2 is located on the side of the second capacitor connection transistor T5 away from the first voltage signal line VGH; the first node control transistor T2 is located on the third voltage signal line VGL2 and the Between the first voltage signal lines VGH;
  • the first plate C2a of the second capacitor C2 further includes a second vertical plate portion C2a2 coupled with the second horizontal plate portion C2a1; the second vertical plate portion C2a2
  • the orthographic projection of the portion C2a2 on the substrate partially overlaps the orthographic projection of the third voltage signal line VGL2 on the substrate.
  • the pole plate of C2 is arranged in an L shape, and the orthographic projection of the second vertical pole plate portion C2a2 of C2 on the substrate partially overlaps with the orthographic projection of the third voltage signal line VGL2 on the substrate. , In order to reduce the vertical height of the shift register unit.
  • the orthographic projection of the second active pattern A2 of T2 on the substrate and the orthographic projection of the second horizontal plate portion C2a1 on the substrate are arranged in sequence along the first direction , Using the space between A2 in the n-th stage shift register unit and the n+1-th stage shift register unit to set the horizontal plate portion of C2.
  • the first clock signal line CB is located on a side of the third voltage signal line VGL2 away from the first voltage signal line VGH;
  • the output circuit includes an output transistor T10; as shown in FIG. 5, the at least one shift register unit further includes one of the gate G10 of the output transistor T10 and the second plate C2b of the second capacitor C2.
  • the second conductive connection portion L2 between the two; the second conductive connection portion L2 is respectively coupled to the gate G10 of the output transistor T10 and the second plate C2b of the second capacitor C2;
  • the at least one shift register unit further includes a third conductive connection portion L3 coupled to the first plate C2a of the second capacitor C2;
  • FIGS. 3 and 7 there is a sixth overlap area between the orthographic projection of the third conductive connection portion L3 on the substrate and the orthographic projection of the first clock signal line CB on the substrate.
  • the clock signal line CB is coupled to the first plate C2a of the second capacitor C2 through at least one sixth via hole H6 provided in the sixth overlapping area.
  • the second conductive connection portion L2 may extend in a second direction for coupling the gate G10 of the output transistor T10 and the second plate C2b of the second capacitor C2;
  • the third conductive connection portion L3 may extend in the second direction, and the third conductive connection portion L3 is coupled to the first plate C2a of the second capacitor C2 through a sixth via H6.
  • the first capacitor connection transistor T6 includes a first active pattern A1; the first active pattern A1 extends along a first direction;
  • the first active pattern includes a first first capacitor connection conductive portion L111 and a second first capacitor connection conductive portion L112 arranged opposite to each other along the first direction A1, and a first capacitor connection conductive portion L112 located on the first first capacitor connection.
  • the first capacitor between the portion L111 and the second first capacitor connection conductive portion L112 is connected to the channel portion L12.
  • the first first capacitor connection conductive portion L111 is used as the first electrode S6 of the first capacitor connection transistor T6, and the second first capacitor connection conductive portion L112 is used for The first capacitor is connected to the second electrode D6 of the transistor T6.
  • the first active pattern A1 of T6 extends along the first direction, and T6 is disposed between T5 and VGH, so as to narrow the lateral width of the shift register unit.
  • the at least one shift register unit may include a second transistor T7;
  • the second electrode D7 of the second transistor T7 is coupled to the first conductive connection portion L1.
  • the second electrode D7 of the second transistor T7 is coupled to the first conductive connection portion L1 through a sixth connection via H86.
  • the first node control transistor T2 may include a second active pattern A2; the second active pattern A2 may be U-shaped;
  • the second active pattern A2 includes a first first node control channel portion A211, a second first node control channel portion A212, a first first node control conductive portion A221, and a second first node control channel portion A211.
  • One node controls the conductive part A222;
  • the gate of the first node control transistor T2 includes a first gate pattern G21 and a second gate pattern G22 that are coupled to each other;
  • the first gate pattern G21 corresponds to the first first node control channel portion A211, and the second gate pattern G22 corresponds to the second first node control channel portion A212;
  • the first first node control conductive portion A221 is used as the second electrode D2 of the first node control transistor T2, and the second first node control conductive portion A222 is used As the first node, the first electrode S2 of the transistor T2 is controlled.
  • the active pattern of the first node control transistor T2 is configured as a U-shaped structure, so that T2 is formed as a double gate structure.
  • the purpose of the double-gate structure design is: in the second stage P2, when the shift register unit included in the scan driving circuit outputs a high voltage signal Vgh, T10 should be completely closed, and the high level of the gate of T10 is connected by the source of T5. ⁇ input.
  • T2 is set to adopt a double-gate design, which makes it easier to turn off T2.
  • the active pattern of T2 In actual production exposure, if the active pattern of T2 is set to a U-shape without missing corners, metal will be deposited after exposure, which will make the U-shaped active pattern a V-shape. Therefore, in actual products, taking into account the actual production exposure process, a small part of the inner side of the U-shaped active pattern is dug at the two right-angle parts to compensate, and the actual pattern is made to be U-shaped as much as possible, without affecting the aspect ratio of T2. .
  • the at least one shift register unit may further include a second node control transistor T3; the at least one shift register unit includes a second capacitor connection transistor T5;
  • the second electrode D3 of the second node control transistor T3 and the second electrode D2 of the first node control transistor T2 are coupled through a fourth conductive connection portion L4;
  • the at least one shift register unit further includes a fifth conductive connection portion L5 coupled to the gate G5 of the second capacitor connection transistor T5; There is a seventh overlapping area between the orthographic projection of the fifth conductive connecting portion L5 on the substrate and the orthographic projection of the fourth conductive connecting portion L4 on the substrate;
  • the fifth conductive connecting portion L5 is coupled to the fourth conductive connecting portion L4 through a seventh via H7 provided in the seventh overlapping area.
  • the second electrode D3 of the second node control transistor T3 is coupled to the fourth conductive connection portion L4 through a seventh connection via H87. Then, the second electrode D2 of the first node control transistor T2 is coupled to the fourth conductive connection portion L4 through the eighth connection via H88, so that the second electrode D3 of the second node control transistor T3 is connected to the fourth conductive connection portion L4. The second electrode D2 of the first node control transistor T2 is coupled.
  • the fourth conductive connection portion L4 may extend along the first direction to reduce the lateral width of the shift register unit.
  • the display substrate may further include a third voltage signal line VGL2; the third voltage signal line VGL2 is disposed at the second node and the control transistor T3 is away from the first One side of the voltage signal line VGH;
  • the first electrode S2 of the first node control transistor T2 is coupled to the sixth conductive connection portion L6; the gate G3 of the second node control transistor T3 is coupled to the seventh The conductive connection portion L7 is coupled;
  • the first electrode S3 of the second node control transistor T3 is coupled to the third voltage signal line VGL2.
  • the first electrode S2 of the first node control transistor T2 is coupled to the sixth conductive connection portion L6 through a ninth connection via H89, and the sixth conductive connection portion L6 may It extends along the first direction to narrow the lateral width of the shift register unit.
  • the gate G3 of the second node control transistor T3 is coupled to the seventh conductive connection portion L7, and the sixth conductive connection portion L6 passes through the eighth via hole H8 and the seventh conductive connection portion L6 provided in the eighth overlap region.
  • the conductive connection portion L7 is coupled so that the first electrode S2 of the first node control transistor T2 is coupled to the gate G3 of the second node control transistor T3.
  • the second node control transistor T3 includes a third active pattern A3, and the third active pattern includes a first control conductive portion A311, a control channel portion A32, and a The second control conductive part A312;
  • the first control conductive portion A311 serves as the first electrode S3 of T3, and the second control conductive portion A312 serves as the second electrode D3 of T3.
  • the gate G3 of the second node control transistor T3 is also coupled to the eighth conductive connection portion L8; as shown in FIG. 3, the eighth conductive connection portion L8 is on the positive side of the substrate.
  • the nine via holes H9 are coupled to the second clock signal line CK.
  • the gate of T3 is coupled to the second clock signal line CK, the gate of T3 can be set close to the second clock signal line CK for a reasonable layout.
  • the scan driving circuit may include a first clock signal line CB and a third voltage signal line VGL2; the first clock signal line CB and the third voltage signal line VGL2 Extend along the first direction;
  • the second clock signal line CK is disposed between the first clock signal line CB and the third voltage signal line VGL2.
  • the first clock signal line may also be arranged between the second clock signal line and the third voltage signal line.
  • the at least one shift register unit may further include an input transistor T1;
  • the gate G1 of the input transistor T1 is coupled to the seventh conductive connection portion L7; as shown in FIG. 3, the first electrode S1 of the input transistor T1 is coupled to the input signal terminal E1 ;
  • the second electrode D1 of the input transistor T1 is coupled to a ninth conductive connection portion L9, and the orthographic projection of the ninth conductive connection portion L9 on the substrate is in contact with the second plate C2b of the second capacitor C2.
  • the first electrode S1 of the input transistor T1 is coupled to the input conductive connection portion L70 through the ninth connection via H89, and the input conductive connection portion L70 is coupled to the input signal terminal E1 through the tenth connection via H810, so that the first electrode S1 of the input transistor T1 is coupled to the input signal terminal E1;
  • the second electrode D1 of the input transistor T1 is coupled to the ninth conductive connection portion L9, and the ninth conductive connection portion L9 is disposed at the The tenth via hole H10 of the tenth overlapping area is coupled to the second plate C2b of the second capacitor C2, so that the second electrode D1 of the input transistor T1 and the second electrode of the second capacitor C2 Board C2b is coupled;
  • the ninth conductive connection portion L9 may extend along the first direction to narrow the lateral width of the shift register unit.
  • the at least one shift register unit may further include a third node control transistor T4;
  • the gate G4 of the third node control transistor T4 is coupled to the tenth conductive connection portion L10;
  • the tenth conductive connection portion L10 may be arranged along the second direction, but it is not limited to this.
  • the at least one shift register includes a second transistor T7;
  • the gate G4 of the third node control transistor T4 is coupled to the gate G7 of the second transistor T7.
  • T4 and T7 can be set close to each other.
  • the at least one shift register unit may include a second capacitor connection transistor T5;
  • the active layer of the input transistor T1, the active layer of the third node control transistor T4, and the active layer of the second capacitor connection transistor T5 may consist of a continuous third semiconductor layer. 30 formed;
  • the active layer of the input transistor T1 includes a first fifth conductive portion 311, a fifth channel portion 32, and a second fifth conductive portion 312 sequentially arranged along the first direction;
  • the second fifth conductive part 312 is multiplexed into the first sixth conductive part
  • the active layer of the third node control transistor T4 includes a first sixth conductive portion, a sixth channel portion 34, and a second sixth conductive portion 332 sequentially arranged along the first direction;
  • the second sixth conductive part 332 is multiplexed into the first seventh conductive part
  • the active layer of the second capacitor connection transistor T5 includes a first seventh conductive portion, a seventh channel portion 36 and a second seventh conductive portion 352 that are sequentially arranged along the first direction.
  • the first fifth conductive portion 311 is used as the first electrode S1 of the input transistor T1
  • the second fifth conductive portion 312 is used as the first electrode S1 of the input transistor T1.
  • the second electrode D1 of the input transistor T1 the second sixth conductive portion 332 serves as the first electrode S4 of the third node control transistor T4, and the second seventh conductive portion 352 serves as the The second capacitor is connected to the first electrode S5 of the transistor T5;
  • the second electrode D1 of the input transistor T1 is multiplexed as the second electrode D4 of the third node control transistor T4, and the first electrode S4 of the third node control transistor T4 is multiplexed as the second electrode S4 of the third node control transistor T4.
  • the second capacitor is connected to the second electrode D5 of the transistor T5. That is, in the display substrate according to at least one embodiment of the present disclosure, in the input transistor T1, the third node control transistor T4, and the second capacitor connection transistor T5, adjacent transistors can pass through The conductive parts included in the three semiconductor layers 30 are directly coupled, which reduces the area occupied by T1, T4, and T5 in the first direction.
  • the scan driving circuit may further include a third voltage signal line;
  • the third voltage signal line, the first clock signal line, and the second clock signal line all extend in a first direction
  • the orthographic projection of the third voltage signal line on the substrate, the orthographic projection of the first clock signal line on the substrate, and the orthographic projection of the second clock signal line on the substrate are all located
  • the orthographic projection of the shift register unit on the base is away from the side of the display area of the display substrate;
  • the signal output line extends along a second direction, and the first direction intersects the second direction.
  • the specific positions of the first clock signal line, the second clock signal line, and the third voltage signal line can be set according to actual needs.
  • the second clock signal line and the third voltage signal line are both arranged at the edge of the display substrate, that is, the orthographic projection of the third voltage signal line on the substrate, the first clock signal line
  • the orthographic projection on the substrate and the orthographic projection of the second clock signal line on the substrate are both located on the orthographic projection of the shift register unit on the substrate away from the display area of the display substrate
  • the shift register unit is laid out, it is possible to prevent the transistors in the shift register unit from interacting with the first clock signal line, the second clock signal line, and the third voltage signal line. Excessive overlap is generated, which is more conducive to improving the working performance of the shift register unit.
  • the display substrate by arranging the first clock signal line, the second clock signal line, and the third voltage signal line to extend along the first direction, it is more advantageous for the display substrate to realize a narrow frame.
  • the phases of the first clock signal output by the first clock signal line and the second clock signal output by the second clock signal line may be opposite, but not limited to this.
  • the scan driving circuit may include a first voltage signal line VGH, a second voltage signal line VGL1, a third voltage signal line VGL2, a first clock signal line CB, and The second clock signal line CK;
  • the at least one shift register unit may also include a signal output line EOUT, an output capacitor C3, a first capacitor C1, a second capacitor C2, an output reset transistor T9, an output transistor T10, and a first transistor T8 ,
  • the output reset transistor T9 and the output transistor T10 are arranged along a first direction;
  • the first electrode S9 of the output reset transistor T9 is coupled to the first voltage signal line VGH, and the first electrode S10 of the output transistor T10 is coupled to the second voltage signal line VGL1;
  • the output transistor T10 and the signal output line EOUT are arranged along a first direction, and the second electrode D9 of the output reset transistor T9 and the second electrode D10 of the output transistor T10 are both coupled to the signal output line EOUT catch;
  • the signal output line EOUT extends along a second direction, and the first direction intersects the second direction;
  • the second electrode D8 of the first transistor T8 is coupled to the second plate C3b of the output capacitor C3, and the first electrode S8 of the first transistor T8 is coupled to the first voltage signal line VGH, so The gate G8 of the first transistor T8 is coupled to the second electrode D4 of the third node control transistor T4;
  • the second electrode D7 of the second transistor T7 is coupled to the first plate C1a of the first capacitor C1, and the first electrode S7 of the second transistor T7 is coupled to the second plate C3b of the output capacitor C3 ,
  • the gate G7 of the second transistor T7 is coupled to the gate G4 of the third node control transistor T4;
  • the gate G6 of the first capacitor connecting transistor T6 and the gate G5 of the second capacitor connecting transistor T5 are respectively coupled to the second plate C1b of the first capacitor C1; the first capacitor is connected to the transistor T6
  • the second electrode D6 of the first capacitor is coupled to the first plate C1a of the first capacitor C1; the first electrode S6 of the first capacitor connecting transistor T6 is coupled to the gate G7 of the second transistor T7;
  • the first electrode S5 of the second capacitor connecting transistor T5 is coupled to the first voltage signal line VGH; the second capacitor connecting the gate G5 of the transistor T5 and the second electrode of the second node control transistor T3 D3 is coupled; the second electrode D5 of the second capacitor connection transistor T5 is coupled to the first electrode S4 of the third node control transistor T4;
  • the first electrode S2 of the first node control transistor T2 is coupled to the gate G3 of the second node control transistor T3; the gate G2 of the first node control transistor T2 and the second capacitor C2 are The diode C2b is coupled;
  • the second electrode D3 of the second node control transistor T3 is coupled to the second electrode D2 of the first node control transistor T2; the gate G3 of the second node control transistor T3 is connected to the second clock signal line CK is coupled; the first electrode S3 of the second node control transistor T3 is coupled to the third voltage signal line VGL2;
  • the gate G1 of the input transistor T1 is coupled to the gate G3 of the second node control transistor T3; the first electrode S1 of the input transistor T1 is coupled to the input signal terminal E1; the first electrode of the input transistor T1 is coupled to the input signal terminal E1.
  • the two electrodes D1 are coupled to the second plate C2b of the second capacitor C2;
  • the gate G4 of the third node control transistor T4 is coupled to the first clock signal line CB;
  • the first plate C3a of the output capacitor C3 is coupled to the first voltage signal line VGH, and the second plate C3b of the output capacitor C3 is coupled to the gate G9 of the output reset transistor T9;
  • the second plate C2b of the second capacitor C2 is coupled to the gate G10 of the output transistor T10, and the first plate C2a of the second capacitor C2 is coupled to the first clock signal line CB;
  • the second electrode D9 of the output reset transistor T9 and the second electrode D10 of the output transistor T10 are both coupled to the signal output line EOUT.
  • the first clock signal line, the second clock signal line, and the third voltage signal line are arranged in sequence; or, along the direction close to the In the direction of the display area, the second clock signal line, the first clock signal line, and the third voltage signal line are arranged in sequence.
  • the first electrode plate C1a of the first capacitor C1 may include a first horizontal electrode plate portion C1a1 and a first vertical electrode plate portion C1a2;
  • the output reset transistor T9 and the output transistor T10 are arranged between the first voltage signal line VGH and the second voltage signal line VGL1; along the first direction, the The output reset transistor T9, the output transistor T10, and the signal output line EOUT are arranged in sequence;
  • the third voltage signal line VGL2 is arranged on a side of the first voltage signal line VGH away from the second voltage signal line VGL1; the first capacitor C1, the first transistor T8, the second transistor T7, The first capacitor connection transistor T6, the second capacitor connection transistor T5, the first node control transistor T2, the second node control transistor T3, the input transistor T1 and the third node control transistor T4 are all arranged on the first voltage signal line VGH and Between the third voltage signal lines VGL2;
  • the first transistor T8, the second transistor T7, and the first vertical plate portion C1a2 are sequentially arranged along a first direction.
  • the input transistor T1, the third node control transistor T4, and the first The two capacitor connection transistors T5 and the first horizontal plate portion C1a1 are arranged in sequence along the first direction, and the second node control transistor T3 and the first node control transistor T2 are arranged in sequence along the first direction;
  • the orthographic projection of the gate G6 of the first capacitor connecting transistor T6 on the substrate is arranged on the orthographic projection of the second plate C1b of the first capacitor C1 on the substrate and the first voltage signal line Between the orthographic projections of VGH on the substrate;
  • the orthographic projection of the gate G7 of the second transistor T7 on the substrate is arranged at the third node.
  • the orthographic projection of the gate G4 of the third node control transistor T4 on the substrate is in the same position as the first voltage signal line VGH. Between the orthographic projections on the substrate;
  • the orthographic projection of the gate G2 of the first node control transistor T2 on the substrate is set on the orthographic projection of the third voltage signal line VGL2 on the substrate and the first plate of the first capacitor C1 C1a between the orthographic projections on the substrate;
  • the minimum distance between the orthographic projection of the gate G2 of the first node control transistor T2 on the substrate and the orthographic projection of the third voltage signal line VGL2 on the substrate in the second direction is greater than the first The minimum distance between the orthographic projection of the gate G5 of the two-capacitor connection transistor T5 on the substrate and the orthographic projection of the third voltage signal line VGL2 on the substrate in the second direction.
  • the output reset transistor T9 is coupled to the first voltage signal line VGH, and the output transistor T10 is coupled to the second voltage signal line VGL1, the output reset transistor T9 and the output transistor T10 are coupled to each other.
  • the transistor includes components, the second voltage signal line VGL1 is arranged on the side of the output circuit O1 close to the display area, no other signal lines are arranged between the second voltage signal line VGL1 and the output circuit O1, and other transistors include Narrow the distance from VGH to T9 and T10, and narrow the distance from VGL1 to T9 and T10, so that the lateral width of the shift register unit is reduced.
  • T8 is moved to the side of the first voltage signal line VGH far away from the second voltage signal line VGL1, and the orthographic projection of the plate of the output capacitor C3 on the substrate is set to and The orthographic projection of the first voltage signal line VGH on the substrate is partially overlapped to reduce the distance between the first electrode S8 of the first transistor T8 and the first voltage signal line VGH, and to reduce the distance between the second electrode D8 of the first transistor T8 and the first voltage signal line VGH.
  • the distance between the second plate C3b of the output capacitor C3 allows T8 to be easily coupled to the first voltage signal line VGH and the second plate C3b of the output capacitor C3, so that the space is compact and the layout is more reasonable.
  • T5 and T6 are set to be relatively close to the shape of the pole plate of C1, and the first pole plate C1a of C1 is set to an L shape, which makes full use of the T5
  • the wiring space between the gate and the second conductive connection part makes the layout more reasonable, effectively narrows the horizontal width of the shift register unit, and reduces the vertical height of the shift register unit.
  • the orthographic projection of the gate G2 of the first node control transistor T2 on the substrate and the orthographic projection of the third voltage signal line VGL2 on the substrate are in the second direction
  • the minimum distance above refers to the minimum distance in the second direction between any point on the edge line of the orthographic projection of G2 on the substrate and the edge line of the orthographic projection of VGL2 on the substrate;
  • the minimum distance between the orthographic projection of the gate G5 of the second capacitor connection transistor T5 on the substrate and the orthographic projection of the third voltage signal line VGL2 on the substrate in the second direction refers to: G5 The minimum distance between any point on the edge line of the orthographic projection on the substrate and the edge line of the orthographic projection of VGL2 on the substrate in the second direction.
  • the orthographic projection of the first plate C3a of the output capacitor C3 on the substrate has a signal line overlapping area with the orthographic projection of the first voltage signal line VGH on the substrate;
  • the orthographic projection of the second plate C3b of the output capacitor C3 and the substrate partially overlaps the orthographic projection of the first voltage signal line VGH on the substrate;
  • the orthographic projection of the first electrode plate C2a of the second capacitor C2 on the substrate is within the orthographic projection of the second electrode plate C2b of the second capacitor C2 on the substrate; the second capacitor C2
  • the first plate C2a is L-shaped;
  • the first plate C2a of the second capacitor C2 includes a second horizontal plate portion C2a1 and a second vertical plate portion C2a2;
  • the gate G2 of the first node control transistor T2 and the second horizontal plate portion C2a1 are arranged along a first direction;
  • the orthographic projection of the second vertical plate portion C2a2 on the substrate partially overlaps the orthographic projection of the third voltage signal line VGL2 on the substrate.
  • the plate of C2 is set to an L shape, and the space between T2 in the n-th stage shift register unit and the n+1-th stage shift register unit is used to place the C2
  • the electrode plate includes a horizontal electrode plate portion to narrow the lateral width of the shift register unit.
  • a first gate insulating layer may also be provided between the semiconductor layer shown in FIG. 4 and the first gate metal layer shown in FIG. 5;
  • a second gate insulating layer may also be provided between the first gate metal layer and the second gate metal layer shown in FIG. 6; between the second gate metal layer shown in FIG. 6 and the second gate metal layer shown in FIG.
  • An insulating layer may also be included between the source and drain metal layers.
  • a semiconductor material layer is first arranged on the base, and the semiconductor material layer is patterned to form the active layer of each transistor; as shown in FIG. 4, The first semiconductor layer 10, the second semiconductor layer 20, and the third semiconductor layer 30 are formed.
  • the first capacitor connection transistor T6 includes a first active pattern A1, a second active pattern A2 of the first node control transistor T2, and
  • the second node control transistor T3 includes a third active pattern A3;
  • a first gate metal layer is fabricated, and a patterning process is performed on the first gate metal layer. As shown in FIG. 5, each transistor included in the shift register unit is formed The gate of the output capacitor C3, the second plate of the first capacitor C1, and the second plate of the second capacitor C2;
  • each transistor doping the part of the active layer that is not covered by the gate, so that the part of the active layer that is not covered by the gate is formed as a conductive part,
  • the portion of the active layer covered by the gate is formed as a channel portion;
  • the conductive portion is used as a first electrode or a second electrode; or, the conductive portion is coupled to the first electrode or the second electrode ;
  • a second gate metal layer is provided on the side of the second gate insulating layer facing away from the first gate metal layer, and a patterning process is performed on the second gate metal layer, as shown in FIG. 6, to form signal output lines EOUT,
  • a plurality of via holes are provided on the substrate provided with the active layer, the first gate insulating layer, the first gate metal layer, the second gate insulating layer, the second gate metal layer and the insulating layer;
  • a source-drain metal layer is provided on the side of the insulating layer facing away from the second gate metal layer, and a patterning process is performed on the source-drain metal layer. As shown in FIG. 8, a first voltage signal line VGH and a second voltage are formed.
  • the method for fabricating a display substrate includes fabricating a scan driving circuit on a base, and fabricating at least one driving transistor in a display area included in the display substrate; the driving transistor is configured to drive a light-emitting element for display;
  • the scan driving circuit includes a plurality of shift register units, a first voltage signal line, a second voltage signal line, a first clock signal line, and a second clock signal line, and at least one of the plurality of shift register units shifts
  • the bit register unit includes an output circuit and a signal output line;
  • the manufacturing method of the display substrate further includes:
  • the first voltage signal line, the second voltage signal line, the first clock signal line, and the second clock signal line are arranged to extend along the first direction, and the signal output line is arranged to extend along the first direction. Extend in two directions;
  • the first direction and the second direction intersect.
  • the output circuit is arranged between the first voltage signal line and the second voltage signal line, so that in terms of the spatial structure, the first voltage signal line is arranged at the output The side of the circuit away from the display area, and no other signal lines and components included in other transistors are arranged between the first voltage signal line and the output circuit, and the second voltage signal line is arranged on the side of the output circuit close to the display area No other signal lines and components included in other transistors are arranged between the second voltage signal line and the output circuit, which can narrow the distance between the first voltage signal line and the output circuit, and narrow the distance between the second voltage signal line and the output circuit. The distance of the output circuit reduces the lateral width of the shift register unit.
  • the first voltage signal line may be located on a side of the second voltage signal line away from the display area.
  • the manufacturing method of the display substrate according to at least one embodiment of the present disclosure may further include: arranging the signal output line between output circuits in adjacent shift register units.
  • the output circuit if the output circuit is coupled to the signal output line, the output circuit should be closer to the signal output line. At least one embodiment of the present disclosure moves the signal output line down to the adjacent Between the output circuits in the shift register unit, the lateral width of the shift register unit is narrowed.
  • the output circuit may include an output transistor and an output reset transistor, and the step of manufacturing the transistor included in the output circuit specifically includes:
  • a first gate metal layer is fabricated, and a patterning process is performed on the first gate metal layer to form the gate of the output transistor and the output reset transistor ⁇ Grid;
  • the portion of the first semiconductor layer that is not covered by the gate is doped so that the first semiconductor layer is not covered by the gate.
  • the part covered by the gate is formed as a conductive part, and the part covered by the gate in the first semiconductor layer is formed as a channel part.
  • the active layer of the output transistor and the active layer of the output reset transistor may be formed by a continuous first semiconductor layer, but it is not limited to this.
  • the active layer of the output transistor and the active layer of the output reset transistor may be formed by a continuous first semiconductor layer, and the first semiconductor layer extends in a first direction;
  • the active layer of the output reset transistor includes at least one first conductive portion and at least one first channel portion arranged oppositely along the first direction; each of the first channel portions is arranged on two adjacent first Between conductive parts;
  • the active layer of the output transistor may include at least two second conductive parts arranged oppositely along the first direction, and at least one second channel part; each of the second channel parts is arranged at Between two adjacent second conductive parts; the first conductive part of the active layer of the output reset transistor that is closest to the active layer of the output transistor can be multiplexed as the first conductive part of the output transistor Two conductive parts, which can further reduce the layout space of the output transistor and the output reset transistor, which is beneficial to realize the narrow frame of the display substrate.
  • the manufacturing method of the display substrate may further include: disposing a second gate metal layer on the side of the first gate metal layer that faces away from the first semiconductor layer. Performing a patterning process to form a signal output line extending in the second direction;
  • the orthographic projection of the first semiconductor layer on the substrate and the orthographic projection of the signal output line on the substrate are arranged along a first direction, and the first direction intersects the second direction.
  • the orthographic projection of the first semiconductor layer on the substrate and the orthographic projection of the signal output line on the substrate are arranged along the first direction, which can narrow the shift register The horizontal width of the unit.
  • the steps of manufacturing the first voltage signal line, the second voltage signal line, the first clock signal line, and the second clock signal line may specifically include:
  • a source-drain metal layer is formed on the side of the second gate metal layer facing away from the first gate metal layer, and a patterning process is performed on the source-drain metal layer to form the first voltage signal line and the second voltage signal line.
  • the voltage signal line, the first clock signal line, and the second clock signal line are formed on the side of the second gate metal layer facing away from the first gate metal layer, and a patterning process is performed on the source-drain metal layer to form the first voltage signal line and the second voltage signal line.
  • the maximum distance in the second direction between the orthographic projection of the first electrode of the first transistor on the substrate and the orthographic projection of the first voltage signal line on the substrate is less than the first predetermined distance
  • the maximum distance in the second direction between the orthographic projection of the second electrode of the first transistor on the substrate and the orthographic projection of the plate of the output capacitor on the substrate is less than a second predetermined distance .
  • the first transistor is arranged on the side of the first voltage signal line away from the second voltage signal line to form the side of the first transistor, and the first electrode of the first transistor is on the substrate
  • the maximum distance in the second direction between the orthographic projection of the first voltage signal line and the orthographic projection of the first voltage signal line on the substrate is less than the first predetermined distance
  • the second electrode of the first transistor is on the substrate. The maximum distance in the second direction between the projection and the orthographic projection of the electrode plate of the output capacitor on the substrate is smaller than the second predetermined distance for reasonable layout.
  • the at least one shift register unit may further include a second transistor, and the step of manufacturing the first transistor and the second transistor specifically includes:
  • a first gate metal layer is fabricated, and a patterning process is performed on the first gate metal layer to form the gate of the first transistor and the second The gate of the transistor;
  • the portion of the second semiconductor layer that is not covered by the gate is doped so that the second semiconductor layer is not covered by the gate.
  • the part covered by the gate is formed as a conductive part, and the part covered by the gate in the second semiconductor layer is formed as a channel part;
  • the second semiconductor layer includes a third conductive portion, a third channel portion, a second third conductive portion, a fourth channel portion, and a second fourth conductive portion that are sequentially arranged along the first direction;
  • the second third conductive part is multiplexed into the first fourth conductive part
  • the first third conductive portion is used as the first electrode of the first transistor
  • the second third conductive portion is used as the second electrode of the first transistor
  • the second fourth conductive portion is used Used as the second electrode of the second transistor.
  • the plate of the output capacitor coupled to the second electrode of the first transistor may be the second plate of the output capacitor; the specific steps of making the output capacitor include:
  • a source-drain metal layer is formed on the side of the second gate metal layer facing away from the first gate metal layer, and a patterning process is performed on the source-drain metal layer to form a conductive connection portion of the electrode plate and the first voltage signal Line and the second voltage signal line;
  • the orthographic projection of the first electrode plate of the output capacitor on the substrate has a signal line overlap area with the orthographic projection of the first voltage signal line on the substrate, and the first electrode plate of the output capacitor passes At least one signal line via provided in the signal line overlapping area is coupled to the first voltage signal line;
  • the orthographic projection of the conductive connection part of the electrode plate on the substrate and the orthographic projection of the second electrode plate of the output capacitor on the substrate have an overlap area of the electrode plate, and the conductive connection part of the electrode plate is arranged at At least one plate via hole in the plate overlap area is coupled to the second plate of the output capacitor.
  • the active layer of the first transistor and the active layer of the second transistor may be formed by a continuous second semiconductor layer; the second semiconductor layer extends along the first direction
  • the active layer of the first transistor includes a first third conductive portion, a third channel portion, and a second third conductive portion that are sequentially arranged along the first direction; the second third conductive portion is complex Used as the first fourth conductive portion; the active layer of the second transistor includes the first fourth conductive portion, the fourth channel portion, and the second fourth conductive portion sequentially arranged along the first direction ;
  • the first third conductive portion is used as the first electrode of the first transistor, the second third conductive portion is used as the second electrode of the first transistor; the second fourth conductive portion Used as the second electrode of the second transistor.
  • the second transistor is disposed between the first transistor and the first capacitor, and the second electrode of the first transistor is multiplexed as the second electrode of the second transistor to narrow the shift register. While the horizontal width of the unit is reduced, the vertical height of the shift register unit is reduced.
  • the maximum distance in the second direction between the orthographic projection of the gates of the at least two transistors on the substrate and the orthographic projection of the first voltage signal line on the substrate is smaller than the third predetermined distance.
  • the position of the transistor coupled to the second plate of the first capacitor is It is better to be close to the first voltage signal line.
  • At least one embodiment of the present disclosure connects the orthographic projection of the gate of the transistor coupled to the second plate of the first capacitor on the substrate to the first voltage signal line The maximum distance in the second direction between the orthographic projections on the substrate is set to be smaller than the third predetermined distance to narrow the lateral width of the shift register unit.
  • the at least two transistors include a first capacitor-connected transistor and a second capacitor-connected transistor;
  • the specific steps of manufacturing the first capacitor connection transistor and the second capacitor connection transistor include:
  • a first gate metal layer is fabricated on the side of the active layer facing away from the substrate, and a patterning process is performed on the first gate metal layer to form the gate of the first capacitor connected to the transistor and the second capacitor Connect the gate of the transistor and the second plate of the first capacitor so that the gate of the first capacitor is connected to the gate of the transistor and the gate of the second capacitor is connected to the second capacitor of the transistor respectively.
  • the part of the active layer that is not covered by the gate is doped, so that the active
  • the part of the layer that is not covered by the gate is formed as a conductive part, and the part of the active layer that is covered by the gate is formed as a channel part;
  • the first first capacitor connection conductive portion, the first capacitor connection channel portion, and the second first capacitor connection conductive portion are arranged in one direction;
  • the active layer of the second capacitor connection transistor includes sequentially along the first direction
  • the first seventh conductive portion, the seventh channel portion and the second seventh conductive portion are provided; the first first capacitor connection conductive portion is used as the first electrode of the first capacitor connection transistor, so The second first capacitor connecting conductive part is used as the second electrode of the first capacitor connecting transistor;
  • a source-drain metal layer is formed on the side of the second gate metal layer facing away from the first gate metal layer, and a patterning process is performed on the source-drain metal layer to form the first voltage signal line and the second voltage signal line.
  • the first seventh conductive portion may be used as the second electrode of the second capacitor connecting transistor, and the second seventh conductive portion may be used as the second capacitor Connected to the first electrode of the transistor, and the second capacitor is connected to the first electrode of the transistor to be coupled to the first voltage signal line;
  • the distance in the second direction between the orthographic projection of the gate of the first capacitor-connected transistor on the substrate and the orthographic projection of the first voltage signal line on the substrate is smaller than that of the gate of the second capacitor-connected transistor.
  • the distance in the second direction between the orthographic projection of the gate of the first capacitor-connected transistor on the substrate and the orthographic projection of the first voltage signal line on the substrate is smaller than that of the second
  • the distance in the second direction between the orthographic projection of the gate of the capacitor connecting transistor on the substrate and the orthographic projection of the first voltage signal line on the substrate, that is, the second capacitor connecting transistor is arranged on the first capacitor connecting transistor A side away from the first voltage signal line.
  • the longest distance in the second direction between the gate of the first capacitor connection transistor and the gate of the second capacitor connection transistor is less than the fourth predetermined distance
  • the orthographic projection of the first electrode plate of the first capacitor on the substrate is within the orthographic projection of the second electrode plate of the first capacitor on the substrate;
  • the first electrode plate of the first capacitor is L-shaped.
  • the first capacitor connection transistor and the second capacitor connection transistor are set to be relatively close to each other so as to be able to adjust the shape of the plate of the first capacitor, and the first plate of the first capacitor is set to The L shape makes full use of the wiring space between the gate of the second capacitor connecting transistor and the second conductive connection part, so that the layout is more reasonable, the lateral width of the shift register unit is effectively narrowed, and the shift register is reduced The vertical height of the unit.
  • the at least one shift register unit may further include a first node control transistor and a second capacitor;
  • the step of fabricating the first node control transistor and the second capacitor may include:
  • a patterning process is performed on the first gate metal layer to form the gate of the first node control transistor and the second plate of the second capacitor, and make the gate of the first node control transistor and the second electrode plate of the second capacitor The second plate of the second capacitor is coupled;
  • a patterning process is performed on the second gate metal layer to form the first plate of the second capacitor, and the orthographic projection of the first plate of the second capacitor on the substrate is on the second The second plate of the capacitor is within the orthographic projection on the substrate; the first plate of the second capacitor is L-shaped;
  • the first plate of the second capacitor includes a second horizontal plate portion; the orthographic projection of the gate of the first node control transistor on the substrate and the second horizontal plate portion on the substrate The orthographic projections are arranged along the first direction.
  • the first plate of the second capacitor is arranged in an L shape, and the space between the first node control transistor and the adjacent next-stage shift register unit is used to place the first plate of the second capacitor.
  • the electrode plate includes a horizontal electrode plate portion to narrow the lateral width of the shift register unit.
  • the manufacturing method of the display substrate described in at least one embodiment of the present disclosure may further include:
  • the first node control transistor is located on a side of the second capacitor connection transistor away from the first voltage signal line; the first node control transistor is located on the third voltage signal line and the first voltage signal line between;
  • the first electrode plate of the second capacitor further includes a second vertical electrode plate portion coupled with the second horizontal electrode plate portion; the orthographic projection of the second vertical electrode plate portion on the substrate and The orthographic projection of the third voltage signal line on the substrate partially overlaps.
  • the first electrode plate of the second capacitor is arranged in an L shape, and the orthographic projection of the second vertical electrode plate portion of the second capacitor on the substrate and the third voltage signal line on the substrate The orthographic projections overlap to reduce the vertical height of the shift register unit.
  • the number of the first voltage signal line is one;
  • the output circuit includes an output reset transistor;
  • the at least one shift register unit further includes an output capacitor, a first plate, and a second capacitor connecting transistor;
  • the manufacturing method of the display substrate further includes:
  • the first electrode of the output reset transistor, the first plate of the output capacitor, the first electrode of the first transistor, and the first electrode of the second capacitor connecting transistor are set to be all connected to the first electrode.
  • the voltage signal lines are coupled to reduce the number of voltage signal lines used and facilitate layout.
  • the display device includes the above-mentioned display substrate.
  • the display device provided by the foregoing embodiment can achieve a narrow frame
  • the display device provided by at least one embodiment of the present disclosure can also achieve the beneficial effect of having a narrower frame when the display device provided by at least one embodiment of the present disclosure includes the foregoing display substrate, which will not be repeated here.
  • the display device provided by at least one embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

Abstract

一种显示基板、制作方法和显示装置，该显示基板包括扫描驱动电路和显示区域，扫描驱动电路包括多个移位寄存器单元、第一电压信号线（VGH）、第二电压信号线（VGL1）、第一时钟信号线（CB）和第二时钟信号线（CK），第一电压信号线（VGH）、第二电压信号线（VGL1）、第一时钟信号线（CB）和第二时钟信号线（CK）沿着第一方向延伸；显示区域包括至少一个驱动晶体管，驱动晶体管被配置为驱动发光元件进行显示；多个移位寄存器单元中的至少一个移位寄存器单元包括输出电路和信号输出线（EOUT）；输出电路分别与第一电压信号线（VGH）、第二电压信号线（VGL1）和信号输出线（EOUT）耦接；信号输出线（EOUT）沿着第二方向延伸，第一方向与第二方向相交；输出电路包括的晶体管设置于第一电压信号线（VGH）和第二电压信号线（VGL1）之间。

Description

显示基板、制作方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、制作方法和显示装置。
背景技术
有源矩阵有机发光二极管(英文：Active-Matrix Organic Light-Emitting Diode，以下简称：AMOLED)显示面板以其低功耗、低制作成本、广色域等优点被广泛的应用在各个领域。
AMOLED显示面板包括位于显示区域的像素电路和位于边缘区域的扫描驱动电路，所述像素电路包括阵列分布的多个子像素电路，所述扫描驱动电路包括多个移位寄存器单元，每个移位寄存器单元用于为对应的子像素电路提供发光控制信号。由于所述扫描驱动电路设置在AMOLED显示面板的边缘区域，因此，扫描驱动电路的排布方式决定了AMOLED显示面板的边框宽度。
发明内容
在一个方面中，本公开实施例提供了一种显示基板，包括设置于基底上的扫描驱动电路和显示区域，所述扫描驱动电路包括多个移位寄存器单元，所述扫描驱动电路还包括第一电压信号线、第二电压信号线、第一时钟信号线和第二时钟信号线；所述第一电压信号线、所述第二电压信号线、所述第一时钟信号线和所述第二时钟信号线沿着第一方向延伸；所述显示区域包括至少一个驱动晶体管，所述驱动晶体管被配置为驱动发光元件进行显示；
所述多个移位寄存器单元中的至少一个移位寄存器单元包括输出电路和信号输出线；所述输出电路分别与所述第一电压信号线、所述第二电压信号线和所述信号输出线耦接；所述信号输出线沿着第二方向延伸，所述第一方向与所述第二方向相交；
所述输出电路包括的晶体管设置于所述第一电压信号线和所述第二电压 信号线之间。
可选的，所述第一电压信号线提供第一电压给所述输出电路，所述第二电压信号线提供第二电压给所述输出电路，所述第一电压高于所述第二电压。
可选的，所述信号输出线位于相邻的移位寄存器单元中的输出电路之间。
可选的，所述第一电压信号线位于所述第二电压信号线远离所述显示区域的一侧。
可选的，所述输出电路包括输出晶体管和输出复位晶体管；
所述输出复位晶体管和所述输出晶体管沿着第一方向排列；
所述输出复位晶体管的第一电极与所述第一电压信号线耦接，所述输出晶体管的第一电极与所述第二电压信号线耦接；
所述输出晶体管的第二电极和所述输出复位晶体管的第二电极都与所述信号输出线耦接。
可选的，所述输出晶体管的有源层和所述输出复位晶体管的有源层由一个连续的第一半导体层形成；
所述第一半导体层与所述信号输出线沿第一方向排列。
可选的，所述输出复位晶体管的栅极包括至少一个输出复位栅极图形，所述输出复位晶体管的第一电极包括至少一个第一电极图形，所述输出复位晶体管的第二电极包括至少一个第二电极图形；
所述输出复位栅极图形位于相邻的所述第一电极图形和所述第二电极图形之间；
所述第二电极图形、所述输出复位栅极图形和所述第一电极图形都沿着第二方向延伸；
所述第一方向与所述第二方向相交。
可选的，所述输出晶体管的栅极包括至少一个输出栅极图形，所述输出晶体管的第一电极包括至少一个第三电极图形，所述输出晶体管的第二电极包括至少一个第四电极图形；
所述输出栅极图形位于相邻的所述第三电极图形和所述第四电极图形之间；
所述第四电极图形、所述输出栅极图形和所述第三电极图形都沿着第二 方向延伸；
所述第一方向与所述第二方向相交；
所述输出复位晶体管中最靠近所述输出晶体管的栅极的所述第二电极图形复用为所述输出晶体管的第四电极图形。
可选的，所述输出复位晶体管的有源层包括沿第一方向相对设置的至少两个第一导电部分，以及至少一个第一沟道部分；每一所述第一沟道部分设置于两相邻的所述第一导电部分之间；
所述第一沟道部分与所述输出复位栅极图形一一对应，每个所述第一沟道部分在所述基底上的正投影，均位于对应的所述输出复位栅极图形在所述基底上的正投影的内部；
所述输出复位晶体管中的一部分所述第一导电部分与所述第一电极图形一一对应，所述第一电极图形在所述基底上的正投影，与对应的所述第一导电部分在所述基底上的正投影存在第一重叠区域，所述第一电极图形通过设置在所述第一重叠区域的至少一个第一过孔与对应的所述第一导电部分耦接；
所述输出复位晶体管中的另一部分所述第一导电部分与所述第二电极图形一一对应，所述第二电极图形在所述基底上的正投影，与对应的所述第一导电部分在所述基底上的正投影存在第二重叠区域，所述第二电极图形通过设置在所述第二重叠区域的至少一个第二过孔与对应的所述第一导电部分耦接。
可选的，所述输出晶体管的有源层包括沿第一方向相对设置的至少两个第二导电部分，以及至少一个第二沟道部分；每一所述第二沟道部分设置于两相邻的所述第二导电部分之间；
所述第二沟道部分与所述输出栅极图形一一对应，每个所述第二沟道部分在所述基底上的正投影，均位于对应的所述输出栅极图形在所述基底上的正投影的内部；
所述输出晶体管中的一部分所述第二导电部分与所述第三电极图形一一对应，所述第三电极图形在所述基底上的正投影，与对应的所述第二导电部分在所述基底上的正投影存在第三重叠区域，所述第三电极图形通过设置在所述第三重叠区域的至少一个第三过孔与对应的所述第二导电部分耦接；
所述输出晶体管中的另一部分所述第二导电部分与所述第四电极图形一一对应，所述第四电极图形在所述基底上的正投影，与对应的所述第二导电部分在所述基底上的正投影存在第四重叠区域，所述第四电极图形通过设置在所述第四重叠区域的至少一个第四过孔与对应的所述第二导电部分耦接。
可选的，所述第一电压信号线的个数为一个；
所述输出电路包括输出复位晶体管；所述至少一个移位寄存器单元还包括输出电容、第一晶体管和第二电容连接晶体管；
所述输出复位晶体管的第一电极、所述输出电容的第一极板、所述第一晶体管的第一电极和所述第二电容连接晶体管的第一电极都与所述第一电压信号线耦接。
可选的，所述显示基板还包括第三电压信号线，所述第一电压信号线位于所述第二电压信号线与所述第三电压信号线之间。
可选的，所述第二电容连接晶体管的第一电极通过第五连接过孔与信号线导电连接部耦接，所述信号线导电连接部与所述第一电压信号线耦接，以使得所述第二电容连接晶体管的第一电极与所述第一电压信号线耦接；
所述信号线导电连接部与所述第一电压信号线包含于源漏金属层，所述第二电容连接晶体管的第一电极包含于有源层。
可选的，所述至少一个移位寄存器单元还包括第一电容；
所述信号线导电连接部在基底上的正投影与第一电容的第一极板在基底上的正投影部分重叠。
可选的，所述输出电容的第一极板在所述基底上的正投影，与所述第一电压信号线在所述基底上的正投影存在信号线重叠区域，所述输出电容的第一极板通过设置在所述信号线重叠区域的至少一个信号线过孔与所述第一电压信号线耦接。
可选的，所述至少一个移位寄存器单元还包括第一节点控制晶体管和第二电容；
所述第一节点控制晶体管的栅极与所述第二电容的第二极板耦接；
所述第二电容的第一极板在所述基底上的正投影在所述第二电容的第二极板在所述基底上的正投影之内；
所述第二电容的第一极板为L形；
所述第二电容的第一极板包括第二水平极板部；
所述第一节点控制晶体管的栅极在所述基底上的正投影与所述第二水平极板部在所述基底上的正投影沿第一方向排列。
可选的，所述扫描驱动电路还包括第三电压信号线；所述第三电压信号线沿第一方向延伸；所述第三电压信号线位于所述第一电压信号线远离所述第二电压信号线的一侧；所述第一节点控制晶体管位于所述第三电压信号线与所述第一电压信号线之间；
所述第二电容的第一极板还包括与所述第二水平极板部耦接的第二竖直极板部；所述第二竖直极板部在所述基底上的正投影与所述第三电压信号线在所述基底上的正投影部分重叠。
可选的，所述第一时钟信号线位于所述第三电压信号线远离所述第一电压信号线的一侧；
所述输出电路包括输出晶体管；所述至少一个移位寄存器单元还包括设置于所述输出晶体管的栅极与所述第二电容的第二极板之间的第二导电连接部；所述第二导电连接部分别与所述输出晶体管的栅极和所述第二电容的第二极板耦接；
所述至少一个移位寄存器单元还包括与所述第二电容的第二极板耦接的第三导电连接部；
所述第三导电连接部在所述基底上的正投影与第一时钟信号线在所述基底上的正投影存在第六重叠区域，所述第一时钟信号线通过设置于所述第六重叠区域的至少一第六过孔与所述第二电容的第一极板耦接。
可选的，所述第一节点控制晶体管包括第二有源图形；所述第二有源图形为U形；
所述第二有源图形包括第一个第一节点控制沟道部分、第二个第一节点控制沟道部分、与所述第一个第一节点控制沟道部分耦接的第一个第一节点控制导电部分，以及，与所述第二个第一节点控制沟道部分耦接的第二个第一节点控制导电部分；
所述第一节点控制晶体管的栅极包括相互耦接的第一栅极图形和第二栅 极图形；
所述第一栅极图形与所述第一个第一节点控制沟道部分对应，所述第二栅极图形与所述第二个第一节点控制沟道部分对应；
所述第一个第一节点控制导电部分与所述第一节点控制晶体管的第二电极对应，所述第二个第一节点控制导电部分与所述第一节点控制晶体管的第一电极对应。
可选的，所述至少一个移位寄存器单元还包括第二节点控制晶体管；所述至少一个移位寄存器单元包括第二电容连接晶体管；
所述第二节点控制晶体管的第二电极与所述第一节点控制晶体管的第二电极之间通过第四导电连接部耦接；
所述至少一个移位寄存器单元还包括与所述第二电容连接晶体管的栅极耦接的第五导电连接部；所述第五导电连接部在所述基底上的正投影与所述第四导电连接部在所述基底上的正投影之间存在第七重叠区域；
所述第五导电连接部通过设置于所述第七重叠区域的第七过孔与所述第四导电连接部耦接。
可选的，所述扫描驱动电路还包括第三电压信号线；所述第三电压信号线位于所述第一电压信号线远离所述第二电压信号线的一侧；
所述第一节点控制晶体管的第一电极与第六导电连接部耦接；所述第二节点控制晶体管的栅极与第七导电连接部耦接；
所述第六导电连接部在所述基底上的正投影与所述第七导电连接部在所述基底上的正投影之间存在第八重叠区域，所述第六导电连接部通过设置于所述第八重叠区域之内的第八过孔与所述第七导电连接部耦接；
所述第二节点控制晶体管的第一电极与所述第三电压信号线耦接。
可选的，所述第二节点控制晶体管的栅极还与第八导电连接部耦接；所述第八导电连接部在所述基底上的正投影与所述第二时钟信号线在所述基底上的正投影之前存在第九重叠区域，所述第八导电连接部通过设置于所述第九重叠区域的第九过孔与所述第二时钟信号线耦接。
可选的，所述扫描驱动电路还包括第三电压信号线；所述第三电压信号线沿第一方向延伸；
所述第二时钟信号线设置于所述第一时钟信号线与所述第三电压信号线之间；或者，第一时钟信号线设置于所述第二时钟信号线与所述第三电压信号线之间。
可选的，所述至少一个移位寄存器单元还包括输入晶体管；
所述输入晶体管的第一电极与输入信号端耦接；
所述输入晶体管的第二电极与第九导电连接部耦接，所述第九导电连接部在所述基底上的正投影与所述第二电容的第二极板在所述基底上的正投影之间存在第十重叠区域，所述第九导电连接部通过设置于所述第十重叠区域的第十过孔与所述第二电容的第二极板耦接。
可选的，所述至少一个移位寄存器单元还包括第三节点控制晶体管、第二电容连接晶体管和输入晶体管；
所述第三节点控制晶体管的栅极与第一时钟信号线耦接；
所述输入晶体管的有源层、所述第三节点控制晶体管的有源层和所述第二电容连接晶体管的有源层由一个连续的第三半导体层形成；
所述输入晶体管的有源层包括沿第一方向依次设置的第一个第五导电部分、第五沟道部分和第二个第五导电部分；
所述第二个第五导电部分复用为第一个第六导电部分；
所述第三节点控制晶体管的有源层包括沿第一方向依次设置的第一个第六导电部分、第六沟道部分和第二个第六导电部分；
所述第二个第六导电部分复用为第一个第七导电部分；
所述第二电容连接晶体管的有源层包括沿第一方向依次设置的第一个第七导电部分、第七沟道部分和第二个第七导电部分。
可选的，所述扫描驱动电路还包括第三电压信号线；
所述第三电压信号线沿第一方向延伸；
所述第三电压信号线在所述基底上的正投影、所述第一时钟信号线在所述基底上的正投影和所述第二时钟信号线在所述基底上的正投影，都位于所述移位寄存器单元在所述基底上的正投影远离所述显示基板的显示区域的一侧。
可选的，所述扫描驱动电路还包括第三电压信号线；所述至少一个移位 寄存器单元还包括输出电容、第一电容、第二电容、第一晶体管、第二晶体管、第一电容连接晶体管、第二电容连接晶体管、第一节点控制晶体管、第二节点控制晶体管、输入晶体管、第三节点控制晶体管；
所述第一晶体管的第二电极与所述输出电容的第二极板耦接，所述第一晶体管的第一电极与所述第一电压信号线耦接，所述第一晶体管的栅极与所述第三节点控制晶体管的第二电极耦接；
所述第二晶体管的第一电极与所述第一电容的第一极板耦接，所述第二晶体管的第二电极与第一电容连接晶体管的第二电极耦接，所述第二晶体管的栅极与所述第三节点控制晶体管的栅极耦接；
所述第一电容连接晶体管的栅极和所述第二电容连接晶体管的栅极分别与所述第一电容的第二极板耦接；所述第一电容连接晶体管的第二电极与所述第一电容的第一极板耦接；所述第一电容连接晶体管的第一电极与第二晶体管的栅极耦接；
所述第二电容连接晶体管的第一电极与所述第一电压信号线耦接；所述第二电容连接晶体管的栅极与所述第二节点控制晶体管的第二电极耦接；所述第二电容连接晶体管的第二电极与所述第三节点控制晶体管的第一电极耦接；
所述第一节点控制晶体管的第一电极与所述第二节点控制晶体管的栅极耦接；所述第一节点控制晶体管的栅极与所述第二电容的第二极板耦接；
所述第二节点控制晶体管的第二电极与所述第一节点控制晶体管的第二电极耦接；所述第二节点控制晶体管的栅极与所述第二时钟信号线耦接；所述第二节点控制晶体管的第一电极与所述第三电压信号线耦接；
所述输入晶体管的栅极与所述第二节点控制晶体管的栅极耦接；所述输入晶体管的第一电极与输入信号端耦接；所述输入晶体管的第二电极与所述第二电容的第二极板耦接；
所述第三节点控制晶体管的栅极与所述第一时钟信号线耦接；
所述输出电容的第一极板与所述第一电压信号线耦接，所述输出电容的第二极板与所述输出复位晶体管的栅极耦接；
所述第二电容的第二极板与所述输出晶体管的栅极耦接，所述第二电容 的第一极板与所述第一时钟信号线耦接；
所述输出晶体管的第二电极和所述输出复位晶体管的第二电极都与所述信号输出线耦接。
可选的，沿靠近所述显示区域的方向，所述第一时钟信号线、所述第二时钟信号线和所述第三电压信号线依次排列；或者，沿靠近所述显示区域的方向，所述第二时钟信号线、所述第一时钟信号线和所述第三电压信号线依次排列。
可选的，所述第一电容的第一极板包括第一水平极板部和第一竖直极板部；
所述输出晶体管和所述输出复位晶体管设置于所述第一电压信号线和所述第二电压信号线之间；沿着所述第一方向，所述输出复位晶体管、所述输出晶体管和所述信号输出线依次排列；
所述第三电压信号线设置于所述第一电压信号线远离所述第二电压信号线的一侧；所述第一电容、所述第一晶体管、第二晶体管、第一电容连接晶体管、第二电容连接晶体管、第一节点控制晶体管、第二节点控制晶体管、输入晶体管和第三节点控制晶体管都设置于所述第一电压信号线和所述第三电压信号线之间；
所述第一晶体管、所述第二晶体管和所述第一竖直极板部沿着第一方向依次排列，所述输入晶体管、所述第三节点控制晶体管、所述第二电容连接晶体管和所述第一水平极板部沿着第一方向依次排列，所述第二节点控制晶体管和所述第一节点控制晶体管沿着第一方向依次排列；
所述第一电容连接晶体管的栅极在所述基底上的正投影设置于所述第一电容的第二极板在所述基底上的正投影与所述第一电压信号线在所述基底上的正投影之间；
所述第二晶体管的栅极在所述基底上的正投影设置于所述第三节点控制晶体管的栅极在所述基底上的正投影与所述第一电压信号线在所述基底上的正投影之间；
所述第一节点控制晶体管的栅极在所述基底上的正投影设置于所述第三电压信号线在所述基底上的正投影与所述第一电容的第一极板在所述基底上 的正投影之间；
所述第一节点控制晶体管的栅极在所述基底上的正投影与所述第三电压信号线在所述基底上的正投影在第二方向上的最小距离，大于所述第二电容连接晶体管的栅极在所述基底上的正投影与所述第三电压信号线在所述基底上的正投影在第二方向上的最小距离。
可选的，所述输出电容的第一极板在所述基底上的正投影，与所述第一电压信号线在所述基底上的正投影存在信号线重叠区域；所述输出电容的第二极板与所述基底上的正投影与所述第一电压信号线在所述基底上的正投影部分重叠；
所述第二电容的第一极板在所述基底上的正投影在所述第二电容的第二极板在所述基底上的正投影之内；所述第二电容的第一极板为L形；
所述第二电容的第一极板包括第二水平极板部和第二竖直极板部；
所述第一节点控制晶体管的栅极与所述第二水平极板部沿第一方向排列；
所述第二竖直极板部在所述基底上的正投影与所述第三电压信号线在所述基底上的正投影部分重叠。
可选的，所述显示基板还包括设置于所述基底上的多行像素电路；所述像素电路包括发光控制端；
所述扫描驱动电路包括的所述移位寄存器单元与所述行像素电路一一对应
所述移位寄存器单元的信号输出线与相应行像素电路的发光控制端耦接，用于为所述相应行像素电路的发光控制端提供发光控制信号。
在第二个方面中，本公开实施例还提供了一种显示基板的制作方法，所述显示基板的制作方法包括在基底上制作扫描驱动电路，并在显示基板包括的显示区域制作至少一个驱动晶体管；所述驱动晶体管被配置为驱动发光元件进行显示；
所述扫描驱动电路包括多个移位寄存器单元、第一电压信号线、第二电压信号线、第一时钟信号线和第二时钟信号线，所述多个移位寄存器单元中的至少一个移位寄存器单元包括输出电路和信号输出线；
所述显示基板的制作方法还包括：
在所述第一电压信号线和所述第二电压信号线之间制作所述输出电路包括的晶体管；
将所述第一电压信号线、所述第二电压信号线、所述第一时钟信号线和所述第二时钟信号线设置为沿着第一方向延伸，将信号输出线设置为沿着第二方向延伸；
所述第一方向和所述第二方向相交。
可选的，本公开至少一实施例所述的显示基板的制作方法还包括：
将所述信号输出线设置于相邻的移位寄存器单元中的输出电路之间。
可选的，所述第一电压信号线位于所述第二电压信号线远离显示区域的一侧。
可选的，所述输出电路包括输出晶体管和输出复位晶体管，制作所述输出电路包括的晶体管的步骤具体包括：
在所述第一电压信号线和所述第二电压信号线之间形成第一半导体层；
在所述第一半导体层背向所述基底上的一面，制作第一栅金属层，对所述第一栅金属层进行构图工艺，以形成所述输出晶体管的栅极和所述输出复位晶体管的栅极；
以所述输出晶体管的栅极和所述输出复位晶体管的栅极为掩膜，对第一半导体层中未被所述栅极覆盖的部分进行掺杂，使得所述第一半导体层中未被所述栅极覆盖的部分形成为导电部分，所述第一半导体层中被所述栅极覆盖的部分形成为沟道部分。
可选的，所述显示基板的制作方法还包括：在所述第一栅极金属层背向所述第一半导体层的一面设置第二栅金属层，对所述第二栅金属层进行构图工艺，以形成沿第二方向延伸的信号输出线；
所述第一半导体层在所述基底上的正投影和所述信号输出线在所述基底上的正投影沿着第一方向排列，所述第一方向与所述第二方向相交。
可选的，制作第一电压信号线、第二电压信号线、第一时钟信号线和第二时钟信号线的步骤具体包括：
在所述第二栅金属层背向所述第一栅金属层的一面制作源漏金属层，对所述源漏金属层进行构图工艺，以形成所述第一电压信号线、所述第二电压 信号线、第一时钟信号线和第二时钟信号线。
可选的，所述第一电压信号线的个数为一个；所述输出电路包括输出复位晶体管；所述至少一个移位寄存器单元还包括输出电容、第一极板和第二电容连接晶体管；所述显示基板的制作方法还包括：
将所述输出复位晶体管的第一电极、所述输出电容的第一极板、所述第一晶体管的第一电极和所述第二电容连接晶体管的第一电极设置为都与所述第一电压信号线耦接。
在第三个方面中，本公开实施例还提供了一种显示装置，包括上述的显示基板。
附图说明
图1是本公开实施例所述的显示基板包括的至少一移位寄存器单元的至少一实施例的电路图；
图2A是图1所示的移位寄存器单元的至少一实施例的工作时序图
图2B是本公开至少一实施例所述的显示基板的区域划分示意图；
图2C是本公开至少一实施例所述的显示基板包括的扫描驱动电路与像素电路之间的连接关系示意图；
图2D是本公开至少一实施例提供的移位寄存器单元的一种布局示意图；
图3为本公开至少一实施例提供的移位寄存器单元的另一种布局示意图；
图4是本公开至少一实施例提供的移位寄存器单元中的有源层的示意图；
图5是本公开至少一实施例提供的移位寄存器单元中的第一栅金属层的示意图；
图6是本公开至少一实施例提供的移位寄存器单元中的第二栅金属层的示意图；
图7是本公开至少一实施例提供的移位寄存器单元中采用的过孔的示意图；
图8本公开至少一实施例提供的移位寄存器单元中的源漏金属层的示意图；
图9是在图6的基础上的电容的极板的划分示意图；
图10A是第一电压信号线VGH在基底上的正投影与第二半导体层包括的用作所述第一晶体管T8的第一电极S8的第一个第三导电部分211在基底上的正投影之间的距离示意图；
图10B是第一电压信号线VGH在基底上的正投影与第二半导体层包括的用作所述第一晶体管T8的第二电极D8的第二个第三导电部分212在基底上的正投影之间的距离示意图；
图10C是T5的栅极G5在基底上的正投影、T6的栅极G6在基底上的正投影与第一电压信号线VGH在基底上的正投影之间的距离示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
如图1所示，本公开提供一种显示基板，所述显示基板包括位于显示基板的边缘区域的扫描驱动电路，所述扫描驱动电路包括第一电压信号线VGH、第二电压信号线VGL1、第三电压信号线VGL2、第一时钟信号线CB、第二时钟信号线CK和信号输出线EOUT；所述扫描驱动电路还包括多个移位寄存器单元；
如图1所示，所述多个移位寄存器单元中的至少一个移位寄存器单元的至少一实施例包括输出复位晶体管T9、输出晶体管T10、输出电容C3、第一电容C1、第二电容C2、第一晶体管T8、第二晶体管T7、第一电容连接晶体管T6、第二电容连接晶体管T5、第一节点控制晶体管T2、第二节点控制晶体管T3、输入晶体管T1和第三节点控制晶体管T4；
所述输出复位晶体管T9的栅极G9与所述输出电容C3的第二极板C3b耦接，所述输出复位晶体管T9的第一电极S9接入高电压信号Vgh；
所述输出晶体管T10的栅极G10和所述第二电容C2的第二极板C2b耦接，所述输出晶体管T10的第一电极S10接入低电压信号Vgl；
所述输出复位晶体管T9的第二电极D9和所述输出晶体管T10的第二电 极D10都与所述信号输出线EOUT耦接；
所述第一晶体管T8的第二电极D8与所述输出电容C3的第二极板C3b耦接，所述第一晶体管T8的第一电极S8接入所述高电压信号Vgh，所述第一晶体管T8的栅极G8与所述第三节点控制晶体管T4的第二电极D4耦接；
所述第二晶体管T7的第二电极D7与所述第一电容C1的第一极板C1a耦接，所述第二晶体管T7的第一电极S7与所述输出电容C3的第二极板C3b耦接，所述第二晶体管T7的栅极G7与所述第三节点控制晶体管T4的栅极G4耦接；
所述第一电容连接晶体管T6的栅极G6和所述第二电容连接晶体管T5的栅极G5分别与所述第一电容C1的第二极板C1b耦接；所述第一电容连接晶体管T6的第二电极D6与所述第一电容C1的第一极板C1a耦接；所述第一电容连接晶体管T6的第一电极S6与第二晶体管T7的栅极G7耦接；
所述第二电容连接晶体管T5的第一电极S5与所述第一电压信号线VGH耦接；所述第二电容连接晶体管T5的栅极G5与所述第二节点控制晶体管T3的第二电极D3耦接；所述第二电容连接晶体管T5的第二电极D5与所述第三节点控制晶体管T4的第一电极S4耦接；
所述第一节点控制晶体管T2的第一电极S2与所述第二节点控制晶体管T3的栅极G3耦接；所述第一节点控制晶体管T2的栅极G2与所述第二电容C2的第二极板C2b耦接；
所述第二节点控制晶体管T3的第二电极D3与所述第一节点控制晶体管T2的第二电极D2耦接；所述第二节点控制晶体管T3的栅极G3与所述第二时钟信号线CK耦接；所述第二节点控制晶体管T3的第一电极S3接入所述低电压信号Vgl；
所述输入晶体管T1的栅极G1与所述第二节点控制晶体管T3的栅极G3耦接；所述输入晶体管T1的第一电极S1与输入信号端E1耦接；所述输入晶体管T1的第二电极D1与所述第二电容C2的第二极板C2b耦接；
所述第三节点控制晶体管T4的栅极G4与所述第一时钟信号线CB耦接；
所述输出电容C3的第一极板C3a接入所述高电压信号Vgh，所述输出电容C3的第二极板C3b与所述输出复位晶体管T9的栅极G9耦接；
所述第二电容C2的第二极板C2b与所述输出晶体管T10的栅极G10耦接，所述第二电容C2的第一极板C2a与第一时钟信号线CB耦接。
在图1所示的移位寄存器单元的至少一实施例中，所有的晶体管都为p型晶体管，但不以此为限。
在本公开实施例中，图1所示的移位寄存器单元的至少一实施例可以为发光控制扫描驱动电路，但不以此为限。
在本公开至少一实施例中，晶体管的第一电极可以为源极，晶体管的第二电极可以为漏极；或者，晶体管的第一电极可以为漏极，晶体管的第二电极可以为源极。
在图1中，标号为N1的为第一节点，标号为N2的为第二节点，标号为N3的为第三节点，标号为N4的为第四节点。
如图2A所示，本公开如图1所示的移位寄存器单元的至少一实施例在工作时，
在第一阶段P1，CK输入低电平，T1和T3导通，导通的T1将E1提供的高电平的输入信号传输至第一节点N1，从而使得第一节点N1的电位变为高电平，以使得T2、T8以及T10截止；另外，导通的T3将Vgl传输至第二节点N2，从而使得第二节点N2的电平变为低电平，所以T5和T6导通。由于CB输入高电平，所以T7截止；另外，由于C3的储能作用，第四节点N4的电位可以保持为高电平，从而使得T9截止；在第一阶段P1中，由于T9以及T10均截止，则EOUT保持输出低电平；
在第二阶段P2，CB输入低电平，T4和T7导通；由于第一时钟信号CK输入高电平，所以T1和T3截止；由于第一电容C1的储能作用，所以第二节点N2的电位可以继续保持上一阶段的低电平，T5以及T6导通，Vgh通过导通的T5以及T4传输至第一节点N1，从而使得第一节点N1的电位继续保持上一阶段的高电平，所以T2、T8以及T10截止；另外，CB提供的低电平通过导通的T6以及T7被传输至第四节点N4，从而使得第四节点N4的电位变为低电平，所以T9导通，EOUT输出高电压信号Vgh；
在第三阶段P3，CK输入低电平，T1以及T3导通；CB提供高电平，所以T4以及T7截止；由于C3的储能作用，所以第四节点N4的电位可以保持 上一阶段的低电平，从而T9保持导通状态，EOUT输出高电压信号Vgh；
在第四阶段P4，CK输入高电平，T1以及T3截止；CB输入低电平，T4以及T7导通；由于第二电容C2的储能作用，第一节点N1的电位保持上一阶段的高电平，从而使得T2、T8以及T10截止。由于第一电容C1的储能作用，第二节点N2的电位继续保持上一阶段的低电平，从而使得T5以及T6导通。另外，CB输入的低电压信号通过导通的T6以及T7被传输至第四节点N4，从而使得第四节点N4的电平变为低电平，T9导通，导通的T9将高电压Vgh输出，EOUT输出高电压信号Vgh；
在第五阶段P5，CK输入低电压信号，T1以及T3导通；CB输入高电压信号，T4以及T7截止。导通的T1将E1提供的低电平的输入信号传输至第一节点N1，从而使得第一节点N1的电位变为低电平，所以T2、T8以及T10导通；导通的T2将低电平的第二时钟信号传输至第二节点N2，从而可以进一步拉低第二节点N2的电位，所以第二节点N2的电位继续保持上一阶段的低电平，从而使得T5以及T6导通；另外，导通的T8将Vgh传输至第四节点N4，从而使得第四节点N4的电位变为高电压，所以T9截止；导通的T10将Vgl输出，EOUT输出低电压信号Vgl。
如图2B所示，标号为J1的为显示基板，标号为A0的为显示区域，标号为B1的为第一边缘区域，标号为B2的为第二边缘区域。
在所述显示基板J1的显示区域A0可以设置有多条发光控制线、多条栅线和多条数据线，以及由所述多条栅线和所述多条数据线交叉限定的多个子像素；
在第一边缘区域B1和/或第二边缘区域B2可以设置有扫描驱动电路，所述扫描驱动电路包括多个移位寄存器单元；
所述扫描驱动电路包括的多个移位寄存器单元与所述多条发光控制线一一对应，每个所述移位寄存器单元的信号输出线与对应的发光控制线耦接，用于为对应的发光控制线提供发光控制信号。
在具体实施时，一所述发光控制线与相应行像素电路的发光控制端耦接。
可选的，所述显示基板还包括设置于所述基底上的多行像素电路；所述像素电路包括发光控制端；
所述扫描驱动电路包括的所述移位寄存器单元与所述行像素电路一一对应
所述移位寄存器单元的信号输出线与相应行像素电路的发光控制端耦接，用于为所述相应行像素电路的发光控制端提供发光控制信号。
在本公开至少一实施例中，所述像素电路可以设置于显示基板的有效显示区，所述扫描驱动电路可以设置于显示基板的边缘区域。
如图2C所示，标号为Y1的为扫描驱动电路，标号为S11的为所述扫描驱动电路S1包括的第一级移位寄存器单元，标号为S12的为所述扫描驱动电路S1包括的第二级移位寄存器单元，标号为S1N-1的为所述扫描驱动电路S1包括的第N-1级移位寄存器单元，标号为S1N的为所述扫描驱动电路S1包括的第N级移位寄存器单元，N为大于3的整数；
在图2C中，标号为R1的为第一行像素电路，标号为R2的为第二行像素电路，标号为RN-1的为第N-1行像素电路，标号为RN的为第N行像素电路；
S11与R1相对应，S12与R2相对应，S1N-1与RN-1相对应，S1N与RN相对应；
S11为R1提供第一行发光控制信号，S12为R2提供第二行发光控制信号，S1N-1为R1N-1提供第N-1行发光控制信号，S1N为R1N提供第N行发光控制信号。
如图2C所示，在边缘区域，所述显示基板还可以包括栅极驱动电路，所述栅极驱动电路包括多级栅极驱动单元，所述栅极驱动单元与像素行也一一对应，用于为相应行像素提供相应的栅极驱动信号；
在图2C中，标号为Y2的为栅极驱动电路，标号为S21的为栅极驱动电路包括的第一行栅极驱动单元，标号为S22的为栅极驱动电路包括的第二行栅极驱动单元，标号为S2N-1的为栅极驱动电路包括的第N-1行栅极驱动单元，标号为S2N的为栅极驱动电路包括的第N行栅极驱动单元。
如图2D所示，第一电压信号线VGH提供高电压信号Vgh，第二电压信号线VGL1和第三电压信号线VGL2提供低电压信号Vgl，第四电压信号线VGH0提供高电压信号Vgh；
如图2D所示，ESTV、VGH0、VGL2、VGH、VGL1、CK和CB沿着远离显示区域的方向排列；ESTV、VGH0、VGL2、VGH、VGL1、CK和CB和第一方向延伸；
T8、T9和T10设置于VGL2与VGH0之间，T9和T10沿第一方向排列；T8设置于T9与VGL2之间；
T6、T7、C1、T1、T4和T5设置于VGH与VGL2之间；
C1设置于VGL2与T6之间；T4设置于VGL2与T6之间；
T7和T6沿第一方向依次排列，T1、T4和T5沿第一方向依次排列；
T2和T3设置于VGL1与VGH之间，T3与T2沿第一方向依次排列；
C3在基底上的正投影与VGH0在基底上的正投影部分重叠，C2在基底上的正投影与VGL1在基底上的正投影部分重叠。
在图2D中，标号为ESTV的为起始信号线。
如图2D所示，D1复用为D4，S4复用为D5，D6复用为D7。
在图2D和图3中，标号为G1的为T1的栅极，标号为S1的为T1的第一电极，标号为D1的为T1的第二电极；标号为G2的为T2的栅极，标号为S2的为T2的第一电极，标号为D2的为T2的第二电极；标号为G3的为T3的栅极，标号为S3的为T3的第一电极，标号为D3的为T3的第二电极；标号为G4的为T4的栅极，标号为S4的为T4的第一电极，标号为D4的为T4的第二电极；标号为G5的为T5的栅极，标号为S5的为T5的第一电极，标号为D5的为T5的第二电极；标号为G6的为T6的栅极，标号为S6的为T6的第一电极，标号为D6的为T6的第二电极；标号为G7的为T7的栅极，标号为S7的为T7的第一电极，标号为D7的为T7的第二电极；标号为G8的为T8的栅极，标号为S8的为T8的第一电极，标号为D8的为T8的第二电极；标号为G9的为T9的栅极，标号为S9的为T9的第一电极，标号为D9的为T9的第二电极；标号为G10的为T10的栅极，标号为S10的为T10的第一电极，标号为D10的为T10的第二电极。
在图2D中，标号为ESTV的为起始信号线。
上述图2D所示的栅极驱动电路的布局方式中，由于采用了两根提供高电压信号的信号线，导致信号线连接方式杂乱，未充分利用第n级移位寄存 器单元中的T10与第n+1级移位寄存器单元中的输出复位晶体管之间的空间设置EOUT，并C1未充分利用T5的栅极与第二导电连接部之间的空间，C2未充分利用T2与相邻下一级移位寄存器单元之间的空间，导致移位寄存器单元的横向宽度较大，不利于显示基板的窄边框化发展。
图2D所示的移位寄存器单元可以为扫描驱动电路包括的第n级移位寄存器单元，n为正整数。
基于上述问题的存在，本公开的发明人经研究发现，可通过调整移位寄存器单元中各晶体管的布局方式，缩小移位寄存器单元的占用面积，从而缩小显示基板的边框宽度。
在图3所示的布局方式中，第一电压信号线VGH提供高电压信号Vgh，第二电压信号线VGL1和第三电压信号线VGL2提供低电压信号Vgl；本公开至少一实施例减少一根提供高电压信号Vgh的信号线，并将VGH设置于VGL1和VGL2之间，以方便布局。
与图2D相比，图3所示的至少一实施例移去第四电压信号线VGH0，仅使用第一电压信号线VGH、第二电压信号线VGL1和第三电压信号线VGL2，并将VGH设置于VGL1和VGL2之间。
如图3所示，所述输出复位晶体管T9的第一电极S9与第一电压信号线VGH耦接，所述输出晶体管T10的第一电极S10与第二电压信号线VGL1耦接，所述第一晶体管T8的第一电极S8与所述第一电压信号线VGH耦接，所述第二电容连接晶体管T5的第一电极S5与所述第一电压信号线VGH耦接，所述第二节点控制晶体管T3的第一电极S3与第三电压信号线VGL2耦接，所述输出电容C3的第一极板C3a与第一电压信号线VGH耦接。
如图3所示，在将上述结构的移位寄存器单元布局在显示基板的边缘区域时，沿着远离显示基板的显示区域的方向，第二电压信号线VGL1、第一电压信号线VGH和第三电压信号线VGL2依次排列；所述第二电压信号线VGL1、所述第一电压信号线VGH和第三电压信号线VGL2都沿第一方向延伸；
并且，进一步的，在所述第三电压信号线VGL2远离所述第一电压信号线VGH的一侧，设置有第一时钟信号线CB、第二时钟信号线CK和起始电 压信号线ESTV；第一时钟信号线CB、第二时钟信号线CK和起始电压信号线ESTV沿着远离所述显示区域的第二方向依次排列；第一时钟信号线CB、第二时钟信号线CK和起始电压信号线ESTV都沿着第一方向延伸；
所述输出复位晶体管T9和所述输出晶体管T10设置于所述第一电压信号线VGH和所述第二电压信号线VGL1之间；沿着第一方向，所述输出复位晶体管T9、所述输出晶体管T10和所述信号输出线EOUT依次排列；
所述第一电容C1、所述第一晶体管T8、第二晶体管T7、第一电容连接晶体管T6、第二电容连接晶体管T5、第一节点控制晶体管T2、第二节点控制晶体管T3、输入晶体管T1和第三节点控制晶体管T4都设置于所述第一电压信号线VGH和所述第三电压信号线VGL2之间；
所述第一晶体管T8、所述第二晶体管T7和所述第一电容C1沿着第一方向依次排列，所述输入晶体管T1、所述第三节点控制晶体管T4、所述第二电容连接晶体管T5和所述第一电容C1沿着第一方向依次排列，所述第二节点控制晶体管T3和所述第一节点控制晶体管T2沿着第一方向依次排列；
所述第二晶体管T7和所述第三节点控制晶体管T4沿着第二方向依次排列；
所述第一电容连接晶体管T6和所述第二电容连接晶体管T5沿第二方向依次排列；
所述第一晶体管T8、所述输入晶体管T1和所述第二节点控制晶体管T3沿着第二方向排列；
并且，所述第一节点控制晶体管T2的有源图形设置为U形结构，以使得T2形成为双栅结构。
在本公开至少一实施例中，扫描驱动电路包括的第一级移位寄存器单元的输入信号端与起始信号线ESTV耦接，所述输入信号端为与所述输入晶体管T1的第一电极S1耦接的端子。
在本公开至少一实施例中，所述第一方向与所述第二方向相交，例如，所述第一方向可以与所述第二方向垂直，但不以此为限。
具体的，所述第二方向与所述第一方向相交的夹角可以根据实际需要设置，示例性的，所述第二方向与所述第一方向垂直。
在本公开至少一实施例中，第一时钟信号线CB的位置和所述第二时钟信号线CK的位置可以对调，但以此为限。
例如，在如图3所示的布局方式中，第一方向可以为从上至下的垂直方向，第二方向可以为从右至左的水平方向，但不以此为限。
在实际操作时，信号线宽度主要会对电阻产生影响，较宽的信号线电阻小，有利于信号稳定。其中，第一电压信号线VGH、第二电压信号线VGL1和第三电压信号线VGL2提供的是直流电压，受线宽影响较小。而第一时钟信号线CB和第二时钟信号线CK提供的是时钟信号，当该时钟信号的电位由高电压转换为低电压时，电阻小的时钟信号线更容易使得该时钟信号的电位迅速达到低电压，因此，在本公开至少一实施例中，将所述第一时钟信号线CB的线宽和所述二时钟信号线的线宽设置为较宽。
如图3所示，所述输出电容C3的第一极板C3a在所述基底上的正投影，与所述第一电压信号线VGH在所述基底上的正投影存在信号线重叠区域；所述输出电容C3的第二极板C3b与所述基底上的正投影与所述第一电压信号线VGH在所述基底上的正投影部分重叠；
所述第二电容C2的第一极板C2a在所述基底上的正投影在所述第二电容C2的第二极板C2b在所述基底上的正投影之内；所述第二电容C2的第一极板C2a为L形；
由图3可知，C2的第一极板的横向部分设置于第n级移位寄存器单元中的T2与第n+1级移位寄存器单元中的第二节点控制晶体管之间，充分利用第n级移位寄存器单元中的T2与第n+1级移位寄存器单元中的第二节点控制晶体管之间的空间，并C1的第一极板的横向部分位于T5的栅极与第二导电连接部L2之间，充分利用T5的栅极与第二导电连接部L2之间的空间。
在本公开图3所示的布局方式中，由于输出复位晶体管T9与第一电压信号线VGH耦接，输出晶体管T10与第二电压信号线VGL1耦接，因此将输出复位晶体管T9和输出晶体管T10设置于第一电压信号线VGH和第二电压信号线VGL1之间，并充分利用第n级移位寄存器单元包括的T10与第n+1级移位寄存器单元包括的输出复位晶体管之间的空间，以设置信号输出线EOUT，以使得T9和T10设置于VGH与VGL1之间，并所述第一电压信号 线VGH与输出电路(所述输出电路包括T9和T10)之间未设置其他信号线和其他晶体管包括的部件，所述第二电压信号线VGL1与所述输出电路(所述输出电路包括T9和T10)之间未设置其他信号线和其他晶体管包括的部件，收窄VGH到T9和T10的距离，并收窄VGL1到T9和T10的距离，使得移位寄存器单元的横向宽度得到缩减。
在本公开至少一实施例中，图3所示的移位寄存器单元可以为扫描驱动电路包括的第n级移位寄存器单元，n为正整数。
并且，在本公开图3所示的布局方式中，由于T8的第一电极S8与第一电压信号线VGH耦接，T8的第二电极D8与输出电容C3的第二极板C3b耦接，因此，T8距离VGH和C3越近，相应布局就会更合理。本公开至少一实施例将T8设置于第一电压信号线VGH远离第二电压信号线VGL1的一侧，并将T8设置为靠近相邻上一级移位寄存器单元，以便利用第n级移位寄存器单元中的T8与第n+1级移位寄存器单元包括的第一晶体管之间的空间，并缩减T8的源极与VGH之间的信号线的长度，缩减T8的漏极与C3之间的信号线的长度，以缩减移位寄存器单元的横向宽度。如图3所示，T7、T6和C1都设置于第n级移位寄存器单元中的T8与第n+1级移位寄存器单元包括的第一晶体管之间的空间，充分利用了第n级移位寄存器单元中的T8与第n+1级移位寄存器单元包括的第一晶体管之间的空间。
进一步的，T5的栅极G5与C1的第二极板C1b耦接，并T6的第二电极D6与所述第一电容C1的第一极板C1a耦接，则T5的位置和T6的位置应靠近VGH，并缩短T5与T6的距离便可以调整C1的形状，如图3所示，本公开至少一实施例将第一电容C1的极板设置为L形。并且，如图3所示，C2充分利用第n级移位寄存器单元中的T2与第n+1级移位寄存器单元中的第二节点控制晶体管之间的多余空间，将第二电容C2的极板设置为L形。通过如上设置可以一定程度上缩短移位寄存器单元的横向宽度，优化纵向高度。
如图3所示，本公开至少一实施例所述的显示基板包括设置于所述基底上的扫描驱动电路和显示区域，所述扫描驱动电路包括多个移位寄存器单元；所述扫描驱动电路还包括第一电压信号线VGH、第二电压信号线VGL1、第一时钟信号线CB和第二时钟信号线CK；所述第一电压信号线VGH、所述 第二电压信号线VGL1、所述第一时钟信号线CB和所述第二时钟信号线CK沿着第一方向延伸；所述显示区域包括至少一个驱动晶体管，所述驱动晶体管被配置为驱动发光元件进行显示；
所述多个移位寄存器单元中的至少一个移位寄存器单元包括输出电路O1和信号输出线EOUT；所述输出电路O1分别与所述第一电压信号线VGH、所述第二电压信号线VGL1和所述信号输出线EOUT耦接；所述信号输出线EOUT沿着第二方向延伸，所述第一方向与所述第二方向相交；
所述输出电路O1包括的晶体管设置于所述第一电压信号线VGH和所述第二电压信号线VGL1之间。
本公开至少一实施例所述的显示基板将输出电路O1设置于第一电压信号线VGH和第二电压信号线VGL1之间，使得在空间结构上，第一电压信号线VGH设置于输出电路O1远离显示区域的一侧，并所述第一电压信号线VGH与输出电路O1之间未设置其他信号线和其他晶体管包括的部件，所述第二电压信号线VGL1设置于输出电路O1靠近显示区域的一侧，所述第二电压信号线VGL1与所述输出电路O1之间未设置其他信号线和其他晶体管包括的部件，可以收窄第一电压信号线VGH到输出电路O1的距离，并收窄第二电压信号线VGL1到输出电路O1的距离，使得移位寄存器单元的横向宽度得到缩减。
在具体实施时，所述第一电压信号线VGH位于所述第二电压信号线VGL1远离显示区域的一侧。
在本公开至少一实施例中，所述第一电压信号线VGH提供第一电压给所述输出电路O1，所述第二电压信号线VGL1提供第二电压给所述输出电路O1，所述第一电压高于所述第二电压。
在具体实施时，所述第一电压可以为高电压Vgh，所述第二电压可以为低电压Vgl，但不以此为限。
可选的，所述输出电路可以包括输出晶体管和输出复位晶体管；
所述输出复位晶体管和所述输出晶体管沿着第一方向排列；
所述输出复位晶体管的第一电极与所述第一电压信号线耦接，所述输出晶体管的第一电极与所述第二电压信号线耦接。
如图3所示，所述输出电路O1包括输出复位晶体管T9和输出晶体管T10；
所述输出复位晶体管T9和所述输出晶体管T10从上至下依次排列，所述输出复位晶体管T9的第一电极S9与所述第一电压信号线VGH耦接，所述输出晶体管T10的第一电极S10与所述第二电压信号线VGL1耦接。
在本公开至少一实施例中，所述输出晶体管的第二电极和所述输出复位晶体管的第二电极都与所述信号输出线耦接；
所述信号输出线位于相邻的移位寄存器单元中的输出电路之间。
在具体实施时，所述输出晶体管和所述输出复位晶体管都与所述信号输出线耦接，则所述输出晶体管和所述输出复位晶体管应与所述信号输出线距离较近，本公开至少一实施例将信号输出线下移至相邻的移位寄存器单元中的输出电路之间，收窄移位寄存器单元的横向宽度。
在本公开至少一实施例中，输出复位晶体管T9用于提供无效的发光控制信号，输出晶体管T10用于提供有效的发光控制信号。
在本公开至少一实施例中，所述有效的发光控制信号可以为能够使得像素电路中的发光控制晶体管打开的电压信号(所述发光控制晶体管的栅极与所述发光控制线耦接)，所述无效的发光控制信号可以为能够使得所述发光控制晶体管关断的电压信号。
具体的，所述显示显示基板的显示区域包括多个子像素；所述多个子像素中的至少一个包括像素驱动电路；所述像素驱动电路包括驱动晶体管、栅线、发光控制线和数据线，所述驱动晶体管被配置为驱动发光元件进行显示；所述扫描驱动电路包括的多个移位寄存器单元与多条发光控制线一一对应，每个所述移位寄存器单元的信号输出线与对应的发光控制线耦接，用于为对应的发光控制线提供发光控制信号。
在本公开至少一实施例中，所述输出晶体管的有源层和所述输出复位晶体管的有源层由一个连续的第一半导体层形成；
所述第一半导体层与所述信号输出线沿第一方向排列。
在具体实施时，所述输出晶体管的有源层和所述输出复位晶体管的有源层可以由一个连续的第一半导体层形成，但不以此为限。
在本公开至少一实施例中，所述输出晶体管的有源层和所述输出复位晶 体管的有源层可以由一个连续的第一半导体层形成；
所述输出复位晶体管的有源层包括沿第一方向相对设置的至少两个第一导电部分，以及至少一个第一沟道部分；每一所述第一沟道部分设置于两相邻的第一导电部分之间；
所述输出晶体管的有源层可以包括沿第一方向相对设置的至少两个第二导电部分，以及至少一个第二沟道部分；每一所述第二沟道部分设置于两相邻的所述第二导电部分之间；
所述输出复位晶体管的有源层中与所述输出晶体管的有源层距离最近的第一导电部分可以复用为所述输出晶体管中的第二导电部分，这样能够进一步缩小所述输出晶体管和输出复位晶体管的布局空间，有利于实现所述显示基板的窄边框化。
如图4所示，所述输出复位晶体管T9的有源层和所述输出晶体管T10的有源层可以由一个连续的第一半导体层10形成；
所述输出复位晶体管T9的有源层包括沿第一方向相对设置的第一个第一导电部分111、第二个第一导电部分112和第三个第一导电部分113，所述输出复位晶体管T9的有源层还包括第一个第一沟道部分121和第二个第一沟道部分122；
所述第一个第一沟道部分121设置于所述第一个第一导电部分111和所述第二个第一导电部分112之间，所述第二个第一沟道部分122设置于所述第二个第一导电部分112和所述第三个第一导电部分113之间；
所述第一导电部分113复用为所述输出晶体管T10的有源层包括的第一个第二导电部分；
所述输出晶体管T10的有源层还包括沿第一方向相对设置的第二个第二导电部分132和第三个第二导电部分133，所述输出晶体管T10的有源层还包括第一个第二沟道部分141和第二个第二沟道部分142；
所述第一个第二沟道部分141设置于第一个第二导电部分与第二个第二导电部分132之间，所述第二个第二沟道部分142设置于所述第二个第二导电部分132和第三个第二导电部分133之间。
在所述输出复位晶体管T9和所述输出晶体管T10中，每个晶体管的沟 道部分两侧的导电部分，可以分别对应作为该晶体管的第一电极和第二电极，或者可以分别与该晶体管的第一电极和该晶体管的第二电极耦接，从而使得T9和T10可以通过第三个第一导电部分113实现电连接。
在制作所述第一半导体层11时，示例性的，可以先形成第一半导体材料层，然后在形成输出复位晶体管T9的栅极G9和输出晶体管T10的栅极G10之后，以输出复位晶体管T9的栅极G9和输出晶体管T10的栅极G10为掩膜，对第一半导体材料层中未被各晶体管的栅极覆盖的部分进行掺杂，使得所述第一半导体材料层中未被各晶体管的栅极覆盖的部分形成为所述导电部分，所述第一半导体材料层中被各晶体管覆盖的部分形成为所述沟道部分。
根据上述显示基板的具体结构可知，本公开至少一实施例所述的显示基板中，移位寄存器单元中的所述输出复位晶体管T9和输出晶体管T10能够沿着所述第一方向排列，缩小了移位寄存器单元在第二方向上占用的面积，从而使得所述显示基板更符合窄边框化的发展需求。
具体的，所述输出复位晶体管的栅极可以包括至少一个输出复位栅极图形，所述输出复位晶体管的第一电极包括至少一个第一电极图形，所述输出复位晶体管的第二电极包括至少一个第二电极图形；
所述输出复位栅极图形位于相邻的所述第一电极图形和所述第二电极图形之间；
所述第二电极图形、所述输出复位栅极图形和所述第一电极图形都沿着第二方向延伸；
所述第一方向与所述第二方向相交。
具体的，所述输出晶体管的栅极可以包括至少两个沿第一方向排列的输出栅极图形，所述输出晶体管的第一电极包括至少一个第三电极图形，所述输出晶体管的第二电极包括至少一个第四电极图形；
所述输出栅极图形位于相邻的所述第三电极图形和所述第四电极图形之间；
所述第四电极图形、所述输出栅极图形和所述第三电极图形都沿着第二方向延伸；
所述第一方向与所述第二方向相交；
所述输出复位晶体管中最靠近所述输出晶体管的栅极的所述第二电极图形复用为所述输出晶体管的第四电极图形。
在具体实施时，所述输出复位栅极图形的数量、所述第一电极图形的数量、所述第二电极图形的数量、所述输出栅极图形的数量、所述第三电极图形的数量和所述第四电极图形的数量可以根据实际需要设置。示例性的，如图5和图8所示，所述输出栅极图形的数量和所述输出复位栅极图形的数量可以为两个，第一电极图形的数量和第三电极图形的数量可以为一个，所述第二电极图形的数量和所述第四电极图形的数量可以为两个。
并且，由于所述输出晶体管的第二电极和输出复位晶体管的第二电极都与信号输出线耦接，因此，在布局输出晶体管和输出复位晶体管时，可以将所述输出复位晶体管中最靠近所述输出晶体管的栅极的所述第二电极图形复用为所述输出晶体管的第四电极图形，这样能够进一步缩小输出晶体管和输出复位晶体管的布局空间，有利于实现显示基板的窄边框化。
如图3和图5所示，在一些实施例中，所述输出复位晶体管T9的栅极G9可以包括：第一输出复位栅极图形G91和第二输出复位栅极图形G92；
所述输出晶体管T10的栅极G10可以包括：第一输出栅极图形G101和第二输出栅极图形G102；
第一输出复位栅极图形G91、第二输出复位栅极图形G92、所述第一输出栅极图形G101和所述第二输出栅极图形G102沿第一方向依次排列；
第一输出复位栅极图形G91、第二输出复位栅极图形G92、所述第一输出栅极图形G101和所述第二输出栅极图形G102都沿第二方向延伸，第二方向与第一方向相交；
所述第一输出复位栅极图形G91和所述第二输出复位栅极图形G92相互耦接，所述第一输出栅极图形G101和所述第二输出栅极图形G102相互耦接；
如图8所示，所述输出复位晶体管T9的第二电极D9包括第一个第二电极图形D91和第二个第二电极图形D92；
D91、S9和D92沿第一方向依次排列，并且，D91、S9和D92都沿第二方向延伸，S9与第一电压信号线VGH耦接；
D92复用为所述输出晶体管T10的第二电极D10中的第一个第四电极图 形；
所述输出晶体管T10的第二电极D10还包括第二个第四电极图形D102；
D92、S10和D102沿第一方向依次排列；S10与第二电压信号线VGL1耦接；
如图3、图5、图8所示，G91在所述基底上的正投影设置于D91在基底上的正投影与S9在基底上的正投影之间，G92在所述基底上的正投影设置于S9在基底上的正投影与D92在基底上的正投影之间，G101在所述基底上的正投影在D92在基底上的正投影与S10在基底上的正投影之间，G102在所述基底上的正投影在S10在基底上的正投影与D102在基底上的正投影之间。
在本公开至少一实施例中，扫描驱动电路包括的至少一个移位寄存器单元在工作时，当T10开启时，所述移位寄存器单元持续输出低电压信号，为了保持T10的栅极接入的电压信号稳定，应避免T10的栅极G10与时钟信号线交叠，此处将G10设置为与第二电压信号线VGL1(VGL1为直流电压信号线)交叠，对T10的栅极G10接入的电压信号影响最小。
在具体实施时，所述输出复位晶体管的有源层可以包括沿第一方向相对设置的至少两个第一导电部分，以及至少一个第一沟道部分；每一所述第一沟道部分设置于两相邻的所述第一导电部分之间；
所述第一沟道部分与所述输出复位栅极图形一一对应，每个所述第一沟道部分在所述基底上的正投影，均位于对应的所述输出复位栅极图形在所述基底上的正投影的内部；
所述输出复位晶体管中的一部分所述第一导电部分与所述第一电极图形一一对应，所述第一电极图形在所述基底上的正投影，与对应的所述第一导电部分在所述基底上的正投影存在第一重叠区域，所述第一电极图形通过设置在所述第一重叠区域的至少一个第一过孔与对应的所述第一导电部分耦接；
所述输出复位晶体管中的另一部分所述第一导电部分与所述第二电极图形一一对应，所述第二电极图形在所述基底上的正投影，与对应的所述第一导电部分在所述基底上的正投影存在第二重叠区域，所述第二电极图形通过设置在所述第二重叠区域的至少一个第二过孔与对应的所述第一导电部分耦接。
在具体实施时，所述输出晶体管的有源层可以包括沿第一方向相对设置的至少两个第二导电部分，以及至少一个第二沟道部分；每一所述第二沟道部分设置于两相邻的所述第二导电部分之间；
所述第二沟道部分与所述输出栅极图形一一对应，每个所述第二沟道部分在所述基底上的正投影，均位于对应的所述输出栅极图形在所述基底上的正投影的内部；
所述输出晶体管中的一部分所述第二导电部分与所述第三电极图形一一对应，所述第三电极图形在所述基底上的正投影，与对应的所述第二导电部分在所述基底上的正投影存在第三重叠区域，所述第三电极图形通过设置在所述第三重叠区域的至少一个第三过孔与对应的所述第二导电部分耦接；
所述输出晶体管中的另一部分所述第二导电部分与所述第四电极图形一一对应，所述第四电极图形在所述基底上的正投影，与对应的所述第二导电部分在所述基底上的正投影存在第四重叠区域，所述第四电极图形通过设置在所述第四重叠区域的至少一个第四过孔与对应的所述第二导电部分耦接。
如图4、图5、图7和图8所示，第一个第一沟道部分121与第一输出复位栅极图形G91对应，第二个第一沟道部分122与第二输出复位栅极图形G92对应；
第一个第一沟道部分121在基底上的正投影，位于G91在基底上的正投影的内部；
第二个第一沟道部分122在基底上的正投影，位于G92在基底上的正投影的内部；
第一个第一导电部分111与第一个第二电极图形D91对应，第二个第一导电部分112与输出复位晶体管的第一电极S9对应，第三个第一导电部分113与第二个第二电极图形D92对应；
S9在基底上的正投影，与第二个第一导电部分112在基底上的正投影存在第一重叠区域，S9通过设置于所述第一重叠区域的至少一个第一过孔H1与第二个第一导电部分112耦接；
D91在基底上的正投影，与第一个第一导电部分111在基底上的正投影存在第一个第二重叠区域，D91通过设置于所述第一第二重叠区域中的至少 一个第二过孔H2与第一个第一导电部分111耦接；
D92在基底上的正投影，与第三个第一导电部分113在基底上的正投影存在第二个第二重叠区域，D92通过设置于所述第二个第二重叠区域中的至少一个第二过孔H2与第三个第一导电部分113耦接；
第一个第二沟道部分141与第一输出栅极图形G101对应，第二个第二沟道部分142与第二输出栅极图形G102对应；
第一个第二沟道部分141在基底上的正投影，位于G101在基底上的正投影的内部；
第二个第二沟道部分142在基底上的正投影，位于G102在基底上的正投影的内部；
D92复用为第一个第四电极图形；第三个第一导电部分113复用为第一个第二导电部分；
第一个第二导电部分与第一个第四电极图形对应；
第二个第二导电部分132与输出晶体管的第一电极S10对应，第三个第二导电部分133与第二个第四电极图形D102对应；
S10在基底上的正投影，与第二个第二导电部分132在基底上的正投影存在第三重叠区域，S10通过设置于所述第三重叠区域的至少一个第三过孔H3与第二个第二导电部分132耦接；
D102在基底上的正投影，与第三个第二导电部分133在基底上的正投影存在第四重叠区域，D102通过设置于所述第四重叠区域中的至少一个第四过孔H4与第三个第二导电部分133耦接。
在本公开至少一实施例中，第一过孔的数量、第二过孔的数量、第三过孔的数量和第四过孔的数量可以根据实际需要设置。
上述实施例提供的显示基板中，利用第一半导体层10形成输出复位晶体管T9的有源层和输出晶体管T10的有源层，不仅使得T9和T10在第二方向上占用的空间较小，而且可以通过增加输出复位晶体管T9的有源层和输出晶体管T10的有源层在第一方向上的尺寸，来保证T9的沟道宽度和T10的沟道宽度，从而实现在保证T9的工作性能和T10的工作性能的情况下，缩小显示基板的边框宽度。
如图3、图4和图6所示，信号输出线EOUT在基底上的正投影在第n级移位寄存器单元中的第一半导体层10在基底上的正投影与第n+1级移位寄存器单元中的第一半导体层在基底上的正投影之间，第一半导体层10和信号输出线EOUT沿第一方向排列，可以收窄移位寄存器单元的横向宽度。
在本公开至少一实施例中，图4是图3中的有源层的示意图，图5是图3中的第一栅金属层的示意图，图6是图3中的第二栅金属层的示意图，图7是依次设置了有源层、第一栅金属层和第二栅金属层之后制作的过孔的示意图，图8是图3中的源漏金属层的示意图。
在具体实施时，在基底上依次设置有源层、第一栅金属层、第二栅金属层、过孔和源漏金属层，以形成显示基板。
在本公开至少一实施例中，所述至少一个移位寄存器单元除了包括输出晶体管和输出复位晶体管之外，还可以包括多个晶体管；每个晶体管的沟道部分两侧的导电部分，可以分别对应作为该晶体管的第一电极和第二电极，或者可以分别与该晶体管的第一电极和该晶体管的第二电极耦接。
在本公开至少一实施例中，如图3所示，所述第一电压信号线VGH的个数可以为一个；
如图1和图3所示，所述输出电路包括输出复位晶体管T9；所述至少一个移位寄存器单元还包括输出电容C3、第一晶体管T8和第二电容连接晶体管T5；
所述输出复位晶体管T9的第一电极、所述输出电容C3的第一极板、所述第一晶体管T8的第一电极和所述第二电容连接晶体管T5的第一电极都与所述第一电压信号线VGH耦接，以使得所述移位寄存器单元包括的各晶体管都与同一第一电压信号线VGH耦接，减少采用的信号线的个数。
在本公开至少一实施例中，通过将VGH设置于VGL1和VGL2之间，以使得第一电压信号线VGH能够同时为第二电容连接晶体管T5的第一电极和第一晶体管T8的第一电极提供第一电压信号，并使得所述第一电压信号线VGH能够为所述输出电容C3的第一极板进行充电。
如图3所示，所述显示基板还包括第三电压信号线VGL2，所述第一电压信号线VGH位于所述第二电压信号线VGL1与所述第三电压信号线VGL3 之间。
如图3、图4、图7和图8所示，所述第二电容连接晶体管T5的第一电极S5通过第五连接过孔H85与信号线导电连接部L40耦接，所述信号线导电连接部L40与所述第一电压信号线VGH耦接，以使得所述第二电容连接晶体管T5的第一电极S5与所述第一电压信号线VGH耦接；
所述信号线导电连接部L40与所述第一电压信号线VGH包含于源漏金属层，所述第二电容连接晶体管T5的第一电极S5包含于有源层。
如图3、图4、图7和图8所示，所述至少一个移位寄存器单元还包括第一电容C1；
所述信号线导电连接部L40在基底上的正投影与第一电容C1的第一极板C1a在基底上的正投影部分重叠。
如图3、图6和图7所示，所述输出电容C3的第一极板C3a在所述基底上的正投影，与所述第一电压信号线VGH在所述基底上的正投影存在信号线重叠区域，所述输出电容C3的第一极板C3a通过设置在所述信号线重叠区域的至少一个信号线过孔H01与所述第一电压信号线VGH耦接。在本公开至少一实施例中，如图2所示，所述至少一个移位寄存器单元还可以包括输出电容C3和第一晶体管T8；
如图3、图6和图7所示，所述输出电容C3的第一极板C3a在所述基底上的正投影，与所述第一电压信号线VGH在所述基底上的正投影存在信号线重叠区域，所述输出电容C3的第一极板C3a通过设置在所述信号线重叠区域的至少一个信号线过孔H01与所述第一电压信号线VGH耦接；
所述第一晶体管T8位于所述第一电压信号线VGH远离所述输出复位晶体管T9的一侧；
如图8所示，所述至少一个移位寄存器单元还包括与所述第一晶体管T8的第二电极D8耦接的极板导电连接部71；
如图3、图4、图7和图8所示，所述第一晶体管T8的第二电极D8通过第一连接过孔H81与所述极板导电连接部71耦接；
如图3、图5、图7和图8所示，所述极板导电连接部71在所述基底上的正投影，与所述输出电容C3的第二极板C3b在所述基底上的正投影存在 极板重叠区域，所述极板导电连接部71通过设置于所述极板重叠区域的至少一个极板过孔H02与所述输出电容C3的第二极板C3b耦接；
所述第一晶体管T8的第一电极S8与所述第一电压信号线VGH耦接。
在具体实施时，如图7所示，所述第一晶体管T8的第一电极S8通过第二连接过孔H82与所述第一电压信号线VGH耦接。
在本公开至少一实施例中，将T8移至第一电压信号线VGH远离第二电压信号线VGL1的一侧，并将输出电容C3的极板在基底上的正投影设置为与第一电压信号线VGH在基底上的正投影部分重叠，以缩减第一晶体管T8的第一电极S8与第一电压信号线VGH之间的距离，缩减第一晶体管T8的第二电极D8与所述输出电容C3的第二极板C3b之间的距离，使得T8可以方便的分别耦接至第一电压信号线VGH和输出电容C3的第二极板C3b，使得空间紧凑，布局更为合理。
在优选情况下，所述第一晶体管T8的第一电极S8在基底上的正投影与所述第一电压信号线VGH在基底上的正投影之间在第二方向上的最大距离小于第一预定距离，所述第一晶体管T8的第二电极D8在基底上的正投影与所述输出电容C3的第二极板C3b在基底上的正投影之间在第二方向上的最大距离小于第二预定距离，以使得第一晶体管T8靠近第一电压信号线VGH和输出电容C3，缩短移位寄存器单元的横向宽度，利于实现窄边框。
在本公开至少一实施例中，所述第一预定距离和所述第二预定距离可以根据实际情况选定，例如，所述第一预定距离可以大于或等于20um(微米)而小于或等于30um，所述第二预定距离可以大于或等于25um(微米)而小于或等于35um。
在本公开至少一实施例中，S8和D8设置于有源层，如图4所示，所述第一个第三导电部分211用作所述第一晶体管T8的第一电极S8，所述第二个第三导电部分212用作所述第一晶体管T8的第二电极D8。
在本公开至少一实施例中，所述第一晶体管T8的第一电极S8在基底上的正投影与所述第一电压信号线VGH在基底上的正投影之间在第二方向上的最大距离指的是：所述第一晶体管T8的第一电极S8在基底上的正投影的 边缘线上的任一点，与所述第一电压信号线VGH在基底上的正投影的边缘线之间，沿第二方向上的最大距离；
所述第一晶体管T8的第二电极D8在基底上的正投影与所述输出电容C3的第二极板C3b在基底上的正投影之间在第二方向上的最大距离指的是：所述第一晶体管T8的第二电极D8在基底上的正投影的边缘线上的任一点，与所述输出电容C3的第二极板C3b在基底上的正投影的边缘线之间，沿第二方向上的最大距离。
在图10A中，仅绘制出了图4中的第二半导体层(所述第二半导体层包括第一个第三导电部分211和第二个第三导电部分212)在基板上的正投影和所述第一电压信号线VGH在基板上的正投影；
在图10B中，仅绘制出了图4中的第二半导体层(所述第二半导体层包括第一个第三导电部分211和第二个第三导电部分212)在基板上的正投影和所述输出电容C3的第二极板的正投影在基底上的正投影；
在图10A和图10B中，标号为X1的是所述第一晶体管T8的第一电极S8在基底上的正投影的边缘线，标号为X2的是所述第一电压信号线VGH在基底上的正投影的边缘线，标号为X3的是所述第一晶体管T8的第二电极D8在基底上的正投影的边缘线，标号为X4的是所述输出电容C3的第二极板C3b在基底上的正投影的边缘线。
在图10A中，标号为d1的为所述第一晶体管T8的第一电极S8在基底上的正投影与所述第一电压信号线VGH在基底上的正投影之间在第二方向上的最大距离。
在图10B中，标号为d2的为所述第一晶体管T8的第二电极D8在基底上的正投影与所述输出电容C3的第二极板C3b在基底上的正投影之间在第二方向上的最大距离。
具体的，如图5所示，所述输出复位晶体管T9的栅极G9包括的第一输出复位栅极图形G91和第二输出复位栅极图形G92与所述输出电容C3的第二极板C3b耦接；
如图3和图6所示，所述输出电容C3的第一极板C3a在所述基底上的 正投影与所述输出电容C3的第二极板C3b在所述基底上的正投影至少部分重叠。
在具体实施时，所述显示基板还可以包括第三电压信号线；所述第三电压信号线位于所述第一晶体管远离所述第一电压信号线的一侧；
所述第三电压信号线沿第一方向延伸。
在本公开至少一实施例中，所述第三电压信号线可以为低电压信号线，第三电压信号线提供的低电压可以与第一电压信号线提供的低电压相同，但不以此为限。
具体的，第一晶体管可以设置于第一电压信号线和第三电压信号线之间。
在本公开至少一实施例中，如图3所示，所述至少一个移位寄存器单元还可以包括第二晶体管T7；
如图4所示，所述第一晶体管T8的有源层和所述第二晶体管T7的有源层由一个连续的第二半导体层20形成；所述第二半导体层20沿第一方向延伸；
所述第一晶体管T8的有源层包括沿第一方向依次设置的第一个第三导电部分211、第三沟道部分221和第二个第三导电部分212；
所述第二个第三导电部分212复用为第一个第四导电部分；
所述第二晶体管T7的有源层包括沿第一方向依次设置的所述第一个第四导电部分、第四沟道部分241和第二个第四导电部分232；
如图3和图8所示，所述第一晶体管T8的第二电极D8复用为所述第二晶体管T7的第一电极S7。
在本公开至少一实施例中，所述第一个第三导电部分211用作所述第一晶体管T8的第一电极S8，所述第二个第三导电部分212用作所述第一晶体管T8的第二电极D8；第二个第四导电部分232用作所述第二晶体管T7的第二电极D7。
在本公开至少一实施例中，T7设置于T8与C1之间，并T8的第二电极S8复用为T7的第二电极，以在收窄移位寄存器单元的横向宽度的同时，减小移位寄存器单元的纵向高度。
可选的，所述至少一个移位寄存器单元还可以包括第一电容，以及，与 所述第一电容的第二极板耦接的晶体管；
所述第一电容和所述与所述第一电容的第二极板耦接的晶体管都设置于所述第一电压信号线远离所述第二电压信号线的一侧；
所述与所述第一电容的第二极板耦接的晶体管的栅极在基底上的正投影与所述第一电压信号线在基底上的正投影之间在第二方向上的最大距离小于第三预定距离。
在具体实施时，由于与所述第一电容的第二极板耦接的晶体管也与第一电压信号线耦接，因此与所述第一电容的第二极板耦接的晶体管的位置以靠近第一电压信号线为宜，本公开至少一实施例将所述与所述第一电容的第二极板耦接的晶体管的栅极在基底上的正投影与所述第一电压信号线在基底上的正投影之间在第二方向上的最大距离设置为小于第三预定距离，以收窄移位寄存器单元的横向宽度。
在本公开至少一实施例中，所述第三预定距离可以根据实际情况选定，例如，所述第三预定距离大于或等于30um(微米)而小于或等于40um。
在本公开至少一实施例中，与所述第一电容的第二极板耦接的晶体管的栅极在基底上的正投影与所述第一电压信号线在基底上的正投影之间在第二方向上的最大距离指的是：与所述第一电容的第二极板耦接的晶体管的栅极在基底上的正投影的边缘线的任一点，与第一电压信号线在基底上的正投影的边缘线之间，沿第二方向上的最大距离。
具体的，如图1和图3所示，所述与所述第一电容C1的第二极板C1b耦接的晶体管可以包括第一电容连接晶体管T6和第二电容连接晶体管T5；
如图3和图5所示，所述第一电容连接晶体管T6的栅极G6和所述第二电容连接晶体管T5的栅极G5分别与所述第一电容C1的第二极板C1b耦接；
如图3、图7和图8所示，所述至少一个移位寄存器单元还包括与所述第一电容连接晶体管T6的第二电极D6耦接的第一导电连接部L1，所述第一导电连接部L1在所述基底上的正投影与所述第一电容C1的第一极板C1a在所述基底上的正投影之间存在第五重叠区域，所述第一导电连接部L1通过设置于所述第五重叠区域的至少一个第五过孔H5与所述第一电容C1的第一极板C1a耦接。
在本公开至少一实施例中，所述第一电容连接晶体管T6的第二电极S6通过第三连接过孔H83与所述第一导电连接部L1耦接。
可选的，所述第一导电连接部L1可以为L形，但不以此为限。
在图10C中，仅示出了T5的栅极G5、T6的栅极G6、C1的第二极板C1b和第五导电连接部L5在基底上的正投影，以及，第一电压信号线VGH在基底上的正投影；
在图10C中，标示为X2的是所述第一电压信号线VGH在基底上的正投影的边缘线，标号为X5的是G5在基底上的正投影的边缘线，标号为X6的是G5在基底上的正投影的边缘线；
如图10C所示，标号为d3的是T5的栅极G5在基底上的正投影，与VGH在基底上的正投影之间，在第二方向上的最大距离；
标号为d4的是T6的栅极G6在基底上的正投影，与VGH在基底上的正投影之间，在第二方向上的最大距离。
在本公开至少一实施例中，如图1和图3所示，所述至少一个移位寄存器单元还可以包括第二晶体管T7；
如图3、图5、图7和图8所示，所述至少一个移位寄存器单元还包括与所述第二晶体管T7的栅极G7耦接的栅极连接导电部51，以及，与所述第一电容连接晶体管T6的第一电极S6耦接的第一电极连接导电部52；
所述栅极连接导电部与51与所述第一电极连接导电部52之间存在连接重叠区域；
所述栅极连接导电部51通过设置于所述连接重叠区域的电极连接过孔H05与所述第一电极连接导电部52耦接，以使得所述第二晶体管T7的栅极G7与所述第一电容连接晶体管T6的第一电极S6耦接。
在本公开至少一实施例中，所述第一电容连接晶体管T6的第一电极S6通过第四连接过孔H84与所述第一电极连接导电部52耦接；
所述第二晶体管T7的第二电极D7与所述第一导电连接部L1耦接。
具体的，如图3所示，所述第二电容连接晶体管T5的第一电极S5可以与所述第一电压信号线VGH耦接；
如图3和图10C所示，所述第一电容连接晶体管T6的栅极G6在基底上 的正投影与所述第一电压信号线VGH在基底上的正投影之间在第二方向上的最大距离d32，小于所述第二电容连接晶体管T5的栅极在基底上的正投影与所述第一电压信号线VGH在基底上的正投影之间在第二方向上的最大距离d31，也即T5设置于T6远离所述第一电压信号线VGH的一侧。
在本公开至少一实施例中，如图3、图4、图7和图8所示，所述第二电容连接晶体管T5的第一电极S5通过第五连接过孔H85与信号线导电连接部L40耦接，所述信号线导电连接部L40与所述第一电压信号线VGH耦接，以使得所述第二电容连接晶体管T5的第一电极S5与所述第一电压信号线VGH耦接。
可选的，所述信号线导电连接部L40可以为L形。
在本公开至少一实施例中，所述信号线导电连接部L40在基底上的正投影与所述第一电容C1的第一极板C1a在基底上的正投影部分重叠。
在优选情况下，如图5所示，所述第一电容连接晶体管T6的栅极G6与所述第二电容连接晶体管T5的栅极G5之间在第二方向上的最长距离小于第四预定距离；
如图3所示，所述第一电容C1的第一极板C1a在所述基底上的正投影在所述第一电容C1的第二极板C1b在所述基底上的正投影之内；
如图6所示，所述第一电容C1的第一极板C1a为L形。
在本公开至少一实施例中，将T5和T6设置为距离较近，以能够调整C1的极板的形状，将C1的第一极板C1a设置为L形，充分利用了T5的栅极和第二导电连接部之间的走线空间，以使得布局更加合理，有效收窄移位寄存器单元的横向宽度，并减小移位寄存器单元的纵向高度。
在本公开至少一实施例中，所述第四预定距离可以根据实际情况选定，例如，所述第四预定距离大于或等于20um(微米)而小于或等于30um。
在本公开至少一实施例中，所述第一电容连接晶体管T6的栅极G6与所述第二电容连接晶体管T5的栅极G5之间在第二方向上的最长距离指的是：G5的边缘线上的任一点与G6的边缘线在第二方向上的最大距离，如图10C所示，标示为d4的为G5的边缘线上的任一点与G6的边缘线在第二方向上 的最大距离。
在具体实施时，如图1所示，所述移位寄存器单元可以包括第一晶体管T8和第二晶体管T7；
如图9所示，在图6的基础上，所述第一电容C1的第一极板C1a包括第一水平极板部C1a1和第一竖直极板部C1a2；
如图3和图9所示，所述第二电容连接晶体管T5的栅极G5在所述基底上的正投影和所述第一水平极板部C1a1在所述基底上的正投影沿第一方向排列；
第一晶体管T8的栅极G8在所述基底上的正投影、第二晶体管T7的栅极G7在所述基底上的正投影和所述第一竖直极板部C1a2在所述基底上的正投影沿第一方向排列；
所述第一竖直极板部C1a2在所述基底上的正投影，位于所述第一电容连接晶体管T6的第二电极D6在所述基底上的正投影和所述第二电容连接晶体管T5的第一电极S5在所述基底上的正投影之间；
所述第二晶体管T7的第一电极S7与输出电容C3的第二极板C3b耦接。
在本公开至少一实施例中，利用T5和T6之间的空间，以及T5的栅极和第二导电连接部之间的空间设置C1，并将C1的极板设置为L形，以合理布局。
在本公开至少一实施例中，所述第二晶体管T7的第二电极D7通过第六连接过孔H86与所述第一导电连接部L1耦接，以使得所述第二晶体管T7的第二电极D7与所述第一电容连接晶体管T6的第二电极D6耦接。
可选的，如图1所示，所述至少一个移位寄存器单元还可以包括第一节点控制晶体管T2和第二电容C2；
如图5所示，所述第一节点控制晶体管T2的栅极包括的第一栅极图形G21和第二栅极图形G22分别与所述第二电容C2的第二极板C2b耦接；
如图3、图5和图6所示，所述第二电容C2的第一极板C2a在所述基底上的正投影在所述第二电容C2的第二极板C2b在所述基底上的正投影之内；
所述第二电容C2的第一极板C2a为L形；
如图9所示，在图6的基础上，所述第二电容C2的第一极板C2a包括第二水平极板部C2a1；
所述第一节点控制晶体管T2的栅极G2在所述基底上的正投影，与所述第二水平极板部C2a1在所述基底上的正投影沿第一方向排列。
在本公开至少一实施例中，将C2的极板设置为L形，利用第n级移位寄存器单元中的T2与第n+1级移位寄存器单元中的第二节点控制晶体管之间的空间放置C2的极板包括的水平极板部，以收窄移位寄存器单元的横向宽度。
在本公开至少一实施例中，如图3和图8所示，所述扫描驱动电路还包括第三电压信号线VGL2；所述第三电压信号线VGL2沿第一方向延伸；
所述第一节点控制晶体管T2位于所述第二电容连接晶体管T5远离所述第一电压信号线VGH的一侧；所述第一节点控制晶体管T2位于所述第三电压信号线VGL2与所述第一电压信号线VGH之间；
如图9所示，所述第二电容C2的第一极板C2a还包括与所述第二水平极板部C2a1耦接的第二竖直极板部C2a2；所述第二竖直极板部C2a2在所述基底上的正投影与所述第三电压信号线VGL2在所述基底上的正投影部分重叠。
具体的，C2的极板被设置为L形，C2的第二竖直极板部C2a2在所述基底上的正投影与所述第三电压信号线VGL2在所述基底上的正投影部分重叠，以减小移位寄存器单元的纵向高度。
如图3、图4和图9所示，T2的第二有源图形A2在基底上的正投影与所述第二水平极板部C2a1在所述基底上的正投影沿第一方向依次排列，利用第n级移位寄存器单元中的A2与第n+1级移位寄存器单元之间的空间设置C2的水平极板部。
如图1和图3所示，所述第一时钟信号线CB位于所述第三电压信号线VGL2远离所述第一电压信号线VGH的一侧；
所述输出电路包括输出晶体管T10；如图5所示，所述至少一个移位寄存器单元还包括设置于所述输出晶体管T10的栅极G10与所述第二电容C2的第二极板C2b之间的第二导电连接部L2；所述第二导电连接部L2分别与所述输出晶体管T10的栅极G10和所述第二电容C2的第二极板C2b耦接；
所述至少一个移位寄存器单元还包括与所述第二电容C2的第一极板C2a耦接的第三导电连接部L3；
如图3和图7所示，所述第三导电连接部L3在所述基底上的正投影与第一时钟信号线CB在所述基底上的正投影存在第六重叠区域，所述第一时钟信号线CB通过设置于所述第六重叠区域的至少一第六过孔H6与所述第二电容C2的第一极板C2a耦接。
可选的，所述第二导电连接部L2可以沿第二方向延伸，用于耦接所述输出晶体管T10的栅极G10和所述第二电容C2的第二极板C2b；
所述第三导电连接部L3可以沿第二方向延伸，所述第三导电连接部L3通过第六过孔H6与所述第二电容C2的第一极板C2a耦接。
具体的，如图3和图4所示，所述第一电容连接晶体管T6包括第一有源图形A1；所述第一有源图形A1沿第一方向延伸；
所述第一有源图形包括A1沿第一方向相对设置的第一个第一电容连接导电部分L111和第二个第一电容连接导电部分L112，以及位于所述第一个第一电容连接导电部分L111和第二个第一电容连接导电部分L112之间的第一电容连接沟道部分L12。
在本公开至少一实施例中，所述第一个第一电容连接导电部分L111用作所述第一电容连接晶体管T6的第一电极S6，所述第二个第一电容连接导电部分L112用作所述第一电容连接晶体管T6的第二电极D6。
可选的，T6的第一有源图形A1沿第一方向延伸，并T6设置于T5和VGH之间，以能够收窄移位寄存器单元的横向宽度。
在具体实施时，如图1和图3所示，所述至少一个移位寄存器单元可以包括第二晶体管T7；
所述第二晶体管T7的第二电极D7与所述第一导电连接部L1耦接。
如图3、图7和图8所示，所述第二晶体管T7的第二电极D7通过第六连接过孔H86与所述第一导电连接部L1耦接。
具体的，如图4所示，所述第一节点控制晶体管T2可以包括第二有源图形A2；所述第二有源图形A2可以为U形；
所述第二有源图形A2包括第一个第一节点控制沟道部分A211、第二个 第一节点控制沟道部分A212、第一个第一节点控制导电部分A221，以及，第二个第一节点控制导电部分A222；
如图5所示，所述第一节点控制晶体管T2的栅极包括相互耦接的第一栅极图形G21和第二栅极图形G22；
所述第一栅极图形G21与所述第一个第一节点控制沟道部分A211对应，所述第二栅极图形G22与所述第二个第一节点控制沟道部分A212对应；
如图3和图4所示，所述第一个第一节点控制导电部分A221用作所述第一节点控制晶体管T2的第二电极D2，所述第二个第一节点控制导电部分A222用作所述第一节点控制晶体管T2的第一电极S2。
如图3和图4所示，所述第一节点控制晶体管T2的有源图形设置为U形结构，以使得T2形成为双栅结构。双栅结构设计的目的在于：在第二阶段P2，扫描驱动电路包括的移位寄存器单元输出高电压信号Vgh时，T10应完全关闭，而T10的栅极接入的高电平由T5的源极输入。因此，在第二阶段P2，应务必保证T5打开，即需要使得第二节点N2的电位为低电压；而在第二阶段P2，T2栅极的电位为高电压，为保证T2不漏电造成第二节点N2电位升高，因此将T2设置为采用双栅设计，使得T2更容易关断。
由于在实际生产曝光中，如果将T2的有源图形设置为不带缺角的U字形，会在曝光后沉积金属，会使得该U字形的有源图形为V字形。因此，在实际产品中，考虑到实际生产曝光过程，U字形的有源图形内侧在两个直角部分挖了一小部分进行补偿，尽量使实际图案为U字形，不对T2的宽长比产生影响。
在本公开至少一实施例中，如图1和图3所示，所述至少一个移位寄存器单元还可以包括第二节点控制晶体管T3；所述至少一个移位寄存器单元包括第二电容连接晶体管T5；
如图4和图8所示，所述第二节点控制晶体管T3的第二电极D3与所述第一节点控制晶体管T2的第二电极D2之间通过第四导电连接部L4耦接；
如图3、图4、图5和图8所示，所述至少一个移位寄存器单元还包括与所述第二电容连接晶体管T5的栅极G5耦接的第五导电连接部L5；所述第五导电连接部L5在所述基底上的正投影与所述第四导电连接部L4在所述基底 上的正投影之间存在第七重叠区域；
所述第五导电连接部L5通过设置于所述第七重叠区域的第七过孔H7与所述第四导电连接部L4耦接。
在具体实施时，如图3、图4、图7和图8所示，所述第二节点控制晶体管T3的第二电极D3通过第七连接过孔H87与所述第四导电连接部L4耦接，所述第一节点控制晶体管T2的第二电极D2通过第八连接过孔H88与所述第四导电连接部L4耦接，以使得所述第二节点控制晶体管T3的第二电极D3与所述第一节点控制晶体管T2的第二电极D2耦接。
在本公开至少一实施例中，所述第四导电连接部L4可以沿第一方向延伸，以减小移位寄存器单元的横向宽度。
在具体实施时，如图1和图3所示，所述显示基板还可以包括第三电压信号线VGL2；所述第三电压信号线VGL2设置于所述第二节点控制晶体管T3远离所述第一电压信号线VGH的一侧；
如图3、图4和图5所示，所述第一节点控制晶体管T2的第一电极S2与第六导电连接部L6耦接；所述第二节点控制晶体管T3的栅极G3与第七导电连接部L7耦接；
所述第六导电连接部L6在所述基底上的正投影与所述第七导电连接部L7在所述基底上的正投影之间存在第八重叠区域，所述第六导电连接部L6通过设置于所述第八重叠区域之内的第八过孔H8与所述第七导电连接部L7耦接；
所述第二节点控制晶体管T3的第一电极S3与所述第三电压信号线VGL2耦接。
如图3和图7所示，所述第一节点控制晶体管T2的第一电极S2通过第九连接过孔H89与所述第六导电连接部L6耦接，所述第六导电连接部L6可以沿第一方向延伸，以收窄移位寄存器单元的横向宽度。
如图5所示，所述第二节点控制晶体管T3的栅极G3与第七导连接部L7耦接，第六导电连接部L6通过设置于第八重叠区域的第八过孔H8与第七导电连接部L7耦接，以使得所述第一节点控制晶体管T2的第一电极S2与所述第二节点控制晶体管T3的栅极G3耦接。
如图4所示，所述第二节点控制晶体管T3包括第三有源图形A3，所述第三有源图形包括沿第一方向依次排列的第一控制导电部分A311、控制沟道部分A32和第二控制导电部分A312；
所述第一控制导电部分A311用作T3的第一电极S3，所述第二控制导电部分A312用作T3的第二电极D3。
如图5所示，所述第二节点控制晶体管T3的栅极G3还与第八导电连接部L8耦接；如图3所示，所述第八导电连接部L8在所述基底上的正投影与所述第二时钟信号线CK在所述基底上的正投影之前存在第九重叠区域，如图7所示，所述第八导电连接部L8通过设置于所述第九重叠区域的第九过孔H9与所述第二时钟信号线CK耦接。
由于T3的栅极与第二时钟信号线CK耦接，因此可以将T3的栅极设置为与第二时钟信号线CK距离较近，以合理布局。
具体的，如图1和图3所示，所述扫描驱动电路可以包括第一时钟信号线CB和第三电压信号线VGL2；所述第一时钟信号线CB和所述第三电压信号线VGL2沿第一方向延伸；
所述第二时钟信号线CK设置于所述第一时钟信号线CB与所述第三电压信号线VGL2之间。
可选的，第一时钟信号线也可以设置于所述第二时钟信号线与所述第三电压信号线之间。
在具体实施时，如图1和图3所示，所述至少一个移位寄存器单元还可以包括输入晶体管T1；
如图5所示，所述输入晶体管T1的栅极G1与所述第七导电连接部L7耦接；如图3所示，所述输入晶体管T1的第一电极S1与输入信号端E1耦接；
所述输入晶体管T1的第二电极D1与第九导电连接部L9耦接，所述第九导电连接部L9在所述基底上的正投影与所述第二电容C2的第二极板C2b在所述基底上的正投影之间存在第十重叠区域，所述第九导电连接部L9通过设置于所述第十重叠区域的第十过孔H10与所述第二电容C2的第二极板C2b耦接。
如图3、图4、图6、图7和图8所示，所述输入晶体管T1的第一电极S1通过第九连接过孔H89与输入导电连接部L70耦接，所述输入导电连接部L70通过第十连接过孔H810与所述输入信号端E1耦接，以使得所述输入晶体管T1的第一电极S1与输入信号端E1耦接；
如图3、图4、图6、图7和图8所示，所述输入晶体管T1的第二电极D1与第九导电连接部L9耦接，所述第九导电连接部L9通过设置于所述第十重叠区域的第十过孔H10与所述第二电容C2的第二极板C2b耦接，以使得所述输入晶体管T1的第二电极D1与所述第二电容C2的第二极板C2b耦接；
在本公开至少一实施例中，第九导电连接部L9可以沿第一方向延伸，以收窄移位寄存器单元的横向宽度。
在本公开至少一实施例中，如图1和图3所示，所述至少一个移位寄存器单元还可以包括第三节点控制晶体管T4；
如图5所示，所述第三节点控制晶体管T4的栅极G4与第十导电连接部L10耦接；
如图3和图7所示，所述第十导电连接部L10在所述基底上的正投影与第一时钟信号线CB在所述基底上的正投影之间存在第十一重叠区域，所述第十导电连接部L10通过设置于所述第十一重叠区域的第十一过孔H11与所述第一时钟信号线CB耦接。
可选的，所述第十导电连接部L10可以沿第二方向排列，但不以此为限。
具体的，如图1和图3所示，所述至少一个移位寄存器包括第二晶体管T7；
如图5所示，所述第三节点控制晶体管T4的栅极G4与所述第二晶体管T7的栅极G7耦接。
由于T4的栅极G4和T7的栅极G7之间需要耦接，因此在布局时，可以将T4和T7设置为相互距离较近。
在本公开至少一实施例中，如图1和图3所示，所述至少一个移位寄存器单元可以包括第二电容连接晶体管T5；
如图4所示，所述输入晶体管T1的有源层、所述第三节点控制晶体管T4的有源层和所述第二电容连接晶体管T5的有源层可以由一个连续的第三 半导体层30形成；
所述输入晶体管T1的有源层包括沿第一方向依次设置的第一个第五导电部分311、第五沟道部分32和第二个第五导电部分312；
所述第二个第五导电部分312复用为第一个第六导电部分；
所述第三节点控制晶体管T4的有源层包括沿第一方向依次设置的第一个第六导电部分、第六沟道部分34和第二个第六导电部分332；
所述第二个第六导电部分332复用为第一个第七导电部分；
所述第二电容连接晶体管T5的有源层包括沿第一方向依次设置的第一个第七导电部分、第七沟道部分36和第二个第七导电部分352。
在本公开至少一实施例中，如图3和图4所示，所述第一个第五导电部分311用作输入晶体管T1的第一电极S1，所述第二个第五导电部分312用作输入晶体管T1的第二电极D1，所述第二个第六导电部分332用作所述第三节点控制晶体管T4的第一电极S4，所述第二个第七导电部分352用作所述第二电容连接晶体管T5的第一电极S5；
并且，如图3所示，输入晶体管T1的第二电极D1复用为所述第三节点控制晶体管T4的第二电极D4，所述第三节点控制晶体管T4的第一电极S4复用为所述第二电容连接晶体管T5的第二电极D5。也即，在本公开至少一实施例所述的显示基板中，在输入晶体管T1、所述第三节点控制晶体管T4和所述第二电容连接晶体管T5中，相邻的晶体管之间能够通过第三半导体层30包括的导电部分直接耦接，缩小了T1、T4和T5在第一方向上占用的面积。
具体的，所述扫描驱动电路还可以包括第三电压信号线；
所述第三电压信号线、所述第一时钟信号线和所述第二时钟信号线都沿第一方向延伸；
所述第三电压信号线在所述基底上的正投影、所述第一时钟信号线在所述基底上的正投影和所述第二时钟信号线在所述基底上的正投影，都位于所述移位寄存器单元在所述基底上的正投影远离所述显示基板的显示区域的一侧；
所述信号输出线沿着第二方向延伸，所述第一方向与所述第二方向相交。
具体地，所述第一时钟信号线、所述第二时钟信号线和所述第三电压信 号线的具体位置可根据实际需要设置，示例性的，可将所述第一时钟信号线、所述第二时钟信号线和所述第三电压信号线均设置在所述显示基板的边缘处，即使得所述第三电压信号线在所述基底上的正投影、所述第一时钟信号线在所述基底上的正投影和所述第二时钟信号线在所述基底上的正投影，都位于所述移位寄存器单元在所述基底上的正投影远离所述显示基板的显示区域的一侧，这样在布局所述移位寄存器单元时，能够避免所述移位寄存器单元中的各晶体管与所述第一时钟信号线、所述第二时钟信号线和所述第三电压信号线产生过多的交叠，从而更有利于提升所述移位寄存器单元的工作性能。
另外，通过设置所述第一时钟信号线、所述第二时钟信号线和所述第三电压信号线均沿所述第一方向延伸，更有利于所述显示基板实现窄边框化。
在具体实施时，所述第一时钟信号线输出的第一时钟信号和所述第二时钟信号线输出的第二时钟信号的相位可以相反，但不以此为限。
在具体实施时，如图1和图3所示，所述扫描驱动电路可以包括第一电压信号线VGH、第二电压信号线VGL1、第三电压信号线VGL2、第一时钟信号线CB、和第二时钟信号线CK；所述至少一个移位寄存器单元还可以包括信号输出线EOUT、输出电容C3、第一电容C1、第二电容C2、输出复位晶体管T9、输出晶体管T10、第一晶体管T8、第二晶体管T7、第一电容连接晶体管T6、第二电容连接晶体管T5、第一节点控制晶体管T2、第二节点控制晶体管T3、输入晶体管T1、第三节点控制晶体管T4；
所述输出复位晶体管T9和所述输出晶体管T10沿着第一方向排列；
所述输出复位晶体管T9的第一电极S9与所述第一电压信号线VGH耦接，所述输出晶体管T10的第一电极S10与所述第二电压信号线VGL1耦接；
所述输出晶体管T10和所述信号输出线EOUT沿着第一方向排列，所述输出复位晶体管T9的第二电极D9和所述输出晶体管T10的第二电极D10都与所述信号输出线EOUT耦接；
所述信号输出线EOUT沿着第二方向延伸，所述第一方向与所述第二方向相交；
所述第一晶体管T8的第二电极D8与所述输出电容C3的第二极板C3b耦接，所述第一晶体管T8的第一电极S8与所述第一电压信号线VGH耦接， 所述第一晶体管T8的栅极G8与所述第三节点控制晶体管T4的第二电极D4耦接；
所述第二晶体管T7的第二电极D7与所述第一电容C1的第一极板C1a耦接，所述第二晶体管T7的第一电极S7与输出电容C3的第二极板C3b耦接，所述第二晶体管T7的栅极G7与所述第三节点控制晶体管T4的栅极G4耦接；
所述第一电容连接晶体管T6的栅极G6和所述第二电容连接晶体管T5的栅极G5分别与所述第一电容C1的第二极板C1b耦接；所述第一电容连接晶体管T6的第二电极D6与所述第一电容C1的第一极板C1a耦接；所述第一电容连接晶体管T6的第一电极S6与第二晶体管T7的栅极G7耦接；
所述第二电容连接晶体管T5的第一电极S5与所述第一电压信号线VGH耦接；所述第二电容连接晶体管T5的栅极G5与所述第二节点控制晶体管T3的第二电极D3耦接；所述第二电容连接晶体管T5的第二电极D5与所述第三节点控制晶体管T4的第一电极S4耦接；
所述第一节点控制晶体管T2的第一电极S2与所述第二节点控制晶体管T3的栅极G3耦接；所述第一节点控制晶体管T2的栅极G2与所述第二电容C2的第二极板C2b耦接；
所述第二节点控制晶体管T3的第二电极D3与所述第一节点控制晶体管T2的第二电极D2耦接；所述第二节点控制晶体管T3的栅极G3与所述第二时钟信号线CK耦接；所述第二节点控制晶体管T3的第一电极S3与所述第三电压信号线VGL2耦接；
所述输入晶体管T1的栅极G1与所述第二节点控制晶体管T3的栅极G3耦接；所述输入晶体管T1的第一电极S1与输入信号端E1耦接；所述输入晶体管T1的第二电极D1与所述第二电容C2的第二极板C2b耦接；
所述第三节点控制晶体管T4的栅极G4与所述第一时钟信号线CB耦接；
所述输出电容C3的第一极板C3a与所述第一电压信号线VGH耦接，所述输出电容C3的第二极板C3b与所述输出复位晶体管T9的栅极G9耦接；
所述第二电容C2的第二极板C2b与所述输出晶体管T10的栅极G10耦接，所述第二电容C2的第一极板C2a与所述第一时钟信号线CB耦接；
所述输出复位晶体管T9的第二电极D9和所述输出晶体管T10的第二电极D10都与所述信号输出线EOUT耦接。
在本公开至少一实施例中，沿靠近所述显示区域的方向，所述第一时钟信号线、所述第二时钟信号线和所述第三电压信号线依次排列；或者，沿靠近所述显示区域的方向，所述第二时钟信号线、所述第一时钟信号线和所述第三电压信号线依次排列。
如图9所示，在图6的基础上，所述第一电容C1的第一极板C1a可以包括第一水平极板部C1a1和第一竖直极板部C1a2；
如图3所示，所述输出复位晶体管T9和所述输出晶体管T10设置于所述第一电压信号线VGH和所述第二电压信号线VGL1之间；沿着所述第一方向，所述输出复位晶体管T9、所述输出晶体管T10和所述信号输出线EOUT依次排列；
所述第三电压信号线VGL2设置于所述第一电压信号线VGH远离所述第二电压信号线VGL1的一侧；所述第一电容C1、所述第一晶体管T8、第二晶体管T7、第一电容连接晶体管T6、第二电容连接晶体管T5、第一节点控制晶体管T2、第二节点控制晶体管T3、输入晶体管T1和第三节点控制晶体管T4都设置于所述第一电压信号线VGH和所述第三电压信号线VGL2之间；
所述第一晶体管T8、所述第二晶体管T7和所述第一竖直极板部C1a2沿着第一方向依次排列，所述输入晶体管T1、所述第三节点控制晶体管T4、所述第二电容连接晶体管T5和所述第一水平极板部C1a1沿着第一方向依次排列，所述第二节点控制晶体管T3和所述第一节点控制晶体管T2沿着第一方向依次排列；
所述第一电容连接晶体管T6的栅极G6在所述基底上的正投影设置于所述第一电容C1的第二极板C1b在所述基底上的正投影与所述第一电压信号线VGH在所述基底上的正投影之间；
所述第二晶体管T7的栅极G7在所述基底上的正投影设置于所述第三节点控制晶体管T4的栅极G4在所述基底上的正投影与所述第一电压信号线VGH在所述基底上的正投影之间；
所述第一节点控制晶体管T2的栅极G2在所述基底上的正投影设置于所述第三电压信号线VGL2在所述基底上的正投影与所述第一电容C1的第一极板C1a在所述基底上的正投影之间；
所述第一节点控制晶体管T2的栅极G2在所述基底上的正投影与所述第三电压信号线VGL2在所述基底上的正投影在第二方向上的最小距离，大于所述第二电容连接晶体管T5的栅极G5在所述基底上的正投影与所述第三电压信号线VGL2在所述基底上的正投影在第二方向上的最小距离。
在本公开图3所示的布局方式中，由于输出复位晶体管T9与第一电压信号线VGH耦接，输出晶体管T10与第二电压信号线VGL1耦接，因此将输出复位晶体管T9和输出晶体管T10设置于第一电压信号线VGH和第二电压信号线VGL1之间，并充分利用第n级移位寄存器单元中的T10与第n+1级移位寄存器单元中的输出复位晶体管之间的空间，以设置信号输出线EOUT，以使得第一电压信号线VGH设置于输出电路O1远离显示区域的一侧，并所述第一电压信号线VGH与输出电路O1之间未设置其他信号线和其他晶体管包括的部件，所述第二电压信号线VGL1设置于输出电路O1靠近显示区域的一侧，所述第二电压信号线VGL1与所述输出电路O1之间未设置其他信号线和其他晶体管包括的部件，收窄VGH到T9和T10的距离，并收窄VGL1到T9和T10的距离，使得移位寄存器单元的横向宽度得到缩减。
在本公开图3所示的布局方式中，将T8移至第一电压信号线VGH远离第二电压信号线VGL1的一侧，并将输出电容C3的极板在基底上的正投影设置为与第一电压信号线VGH在基底上的正投影部分重叠，以缩减第一晶体管T8的第一电极S8与第一电压信号线VGH之间的距离，缩减第一晶体管T8的第二电极D8与所述输出电容C3的第二极板C3b之间的距离，使得T8可以方便的分别耦接至第一电压信号线VGH和输出电容C3的第二极板C3b，使得空间紧凑，布局更为合理。
在本公开图3所示的布局方式中,将T5和T6设置为距离较近，以能够调整C1的极板的形状，将C1的第一极板C1a设置为L形，充分利用了T5的栅极与第二导电连接部之间的走线空间，以使得布局更加合理，有效收窄移位寄存器单元的横向宽度，并减小移位寄存器单元的纵向高度。
在本公开至少一实施例中，所述第一节点控制晶体管T2的栅极G2在所述基底上的正投影与所述第三电压信号线VGL2在所述基底上的正投影在第二方向上的最小距离指的是：G2在基底上的正投影的边缘线上的任一点，与VGL2在基底上的正投影的边缘线，在第二方向上的最小距离；
所述第二电容连接晶体管T5的栅极G5在所述基底上的正投影与所述第三电压信号线VGL2在第二方向上在所述基底上的正投影的最小距离指的是：G5在基底上的正投影的边缘线上的任一点，与VGL2在基底上的正投影的边缘线，在第二方向上的最小距离。在具体实施时，所述输出电容C3的第一极板C3a在所述基底上的正投影，与所述第一电压信号线VGH在所述基底上的正投影存在信号线重叠区域；所述输出电容C3的第二极板C3b与所述基底上的正投影与所述第一电压信号线VGH在所述基底上的正投影部分重叠；
所述第二电容C2的第一极板C2a在所述基底上的正投影在所述第二电容C2的第二极板C2b在所述基底上的正投影之内；所述第二电容C2的第一极板C2a为L形；
如图9所示，所述第二电容C2的第一极板C2a包括第二水平极板部C2a1和第二竖直极板部C2a2；
所述第一节点控制晶体管T2的栅极G2与所述第二水平极板部C2a1沿第一方向排列；
所述第二竖直极板部C2a2在所述基底上的正投影与所述第三电压信号线VGL2在所述基底上的正投影部分重叠。
在本公开图3所示的布局方式中,将C2的极板设置为L形，利用第n级移位寄存器单元中的T2与第n+1级移位寄存器单元之间的空间放置C2的极板包括的水平极板部，以收窄移位寄存器单元的横向宽度。
在本公开至少一实施例中，在如图4所示的半导体层和如图5所示的第一栅金属层之间，还可以设置有第一栅绝缘层；在如图5所示的第一栅金属层和如图6所示的的第二栅金属层之间，还可以设置有第二栅绝缘层；在如图6所示的第二栅金属层和如图8所示的源漏金属层之间还可以包括一层绝缘层。
并在制作本公开至少一实施例所述的显示基板时，首先在基底上设置半 导体材料层，对所述半导体材料层进行构图工艺，以形成各晶体管的有源层；如图4所示，形成了第一半导体层10、第二半导体层20、第三半导体层30、所述第一电容连接晶体管T6包括第一有源图形A1、第一节点控制晶体管T2的第二有源图形A2和所述第二节点控制晶体管T3包括第三有源图形A3；
在所述有源层背向所述基底的一面制作第一栅绝缘层；
在所述第一栅绝缘层背向所述有源层的一面，制作第一栅金属层，对第一栅金属层进行构图工艺，如图5所示，形成移位寄存器单元包括的各晶体管的栅极、输出电容C3的第二极板、第一电容C1的第二极板和第二电容C2的第二极板；
以所述各晶体管的栅极为掩膜，对有源层中未被所述栅极覆盖的部分进行掺杂，使得所述有源层中未被所述栅极覆盖的部分形成为导电部分，所述有源层中被所述栅极覆盖的部分形成为沟道部分；所述导电部分用作第一电极或第二电极；或者，所述导电部分与第一电极或第二电极耦接；
在所述第一栅金属层背向所述第一栅金属层的一面设置第二栅绝缘层；
在所述第二栅绝缘层背向所述第一栅金属层的一面设置第二栅金属层，对所述第二栅金属层进行构图工艺，如图6所示，形成信号输出线EOUT、输入信号端R1、输出电容C3的第一极板、第一电容C1的第一极板和第二电容C2的第一极板；
在所述第二栅金属层背向所述第二栅绝缘层的一面设置绝缘层；
如图7所示，在设置了有源层、第一栅绝缘层、第一栅金属层、第二栅绝缘层、第二栅金属层和绝缘层的基底上，设置多个过孔；
在所述绝缘层背向所述第二栅金属层的一面设置源漏金属层，对所述源漏金属层进行构图工艺，如图8所示，形成第一电压信号线VGH、第二电压信号线VGL1、第三电压信号线VGL2、第一时钟信号线CB、第二时钟信号线CB、起始信号线ESTV、所述输出复位晶体管T9的第二电极、所述输出复位晶体管T9的第一电极S9、所述输出晶体管T10的第二电极D10、所述输出晶体管T10的第一电极S10。
本公开至少一实施例所述的显示基板的制作方法包括在基底上制作扫描驱动电路，并在显示基板包括的显示区域制作至少一个驱动晶体管；所述驱 动晶体管被配置为驱动发光元件进行显示；
所述扫描驱动电路包括多个移位寄存器单元、第一电压信号线、第二电压信号线、第一时钟信号线和第二时钟信号线，所述多个移位寄存器单元中的至少一个移位寄存器单元包括输出电路和信号输出线；
所述显示基板的制作方法还包括：
在所述第一电压信号线和所述第二电压信号线之间制作所述输出电路包括的晶体管；
将所述第一电压信号线、所述第二电压信号线、所述第一时钟信号线和所述第二时钟信号线设置为沿着第一方向延伸，将信号输出线设置为沿着第二方向延伸；
所述第一方向和所述第二方向相交。
在本公开至少一实施例所述的显示基板的制作方法中，将输出电路设置于第一电压信号线和第二电压信号线之间，使得在空间结构上，第一电压信号线设置于输出电路远离显示区域的一侧，并所述第一电压信号线与输出电路之间未设置其他信号线和其他晶体管包括的部件，所述第二电压信号线设置于输出电路靠近显示区域的一侧，所述第二电压信号线与所述输出电路之间未设置其他信号线和其他晶体管包括的部件，可以收窄第一电压信号线到输出电路的距离，并收窄第二电压信号线到输出电路的距离，使得移位寄存器单元的横向宽度得到缩减。
在本公开至少一实施例中，所述第一电压信号线可以位于所述第二电压信号线远离显示区域的一侧。
可选的，本公开至少一实施例所述的显示基板的制作方法还可以包括：将所述信号输出线设置于相邻的移位寄存器单元中的输出电路之间。
在具体实施时，所述输出电路与所述信号输出线耦接，则所述输出电路应与所述信号输出线距离较近，本公开至少一实施例将信号输出线下移至相邻的移位寄存器单元中的输出电路之间，收窄移位寄存器单元的横向宽度。
可选的，所述输出电路可以包括输出晶体管和输出复位晶体管，制作所述输出电路包括的晶体管的步骤具体包括：
在所述第一电压信号线和所述第二电压信号线之间形成沿第一方向延伸 的第一半导体层；
在所述第一半导体层背向所述基底上的一面，制作第一栅金属层，对所述第一栅金属层进行构图工艺，以形成所述输出晶体管的栅极和所述输出复位晶体管的栅极；
以所述输出晶体管的栅极和所述输出复位晶体管的栅极为掩膜，对第一半导体层中未被所述栅极覆盖的部分进行掺杂，使得所述第一半导体层中未被所述栅极覆盖的部分形成为导电部分，所述第一半导体层中被所述栅极覆盖的部分形成为沟道部分。
在具体实施时，所述输出晶体管的有源层和所述输出复位晶体管的有源层可以由一个连续的第一半导体层形成，但不以此为限。
在本公开至少一实施例中，所述输出晶体管的有源层和所述输出复位晶体管的有源层可以由一个连续的第一半导体层形成，所述第一半导体层沿第一方向延伸；所述输出复位晶体管的有源层包括沿第一方向相对设置的至少一个第一导电部分，以及至少一个第一沟道部分；每一所述第一沟道部分设置于两相邻的第一导电部分之间；所述输出晶体管的有源层可以包括沿第一方向相对设置的至少两个第二导电部分，以及至少一个第二沟道部分；每一所述第二沟道部分设置于两相邻的所述第二导电部分之间；所述输出复位晶体管的有源层中与所述输出晶体管的有源层距离最近的第一导电部分可以复用为所述输出晶体管中的第二导电部分，这样能够进一步缩小所述输出晶体管和输出复位晶体管的布局空间，有利于实现所述显示基板的窄边框化。
在具体实施时，所述显示基板的制作方法还可以包括：在所述第一栅极金属层背向所述第一半导体层的一面设置第二栅金属层，对所述第二栅金属层进行构图工艺，以形成沿第二方向延伸的信号输出线；
所述第一半导体层在所述基底上的正投影和所述信号输出线在所述基底上的正投影沿着第一方向排列，所述第一方向与所述第二方向相交。
在本公开至少一实施例中，所述第一半导体层在所述基底上的正投影和所述信号输出线在所述基底上的正投影沿着第一方向排列，可以收窄移位寄存器单元的横向宽度。
在本公开至少一实施例中，制作第一电压信号线、第二电压信号线、第 一时钟信号线和第二时钟信号线的步骤可以具体包括：
在所述第二栅金属层背向所述第一栅金属层的一面制作源漏金属层，对所述源漏金属层进行构图工艺，以形成所述第一电压信号线、所述第二电压信号线、第一时钟信号线和第二时钟信号线。
可选的，所述至少一个移位寄存器单元还可以包括输出电容和第一晶体管；所述显示基板的制作方法还可以包括：
制作所述输出电容，在所述第一电压信号线远离所述第二电压信号线的一侧形成第一晶体管，使得所述第一晶体管的第一电极与所述第一电压信号线耦接，所述第一晶体管的第二电极与所述输出电容的一极板耦接。
在优选情况下，所述第一晶体管的第一电极在基底上的正投影与所述第一电压信号线在基底上的正投影之间在第二方向上的最大距离小于第一预定距离，所述第一晶体管的第二电极在所述基底上的正投影与所述输出电容的所述极板在所述基底上的正投影之间在第二方向上的最大距离小于第二预定距离。
在本公开至少一实施例中，由于第一晶体管的第一电极与第一电压信号线耦接，所述第一晶体管的第二电极与输出电容的第二极板耦接，因此，在制作显示基板时，第一晶体管距离第一电压信号线和输出电容越近，相应布局就会更合理。本公开至少一实施例将第一晶体管设置于第一电压信号线远离所述第二电压信号线的一侧形成第一晶体管的一侧，并将所述第一晶体管的第一电极在基底上的正投影与所述第一电压信号线在基底上的正投影之间在第二方向上的的最大距离小于第一预定距离，所述第一晶体管的第二电极在所述基底上的正投影与所述输出电容的所述极板在所述基底上的正投影之间在第二方向上的最大距离小于第二预定距离，以合理布局。
可选的，所述至少一个移位寄存器单元还可以包括第二晶体管，制作所述第一晶体管和所述第二晶体管的步骤具体包括：
在所述第一电压信号线远离所述第二电压信号线的一侧形成沿第一方向延伸的第二半导体层；
在所述第二半导体层背向所述基底上的一面，制作第一栅金属层，对所述第一栅金属层进行构图工艺，以形成所述第一晶体管的栅极和所述第二晶 体管的栅极；
以所述第一晶体管的栅极和所述第二晶体管的栅极为掩膜，对第二半导体层中未被所述栅极覆盖的部分进行掺杂，使得所述第二半导体层中未被所述栅极覆盖的部分形成为导电部分，所述第二半导体层中被所述栅极覆盖的部分形成为沟道部分；
所述第二半导体层包括沿第一方向依次排列的第三导电部分、第三沟道部分、第二个第三导电部分、第四沟道部分和第二个第四导电部分；
所述第二个第三导电部分复用为第一个第四导电部分；
所述第一个第三导电部分用作所述第一晶体管的第一电极，所述第二个第三导电部分用作所述第一晶体管的第二电极；第二个第四导电部分用作所述第二晶体管的第二电极。
在具体实施时，所述输出电容的与所述第一晶体管的第二电极耦接的极板可以为所述输出电容的第二极板；制作所述输出电容的具体步骤包括：
对所述第一栅金属层进行构图工艺，以形成所述输出电容的第二极板；
在所述第一栅金属层背向所述第二半导体层的一面制作第二栅金属层，对所述第二栅金属层进行构图工艺，以形成所述输出电容的第一极板；
在所述第二栅金属层背向所述第一栅金属层的一面制作源漏金属层，对所述源漏金属层进行构图工艺，以形成极板导电连接部、所述第一电压信号线和所述第二电压信号线；
所述输出电容的第一极板在所述基底上的正投影，与所述第一电压信号线在所述基底上的正投影存在信号线重叠区域，所述输出电容的第一极板通过设置在所述信号线重叠区域的至少一个信号线过孔与所述第一电压信号线耦接；
所述极板导电连接部在所述基底上的正投影，与所述输出电容的第二极板在所述基底上的正投影存在极板重叠区域，所述极板导电连接部通过设置于所述极板重叠区域的至少一个极板过孔与所述输出电容的第二极板耦接。
在本公开至少一实施例中，所述第一晶体管的有源层和所述第二晶体管的有源层可以由一个连续的第二半导体层形成；所述第二半导体层沿第一方向延伸；所述第一晶体管的有源层包括沿第一方向依次设置的第一个第三导 电部分、第三沟道部分和第二个第三导电部分；所述第二个第三导电部分复用为第一个第四导电部分；所述第二晶体管的有源层包括沿第一方向依次设置的所述第一个第四导电部分、第四沟道部分和第二个第四导电部分；所述第一个第三导电部分用作所述第一晶体管的第一电极，所述第二个第三导电部分用作所述第一晶体管的第二电极；第二个第四导电部分用作所述第二晶体管的第二电极。在本公开至少一实施例中，第二晶体管设置于第一晶体管与第一电容之间，并第一晶体管的第二电极复用为第二晶体管的第二电极，以在收窄移位寄存器单元的横向宽度的同时，减小移位寄存器单元的纵向高度。
可选的，所述至少一个移位寄存器单元还可以包括第一电容，以及，与所述第一电容的第二极板耦接的至少两个晶体管；所述显示基板的制作方法还可以包括：
在所述第一电压信号线远离所述第二电压信号线的一侧，制作所述第一电容和所述至少两个晶体管；
所述至少两个晶体管的栅极在基底上的正投影与所述第一电压信号线在基底上的正投影之间在第二方向上的最大距离小于第三预定距离。
在具体实施时，由于与所述第一电容的第二极板耦接的晶体管也与第一电压信号线耦接，因此与所述第一电容的第二极板耦接的晶体管的位置以靠近第一电压信号线为宜，本公开至少一实施例将所述与所述第一电容的第二极板耦接的晶体管的栅极在基底上的正投影与所述第一电压信号线在基底上的正投影之间在第二方向上的最大距离设置为小于第三预定距离，以收窄移位寄存器单元的横向宽度。
在具体实施时，所述至少两个晶体管包括第一电容连接晶体管和第二电容连接晶体管；
制作所述第一电容连接晶体管和所述第二电容连接晶体管的具体步骤包括：
在所述基底上形成所述第一电容连接晶体管的有源层和所述第二电容连接晶体管的有源层；
在所述有源层背向所述基底的一面制作第一栅金属层，对所述第一栅金 属层进行构图工艺，以形成所述第一电容连接晶体管的栅极、所述第二电容连接晶体管的栅极和所述第一电容的第二极板，并使得所述第一电容连接晶体管的栅极和所述第二电容连接晶体管的栅极分别与所述第一电容的第二极板耦接；
以所述第一电容连接晶体管的栅极和所述第二电容连接晶体管的栅极为掩膜，对所述有源层中未被所述栅极覆盖的部分进行掺杂，使得所述有源层中未被所述栅极覆盖的部分形成为导电部分，所述有源层中被所述栅极覆盖的部分形成为沟道部分；所述第一电容连接晶体管的有源层包括沿第一方向依次设置的第一个第一电容连接导电部分、第一电容连接沟道部分和第二个第一电容连接导电部分；所述第二电容连接晶体管的有源层包括沿第一方向依次设置的第一个第七导电部分、第七沟道部分和第二个第七导电部分；所述第一个第一电容连接导电部分用作所述第一电容连接晶体管的第一电极，所述第二个第一电容连接导电部分用作所述第一电容连接晶体管的第二电极；
在所述第一栅金属层背向所述有源层的一面制作第二栅金属层，对所述第二栅金属层进行构图工艺，以形成所述第一电容的第一极板；
在所述第二栅金属层背向所述第一栅金属层的一面制作源漏金属层，对所述源漏金属层进行构图工艺，以形成所述第一电压信号线、所述第二电压信号线和第一导电连接部；
所述第一导电连接部在所述基底上的正投影与所述第一电容的第一极板在所述基底上的正投影之间存在第五重叠区域，所述第一导电连接部通过设置于所述第五重叠区域的至少一个第五过孔与所述第一电容的第一极板耦接。
在本公开至少一实施例中，所述第一个第七导电部分可以用作所述第二电容连接晶体管的第二电极，所述第二个第七导电部分可以用作所述第二电容连接晶体管的第一电极，所述第二电容连接晶体管的第一电极与所述第一电压信号线耦接；
所述第一电容连接晶体管的栅极在基底上的正投影与所述第一电压信号线在基底上的正投影之间在第二方向上的距离，小于所述第二电容连接晶体管的栅极在基底上的正投影与所述第一电压信号线在基底上的正投影之间在第二方向上的距离。
在具体实施时，所述第一电容连接晶体管的栅极在基底上的正投影与所述第一电压信号线在基底上的正投影之间在第二方向上的距离，小于所述第二电容连接晶体管的栅极在基底上的正投影与所述第一电压信号线在基底上的正投影之间在第二方向上的距离，也即第二电容连接晶体管设置于第一电容连接晶体管远离所述第一电压信号线的一侧。
在优选情况下，所述第一电容连接晶体管的栅极与所述第二电容连接晶体管的栅极之间在第二方向上的最长距离小于第四预定距离；
所述第一电容的第一极板在所述基底上的正投影在所述第一电容的第二极板在所述基底上的正投影之内；
所述第一电容的第一极板为L形。
在本公开至少一实施例中，将第一电容连接晶体管和第二电容连接晶体管设置为距离较近，以能够调整第一电容的极板的形状，将第一电容的第一极板设置为L形，充分利用了第二电容连接晶体管的栅极与第二导电连接部之间的走线空间，以使得布局更加合理，有效收窄移位寄存器单元的横向宽度，并减小移位寄存器单元的纵向高度。
可选的，所述至少一个移位寄存器单元还可以包括第一节点控制晶体管和第二电容；
制作所述第一节点控制晶体管和所述第二电容的步骤可以包括：
在所述基底上形成所述第一电容连接晶体管的有源层和所述第二电容连接晶体管的有源层的同时，在所述基底上形成所述第一节点控制晶体管的有源层；
对所述第一栅金属层进行构图工艺，以形成所述第一节点控制晶体管的栅极与所述第二电容的第二极板，并使得所述第一节点控制晶体管的栅极与所述第二电容的第二极板耦接；
以所述第一节点控制晶体管的栅极为掩膜，对所述第一节点控制晶体管的有源层中未被所述所述第一节点控制晶体管的栅极覆盖的部分进行掺杂；
对所述第二栅金属层进行构图工艺，以形成所述第二电容的第一极板，并使得所述第二电容的第一极板在所述基底上的正投影在所述第二电容的第二极板在所述基底上的正投影之内；所述第二电容的第一极板为L形；
所述第二电容的第一极板包括第二水平极板部；所述第一节点控制晶体管的栅极在所述基底上的正投影与所述第二水平极板部在所述基底上的正投影沿第一方向排列。
在本公开至少一实施例中，将第二电容的第一极板设置为L形，利用第一节点控制晶体管与相邻下一级移位寄存器单元之间的空间放置第二电容的第一极板包括的水平极板部，以收窄移位寄存器单元的横向宽度。
可选的，本公开至少一实施例所述的显示基板的制作方法还可以包括：
对所述源漏金属层进行构图工艺，以形成沿第一方向延伸的第三电压信号线；
所述第一节点控制晶体管位于所述第二电容连接晶体管远离所述第一电压信号线的一侧；所述第一节点控制晶体管位于所述第三电压信号线与所述第一电压信号线之间；
所述第二电容的第一极板还包括与所述第二水平极板部耦接的第二竖直极板部；所述第二竖直极板部在所述基底上的正投影与所述第三电压信号线在所述基底上的正投影部分重叠。
具体的，第二电容的第一极板被设置为L形，第二电容的第二竖直极板部在所述基底上的正投影与所述第三电压信号线在所述基底上的正投影部分重叠，以减小移位寄存器单元的纵向高度。
可选的，所述第一电压信号线的个数为一个；所述输出电路包括输出复位晶体管；所述至少一个移位寄存器单元还包括输出电容、第一极板和第二电容连接晶体管；所述显示基板的制作方法还包括：
将所述输出复位晶体管的第一电极、所述输出电容的第一极板、所述第一晶体管的第一电极和所述第二电容连接晶体管的第一电极设置为都与所述第一电压信号线耦接，以减少采用的电压信号线的数目，并方便布局。
本公开至少一实施例所述的显示装置包括上述的显示基板。
由于上述实施例提供的显示基板能够实现窄边框，因此，本公开至少一实施例提供的显示装置在包括上述显示基板时，同样能够实现具有较窄边框的有益效果，此处不再赘述。
本公开至少一实施例所提供的显示装置可以为手机、平板电脑、电视机、 显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (39)

  1. 一种显示基板，包括设置于基底上的扫描驱动电路和显示区域，所述扫描驱动电路包括多个移位寄存器单元，所述扫描驱动电路还包括第一电压信号线、第二电压信号线、第一时钟信号线和第二时钟信号线；所述第一电压信号线、所述第二电压信号线、所述第一时钟信号线和所述第二时钟信号线沿着第一方向延伸；所述显示区域包括至少一个驱动晶体管，所述驱动晶体管被配置为驱动发光元件进行显示；
    所述多个移位寄存器单元中的至少一个移位寄存器单元包括输出电路和信号输出线；所述输出电路分别与所述第一电压信号线、所述第二电压信号线和所述信号输出线耦接；所述信号输出线沿着第二方向延伸，所述第一方向与所述第二方向相交；
    所述输出电路包括的晶体管设置于所述第一电压信号线和所述第二电压信号线之间。
  2. 如权利要求1所述的显示基板，其中，所述第一电压信号线提供第一电压给所述输出电路，所述第二电压信号线提供第二电压给所述输出电路，所述第一电压高于所述第二电压。
  3. 如权利要求1所述的显示基板，其中，所述信号输出线位于相邻的移位寄存器单元中的输出电路之间。
  4. 如权利要求1所述的显示基板，其中，所述第一电压信号线位于所述第二电压信号线远离所述显示区域的一侧。
  5. 如权利要求1所述的显示基板，其中，所述输出电路包括输出晶体管和输出复位晶体管；
    所述输出复位晶体管和所述输出晶体管沿着第一方向排列；
    所述输出复位晶体管的第一电极与所述第一电压信号线耦接，所述输出晶体管的第一电极与所述第二电压信号线耦接；
    所述输出晶体管的第二电极和所述输出复位晶体管的第二电极都与所述信号输出线耦接。
  6. 如权利要求5所述的显示基板，其中，所述输出晶体管的有源层和所 述输出复位晶体管的有源层由一个连续的第一半导体层形成；
    所述第一半导体层与所述信号输出线沿第一方向排列。
  7. 如权利要求5所述的显示基板，其中，所述输出复位晶体管的栅极包括至少一个输出复位栅极图形，所述输出复位晶体管的第一电极包括至少一个第一电极图形，所述输出复位晶体管的第二电极包括至少一个第二电极图形；
    所述输出复位栅极图形位于相邻的所述第一电极图形和所述第二电极图形之间；
    所述第二电极图形、所述输出复位栅极图形和所述第一电极图形都沿着第二方向延伸；
    所述第一方向与所述第二方向相交。
  8. 如权利要求5所述的显示基板，其中，所述输出晶体管的栅极包括至少一个输出栅极图形，所述输出晶体管的第一电极包括至少一个第三电极图形，所述输出晶体管的第二电极包括至少一个第四电极图形；
    所述输出栅极图形位于相邻的所述第三电极图形和所述第四电极图形之间；
    所述第四电极图形、所述输出栅极图形和所述第三电极图形都沿着第二方向延伸；
    所述第一方向与所述第二方向相交；
    所述输出复位晶体管中最靠近所述输出晶体管的栅极的所述第二电极图形复用为所述输出晶体管的第四电极图形。
  9. 如权利要求7所述的显示基板，其中，所述输出复位晶体管的有源层包括沿第一方向相对设置的至少两个第一导电部分，以及至少一个第一沟道部分；每一所述第一沟道部分设置于两相邻的所述第一导电部分之间；
    所述第一沟道部分与所述输出复位栅极图形一一对应，每个所述第一沟道部分在所述基底上的正投影，均位于对应的所述输出复位栅极图形在所述基底上的正投影的内部；
    所述输出复位晶体管中的一部分所述第一导电部分与所述第一电极图形一一对应，所述第一电极图形在所述基底上的正投影，与对应的所述第一导 电部分在所述基底上的正投影存在第一重叠区域，所述第一电极图形通过设置在所述第一重叠区域的至少一个第一过孔与对应的所述第一导电部分耦接；
    所述输出复位晶体管中的另一部分所述第一导电部分与所述第二电极图形一一对应，所述第二电极图形在所述基底上的正投影，与对应的所述第一导电部分在所述基底上的正投影存在第二重叠区域，所述第二电极图形通过设置在所述第二重叠区域的至少一个第二过孔与对应的所述第一导电部分耦接。
  10. 如权利要求8所述的显示基板，其中，
    所述输出晶体管的有源层包括沿第一方向相对设置的至少两个第二导电部分，以及至少一个第二沟道部分；每一所述第二沟道部分设置于两相邻的所述第二导电部分之间；
    所述第二沟道部分与所述输出栅极图形一一对应，每个所述第二沟道部分在所述基底上的正投影，均位于对应的所述输出栅极图形在所述基底上的正投影的内部；
    所述输出晶体管中的一部分所述第二导电部分与所述第三电极图形一一对应，所述第三电极图形在所述基底上的正投影，与对应的所述第二导电部分在所述基底上的正投影存在第三重叠区域，所述第三电极图形通过设置在所述第三重叠区域的至少一个第三过孔与对应的所述第二导电部分耦接；
    所述输出晶体管中的另一部分所述第二导电部分与所述第四电极图形一一对应，所述第四电极图形在所述基底上的正投影，与对应的所述第二导电部分在所述基底上的正投影存在第四重叠区域，所述第四电极图形通过设置在所述第四重叠区域的至少一个第四过孔与对应的所述第二导电部分耦接。
  11. 如权利要求1所述的显示基板，其中，所述第一电压信号线的个数为一个；
    所述输出电路包括输出复位晶体管；所述至少一个移位寄存器单元还包括输出电容、第一晶体管和第二电容连接晶体管；
    所述输出复位晶体管的第一电极、所述输出电容的第一极板、所述第一晶体管的第一电极和所述第二电容连接晶体管的第一电极都与所述第一电压信号线耦接。
  12. 如权利要求11所述的显示基板，其中，所述显示基板还包括第三电压信号线，所述第一电压信号线位于所述第二电压信号线与所述第三电压信号线之间。
  13. 如权利要求11所述的显示基板，其中，所述第二电容连接晶体管的第一电极通过第五连接过孔与信号线导电连接部耦接，所述信号线导电连接部与所述第一电压信号线耦接，以使得所述第二电容连接晶体管的第一电极与所述第一电压信号线耦接；
    所述信号线导电连接部与所述第一电压信号线包含于源漏金属层，所述第二电容连接晶体管的第一电极包含于有源层。
  14. 如权利要求13所述的显示基板，其中，所述至少一个移位寄存器单元还包括第一电容；
    所述信号线导电连接部在基底上的正投影与第一电容的第一极板在基底上的正投影部分重叠。
  15. 如权利要求11所述的显示基板，其中，所述输出电容的第一极板在所述基底上的正投影，与所述第一电压信号线在所述基底上的正投影存在信号线重叠区域，所述输出电容的第一极板通过设置在所述信号线重叠区域的至少一个信号线过孔与所述第一电压信号线耦接。
  16. 如权利要求1至15中任一权利要求所述的显示基板，其中，所述至少一个移位寄存器单元还包括第一节点控制晶体管和第二电容；
    所述第一节点控制晶体管的栅极与所述第二电容的第二极板耦接；
    所述第二电容的第一极板在所述基底上的正投影在所述第二电容的第二极板在所述基底上的正投影之内；
    所述第二电容的第一极板为L形；
    所述第二电容的第一极板包括第二水平极板部；
    所述第一节点控制晶体管的栅极在所述基底上的正投影与所述第二水平极板部在所述基底上的正投影沿第一方向排列。
  17. 如权利要求16所述的显示基板，其中，所述扫描驱动电路还包括第三电压信号线；所述第三电压信号线沿第一方向延伸；所述第三电压信号线位于所述第一电压信号线远离所述第二电压信号线的一侧；所述第一节点控 制晶体管位于所述第三电压信号线与所述第一电压信号线之间；
    所述第二电容的第一极板还包括与所述第二水平极板部耦接的第二竖直极板部；所述第二竖直极板部在所述基底上的正投影与所述第三电压信号线在所述基底上的正投影部分重叠。
  18. 如权利要求17所述的显示基板，其中，所述第一时钟信号线位于所述第三电压信号线远离所述第一电压信号线的一侧；
    所述输出电路包括输出晶体管；所述至少一个移位寄存器单元还包括设置于所述输出晶体管的栅极与所述第二电容的第二极板之间的第二导电连接部；所述第二导电连接部分别与所述输出晶体管的栅极和所述第二电容的第二极板耦接；
    所述至少一个移位寄存器单元还包括与所述第二电容的第二极板耦接的第三导电连接部；
    所述第三导电连接部在所述基底上的正投影与第一时钟信号线在所述基底上的正投影存在第六重叠区域，所述第一时钟信号线通过设置于所述第六重叠区域的至少一第六过孔与所述第二电容的第一极板耦接。
  19. 如权利要求16所述的显示基板，其中，所述第一节点控制晶体管包括第二有源图形；所述第二有源图形为U形；
    所述第二有源图形包括第一个第一节点控制沟道部分、第二个第一节点控制沟道部分、与所述第一个第一节点控制沟道部分耦接的第一个第一节点控制导电部分，以及，与所述第二个第一节点控制沟道部分耦接的第二个第一节点控制导电部分；
    所述第一节点控制晶体管的栅极包括相互耦接的第一栅极图形和第二栅极图形；
    所述第一栅极图形与所述第一个第一节点控制沟道部分对应，所述第二栅极图形与所述第二个第一节点控制沟道部分对应；
    所述第一个第一节点控制导电部分与所述第一节点控制晶体管的第二电极对应，所述第二个第一节点控制导电部分与所述第一节点控制晶体管的第一电极对应。
  20. 如权利要求16所述的显示基板，其中，所述至少一个移位寄存器单 元还包括第二节点控制晶体管；所述至少一个移位寄存器单元包括第二电容连接晶体管；
    所述第二节点控制晶体管的第二电极与所述第一节点控制晶体管的第二电极之间通过第四导电连接部耦接；
    所述至少一个移位寄存器单元还包括与所述第二电容连接晶体管的栅极耦接的第五导电连接部；所述第五导电连接部在所述基底上的正投影与所述第四导电连接部在所述基底上的正投影之间存在第七重叠区域；
    所述第五导电连接部通过设置于所述第七重叠区域的第七过孔与所述第四导电连接部耦接。
  21. 如权利要求20所述的显示基板，其中，所述扫描驱动电路还包括第三电压信号线；所述第三电压信号线位于所述第一电压信号线远离所述第二电压信号线的一侧；
    所述第一节点控制晶体管的第一电极与第六导电连接部耦接；所述第二节点控制晶体管的栅极与第七导电连接部耦接；
    所述第六导电连接部在所述基底上的正投影与所述第七导电连接部在所述基底上的正投影之间存在第八重叠区域，所述第六导电连接部通过设置于所述第八重叠区域之内的第八过孔与所述第七导电连接部耦接；
    所述第二节点控制晶体管的第一电极与所述第三电压信号线耦接。
  22. 如权利要求20所述的显示基板，其中，
    所述第二节点控制晶体管的栅极还与第八导电连接部耦接；所述第八导电连接部在所述基底上的正投影与所述第二时钟信号线在所述基底上的正投影之前存在第九重叠区域，所述第八导电连接部通过设置于所述第九重叠区域的第九过孔与所述第二时钟信号线耦接。
  23. 如权利要求1所述的显示基板，其中，所述扫描驱动电路还包括第三电压信号线；所述第三电压信号线沿第一方向延伸；
    所述第二时钟信号线设置于所述第一时钟信号线与所述第三电压信号线之间；或者，第一时钟信号线设置于所述第二时钟信号线与所述第三电压信号线之间。
  24. 如权利要求16所述的显示基板，其中，所述至少一个移位寄存器单 元还包括输入晶体管；
    所述输入晶体管的第一电极与输入信号端耦接；
    所述输入晶体管的第二电极与第九导电连接部耦接，所述第九导电连接部在所述基底上的正投影与所述第二电容的第二极板在所述基底上的正投影之间存在第十重叠区域，所述第九导电连接部通过设置于所述第十重叠区域的第十过孔与所述第二电容的第二极板耦接。
  25. 如权利要求16所述的显示基板，其中，所述至少一个移位寄存器单元还包括第三节点控制晶体管、第二电容连接晶体管和输入晶体管；
    所述第三节点控制晶体管的栅极与第一时钟信号线耦接；
    所述输入晶体管的有源层、所述第三节点控制晶体管的有源层和所述第二电容连接晶体管的有源层由一个连续的第三半导体层形成；
    所述输入晶体管的有源层包括沿第一方向依次设置的第一个第五导电部分、第五沟道部分和第二个第五导电部分；
    所述第二个第五导电部分复用为第一个第六导电部分；
    所述第三节点控制晶体管的有源层包括沿第一方向依次设置的第一个第六导电部分、第六沟道部分和第二个第六导电部分；
    所述第二个第六导电部分复用为第一个第七导电部分；
    所述第二电容连接晶体管的有源层包括沿第一方向依次设置的第一个第七导电部分、第七沟道部分和第二个第七导电部分。
  26. 如权利要求1所述的显示基板，其中，所述扫描驱动电路还包括第三电压信号线；
    所述第三电压信号线沿第一方向延伸；
    所述第三电压信号线在所述基底上的正投影、所述第一时钟信号线在所述基底上的正投影和所述第二时钟信号线在所述基底上的正投影，都位于所述移位寄存器单元在所述基底上的正投影远离所述显示基板的显示区域的一侧。
  27. 如权利要求5所述的显示基板，其中，所述扫描驱动电路还包括第三电压信号线；所述至少一个移位寄存器单元还包括输出电容、第一电容、第二电容、第一晶体管、第二晶体管、第一电容连接晶体管、第二电容连接 晶体管、第一节点控制晶体管、第二节点控制晶体管、输入晶体管、第三节点控制晶体管；
    所述第一晶体管的第二电极与所述输出电容的第二极板耦接，所述第一晶体管的第一电极与所述第一电压信号线耦接，所述第一晶体管的栅极与所述第三节点控制晶体管的第二电极耦接；
    所述第二晶体管的第一电极与所述第一电容的第一极板耦接，所述第二晶体管的第二电极与第一电容连接晶体管的第二电极耦接，所述第二晶体管的栅极与所述第三节点控制晶体管的栅极耦接；
    所述第一电容连接晶体管的栅极和所述第二电容连接晶体管的栅极分别与所述第一电容的第二极板耦接；所述第一电容连接晶体管的第二电极与所述第一电容的第一极板耦接；所述第一电容连接晶体管的第一电极与第二晶体管的栅极耦接；
    所述第二电容连接晶体管的第一电极与所述第一电压信号线耦接；所述第二电容连接晶体管的栅极与所述第二节点控制晶体管的第二电极耦接；所述第二电容连接晶体管的第二电极与所述第三节点控制晶体管的第一电极耦接；
    所述第一节点控制晶体管的第一电极与所述第二节点控制晶体管的栅极耦接；所述第一节点控制晶体管的栅极与所述第二电容的第二极板耦接；
    所述第二节点控制晶体管的第二电极与所述第一节点控制晶体管的第二电极耦接；所述第二节点控制晶体管的栅极与所述第二时钟信号线耦接；所述第二节点控制晶体管的第一电极与所述第三电压信号线耦接；
    所述输入晶体管的栅极与所述第二节点控制晶体管的栅极耦接；所述输入晶体管的第一电极与输入信号端耦接；所述输入晶体管的第二电极与所述第二电容的第二极板耦接；
    所述第三节点控制晶体管的栅极与所述第一时钟信号线耦接；
    所述输出电容的第一极板与所述第一电压信号线耦接，所述输出电容的第二极板与所述输出复位晶体管的栅极耦接；
    所述第二电容的第二极板与所述输出晶体管的栅极耦接，所述第二电容的第一极板与所述第一时钟信号线耦接；
    所述输出晶体管的第二电极和所述输出复位晶体管的第二电极都与所述信号输出线耦接。
  28. 如权利要求27所述的显示基板，其中，沿靠近所述显示区域的方向，所述第一时钟信号线、所述第二时钟信号线和所述第三电压信号线依次排列；或者，沿靠近所述显示区域的方向，所述第二时钟信号线、所述第一时钟信号线和所述第三电压信号线依次排列。
  29. 如权利要求27所述的显示基板，其中，所述第一电容的第一极板包括第一水平极板部和第一竖直极板部；
    所述输出晶体管和所述输出复位晶体管设置于所述第一电压信号线和所述第二电压信号线之间；沿着所述第一方向，所述输出复位晶体管、所述输出晶体管和所述信号输出线依次排列；
    所述第三电压信号线设置于所述第一电压信号线远离所述第二电压信号线的一侧；所述第一电容、所述第一晶体管、第二晶体管、第一电容连接晶体管、第二电容连接晶体管、第一节点控制晶体管、第二节点控制晶体管、输入晶体管和第三节点控制晶体管都设置于所述第一电压信号线和所述第三电压信号线之间；
    所述第一晶体管、所述第二晶体管和所述第一竖直极板部沿着第一方向依次排列，所述输入晶体管、所述第三节点控制晶体管、所述第二电容连接晶体管和所述第一水平极板部沿着第一方向依次排列，所述第二节点控制晶体管和所述第一节点控制晶体管沿着第一方向依次排列；
    所述第一电容连接晶体管的栅极在所述基底上的正投影设置于所述第一电容的第二极板在所述基底上的正投影与所述第一电压信号线在所述基底上的正投影之间；
    所述第二晶体管的栅极在所述基底上的正投影设置于所述第三节点控制晶体管的栅极在所述基底上的正投影与所述第一电压信号线在所述基底上的正投影之间；
    所述第一节点控制晶体管的栅极在所述基底上的正投影设置于所述第三电压信号线在所述基底上的正投影与所述第一电容的第一极板在所述基底上的正投影之间；
    所述第一节点控制晶体管的栅极在所述基底上的正投影与所述第三电压信号线在所述基底上的正投影在第二方向上的最小距离，大于所述第二电容连接晶体管的栅极在所述基底上的正投影与所述第三电压信号线在所述基底上的正投影在第二方向上的最小距离。
  30. 如权利要求29所述的显示基板，其中，
    所述输出电容的第一极板在所述基底上的正投影，与所述第一电压信号线在所述基底上的正投影存在信号线重叠区域；所述输出电容的第二极板与所述基底上的正投影与所述第一电压信号线在所述基底上的正投影部分重叠；
    所述第二电容的第一极板在所述基底上的正投影在所述第二电容的第二极板在所述基底上的正投影之内；所述第二电容的第一极板为L形；
    所述第二电容的第一极板包括第二水平极板部和第二竖直极板部；
    所述第一节点控制晶体管的栅极与所述第二水平极板部沿第一方向排列；
    所述第二竖直极板部在所述基底上的正投影与所述第三电压信号线在所述基底上的正投影部分重叠。
  31. 如权利要求1所述的显示基板，其中，所述显示基板还包括设置于所述基底上的多行像素电路；所述像素电路包括发光控制端；
    所述扫描驱动电路包括的所述移位寄存器单元与所述行像素电路一一对应
    所述移位寄存器单元的信号输出线与相应行像素电路的发光控制端耦接，用于为所述相应行像素电路的发光控制端提供发光控制信号。
  32. 一种显示基板的制作方法，包括在基底上制作扫描驱动电路，并在显示基板包括的显示区域制作至少一个驱动晶体管；所述驱动晶体管被配置为驱动发光元件进行显示；
    所述扫描驱动电路包括多个移位寄存器单元、第一电压信号线、第二电压信号线、第一时钟信号线和第二时钟信号线，所述多个移位寄存器单元中的至少一个移位寄存器单元包括输出电路和信号输出线；
    所述显示基板的制作方法还包括：
    在所述第一电压信号线和所述第二电压信号线之间制作所述输出电路包括的晶体管；
    将所述第一电压信号线、所述第二电压信号线、所述第一时钟信号线和所述第二时钟信号线设置为沿着第一方向延伸，将信号输出线设置为沿着第二方向延伸；
    所述第一方向和所述第二方向相交。
  33. 如权利要求32所述的显示基板的制作方法，其中，还包括：
    将所述信号输出线设置于相邻的移位寄存器单元中的输出电路之间。
  34. 如权利要求32所述的显示基板的制作方法，其中，所述第一电压信号线位于所述第二电压信号线远离显示区域的一侧。
  35. 如权利要求32所述的显示基板的制作方法，其中，所述输出电路包括输出晶体管和输出复位晶体管，制作所述输出电路包括的晶体管的步骤具体包括：
    在所述第一电压信号线和所述第二电压信号线之间形成第一半导体层；
    在所述第一半导体层背向所述基底上的一面，制作第一栅金属层，对所述第一栅金属层进行构图工艺，以形成所述输出晶体管的栅极和所述输出复位晶体管的栅极；
    以所述输出晶体管的栅极和所述输出复位晶体管的栅极为掩膜，对第一半导体层中未被所述栅极覆盖的部分进行掺杂，使得所述第一半导体层中未被所述栅极覆盖的部分形成为导电部分，所述第一半导体层中被所述栅极覆盖的部分形成为沟道部分。
  36. 如权利要求35所述的显示基板的制作方法，其中，所述显示基板的制作方法还包括：在所述第一栅极金属层背向所述第一半导体层的一面设置第二栅金属层，对所述第二栅金属层进行构图工艺，以形成沿第二方向延伸的信号输出线；
    所述第一半导体层在所述基底上的正投影和所述信号输出线在所述基底上的正投影沿着第一方向排列，所述第一方向与所述第二方向相交。
  37. 如权利要求36所述的显示基板的制作方法，其中，制作第一电压信号线、第二电压信号线、第一时钟信号线和第二时钟信号线的步骤具体包括：
    在所述第二栅金属层背向所述第一栅金属层的一面制作源漏金属层，对所述源漏金属层进行构图工艺，以形成所述第一电压信号线、所述第二电压 信号线、第一时钟信号线和第二时钟信号线。
  38. 如权利要求32所述的显示基板的制作方法，其中，所述第一电压信号线的个数为一个；所述输出电路包括输出复位晶体管；所述至少一个移位寄存器单元还包括输出电容、第一极板和第二电容连接晶体管；所述显示基板的制作方法还包括：
    将所述输出复位晶体管的第一电极、所述输出电容的第一极板、所述第一晶体管的第一电极和所述第二电容连接晶体管的第一电极设置为都与所述第一电压信号线耦接。
  39. 一种显示装置，包括如权利要求1至31中任一权利要求所述的显示基板。
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