WO2014190585A1 - 液晶显示面板及其像素结构和驱动方法 - Google Patents

液晶显示面板及其像素结构和驱动方法 Download PDF

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Publication number
WO2014190585A1
WO2014190585A1 PCT/CN2013/078355 CN2013078355W WO2014190585A1 WO 2014190585 A1 WO2014190585 A1 WO 2014190585A1 CN 2013078355 W CN2013078355 W CN 2013078355W WO 2014190585 A1 WO2014190585 A1 WO 2014190585A1
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pixel
control switch
pixel electrode
electrode
liquid crystal
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PCT/CN2013/078355
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English (en)
French (fr)
Inventor
姚晓慧
许哲豪
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深圳市华星光电技术有限公司
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Priority to US14/232,263 priority Critical patent/US9349330B2/en
Publication of WO2014190585A1 publication Critical patent/WO2014190585A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G09G2300/0447—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/028—Improving the quality of display appearance by changing the viewing angle properties, e.g. widening the viewing angle, adapting the viewing angle to the view direction

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a liquid crystal display panel, a pixel structure thereof and a driving method thereof.
  • the multi-domain vertical alignment type liquid crystal display panel is a display panel of a liquid crystal display. Since the orientation of the liquid crystal is observed at different viewing angles, the color distortion of the liquid crystal panel observed at a large viewing angle is caused. In order to improve the problem of large viewing angle color distortion, one pixel (red, green or blue) is divided into two parts in the pixel structure design: the first pixel area and the second pixel area, and the large viewing angle distortion is improved by controlling the voltage of the two areas. Generally known as low color shift design.
  • the low color shift design is mainly divided into two categories. One is to control the first pixel region and the second pixel region by increasing the data lines. The disadvantage is that the number of drivers is increased, resulting in an increase in cost; the other is in the array substrate.
  • the upper design capacitor is used to control the inconsistency of the potentials of the first pixel region and the second pixel region to achieve a low color shift effect. However, since the capacitor is designed on the array substrate, the aperture ratio of the pixel structure is lowered, resulting in poor display performance.
  • the technical problem to be solved by the present invention is to provide a liquid crystal display panel and a pixel structure and a driving method thereof, which can achieve a low color shift effect without reducing the aperture ratio of the pixel structure, thereby avoiding large viewing angle color distortion.
  • the present invention adopts a technical solution to provide a pixel structure including a plurality of pixels arranged in a matrix, each pixel including a first pixel region, a second pixel region, and a third disposed adjacently.
  • the first pixel region includes a first pixel electrode and a first control switch, the first pixel electrode is connected to the data signal through the first control switch;
  • the second pixel region includes a second pixel electrode and a second control switch, and the second pixel electrode Connecting the data signal by the second control switch, the control ends of the first control switch and the second control switch are connected to the first scan signal;
  • the third pixel region includes a third pixel electrode and a third control switch, and the third pixel electrode passes through the The third control switch and the second control switch are connected to the data signal, the control end of the third control switch is connected to the second scan signal, and the third pixel electrode is further connected to the second pixel electrode through the third control switch to be in the first control switch, the second control When the switch and the third control switch are both turned on, the potentials of the first pixel electrode and the second pixel electrode are different.
  • the pixel structure includes an array substrate, a color filter substrate, and a liquid crystal layer sandwiched between the array substrate and the color filter substrate, wherein the first pixel region, the second pixel region, and the third pixel region are disposed on the array substrate
  • a common electrode is disposed, and a liquid crystal layer is used as a medium to form a voltage dividing liquid crystal capacitor between the third pixel electrode and the common electrode, and the voltage dividing liquid crystal capacitor is used for the first control switch, the second control switch, and the first When the three control switches are both turned on, the potential of the second pixel electrode is lowered such that the potentials of the first pixel electrode and the second pixel electrode are different.
  • the array substrate further includes an insulating layer and a storage capacitor electrode disposed under the first pixel electrode and the second pixel electrode in sequence, and the first liquid crystal capacitor is formed by using the liquid crystal layer as a medium between the first pixel electrode and the common electrode.
  • a first storage capacitor is formed between the one pixel electrode and the storage capacitor electrode by using an insulating layer as a medium; a second liquid crystal capacitor is formed between the second pixel electrode and the common electrode by using a liquid crystal layer as a medium, and between the second pixel electrode and the storage capacitor electrode The second storage capacitor is formed by using the insulating layer as a medium.
  • the common electrode is connected to the first common voltage, and the storage capacitor electrode is connected to the second common voltage.
  • the first control switch is a first thin film transistor
  • the second control switch is a second thin film transistor
  • the third control switch is a third thin film transistor
  • the first pixel electrode is connected to the drain of the first thin film transistor
  • the first thin film transistor is The source is connected to the data signal
  • the gate of the first thin film transistor is connected to the first scan signal
  • the second pixel electrode is connected to the drain of the second thin film transistor
  • the source of the second thin film transistor is connected to the data signal
  • the gate of the second thin film transistor is The first scan signal
  • the third pixel electrode is connected to the drain of the third thin film transistor
  • the source of the third thin film transistor is connected to the drain of the second thin film transistor
  • the gate of the third thin film transistor is connected to the second scan signal.
  • the array substrate further includes a plurality of scan lines disposed laterally and a plurality of data lines disposed longitudinally, wherein the scan lines intersect the data lines, and the first pixel region of the nth pixel is disposed on the n-1th scan line, The area surrounded by the nth scan line, the nth data line, and the n+1th data line; the second pixel area of the nth pixel is set on the nth scan line and the n+1th scan line a region surrounded by the nth data line and the n+1th data line; the third pixel region of the nth pixel is set at the n+1th scan line, the n+2th scan line, and the nth The data line and the area surrounded by the n+1th data line; the nth data line is used to provide the data signal of the nth pixel, and the nth scan line is used to provide the first scan of the nth pixel The signal, the n+1th scan line provides a second scan signal
  • the second scan signal of the nth pixel and the first scan signal of the n+1th pixel are the same signal.
  • a liquid crystal display panel including a pixel structure including a plurality of pixels arranged in a matrix, each pixel including a first pixel disposed adjacently a second pixel region including a first pixel electrode and a first control switch, the first pixel electrode being connected to the data signal by the first control switch; the second pixel region comprising the second pixel electrode and a second control switch, the second pixel electrode is connected to the data signal through the second control switch, the control ends of the first control switch and the second control switch are connected to the first scan signal; the third pixel region comprises a third pixel electrode and a third control a switch, the third pixel electrode sequentially connects the data signal through the third control switch and the second control switch, the control end of the third control switch is connected to the second scan signal, and the third pixel electrode is further connected to the second pixel electrode through the third control switch Making the first pixel electrode and the second electrode when the first control switch, the second control switch, and
  • the pixel structure includes an array substrate, a color filter substrate, and a liquid crystal layer sandwiched between the array substrate and the color filter substrate, wherein the first pixel region, the second pixel region, and the third pixel region are disposed on the array substrate
  • a common electrode is disposed, and a liquid crystal layer is used as a medium to form a voltage dividing liquid crystal capacitor between the third pixel electrode and the common electrode, and the voltage dividing liquid crystal capacitor is used for the first control switch, the second control switch, and the first When the three control switches are both turned on, the potential of the second pixel electrode is lowered such that the potentials of the first pixel electrode and the second pixel electrode are different.
  • the array substrate further includes an insulating layer and a storage capacitor electrode disposed under the first pixel electrode and the second pixel electrode in sequence, and the first liquid crystal capacitor is formed by using the liquid crystal layer as a medium between the first pixel electrode and the common electrode.
  • a first storage capacitor is formed between the one pixel electrode and the storage capacitor electrode by using an insulating layer as a medium; a second liquid crystal capacitor is formed between the second pixel electrode and the common electrode by using a liquid crystal layer as a medium, and between the second pixel electrode and the storage capacitor electrode The second storage capacitor is formed by using the insulating layer as a medium.
  • the common electrode is connected to the first common voltage, and the storage capacitor electrode is connected to the second common voltage.
  • the first control switch is a first thin film transistor
  • the second control switch is a second thin film transistor
  • the third control switch is a third thin film transistor
  • the first pixel electrode is connected to the drain of the first thin film transistor
  • the first thin film transistor is The source is connected to the data signal
  • the gate of the first thin film transistor is connected to the first scan signal
  • the second pixel electrode is connected to the drain of the second thin film transistor
  • the source of the second thin film transistor is connected to the data signal
  • the gate of the second thin film transistor is The first scan signal
  • the third pixel electrode is connected to the drain of the third thin film transistor
  • the source of the third thin film transistor is connected to the drain of the second thin film transistor
  • the gate of the third thin film transistor is connected to the second scan signal.
  • the array substrate further includes a plurality of scan lines disposed laterally and a plurality of data lines disposed longitudinally, wherein the scan lines intersect the data lines, and the first pixel region of the nth pixel is disposed on the n-1th scan line, The area surrounded by the nth scan line, the nth data line, and the n+1th data line; the second pixel area of the nth pixel is set on the nth scan line and the n+1th scan line a region surrounded by the nth data line and the n+1th data line; the third pixel region of the nth pixel is set at the n+1th scan line, the n+2th scan line, and the nth The data line and the area surrounded by the n+1th data line; the nth data line is used to provide the data signal of the nth pixel, and the nth scan line is used to provide the first scan of the nth pixel The signal, the n+1th scan line provides a second scan signal
  • a driving method of a liquid crystal display panel includes a pixel structure, the pixel structure includes a plurality of pixels arranged in a matrix, and each pixel includes an adjacent setting a first pixel region, a second pixel region, and a third pixel region, wherein the first pixel region includes a first pixel electrode and a first control switch, the first pixel electrode is connected to the data signal through the first control switch; the second pixel region includes a second pixel electrode and a second control switch, wherein the second pixel electrode is connected to the data signal through the second control switch, and the control ends of the first control switch and the second control switch are connected to the first scan signal; the third pixel region includes the third pixel An electrode and a third control switch, wherein the third pixel electrode sequentially connects the data signal through the third control switch
  • the pixel structure further includes: an oppositely disposed array substrate, a color filter substrate, and a liquid crystal layer sandwiched between the array substrate and the color filter substrate, wherein the array substrate includes sequentially disposed under the first pixel electrode and the second pixel electrode
  • the insulating layer and the storage capacitor electrode are provided with a common electrode on the color filter substrate, the first pixel region, the second pixel region and the third pixel region are disposed on the array substrate, and the liquid crystal layer is used between the third pixel electrode and the common electrode
  • the medium forms a divided liquid crystal capacitor CL, and a first liquid crystal capacitor CL1 is formed by using a liquid crystal layer as a medium between the first pixel electrode and the common electrode, and a first storage capacitor Cs1 is formed by using an insulating layer as a medium between the first pixel electrode and the storage capacitor electrode.
  • a second liquid crystal capacitor CL2 is formed between the second pixel electrode and the common electrode by using a liquid crystal layer as a medium
  • a second storage capacitor Cs2 is formed between the second pixel electrode and the storage capacitor electrode by using an insulating layer as a medium
  • the common electrode is connected to the first common voltage, and the storage capacitor electrode is connected to the second common voltage.
  • the present invention lowers the potential of the second pixel region by using a divided liquid crystal capacitor formed between the third pixel electrode and the common electrode by adding a third pixel region.
  • the potential of the first pixel region is made different from the potential of the second sub-pixel region, thereby achieving a low color shift effect without reducing the aperture ratio, and large-angle color distortion can be avoided.
  • FIG. 1 is a cross-sectional structural view showing a preferred embodiment of a pixel structure of the present invention
  • FIG. 2 is a schematic circuit diagram of a pixel structure of the present invention.
  • FIG. 3 is a schematic structural view of a liquid crystal display panel of the present invention.
  • FIG. 4 is a flow chart showing a driving method of a liquid crystal display panel of the present invention.
  • FIG. 1 is a cross-sectional structural diagram of a preferred embodiment of a pixel structure of the present invention.
  • the pixel structure 10 preferably includes an array substrate 11 , a liquid crystal layer 12 , and a color filter substrate 13 .
  • the array substrate 11 and the color filter substrate 13 are disposed opposite to each other, and the liquid crystal layer 12 is sandwiched between the array substrate 11 and the color filter substrate 13.
  • the pixel structure 10 of the present invention has a plurality of pixels 14a, 14b, 14c, 14d having the same structure for displaying different colors, wherein each pixel includes a first pixel region 141, a second pixel region 142, and a third disposed adjacently. Pixel area 143.
  • the first pixel region 141, the second pixel region 142, and the third pixel region 143 are disposed on the array substrate 11.
  • the array substrate 11 is further provided with a storage capacitor electrode 15 and an insulating layer 16.
  • the storage capacitor electrode 15 is disposed under the first pixel region 141 and the second pixel region 142, and the insulating layer 16 covers the storage capacitor electrode 15.
  • the color filter substrate 13 includes a common electrode 17 disposed on the lower surface of the color filter substrate 13.
  • FIG. 2 is a schematic diagram of the circuit structure of the pixel structure of the present invention.
  • the array substrate 11 is provided with a plurality of scanning lines S 1 to S N and a plurality of data lines D 1 to D N .
  • the plurality of scanning lines S 1 to S N are laterally disposed, and the plurality of data lines D 1 to D N are longitudinally disposed, and the scanning lines and the data lines are perpendicular to each other. In other embodiments, the scan lines and data lines may also not be vertical.
  • the nth pixel 14c shown in FIG. 1 will be described below as an example.
  • the nth pixel 14c includes a first pixel region 141, a second pixel region 142, and a third pixel region 143.
  • the first pixel region 141 of the nth pixel 14c is disposed on the n-1th scan line Sn -1 , the nth scan line Sn, the nth data line Dn, and the n+1th data line Dn+ 1 enclosed area.
  • the second pixel region 142 of the nth pixel 14c is disposed on the nth scan line S n , the n+1th scan line S n+1 , the nth data line D n , and the n+1th data line D n Within the area enclosed by +1 .
  • the third pixel region 143 of the nth pixel 14c is disposed on the n+1th scan line S n+1 , the n+2th scan line S n+2 , the nth data line D n , and the n+1th strip The area enclosed by the data line D n+1 .
  • the first pixel region 141 includes a first pixel electrode 21 and a first control switch T1, and the first pixel electrode 21 is connected to the data signal through the first control switch T1.
  • the first control switch T1 is preferably the first thin film transistor T1
  • the first pixel electrode 21 is connected to the drain of the first thin film transistor T1
  • the source of the first thin film transistor T1 is connected to the data signal
  • the first thin film transistor is connected.
  • the gate of T1 is its control terminal and is connected to the first scan signal
  • the nth data line D n is used to provide the data signal of the nth pixel 14c, that is, the source of the first thin film transistor T1 is connected to the nth data line D n .
  • N-th scan line S n for providing n-th pixel of the first scan signal 14c, i.e., a first thin film transistor T1 connected to the gate of the n-th scan line S n.
  • the second pixel region 142 includes a second pixel electrode 22 and a second control switch T2, and the second pixel electrode 22 is connected to the data signal through the second control switch T2.
  • the second control switch T2 is preferably the second thin film transistor T2.
  • the second pixel electrode 22 is connected to the drain of the second thin film transistor T2, the source of the second thin film transistor T2 is connected to the data signal, and the gate of the second thin film transistor T2 is its control terminal and is connected to the first scan signal.
  • the nth data line Dn is used to supply the data signal of the nth pixel 14c, that is, the source of the second thin film transistor T2 is connected to the nth data line Dn .
  • N-th scan line S n for providing n-th pixel of the first scan signal 14c, i.e., the second thin film transistor T2 connected to the gate of the n-th scan line S n.
  • the third pixel region 143 includes a third pixel electrode 23 and a third control switch T3.
  • the third pixel electrode 23 sequentially connects the data signal through the third control switch T3 and the second control switch T2, and the third pixel electrode 23 also passes the third control.
  • the switch T3 is connected to the second pixel electrode 22.
  • the third control switch T3 is preferably a third thin film transistor T3, the third pixel electrode T3 is connected to the drain of the third thin film transistor T3, and the source of the third thin film transistor T3 is connected to the drain of the second thin film transistor T2.
  • a gate of the third thin film transistor T3 is connected to the second scan signal, and the n+1th scan line Sn +1 provides a second scan signal of the nth pixel 14c, that is, the third thin film transistor T3.
  • the gate is connected to the n+1th scan line S n+1 .
  • the second scan signal of the nth pixel 14c and the first scan signal of the n+1th pixel 14d are preferably the same signal, that is, the n+1th scan line S n+ 1 and the n+2th scanning line S n+2 are connected to the scanning line end of the same driving IC for generating a scanning signal, thereby saving cost.
  • the second scan signal of the nth pixel 14c and the first scan signal of the n+1th pixel 14d may not be the same signal, that is, the n+1th scan line S n+1 and the nth.
  • the +2 scan lines S n+2 may not be connected to the same driver IC.
  • the second scan signal of the nth pixel 14c and the first scan signal of the n+1th pixel 14d may also be provided by the n+1th scan line Sn +1 .
  • the common electrode 17 is connected to the first common voltage VC1, and the storage capacitor electrode 15 is connected to the second common voltage VC2.
  • a divided liquid crystal capacitor CL is formed between the third pixel electrode 23 and the common electrode 17 with the liquid crystal layer 12 as a medium.
  • a first liquid crystal capacitor CL1 is formed between the first pixel electrode 21 and the common electrode 17 with the liquid crystal layer 15 as a medium, and the first storage capacitor Cs1 is formed between the first pixel electrode 21 and the storage capacitor electrode 15 with the insulating layer 16 as a medium.
  • a second liquid crystal capacitor CL2 is formed between the second pixel electrode 22 and the common electrode 17 with the liquid crystal layer 12 as a medium, and a second storage capacitor Cs2 is formed between the second pixel electrode 22 and the storage capacitor electrode 15 with the insulating layer 16 as a medium.
  • the divided liquid crystal capacitor CL is for lowering the potential of the second pixel electrode 21 when the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 are both turned on so that the first pixel electrode 21 and the second pixel electrode The potential of 22 is different.
  • the first thin film transistor T1 is turned on to conduct between the source and the drain
  • the second thin film transistor T2 and the third thin film transistor T3 are turned on to conduct conduction between the source and the drain.
  • the nth pixel 14c will be described as an example.
  • the first scan signal on the nth scan line Dn controls the first thin film transistor T1 and the second thin film transistor T2 to be turned on and the second scan signal on the n+1th scan line Dn+1 controls the third thin film transistor T3
  • a first equipotential V1 potential at V1 in FIG.
  • a second equipotential V2 (potential at V2 in FIG. 2) is formed between the second pixel electrode 21 and the third pixel electrode 22 at this time. It can be obtained from the capacitance partial pressure formula that the relationship between the first equipotential V1 and the second equipotential V2 is:
  • V2 V1(CL2 +Cs2)/( CL2 +Cs2 +2CL) (1)
  • V2 ⁇ V1 that is, the potential of the first pixel electrode 21 is different from the potential of the second pixel electrode 21, and the requirement of the conventional low color shift pixel structure design is achieved, that is, when the first pixel electrode 21 has a potential and a second
  • the potential of the pixel electrode 22 is different, the color distortion of the liquid crystal display panel is reduced when viewed from a large viewing angle.
  • no capacitance is additionally provided on the array substrate 11, and therefore the aperture ratio of the liquid crystal display panel is not affected.
  • FIG. 3 is a schematic structural view of a liquid crystal display panel of the present invention.
  • the liquid crystal display panel includes a pixel structure 10, a first polarizing plate 18, and a second polarizing plate 19.
  • the pixel structure 10 is the pixel structure 10 described in any of the above embodiments.
  • the first polarizing plate 18 is disposed under the array substrate 11, and the second polarizing plate 19 is disposed above the color filter substrate 13.
  • FIG. 4 is a schematic flow chart of a driving method of the liquid crystal display panel of the present invention.
  • Step S41 The first control switch and the second control switch are controlled to be turned on by using the first scan signal.
  • Step S42 charging the first pixel region and the second pixel region with the data signal such that the first pixel electrode and the second pixel electrode form a first equipotential V1.
  • Step S43 controlling the third control switch to be turned on by using the second scan signal, so that the third pixel electrode and the second pixel electrode are turned on to form the second pixel electrode and the third pixel electrode to form a second different from the first equipotential V1.
  • the present invention increases the potential of the second pixel region by using a divided liquid crystal capacitor formed between the third pixel electrode and the common electrode by adding a third pixel region, so that the potential of the first pixel region is The potentials of the second sub-pixel regions are different, so that a low color shift effect can be achieved without lowering the aperture ratio, and large viewing angle color distortion can be avoided.

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Abstract

一种像素结构（10），其包括多个像素（14a，14b，14c，14d），每一像素（14a，14b，14c，14d）包括相邻设置的第一像素区（141）、第二像素区（142）以及第三像素区（143）。第一像素区（141）包括第一像素电极（21）和第一控制开关（T1），第二像素区（142）包括第二像素电极（22）和第二控制开关（T2），第三像素区（143）包括第三像素电极（23）和第三控制开关（T3）。第三像素电极（23）依次通过第三控制开关（T3）、第二控制开关（T2）连接数据信号，第三像素电极（23）还通过第三控制开关（T3）连接第二像素电极（22）以在第一控制开关（T1）、第二控制开关（T2）、第三控制开关（T3）均导通时使得第一像素电极（21）和第二像素电极（22）的电位不同。

Description

液晶显示面板及其像素结构和驱动方法
【技术领域】
本发明涉及液晶显示领域，特别是涉及一种液晶显示面板及其像素结构和驱动方法。
【背景技术】
多畴垂直配向型液晶显示面板作为液晶显示器的一种显示面板，由于在不同视角下观察到液晶的指向不同，会导致液晶面板在大视角下观察到的颜色失真。为了改善大视角颜色失真的问题，在像素结构设计时，将一个像素（红、绿或蓝）分成两部分：第一像素区和第二像素区，通过控制两区电压来改善大视角失真，一般称为低色偏设计。
低色偏设计主要分为两类，一类是是通过增加数据线，分别对第一像素区和第二像素区控制，其缺点是驱动数目增加，导致成本增加；另一类是在阵列基板上设计电容，用来控制第一像素区和第二像素区的电位不一致，实现低色偏的效果，但由于在阵列基板上设计电容，会降低像素结构的开口率，导致显示效果不佳。
因此，需要提供一种液晶显示面板及其像素结构和驱动方法，以解决上述问题。
【发明内容】
本发明主要解决的技术问题是提供一种液晶显示面板及其像素结构和驱动方法，能够在不降低像素结构开口率的情况下实现低色偏的效果，从而避免大视角颜色失真。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种像素结构，其包括矩阵排列的多个像素，每一像素包括相邻设置的第一像素区、第二像素区以及第三像素区，第一像素区包括第一像素电极和第一控制开关，第一像素电极通过第一控制开关连接数据信号；第二像素区包括第二像素电极和第二控制开关，第二像素电极通过第二控制开关连接数据信号，第一控制开关和第二控制开关的控制端均连接第一扫描信号；第三像素区包括第三像素电极和第三控制开关，第三像素电极依次通过第三控制开关和第二控制开关连接数据信号，第三控制开关的控制端连接第二扫描信号，第三像素电极还通过第三控制开关连接第二像素电极以在第一控制开关、第二控制开关以及第三控制开关均导通时使得第一像素电极和第二像素电极的电位不同。
其中，像素结构包括相对设置的阵列基板、彩膜基板以及夹持在阵列基板和彩膜基板之间的液晶层，其中，第一像素区、第二像素区以及第三像素区设置在阵列基板上，彩膜基板上设置有公共电极，第三像素电极和公共电极之间以液晶层为介质形成分压液晶电容，分压液晶电容用于在第一控制开关、第二控制开关、以及第三控制开关均导通时降低第二像素电极的电位以使得第一像素电极和第二像素电极的电位不同。
其中，阵列基板上还包括依次设置在第一像素电极和第二像素电极的下方的绝缘层和存储电容电极，第一像素电极和公共电极之间以液晶层为介质形成第一液晶电容，第一像素电极和存储电容电极之间以绝缘层为介质形成第一存储电容；第二像素电极和公共电极之间以液晶层为介质形成第二液晶电容，第二像素电极和存储电容电极之间以绝缘层为介质形成第二存储电容。公共电极连接第一公共电压，存储电容电极连接第二公共电压。
其中，第一控制开关为第一薄膜晶体管，第二控制开关为第二薄膜晶体管，第三控制开关为第三薄膜晶体管，第一像素电极连接第一薄膜晶体管的漏极，第一薄膜晶体管的源极连接数据信号，第一薄膜晶体管的栅极连接第一扫描信号，第二像素电极连接第二薄膜晶体管的漏极，第二薄膜晶体管的源极连接数据信号，第二薄膜晶体管的栅极连接第一扫描信号，第三像素电极连接第三薄膜晶体管的漏极，第三薄膜晶体管的源极连接第二薄膜晶体管的漏极，第三薄膜晶体管的栅极连接第二扫描信号。
其中，阵列基板上进一步包括横向设置的多条扫描线和纵向设置的多条数据线，扫描线均与数据线相交，第n个像素的第一像素区设置在第n-1条扫描线、第n条扫描线、第n条数据线以及第n+1条数据线所围成的区域内；第n个像素的第二像素区设置在第n条扫描线、第n+1条扫描线、第n条数据线以及第n+1条数据线所围成的区域内；第n个像素的第三像素区设置在第n+1条扫描线、第n+2条扫描线、第n条数据线以及第n+1条数据线所围成的区域内；第n条数据线用于提供第n个像素的数据信号，第n条扫描线用于提供第n个像素的第一扫描信号，第n+1条扫描线提供第n个像素的第二扫描信号。
其中，第n个像素的第二扫描信号与第n+1个像素的第一扫描信号为同一信号。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示面板，其包括像素结构，该像素结构包括矩阵排列的多个像素，每一像素包括相邻设置的第一像素区、第二像素区以及第三像素区，第一像素区包括第一像素电极和第一控制开关，第一像素电极通过第一控制开关连接数据信号；第二像素区包括第二像素电极和第二控制开关，第二像素电极通过第二控制开关连接数据信号，第一控制开关和第二控制开关的控制端均连接第一扫描信号；第三像素区包括第三像素电极和第三控制开关，第三像素电极依次通过第三控制开关和第二控制开关连接数据信号，第三控制开关的控制端连接第二扫描信号，第三像素电极还通过第三控制开关连接第二像素电极以在第一控制开关、第二控制开关以及第三控制开关均导通时使得第一像素电极和第二像素电极的电位不同。
其中，像素结构包括相对设置的阵列基板、彩膜基板以及夹持在阵列基板和彩膜基板之间的液晶层，其中，第一像素区、第二像素区以及第三像素区设置在阵列基板上，彩膜基板上设置有公共电极，第三像素电极和公共电极之间以液晶层为介质形成分压液晶电容，分压液晶电容用于在第一控制开关、第二控制开关、以及第三控制开关均导通时降低第二像素电极的电位以使得第一像素电极和第二像素电极的电位不同。
其中，阵列基板上还包括依次设置在第一像素电极和第二像素电极的下方的绝缘层和存储电容电极，第一像素电极和公共电极之间以液晶层为介质形成第一液晶电容，第一像素电极和存储电容电极之间以绝缘层为介质形成第一存储电容；第二像素电极和公共电极之间以液晶层为介质形成第二液晶电容，第二像素电极和存储电容电极之间以绝缘层为介质形成第二存储电容。公共电极连接第一公共电压，存储电容电极连接第二公共电压。
其中，第一控制开关为第一薄膜晶体管，第二控制开关为第二薄膜晶体管，第三控制开关为第三薄膜晶体管，第一像素电极连接第一薄膜晶体管的漏极，第一薄膜晶体管的源极连接数据信号，第一薄膜晶体管的栅极连接第一扫描信号，第二像素电极连接第二薄膜晶体管的漏极，第二薄膜晶体管的源极连接数据信号，第二薄膜晶体管的栅极连接第一扫描信号，第三像素电极连接第三薄膜晶体管的漏极，第三薄膜晶体管的源极连接第二薄膜晶体管的漏极，第三薄膜晶体管的栅极连接第二扫描信号。
其中，阵列基板上进一步包括横向设置的多条扫描线和纵向设置的多条数据线，扫描线均与数据线相交，第n个像素的第一像素区设置在第n-1条扫描线、第n条扫描线、第n条数据线以及第n+1条数据线所围成的区域内；第n个像素的第二像素区设置在第n条扫描线、第n+1条扫描线、第n条数据线以及第n+1条数据线所围成的区域内；第n个像素的第三像素区设置在第n+1条扫描线、第n+2条扫描线、第n条数据线以及第n+1条数据线所围成的区域内；第n条数据线用于提供第n个像素的数据信号，第n条扫描线用于提供第n个像素的第一扫描信号，第n+1条扫描线提供第n个像素的第二扫描信号。
其中，第n个像素的第二扫描信号与第n+1个像素的第一扫描信号为同一信号。为解决上述问题，本发明采用的又一个技术方案是：一种液晶显示面板的驱动方法，该液晶显示面板包括像素结构，该像素结构包括矩阵排列的多个像素，每一像素包括相邻设置的第一像素区、第二像素区以及第三像素区，其中第一像素区包括第一像素电极和第一控制开关，第一像素电极通过第一控制开关连接数据信号；第二像素区包括第二像素电极和第二控制开关，第二像素电极通过第二控制开关连接数据信号，第一控制开关和第二控制开关的控制端均连接第一扫描信号；第三像素区包括第三像素电极和第三控制开关，第三像素电极依次通过第三控制开关和第二控制开关连接数据信号，第三像素电极还通过第三控制开关连接第二像素电极，第三控制开关的控制端连接第二扫描信号，液晶显示面板的驱动方法包括：利用第一扫描信号控制第一控制开关和第二控制开关导通；利用数据信号为第一像素区和第二像素区充电以使得第一像素电极与第二像素电极形成第一等电位V1;利用第二扫描信号控制第三控制开关导通，使得第三像素电极与第二像素电极导通以让第二像素电极与第三像素电极形成不同于第一等电位V1的第二等电位V2。
其中，像素结构进一步包括：相对设置的阵列基板、彩膜基板以及夹持在阵列基板和彩膜基板之间的液晶层，阵列基板上包括依次设置在第一像素电极和第二像素电极的下方的绝缘层和存储电容电极，彩膜基板上设置有公共电极，第一像素区、第二像素区以及第三像素区设置在阵列基板上，第三像素电极和公共电极之间以液晶层为介质形成分压液晶电容CL，第一像素电极和公共电极之间以液晶层为介质形成第一液晶电容CL1，第一像素电极和存储电容电极之间以绝缘层为介质形成第一存储电容Cs1，第二像素电极和公共电极之间以液晶层为介质形成第二液晶电容CL2，第二像素电极和存储电容电极之间以绝缘层为介质形成第二存储电容Cs2，第一等电位V1与第二等电位V1的关系为：V2=V1（CL2 +Cs2）/( CL2 +Cs2 +2CL）。
其中，公共电极连接第一公共电压，存储电容电极连接第二公共电压。
本发明的有益效果是：区别于现有技术的情况，本发明通过增加设置第三像素区，利用第三像素电极和公共电极之间形成的分压液晶电容将第二像素区的电位拉低，使得第一像素区的电位与第二子像素区的电位不同，从而在不降低开口率的情况下实现低色偏效果，能够避免大视角颜色失真。
【附图说明】
图1是本发明像素结构的优选实施例的剖面结构示意图；
图2是本发明像素结构的电路结构示意图；
图3是本发明液晶显示面板的结构示意图；
图4是本发明的液晶显示面板的驱动方法的流程示意图。
【具体实施方式】
下面结合附图和实施例对本发明进行详细的说明。
请参阅图1，图1是本发明像素结构的优选实施例的剖面结构示意图。在本实施例中，像素结构10优选为包括：阵列基板11、液晶层12以及彩膜基板13。其中，阵列基板11和彩膜基板13相对设置，液晶层12夹持在阵列基板11和彩膜基板13之间。
本发明像素结构10具有结构相同、用于显示不同色彩的多个像素14a，14b，14c，14d，其中，每个像素包括相邻设置的第一像素区141、第二像素区142以及第三像素区143。
第一像素区141、第二像素区142以及第三像素区143设置在阵列基板11上，阵列基板11上还设置有存储电容电极15和绝缘层16。其中，存储电容电极15设置在第一像素区141和第二像素区142下方，绝缘层16覆盖在存储电容电极15上。
彩膜基板13包括一公共电极17，其设置在彩膜基板13下表面。
请一并参阅图1和图2，图2是本发明像素结构的电路结构示意图。在本实施例中，阵列基板11上设置有多条扫描线S1 ~SN 以及多条数据线D1 ~DN 。多条扫描线S1 ~SN 横向设置，多条数据线D1 ~DN 纵向设置，扫描线和数据线彼此垂直相交。在其他实施例中，扫描线和数据线也可以不垂直。
下面以图1中所示的第n个像素14c为例进行说明。
第n个像素14c包括第一像素区141、第二像素区142、第三像素区143。第n个像素14c的第一像素区141设置在第n-1条扫描线Sn-1 、第n条扫描线Sn、第n条数据线Dn 以及第n+1条数据线Dn+1 所围成的区域内。第n个像素14c的第二像素区142设置在第n条扫描线Sn 、第n+1条扫描线Sn+1 、第n条数据线Dn 以及第n+1条数据线Dn+1 所围成的区域内。第n个像素14c的第三像素区143设置在第n+1条扫描线Sn+1 、第n+2条扫描线Sn+2 、第n条数据线Dn 以及第n+1条数据线Dn+1 所围成的区域内。
第一像素区141包括第一像素电极21和第一控制开关T1，第一像素电极21通过第一控制开关T1连接数据信号。在本实施例中，第一控制开关T1优选为第一薄膜晶体管T1，第一像素电极21连接第一薄膜晶体管T1的漏极，第一薄膜晶体管T1的源极连接数据信号，第一薄膜晶体管T1的栅极为其控制端且连接第一扫描信号，第n条数据线Dn 用于提供第n个像素14c的数据信号，即第一薄膜晶体管T1的源极连接第n条数据线Dn 。第n条扫描线Sn 用于提供第n个像素14c的第一扫描信号，即第一薄膜晶体管T1的栅极连接第n条扫描线Sn 。
第二像素区142包括第二像素电极22和第二控制开关T2，第二像素电极22通过第二控制开关T2连接数据信号。在本实施例中，第二控制开关T2优选为第二薄膜晶体管T2。第二像素电极22连接第二薄膜晶体管T2的漏极，第二薄膜晶体管T2的源极连接数据信号，第二薄膜晶体管T2的栅极为其控制端且连接第一扫描信号。第n条数据线Dn 用于提供第n个像素14c的数据信号，即第二薄膜晶体管T2的源极连接第n条数据线Dn 。第n条扫描线Sn 用于提供第n个像素14c的第一扫描信号，即第二薄膜晶体管T2的栅极连接第n条扫描线Sn 。
第三像素区143包括第三像素电极23和第三控制开关T3，第三像素电极23依次通过第三控制开关T3和第二控制开关T2连接数据信号，第三像素电极23还通过第三控制开关T3连接第二像素电极22。在本实施例中，第三控制开关T3优选为第三薄膜晶体管T3，第三像素电极T3连接第三薄膜晶体管T3的漏极，第三薄膜晶体管T3的源极连接第二薄膜晶体管T2的漏极，第三薄膜晶体管T3的栅极为其控制端且连接第二扫描信号，第n+1条扫描线Sn+1 提供第n个像素14c的第二扫描信号，即第三薄膜晶体管T3的栅极连接第n+1条扫描线Sn+1 。
值得注意的是，在本实施例中，第n个像素14c的第二扫描信号与第n+1个像素14d的第一扫描信号优选为同一信号，即第n+1条扫描线Sn+1 和第n+2条扫描线Sn+2 连接同一用于产生扫描信号的驱动IC的扫描线端，进而可以节约成本。在其他实施例中，第n个像素14c的第二扫描信号与第n+1个像素14d的第一扫描信号也可以不是同一信号，即第n+1条扫描线Sn+1 和第n+2条扫描线Sn+2 连接的也可以不是同一驱动IC。在其他实施例中，第n个像素14c的第二扫描信号和第n+1个像素14d的第一扫描信号也可以都是由第n+1条扫描线Sn+1 提供。
公共电极17连接第一公共电压VC1，存储电容电极15连接第二公共电压VC2。第三像素电极23和公共电极17之间以液晶层12为介质形成分压液晶电容CL。第一像素电极21和公共电极17之间以液晶层15为介质形成第一液晶电容CL1，第一像素电极21和存储电容电极15之间以绝缘层16为介质形成第一存储电容Cs1。第二像素电极22和公共电极17之间以液晶层12为介质形成第二液晶电容CL2，第二像素电极22和存储电容电极15之间以绝缘层16为介质形成第二存储电容Cs2。分压液晶电容CL用于在第一薄膜晶体管T1、第二薄膜晶体管T2、以及第三薄膜晶体管T3均导通时降低第二像素电极21的电位以使得第一像素电极21和第二像素电极22的电位不同。第一薄膜晶体管T1导通指其源极和漏极之间导通，同样第二薄膜晶体管T2和第三薄膜晶体管T3导通指源极和漏极之间导通。
下面结合附图和实施例说明本发明像素结构的工作原理。
如图2所示，同样以第n个像素14c为例进行说明。当第n条扫描线Dn上的第一扫描信号控制第一薄膜晶体管T1和第二薄膜晶体管T2导通且第n+1条扫描线Dn+1上的第二扫描信号控制第三薄膜晶体管T3截至时，第一像素电极21和第二像素电极22之间形成第一等电位V1（图2中V1处电位）；随后，当第二扫描信号控制第三薄膜晶体管T3导通时，分压液晶电容CL上积累电荷，为第二像素电极22分担部分电压，使得第一像素电极21与第二像素电极22电位不同，达到传统低色偏像素结构设计的要求。
具体而言，在本实施例中，此时第二像素电极21和第三像素电极22之间形成第二等电位V2（图2中V2处电位）。由电容分压公式可以得到，第一等电位V1和第二等电位V2之间的关系为：
V2=V1（CL2 +Cs2）/( CL2 +Cs2 +2CL） （1）
由式（1）可知：V2<V1，即第一像素电极21电位与第二像素电极21电位不同，达到了传统低色偏像素结构设计的要求，即当第一像素电极21电位与第二像素电极22电位不同时，液晶显示面板在大视角观看时颜色失真会减小。本实施例未在阵列基板11上另外设置电容，因此也不会影响液晶显示面板的开口率。
请参阅图3，图3是本发明液晶显示面板的结构示意图。在本实施例中，液晶显示面板包括：像素结构10、第一偏光板18以及第二偏光板19。其中，像素结构10为上述任意一实施例所述的像素结构10。第一偏光板18设置在阵列基板11下方，第二偏光板19设置在彩膜基板13的上方。
请参阅图4，图4是本发明的液晶显示面板的驱动方法的流程示意图。
步骤S41：利用第一扫描信号控制第一控制开关和第二控制开关导通。
步骤S42：利用数据信号为第一像素区和第二像素区充电以使得第一像素电极与第二像素电极形成第一等电位V1。
步骤S43：利用第二扫描信号控制第三控制开关导通，使得第三像素电极与第二像素电极导通以让第二像素电极与第三像素电极形成不同于第一等电位V1的第二等电位V2。
区别于现有技术，本发明通过增加设置第三像素区，利用第三像素电极和公共电极之间形成的分压液晶电容将第二像素区的电位拉低，使得第一像素区的电位与第二子像素区的电位不同，从而能够在不降低开口率的情况下实现低色偏效果，能够避免大视角颜色失真。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种像素结构，其中，所述像素结构包括矩阵排列的多个像素，每一像素包括相邻设置的第一像素区、第二像素区以及第三像素区，其中：
    所述第一像素区包括第一像素电极和第一控制开关，所述第一像素电极通过所述第一控制开关连接数据信号；
    所述第二像素区包括第二像素电极和第二控制开关，所述第二像素电极通过所述第二控制开关连接所述数据信号，所述第一控制开关和所述第二控制开关的控制端均连接第一扫描信号；
    所述第三像素区包括第三像素电极和第三控制开关，所述第三像素电极依次通过所述第三控制开关和所述第二控制开关连接所述数据信号，所述第三控制开关的控制端连接第二扫描信号，所述第三像素电极还通过所述第三控制开关连接所述第二像素电极以在所述第一控制开关、所述第二控制开关以及所述第三控制开关均导通时使得所述第一像素电极和所述第二像素电极的电位不同。
  2. 根据权要求1所述的像素结构，其中，所述像素结构包括相对设置的阵列基板、彩膜基板以及夹持在所述阵列基板和所述彩膜基板之间的液晶层，其中，所述第一像素区、所述第二像素区以及所述第三像素区设置在所述阵列基板上，所述彩膜基板上设置有公共电极，所述第三像素电极和所述公共电极之间以所述液晶层为介质形成分压液晶电容，所述分压液晶电容用于在所述第一控制开关、所述第二控制开关、以及所述第三控制开关均导通时降低所述第二像素电极的电位以使得所述第一像素电极和所述第二像素电极的电位不同。
  3. 根据权利要求2所述的像素结构，其中，所述阵列基板上还包括依次设置在所述第一像素电极和所述第二像素电极的下方的绝缘层和存储电容电极，其中：
    所述第一像素电极和所述公共电极之间以所述液晶层为介质形成第一液晶电容，所述第一像素电极和所述存储电容电极之间以所述绝缘层为介质形成第一存储电容；
    所述第二像素电极和所述公共电极之间以所述液晶层为介质形成第二液晶电容，所述第二像素电极和所述存储电容电极之间以所述绝缘层为介质形成第二存储电容，所述公共电极连接第一公共电压，所述存储电容连接第二公共电压。
  4. 根据权利要求1所述的像素结构，其中，所述第一控制开关为第一薄膜晶体管，所述第二控制开关为第二薄膜晶体管，所述第三控制开关为第三薄膜晶体管，所述第一像素电极连接所述第一薄膜晶体管的漏极，所述第一薄膜晶体管的源极连接所述数据信号，所述第一薄膜晶体管的栅极连接所述第一扫描信号，所述第二像素电极连接所述第二薄膜晶体管的漏极，所述第二薄膜晶体管的源极连接所述数据信号，所述第二薄膜晶体管的栅极连接所述第一扫描信号，所述第三像素电极连接所述第三薄膜晶体管的漏极，所述第三薄膜晶体管的源极连接所述第二薄膜晶体管的漏极，所述第三薄膜晶体管的栅极连接所述第二扫描信号。
  5. 根据权利要求2所述的像素结构，其中，所述阵列基板上进一步包括横向设置的多条扫描线和纵向设置的多条数据线，所述扫描线均与所述数据线相交，其中：
    第n个像素的第一像素区设置在第n-1条扫描线、第n条扫描线、第n条数据线以及第n+1条数据线所围成的区域内；
    所述第n个像素的第二像素区设置在所述第n条扫描线、第n+1条扫描线、所述第n条数据线以及所述第n+1条数据线所围成的区域内；
    所述第n个像素的第三像素区设置在所述第n+1条扫描线、第n+2条扫描线、所述第n条数据线以及所述第n+1条数据线所围成的区域内；
    所述第n条数据线用于提供所述第n个像素的数据信号，所述第n条扫描线用于提供所述第n个像素的第一扫描信号，所述第n+1条扫描线提供所述第n个像素的第二扫描信号。
  6. 根据权利要求5所述的像素结构，其中，第n个像素的第二扫描信号与第n+1个像素的第一扫描信号为同一信号。
  7. 一种液晶显示面板，其中，所述液晶显示面板包括像素结构，所述像素结构包括矩阵排列的多个像素，每一像素包括相邻设置的第一像素区、第二像素区以及第三像素区，其中：
    所述第一像素区包括第一像素电极和第一控制开关，所述第一像素电极通过所述第一控制开关连接数据信号；
    所述第二像素区包括第二像素电极和第二控制开关，所述第二像素电极通过所述第二控制开关连接所述数据信号，所述第一控制开关和所述第二控制开关的控制端均连接第一扫描信号；
    所述第三像素区包括第三像素电极和第三控制开关，所述第三像素电极依次通过所述第三控制开关和所述第二控制开关连接所述数据信号，所述第三控制开关的控制端连接第二扫描信号，所述第三像素电极还通过所述第三控制开关连接所述第二像素电极以在所述第一控制开关、所述第二控制开关以及所述第三控制开关均导通时使得所述第一像素电极和所述第二像素电极的电位不同。
  8. 根据权要求7所述的液晶显示面板，其中，所述像素结构包括相对设置的阵列基板、彩膜基板以及夹持在所述阵列基板和所述彩膜基板之间的液晶层，其中，所述第一像素区、所述第二像素区以及所述第三像素区设置在所述阵列基板上，所述彩膜基板上设置有公共电极，所述第三像素电极和所述公共电极之间以所述液晶层为介质形成分压液晶电容，所述分压液晶电容用于在所述第一控制开关、所述第二控制开关、以及所述第三控制开关均导通时降低所述第二像素电极的电位以使得所述第一像素电极和所述第二像素电极的电位不同。
  9. 根据权利要求8所述的液晶显示面板，其中，所述阵列基板上还包括依次设置在所述第一像素电极和所述第二像素电极的下方的绝缘层和存储电容电极，其中：
    所述第一像素电极和所述公共电极之间以所述液晶层为介质形成第一液晶电容，所述第一像素电极和所述存储电容电极之间以所述绝缘层为介质形成第一存储电容；
    所述第二像素电极和所述公共电极之间以所述液晶层为介质形成第二液晶电容，所述第二像素电极和所述存储电容电极之间以所述绝缘层为介质形成第二存储电容，所述公共电极连接第一公共电压，所述存储电容连接第二公共电压。
  10. 根据权利要求7所述的液晶显示面板，其中，所述第一控制开关为第一薄膜晶体管，所述第二控制开关为第二薄膜晶体管，所述第三控制开关为第三薄膜晶体管，所述第一像素电极连接所述第一薄膜晶体管的漏极，所述第一薄膜晶体管的源极连接所述数据信号，所述第一薄膜晶体管的栅极连接所述第一扫描信号，所述第二像素电极连接所述第二薄膜晶体管的漏极，所述第二薄膜晶体管的源极连接所述数据信号，所述第二薄膜晶体管的栅极连接所述第一扫描信号，所述第三像素电极连接所述第三薄膜晶体管的漏极，所述第三薄膜晶体管的源极连接所述第二薄膜晶体管的漏极，所述第三薄膜晶体管的栅极连接所述第二扫描信号。
  11. 根据权利要求8所述的液晶显示面板，其中，所述阵列基板上进一步包括横向设置的多条扫描线和纵向设置的多条数据线，所述扫描线均与所述数据线相交，其中：
    第n个像素的第一像素区设置在第n-1条扫描线、第n条扫描线、第n条数据线以及第n+1条数据线所围成的区域内；
    所述第n个像素的第二像素区设置在所述第n条扫描线、第n+1条扫描线、所述第n条数据线以及所述第n+1条数据线所围成的区域内；
    所述第n个像素的第三像素区设置在所述第n+1条扫描线、第n+2条扫描线、所述第n条数据线以及所述第n+1条数据线所围成的区域内；
    所述第n条数据线用于提供所述第n个像素的数据信号，所述第n条扫描线用于提供所述第n个像素的第一扫描信号，所述第n+1条扫描线提供所述第n个像素的第二扫描信号。
  12. 根据权利要求11所述的像素结构，其中，第n个像素的第二扫描信号与第n+1个像素的第一扫描信号为同一信号。
  13. 一种液晶显示面板的驱动方法，其中，所述液晶显示面板包括像素结构，所述像素结构包括矩阵排列的多个像素，每一像素包括相邻设置的第一像素区、第二像素区以及第三像素区，其中所述第一像素区包括第一像素电极和第一控制开关，所述第一像素电极通过所述第一控制开关连接数据信号；所述第二像素区包括第二像素电极和第二控制开关，所述第二像素电极通过所述第二控制开关连接所述数据信号，所述第一控制开关和所述第二控制开关的控制端均连接第一扫描信号；所述第三像素区包括第三像素电极和第三控制开关，所述第三像素电极依次通过所述第三控制开关和所述第二控制开关连接所述数据信号，所述第三像素电极还通过所述第三控制开关连接所述第二像素电极，所述第三控制开关的控制端连接第二扫描信号，其中，所述液晶显示面板的驱动方法包括：
    利用所述第一扫描信号控制所述第一控制开关和所述第二控制开关导通；
    利用所述数据信号为所述第一像素区和所述第二像素区充电以使得所述第一像素电极与所述第二像素电极形成第一等电位V1;
    利用所述第二扫描信号控制所述第三控制开关导通，使得所述第三像素电极与所述第二像素电极导通以让所述第二像素电极与所述第三像素电极形成不同于所述第一等电位V1的第二等电位V2。
  14. 根据权利要求13所述的液晶显示面板的驱动方法，其中，所述像素结构进一步包括：相对设置的阵列基板、彩膜基板以及夹持在所述阵列基板和所述彩膜基板之间的液晶层，所述阵列基板上包括依次设置在所述第一像素电极和所述第二像素电极的下方的绝缘层和存储电容电极，所述彩膜基板上设置有公共电极，所述第一像素区、所述第二像素区以及所述第三像素区设置在所述阵列基板上，所述第三像素电极和所述公共电极之间以所述液晶层为介质形成分压液晶电容CL，所述第一像素电极和所述公共电极之间以所述液晶层为介质形成第一液晶电容CL1，所述第一像素电极和所述存储电容电极之间以所述绝缘层为介质形成第一存储电容Cs1，所述第二像素电极和所述公共电极之间以所述液晶层为介质形成第二液晶电容CL2，所述第二像素电极和所述存储电容电极之间以所述绝缘层为介质形成第二存储电容Cs2，所述第一等电位V1与所述第二等电位V1的关系为：V2=V1（CL2 +Cs2）/( CL2 +Cs2 +2CL）。
  15. 根据权利要求13所述的液晶显示面板的驱动方法，其中，所述公共电极连接第一公共电压，所述存储电容电极连接第二公共电压。
PCT/CN2013/078355 2013-05-31 2013-06-28 液晶显示面板及其像素结构和驱动方法 WO2014190585A1 (zh)

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