WO2020093539A1 - 阵列基板、显示面板以及显示装置 - Google Patents

阵列基板、显示面板以及显示装置 Download PDF

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Publication number
WO2020093539A1
WO2020093539A1 PCT/CN2018/122110 CN2018122110W WO2020093539A1 WO 2020093539 A1 WO2020093539 A1 WO 2020093539A1 CN 2018122110 W CN2018122110 W CN 2018122110W WO 2020093539 A1 WO2020093539 A1 WO 2020093539A1
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WIPO (PCT)
Prior art keywords
metal layer
layer
array substrate
electrode layer
electrode
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PCT/CN2018/122110
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English (en)
French (fr)
Inventor
林佩欣
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Application filed by 惠科股份有限公司, 重庆惠科金渝光电科技有限公司 filed Critical 惠科股份有限公司
Priority to US16/293,673 priority Critical patent/US20200152670A1/en
Publication of WO2020093539A1 publication Critical patent/WO2020093539A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present application relates to the technical field of display devices, and in particular, to an array substrate, a display panel, and a display device.
  • the process architecture of the display screen is divided by drive design, which can be divided into chip drive (System on chip, SOC for short) and array drive (Gate driver on array, referred to as GOA) Two kinds.
  • GOA is an important technology in panel design. It uses array exposure and development to form the gate drive on the glass, and then generates a logic circuit to drive the gate signal line, that is, the gate drive circuit. , Avoiding the introduction of gate drivers, which can effectively reduce the cost of liquid crystal display panels, therefore, the display screen driven by GOA has been widely used.
  • the GOA circuit For the GOA circuit, it must be equipped with a storage capacitor to maintain the voltage of each pixel area after the transistor is turned off, thereby providing a response time for the liquid crystal.
  • the storage capacitor has a first metal layer in the same layer as the gate layer, a second metal layer in the same layer as the source and drain layers, and an interlayer sandwiched between the first metal layer and the second metal layer The electrical layers are formed together.
  • PPI Pixel Per Inch
  • the main purpose of the present application is to propose an array substrate, which aims to solve the technical problem that the GOA driving circuit in the prior art cannot increase the capacity of the storage capacitor by increasing the plane area of the storage capacitor, but cannot meet the narrow border requirement of display products.
  • the array substrate proposed by the present application includes a gate driving circuit, and the gate driving circuit includes:
  • a second metal layer located on one side of the first metal layer
  • a dielectric layer is provided between the first metal layer and the second metal layer;
  • An electrode layer located on a side of the second metal layer away from the first metal layer; the electrode layer is electrically connected to the first metal layer;
  • the electrode layer and the second metal layer are at least partially overlapped to form a first storage capacitor of the gate driving circuit, and the thickness of the insulating layer is less than Describe the thickness of the dielectric layer.
  • the thickness of the insulating layer is 1/3 ⁇ 3/5 of the dielectric layer.
  • the thickness of the insulating layer ranges from 1000 ⁇ m to 3000 ⁇ m.
  • the projected area of the electrode layer completely covers the projected area of the second metal layer.
  • one end of the projection of the electrode layer is flush with the second metal layer, and the other end protrudes from the second metal layer.
  • the projected area of the electrode layer is equal to the projected area of the second metal layer.
  • the first metal layer and the second metal layer are at least partially overlapped to form a second storage capacitor of the gate driving circuit.
  • the projected area of the first metal layer completely covers the projected area of the second metal layer.
  • one end of the projection of the first metal layer is flush with the second metal layer, and the other end protrudes from the second metal layer.
  • the projected area of the first metal layer is equal to the projected area of the second metal layer.
  • the insulating layer and the dielectric layer are provided with conductive vias spaced apart from the second metal layer, and the electrode layer is electrically connected to the first metal layer via the conductive vias.
  • the insulating layer is made of silicone material.
  • the first metal layer is formed synchronously with the gate layer of the gate driving circuit
  • the second metal layer is formed synchronously with the source-drain layer composed of the source and drain.
  • the present application also proposes a display panel including an array substrate, the array substrate including: a gate drive circuit, the gate drive circuit including:
  • a dielectric layer is provided between the first metal layer and the second metal layer;
  • An electrode layer located on a side of the second metal layer away from the first metal layer; the electrode layer is electrically connected to the first metal layer;
  • the electrode layer and the second metal layer are at least partially overlapped to form a first storage capacitor of the gate drive circuit, and the thickness of the insulating layer is less Describe the thickness of the dielectric layer.
  • the present application also proposes a display device including a display panel, the display panel including an array substrate, the array substrate including: a gate drive circuit, the gate drive circuit including:
  • a dielectric layer is provided between the first metal layer and the second metal layer;
  • An electrode layer located on a side of the second metal layer away from the first metal layer; the electrode layer is electrically connected to the first metal layer;
  • the electrode layer and the second metal layer are at least partially overlapped to form a first storage capacitor of the gate driving circuit, and the thickness of the insulating layer is less than Describe the thickness of the dielectric layer.
  • the thickness of the insulating layer ranges from 1000 ⁇ m to 3000 ⁇ m.
  • the projected area of the electrode layer completely covers the projected area of the second metal layer.
  • the first metal layer and the second metal layer are at least partially overlapped to form a second storage capacitor of the gate driving circuit.
  • the insulating layer and the dielectric layer are provided with conductive vias spaced apart from the second metal layer, and the electrode layer is electrically connected to the first metal layer via the conductive vias.
  • an electrode layer is provided on a side of the second metal layer away from the first metal layer, and an insulating layer (thickness less than the dielectric layer) is provided on the second metal layer and the electrode layer.
  • the electrode layer and the first metal layer Are electrically connected, and the electrode layer and the second metal layer are at least partially overlapped.
  • the first storage capacitor forming the gate drive circuit between the electrode layer and the second metal layer uses the first metal layer compared to the exemplary technology
  • the method of forming a storage capacitor with the second metal layer because the thickness of the insulating layer in this embodiment is smaller than the dielectric layer between the first metal layer and the second metal layer, so it is conducive to increasing the capacitance of the storage capacitor.
  • the planar area of the storage capacitor in this embodiment is smaller, thereby reducing the occupation of the planar area outside the display area of the liquid crystal display device by the storage capacitor, which is beneficial to realize the narrow border of the liquid crystal display device.
  • FIG. 1 is a schematic cross-sectional view of an embodiment of an array substrate of the present application.
  • first”, “second”, etc. are for descriptive purposes only, and cannot be understood as instructions or hints Its relative importance or implicitly indicates the number of technical features indicated.
  • the features defined with “first” and “second” may include at least one of the features either explicitly or implicitly.
  • the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of those skilled in the art to realize. When the combination of technical solutions contradicts or cannot be realized, it should be considered that the combination of such technical solutions does not exist , Nor within the scope of protection required by this application.
  • the present application proposes an array substrate, which is applied to a liquid crystal display panel.
  • the liquid crystal display panel includes a color filter substrate and an array substrate that are arranged at intervals, and a liquid crystal filled between the two substrates.
  • the liquid crystal is located on the array substrate and The liquid crystal cell formed by superimposing the color film substrates.
  • the liquid crystal display panel can be applied to liquid crystal televisions, liquid crystal displays, etc. The design is not limited to this.
  • an array substrate includes a plurality of data lines arranged in a vertical direction, a plurality of scan lines arranged in a lateral direction, and a plurality of pixel areas defined by scan line and data lines.
  • Each pixel area is connected to a corresponding data line and a scanning line
  • each scanning line is connected to a gate driving circuit to provide a scanning voltage to each pixel area
  • each data line is connected to a source driving circuit to each pixel
  • the area provides gray-scale voltage.
  • the gate driving circuit includes a TFT, a storage capacitor, and a liquid crystal capacitor.
  • the liquid crystal capacitor is located in the pixel electrode of the pixel area, the common electrode on the color film substrate side, and the liquid crystal between the two.
  • the TFFs in the same row are simultaneously turned on, and after a certain time, the TFTs in the next row are simultaneously turned on, and so on. Since the TFT turn-on time of each row is relatively short, the time for the liquid crystal capacitor to charge and control the deflection of the liquid crystal is short, it is difficult to reach the response time of the liquid crystal, the storage capacitor can maintain the voltage of each pixel area after the TFT is turned off, thereby providing time for the liquid crystal response .
  • the storage capacitor passes through a first metal layer in the same layer as the gate layer, a second metal layer in the same layer as the source and drain layers, and an intermediary sandwiched between the first metal layer and the second metal layer
  • the electrical layers are formed together.
  • the capacitance of the storage capacitor is proportional to the planar area of the first metal layer and the second metal layer, and The thickness between the second metal layers is inversely proportional.
  • the gate driving circuit of the array substrate includes:
  • the first metal layer 1 The first metal layer 1;
  • the second metal layer 2 is located on one side of the first metal layer 1;
  • the dielectric layer 3 is disposed between the first metal layer 1 and the second metal layer 2;
  • the electrode layer 4 is located on the side of the second metal layer 2 away from the first metal layer 1; the electrode layer 4 is electrically connected to the first metal layer 1; and
  • the insulating layer 5 is provided between the electrode layer 4 and the second metal layer 2; wherein,
  • the electrode layer 4 and the second metal layer 2 are at least partially overlapped to form a first storage capacitor of the gate driving circuit, and the thickness of the insulating layer 5 is smaller than the thickness of the dielectric layer 3.
  • the first metal layer 1 is formed synchronously with the gate layer of the gate driving circuit
  • the second metal layer 2 is formed synchronously with the source-drain layer composed of the source and the drain
  • the dielectric layer 3 and the gate layer It is formed synchronously with the passivation layer between the source and drain layers.
  • the first metal layer 1 is located on the lower side of the second metal layer 2 to form a bottom gate TFT structure.
  • the bottom gate TFT structure is a TFT structure widely used in the prior art. It has the advantages of stable structure and simple design.
  • the first metal layer 1 can also be located on the upper side of the second metal layer 2 to form a top-gate TFT structure. The design is not limited to this.
  • an electrode layer 4 is added on the upper side of the second metal layer 2, and an insulating layer 5 (thickness less than the dielectric layer 3) is provided between the electrode layer 4 and the second metal layer 2 ,
  • the electrode layer 4 and the first metal layer 1 are electrically connected, and the electrode layer 4 and the second metal layer 2 are at least partially overlapped to form a first storage capacitor between the electrode layer 4 and the second metal layer 2.
  • the first storage capacitor When the capacitance of the battery is the same as the original storage capacitor, the plane area of the plates of the first storage capacitor (electrode layer 4 and second metal layer 2) is smaller than the plane area of the plates of the original storage capacitor, which is conducive to reducing storage
  • the capacitance occupies the plane of the liquid crystal display device, realizing the narrow frame design of the liquid crystal display device.
  • the insulating layer 5 and the dielectric layer 3 are provided with conductive vias 6 spaced apart from the second metal layer 2, and the electrode layer 4 is electrically connected to the first metal layer 1 via the conductive vias 6.
  • Opening conductive vias 6 on the array substrate to achieve the conductivity of different interlayers is a common technical method in the art, which has the advantages of simple process and stable conductivity.
  • the electrode layer 4 and the first The metal layer 1 can also be electrically connected by other means, and the design is not limited to this.
  • the technical solution of the present application is to provide an electrode layer 4 on the side of the second metal layer 2 away from the first metal layer 1 and an insulating layer 5 (thickness less than the dielectric layer 3) on the second metal layer 2 and the electrode layer 4
  • the electrode layer 4 is electrically connected to the first metal layer 1, and the electrode layer 4 and the second metal layer 2 are at least partially overlapped.
  • the first storage capacitor of the gate drive circuit is formed between the electrode layer 4 and the second metal layer 2 Compared with the method of forming the storage capacitor using the first metal layer 1 and the second metal layer 2 in the exemplary technology, since the thickness of the insulating layer 5 in this embodiment is smaller than that between the first metal layer 1 and the second metal layer 2
  • the dielectric layer 3 of this embodiment is beneficial to increase the capacitance of the storage capacitor, which is equivalent to keeping the same capacitance, the planar area of the storage capacitor in this embodiment is smaller, thereby reducing the storage capacitor to the liquid crystal display device
  • the occupation of the plane area outside the display area is beneficial to realize the narrow frame of the liquid crystal display device.
  • the thickness of the insulating layer 5 is 1/3 ⁇ 3/5 of the dielectric layer 3; it can be understood that the thickness of the insulating layer 5 is in an appropriate range relative to the dielectric layer 3, in order to both increase the capacity of the storage capacitor and avoid the storage capacitor The plane area is too large, and the process of the array substrate is prevented from being too difficult, so that the processing of the array substrate is too difficult. It should be noted that the design is not limited to this. In other embodiments, the thickness of the insulating layer 5 may also be other ratios where the dielectric layer 3 is less than 1. In particular, in this embodiment, the thickness of the insulating layer 5 ranges from 1000 ⁇ m to 3000 ⁇ m.
  • the storage capacitor is guaranteed to have a large capacitance, on the other hand, the conductive condition between the second metal layer 2 and the electrode layer 4 is prevented.
  • the insulating layer 5 is made of silicone material. It can be understood that the silicone material is an insulating material widely used in the prior art, which has the advantages of easy availability and low price. It should be noted that this design is not limited to this. In other embodiments, the insulating layer 5 may also be made of other materials such as plastic.
  • the plane area of the electrode layer 4 is set to be larger than the second metal layer 2, and the conductive via 6 is located in the second metal layer
  • the front side of the electrode 2, the front side of the electrode layer 4 also protrudes out of the second metal layer 2
  • the projected area of the electrode layer 4 along the vertical direction is also It completely falls within the projected area of the second metal layer 2, that is, the electrode layer 4 and the second metal layer 2 are completely overlapped in the vertical direction.
  • the design is not limited to this. In other embodiments, the projections of the second metal layer 2 and the electrode layer 4 in the vertical direction may only be partially overlapped with each other.
  • the idea of the present application is to use the second metal layer 2, the electrode layer 4 and the insulating layer 5 to form a storage capacitor with a smaller electrode plate spacing, thereby reducing the planar area of the storage capacitor under the condition of satisfying the same capacitance; understandable No matter whether there is a storage capacitor between the first metal layer 1 and the second metal layer 2, it should belong to the protection scope of the present application.
  • the first metal layer 1 and the second metal layer 2 are at least partially overlapped to form a gate
  • the second storage capacitor of the driving circuit it can be understood that the second storage capacitor and the first storage capacitor are arranged in series, and the total capacitance after the series connection is bound to be greater than the first storage capacitor. Therefore, the capacitance of the storage capacitor of the gate drive circuit is obtained Improve better.
  • the plane area of the first metal layer 1 is set to be larger than the second metal layer 2, and the conductive via 6 is located
  • the front side of the second metal layer 2 and the front side of the first metal layer 1 also protrude from the second metal layer 2.
  • the first The projected area of the metal layer 1 in the vertical direction also completely falls within the projected area of the second metal layer 2, that is, the first metal layer 1 and the second metal layer 2 are completely overlapped in the vertical direction.
  • the present design is not limited to this. In other embodiments, the projections of the first metal layer 1 and the electrode layer 4 in the vertical direction may only be partially overlapped with each other.
  • the present application also proposes a display device including a display panel, and the display panel includes an array substrate.
  • the specific structure of the array substrate refers to the above embodiments. Since the display device adopts all the technical solutions of all the above embodiments, at least All the beneficial effects brought by the technical solutions of the above embodiments will not be repeated here.

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Abstract

一种阵列基板、显示面板以及显示装置，阵列基板的第二金属层（2）与电极层（4）之间形成有间距较小的第一存储电容。

Description

阵列基板、显示面板以及显示装置
相关申请
本申请要求2018年11月08日申请的，申请号为201821840986.3，名称为“阵列基板、显示面板以及显示装置”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及显示装置技术领域，特别涉及一种阵列基板、显示面板以及显示装置。
背景技术
显示屏的工艺架构，以驱动设计来划分，可以分为芯片驱动(System on chip，简称SOC)和阵列驱动 (Gate driver on array，简称GOA) 两种。然而，GOA在面板设计上是一项重要技术，其利用阵列（array）曝光显影方式，将栅极驱动成型在玻璃上，进而产生逻辑电路以驱动栅极讯号线，即栅极驱动电路，如此，避免了引入栅极驱动器，能有效降低液晶显示面板的成本，因此，采用GOA驱动的显示屏得到了广泛的应用。
对于GOA电路而言，其必须配备有存储电容，以在晶体管关闭后维持各个像素区域的电压，从而为液晶提供响应时间。现有技术中，该存储电容通过与栅极层同层的第一金属层、与源漏极层同层的第二金属层以及夹持于第一金属层、第二金属层之间的介电层共同形成，随着如今液晶显示产品像素数目（Pixels Per Inch，简称PPI）的提高，对存储电容的容量也提出了更高的要求，由存储电容的公式Holding C=ε0εrA/d 可知，由于第一金属层和第二金属层之间的距离d（即介电层的厚度较大），以致为了获得较大的存储电容容量，只能尽量增大第一金属层和第二金属层的平面面积A，然而，第一金属层和第二金属层占用过大的平面面积，又会与液晶显示产品的窄边框需求产生冲突。
综上，基于液晶显示产品高解析度和窄边框的需求，仍未需找到合适的GOA存储电容设计。
申请内容
本申请的主要目的是提出一种阵列基板，旨在解决现有技术中GOA驱动电路通过增大存储电容的平面面积以增大电容容量，而无法满足显示产品的窄边框需求的技术问题。
为实现上述目的，本申请提出的阵列基板，包括栅极驱动电路，所述栅极驱动电路包括：
第一金属层；
第二金属层，位于所述第一金属层的一侧；
介电层，设于所述第一金属层与第二金属层之间；
电极层，位于所述第二金属层远离第一金属层的一侧；所述电极层与所述第一金属层电连接；以及
绝缘层，设于所述电极层与所述第二金属层之间；其中，
在垂直所述阵列基板板面的方向上，所述电极层与所述第二金属层至少部分重叠设置，以形成所述栅极驱动电路的第一存储电容，所述绝缘层的厚度小于所述介电层的厚度。
可选地，所述绝缘层的厚度为所述介电层的1/3~3/5。
可选地，所述绝缘层的厚度范围为1000μm~3000μm。
可选地，在垂直所述阵列基板板面的方向上，所述电极层的投影面积完全覆盖所述第二金属层的投影面积。
可选地，在垂直所述阵列基板板面的方向上，所述电极层的投影一端与所述第二金属层平齐、另一端凸出于所述第二金属层设置。
可选地，在垂直所述阵列基板板面的方向上，所述电极层的投影面积等于所述第二金属层的投影面积。
可选地，在垂直所述阵列基板板面的方向上，所述第一金属层与所述第二金属层至少部分重叠设置，以形成所述栅极驱动电路的第二存储电容。
可选地，在垂直所述阵列基板板面的方向上，所述第一金属层的投影面积完全覆盖所述第二金属层的投影面积。
可选地，在垂直所述阵列基板板面的方向上，所述第一金属层的投影一端与所述第二金属层平齐、另一端凸出于所述第二金属层设置。
可选地，在垂直所述阵列基板板面的方向上，所述第一金属层的投影面积等于所述第二金属层的投影面积。
可选地，所述绝缘层和介电层上设有与所述第二金属层间隔设置的导电通孔，所述电极层经由所述导电通孔与所述第一金属层电连接。
可选地，所述绝缘层由硅胶材料制成。
可选地，所述第一金属层与所述栅极驱动电路的栅极层同步形成，所述第二金属层与由所述源极和漏极组成的源漏极层同步形成。
本申请还提出一种显示面板，包括阵列基板，该阵列基板包括：栅极驱动电路，所述栅极驱动电路包括：
第一金属层；
第二金属层；
介电层，设于所述第一金属层与第二金属层之间；
电极层，位于所述第二金属层远离第一金属层的一侧；所述电极层与所述第一金属层电连接；以及
绝缘层，设于所述电极层与所述第二金属层之间；其中，
在垂直所述阵列基板板面的方向上，所述电极层与所述第二金属层至少部分重叠设置，以形成所述栅极驱动电路的第一存储电容，所述绝缘层的厚度小于所述介电层的厚度。
本申请还提出一种显示装置，包括显示面板，该显示面板包括阵列基板，该阵列基板包括：栅极驱动电路，所述栅极驱动电路包括：
第一金属层；
第二金属层；
介电层，设于所述第一金属层与第二金属层之间；
电极层，位于所述第二金属层远离第一金属层的一侧；所述电极层与所述第一金属层电连接；以及
绝缘层，设于所述电极层与所述第二金属层之间；其中，
在垂直所述阵列基板板面的方向上，所述电极层与所述第二金属层至少部分重叠设置，以形成所述栅极驱动电路的第一存储电容，所述绝缘层的厚度小于所述介电层的厚度。
可选地，所述绝缘层的厚度范围为1000μm~3000μm。
可选地，在垂直所述阵列基板板面的方向上，所述电极层的投影面积完全覆盖所述第二金属层的投影面积。
可选地，在垂直所述阵列基板板面的方向上，所述第一金属层与所述第二金属层至少部分重叠设置，以形成所述栅极驱动电路的第二存储电容。
可选地，所述绝缘层和介电层上设有与所述第二金属层间隔设置的导电通孔，所述电极层经由所述导电通孔与所述第一金属层电连接。
本申请技术方案通过于第二金属层远离第一金属层的一侧设置电极层、以及于第二金属层和电极层设置绝缘层（厚度小于介电层），该电极层与第一金属层电连接，且电极层与第二金属层至少部分重叠设置，如此，电极层与第二金属层之间形成栅极驱动电路的第一存储电容，相较于示例性技术中利用第一金属层和第二金属层形成存储电容的方式，由于本实施例中的绝缘层厚度小于第一金属层和第二金属层之间的介电层，如此，有利于增大存储电容的电容量，相当于在保持同等电容量的情况下，本实施例的存储电容的平面面积更小，从而减小存储电容对液晶显示装置显示区域外侧的平面面积占用，有利于实现液晶显示装置的窄边框。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请阵列基板一实施例的剖面示意图。
附图标号说明：
标号 名称 标号 名称
1 第一金属层 2 第二金属层
3 介电层 4 电极层
5 绝缘层 6 导电通孔
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，若本申请实施例中有涉及方向性指示（诸如上、下、左、右、前、后……），则该方向性指示仅用于解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本申请实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请提出一种阵列基板，该阵列基板应用于液晶显示面板，可以理解，液晶显示面板包括相对间隔设置的彩膜基板和阵列基板以及填充于两基板之间的液晶，该液晶位于阵列基板和彩膜基板叠加而成的液晶盒内。不失一般性，该液晶显示面板可以应用于液晶电视、液晶显示器等，本设计不限于此。
众所周知，阵列基板包括沿竖向设置的多条数据线、沿横向设置的多条扫描线以及由扫面线和数据线定义的多个像素区域。其中，每一像素区域连接对应的一条数据线和一条扫描线，各条扫描线连接于栅极驱动电路以对各像素区域提供扫描电压，各条数据线连接于源极驱动电路以对各像素区域提供灰阶电压。通常地，栅极驱动电路包括TFT、存储电容以及液晶电容，液晶电容位于像素区域的像素电极、彩膜基板一侧的公共电极以及位于两者之间的液晶形成。
根据液晶显示面板GOA驱动的原理，通过扫描线输入扫描电压，位于同一行的TFF被同时打开，且在一定时间后位于下一行的TFT被同时打开，依次类推。由于每一行TFT打开的时间比较短，液晶电容充电控制液晶偏转的时间较短，很难达到液晶的响应时间，存储电容便可以在TFT关闭后维持各个像素区域的电压，从而为液晶响应提供时间。
在示例性技术中，存储电容通过与栅极层同层的第一金属层、与源漏极层同层的第二金属层以及夹持于第一金属层、第二金属层之间的介电层共同形成，根据存储电容的公式Holding C=ε0εrA/d 可知，存储电容的电容量与第一金属层和第二金属层的平面面积成正比，而与第一金属层和第二金属层之间的厚度成反比，然而，由于介电层的厚度较大，为了保证存储电容的电容量仍能保持在较高数值，只能尽量增大第一金属层和第二金属层的平面面积，然而，如此设置，无疑又会增大液晶显示装置显示区域两侧的面积，而与液晶显示装置窄边框的需求相冲突。因此，本申请对阵列基板进行了相关改进：
在本申请实施例中，参照图1，阵列基板的栅极驱动电路包括：
第一金属层1；
第二金属层2，位于第一金属层1的一侧；
介电层3，设于第一金属层1与第二金属层2之间；
电极层4，位于第二金属层2远离第一金属层1的一侧；电极层4与第一金属层1电连接；以及
绝缘层5，设于电极层4与第二金属层2之间；其中，
在垂直阵列基板板面的方向上，电极层4与第二金属层2至少部分重叠设置，以形成栅极驱动电路的第一存储电容，绝缘层5的厚度小于介电层3的厚度。
本实例中，第一金属层1与栅极驱动电路的栅极层同步形成，第二金属层2与由源极和漏极组成的源漏极层同步形成，介电层3与栅极层和源漏极层之间的钝化层同步形成，如此设置，方便阵列基板的加工成型，有利于提高阵列基板的加工效率，降低其加工成本。
另外，本实施例中，第一金属层1位于第二金属层2的下侧，以形成一底栅TFT结构，可以理解，底栅TFT结构是现有技术中广泛应用的一种TFT结构，具有结构稳定、设计简单等优点；当然，于其他实施例中，第一金属层1也可位于第二金属层2的上侧，以形成一顶栅TFT结构，本设计不限于此。
在此底栅TFT结构的基础上，于第二金属层2的上侧增设一电极层4，且电极层4与第二金属层2之间设置有绝缘层5（厚度小于介电层3），使电极层4与第一金属层1电连接，且电极层4与第二金属层2至少部分重叠设置，以使电极层4与第二金属层2之间形成第一存储电容。本实施例中，由于绝缘层5与介电层3的εr 基本相等（皆为7左右），绝缘层5的厚度小于介电层3的厚度，根据Holding C=ε0εr A/d可知，在第一存储电容的极板平面面积与原存储电容的极板的平面面积一致的情况下，第一存储电容的电容量会大于原存储电容的电容量，换言之，在第一存储电容的电容量与原存储电容一致的情况下，第一存储电容的极板（电极层4和第二金属层2）的平面面积小于原存储电容的极板的平面面积，从而有利于减小存储电容对液晶显示装置的平面占用，实现液晶显示装置的窄边框设计。本实施例中，绝缘层5和介电层3上设有与第二金属层2间隔设置的导电通孔6，电极层4经由导电通孔6与第一金属层1电连接，可以理解，在阵列基板上开设导电通孔6，以实现不同隔层的导电，是本领域中惯用的技术手段，具有工艺简单、导电稳定等优点，当然，于其他实施例中，电极层4与第一金属层1还可通过其他方式导电连接，本设计不限于此。
本申请技术方案通过于第二金属层2远离第一金属层1的一侧设置电极层4、以及于第二金属层2和电极层4设置绝缘层5（厚度小于介电层3），该电极层4与第一金属层1电连接，且电极层4与第二金属层2至少部分重叠设置，如此，电极层4与第二金属层2之间形成栅极驱动电路的第一存储电容，相较于示例性技术中利用第一金属层1和第二金属层2形成存储电容的方式，由于本实施例中的绝缘层5厚度小于第一金属层1和第二金属层2之间的介电层3，如此，有利于增大存储电容的电容量，相当于在保持同等电容量的情况下，本实施例的存储电容的平面面积更小，从而减小存储电容对液晶显示装置显示区域外侧的平面面积占用，有利于实现液晶显示装置的窄边框。
进一步地，绝缘层5的厚度为介电层3的1/3~3/5；可以理解，绝缘层5的厚度相对介电层3处于合适范围，才能既提高存储电容的容量、避免存储电容的平面面积过大，又防止阵列基板的工艺难度过高，以致阵列基板的加工难度过大。需要说明的是，本设计不限于此，于其他实施例中，绝缘层5的厚度也可具体为介电层3小于1的其他比例。特别地，本实施例中，绝缘层5的厚度范围为1000μm~3000μm，一方面，保证存储电容的电容量较大，另一方面，杜绝第二金属层2与电极层4之间发生导电情况。不失一般性，绝缘层5由硅胶材料制成，可以理解，硅胶材料是现有技术中广泛应用的绝缘材料，具有容易获得、价格便宜等优点，应当说明的是，本设计不限于此，于其他实施例中，绝缘层5也可具体由塑料等其他材料制成。
本实施例中，参照图1，在垂直阵列基板板面的方向上，电极层4的投影面积完全覆盖第二金属层2的投影面积。可以理解，在Holding C=ε0εr A/d中，A代表的是两极板正对的面积，因此，为了避免第二金属层2的平面面积的浪费，使第二金属层2沿上下向的投影面积完全落入电极层4的投影面积内，即第二金属层2的平面面积会全部被当做极板的正对面积。另外，本实施例中，考虑到电极层4的一端要与导电通孔6相接，因此，将电极层4的平面面积设置为大于第二金属层2，导电通孔6位于第二金属层2的前侧，电极层4的前侧也凸出于第二金属层2设置，当然，于其他实施例中，为了避免电极层4平面面积的浪费，电极层4沿上下向的投影面积也完全落入第二金属层2的投影面积内，即电极层4与第二金属层2在上下方向上完全重叠设置。应当说明的是，本设计不限于此，于其他实施例中，第二金属层2与电极层4沿上下向的投影也可相互之间仅部分重叠设置。
本申请的构思在于利用第二金属层2、电极层4以及绝缘层5形成一极板间距更小的存储电容，从而在满足同等电容量的情况下，减小存储电容的平面面积；可以理解，无论第一金属层1与第二金属层2之间是否还存在有存储电容，都应属于本申请的保护范围。本实施例中，为了更好地提高栅极驱动电路存储电容的电容量，在垂直阵列基板板面的方向上，第一金属层1与第二金属层2至少部分重叠设置，以形成栅极驱动电路的第二存储电容；可以理解，第二存储电容与第一存储电容串联设置，其串联之后的总电容势必大于第一存储电容，因而，使栅极驱动电路存储电容的电容量得到了更好地提升。另外，本实施例中，考虑到第一金属层1的一端要与导电通孔6相接，因此，将第一金属层1的平面面积设置为大于第二金属层2，导电通孔6位于第二金属层2的前侧，第一金属层1的前侧也凸出于第二金属层2设置，当然，于其他实施例中，为了避免第一金属层1平面面积的浪费，第一金属层1沿上下向的投影面积也完全落入第二金属层2的投影面积内，即第一金属层1与第二金属层2在上下方向上完全重叠设置。应当说明的是，本设计不限于此，于其他实施例中，第一金属层1与电极层4沿上下向的投影也可相互之间仅部分重叠设置。
本申请还提出一种显示装置，该显示装置包括显示面板，显示面板包括阵列基板，该阵列基板的具体结构参照上述实施例，由于本显示装置采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有有益效果，在此不再一一赘述。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的发明构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (20)

  1. 一种阵列基板，其中，包括栅极驱动电路，所述栅极驱动电路包括：
    第一金属层；
    第二金属层，位于所述第一金属层的一侧；
    介电层，设于所述第一金属层与第二金属层之间；
    电极层，位于所述第二金属层远离第一金属层的一侧；所述电极层与所述第一金属层电连接；以及
    绝缘层，设于所述电极层与所述第二金属层之间；其中，
    在垂直所述阵列基板板面的方向上，所述电极层与所述第二金属层至少部分重叠设置，以形成所述栅极驱动电路的第一存储电容，所述绝缘层的厚度小于所述介电层的厚度。
  2. 如权利要求1所述的阵列基板，其中，所述绝缘层的厚度为所述介电层的1/3~3/5。
  3. 如权利要求2所述的阵列基板，其中，所述绝缘层的厚度范围为1000μm~3000μm。
  4. 如权利要求1所述的阵列基板，其中，在垂直所述阵列基板板面的方向上，所述电极层的投影面积完全覆盖所述第二金属层的投影面积。
  5. 如权利要求4所述的阵列基板，其中，在垂直所述阵列基板板面的方向上，所述电极层的投影一端与所述第二金属层平齐、另一端凸出于所述第二金属层设置。
  6. 如权利要求4所述的阵列基板，其中，在垂直所述阵列基板板面的方向上，所述电极层的投影面积等于所述第二金属层的投影面积。
  7. 如权利要求1所述的阵列基板，其中，在垂直所述阵列基板板面的方向上，所述第一金属层与所述第二金属层至少部分重叠设置，以形成所述栅极驱动电路的第二存储电容。
  8. 如权利要求6所述的阵列基板，其中，在垂直所述阵列基板板面的方向上，所述第一金属层的投影面积完全覆盖所述第二金属层的投影面积。
  9. 如权利要求8所述的阵列基板，其中，在垂直所述阵列基板板面的方向上，所述第一金属层的投影一端与所述第二金属层平齐、另一端凸出于所述第二金属层设置。
  10. 如权利要求8所述的阵列基板，其中，在垂直所述阵列基板板面的方向上，所述第一金属层的投影面积等于所述第二金属层的投影面积。
  11. 如权利要求1所述的阵列基板，其中，所述绝缘层和介电层上设有与所述第二金属层间隔设置的导电通孔，所述电极层经由所述导电通孔与所述第一金属层电连接。
  12. 如权利要求1所述的阵列基板，其中，所述绝缘层由硅胶材料制成。
  13. 如权利要求1所述的阵列基板，其中，所述第一金属层与所述栅极驱动电路的栅极层同步形成，所述第二金属层与由所述源极和漏极组成的源漏极层同步形成。
  14. 一种显示面板，其中，包括阵列基板，所述阵列基板包括：栅极驱动电路，所述栅极驱动电路包括：
    第一金属层；
    第二金属层，位于所述第一金属层的一侧；
    介电层，设于所述第一金属层与第二金属层之间；
    电极层，位于所述第二金属层远离第一金属层的一侧；所述电极层与所述第一金属层电连接；以及
    绝缘层，设于所述电极层与所述第二金属层之间；其中，
    在垂直所述阵列基板板面的方向上，所述电极层与所述第二金属层至少部分重叠设置，以形成所述栅极驱动电路的第一存储电容，所述绝缘层的厚度小于所述介电层的厚度。
  15. 一种显示装置，其中，包括显示面板，所述显示面板包括阵列基板，所述阵列基板包括栅极驱动电路，所述栅极驱动电路包括：
    第一金属层；
    第二金属层，位于所述第一金属层的一侧；
    介电层，设于所述第一金属层与第二金属层之间；
    电极层，位于所述第二金属层远离第一金属层的一侧；所述电极层与所述第一金属层电连接；以及
    绝缘层，设于所述电极层与所述第二金属层之间；其中，
    在垂直所述阵列基板板面的方向上，所述电极层与所述第二金属层至少部分重叠设置，以形成所述栅极驱动电路的第一存储电容，所述绝缘层的厚度小于所述介电层的厚度。
  16. 如权利要求15所述的显示装置，其中，所述绝缘层的厚度为所述介电层的1/3~3/5。
  17. 如权利要求16所述的显示装置，其中，所述绝缘层的厚度范围为1000μm~3000μm。
  18. 如权利要求15所述的显示装置，其中，在垂直所述阵列基板板面的方向上，所述电极层的投影面积完全覆盖所述第二金属层的投影面积。
  19. 如权利要求15所述的显示装置，其中，在垂直所述阵列基板板面的方向上，所述第一金属层与所述第二金属层至少部分重叠设置，以形成所述栅极驱动电路的第二存储电容。
  20. 如权利要求15所述的显示装置，其中，所述绝缘层和介电层上设有与所述第二金属层间隔设置的导电通孔，所述电极层经由所述导电通孔与所述第一金属层电连接。
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CN110221492B (zh) * 2019-06-10 2022-12-13 北海惠科光电技术有限公司 阵列基板及其修复方法、显示装置
CN110568686A (zh) * 2019-08-08 2019-12-13 深圳市华星光电半导体显示技术有限公司 阵列基板及显示面板
CN110729308A (zh) * 2019-09-27 2020-01-24 深圳市华星光电技术有限公司 显示面板及显示装置
CN110767665B (zh) * 2019-11-29 2022-05-31 京东方科技集团股份有限公司 一种显示面板、其制备方法及显示装置
CN113724635A (zh) * 2021-08-18 2021-11-30 惠科股份有限公司 阵列基板行驱动电路、阵列基板以及显示面板

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