WO2020015325A1 - 阵列基板、显示面板及其制造方法 - Google Patents

阵列基板、显示面板及其制造方法 Download PDF

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Publication number
WO2020015325A1
WO2020015325A1 PCT/CN2018/124221 CN2018124221W WO2020015325A1 WO 2020015325 A1 WO2020015325 A1 WO 2020015325A1 CN 2018124221 W CN2018124221 W CN 2018124221W WO 2020015325 A1 WO2020015325 A1 WO 2020015325A1
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Prior art keywords
layer
electrode
electrode layer
substrate
array substrate
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PCT/CN2018/124221
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English (en)
French (fr)
Inventor
黄北洲
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惠科股份有限公司
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Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Priority to US16/258,684 priority Critical patent/US11088171B2/en
Publication of WO2020015325A1 publication Critical patent/WO2020015325A1/zh
Priority to US17/368,847 priority patent/US11887990B2/en

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a display panel, and a manufacturing method thereof.
  • a liquid crystal display panel generally includes an upper substrate, a lower substrate, and a liquid crystal layer disposed between the two substrates. Its working principle is to control the rotation of liquid crystal molecules of the liquid crystal layer by applying a driving voltage to the two substrates.
  • Liquid crystal display panels are prone to poor colors and poor display results due to misalignment of the upper and lower panels.
  • the industry often uses color filter technology (COA, Color Filter) on the array. on Array) and spacer technology on the array (POA, PS on Array) to improve these undesirable phenomena, and concentrate the processes in the COA and POA manufacturing processes on the lower substrate, to further simplify the structure of the upper substrate and reduce the probability of the occurrence of defective phenomena.
  • COA color filter technology
  • POA PS on Array
  • the array process in the traditional COA + POA technology is based on thin film transistors (TFT, thin film transistor) process, color filter process, PE (Pixel Electrode process), spacer cell layer (PS, Photo Spacer) process sequence, where the PS process will be arranged after the PE process is completed. Since the PS process is behind the PE process, the spacer unit is formed on the electrode layer.
  • the signal line (not shown) of the lower substrate corresponding to this structure has a larger load, thereby increasing the material and cost of the liquid crystal display panel.
  • the purpose of this application is to provide an array substrate, a display panel and a manufacturing method thereof, so as to reduce the load of the substrate signal line.
  • an array substrate including:
  • Substrate including display area and non-display area
  • An electrode layer is formed on the color filter layer and the spacer unit layer.
  • the electrode layer includes a first electrode layer and a second electrode layer.
  • the first electrode layer is located in the display area and the second electrode layer.
  • An electrode layer is located in the non-display area.
  • the spacer unit layer includes a plurality of spacer units
  • the first electrode layer includes a first electrode region covering the spacer units.
  • the covering of the spacer unit by the first electrode region includes: covering the side surface and / or the upper end surface of the spacer unit by the first electrode region.
  • the first electrode region is formed on at least a part of the spacer unit.
  • the first electrode layer further includes a second electrode region formed on the color resistance unit, and the second electrode region is connected to the first electrode region.
  • the second electrode layer is insulated from the first electrode layer.
  • the present application also provides a display panel, including:
  • a first substrate including a common electrode layer
  • a second substrate including the above-mentioned array substrate, the second substrate and the first substrate are arranged opposite to each other;
  • the second electrode layer is electrically connected to the common electrode layer.
  • the application also provides a method for manufacturing an array substrate, including the following steps:
  • Forming an electrode layer on the color filter layer and the spacer unit layer includes forming a first electrode layer in a display area of the substrate, and forming a second electrode layer in a non-display area of the substrate.
  • a plurality of color resist units are formed on the substrate to form the color filter layer, a space unit is formed on at least a part of the color resist units, and a plurality of the space units constitute the space unit layer.
  • the first electrode layer includes a first electrode region formed on the spacer unit, and the first electrode region is formed on a side surface and / or an upper end surface of the spacer unit.
  • the present application provides an array substrate, a display panel, and a method for manufacturing the same.
  • an electrode layer By forming an electrode layer on the spacer unit layer, the distance between the signal line and the electrode layer is increased, so that the capacitance becomes smaller and lower.
  • the gold ball material and the coating process can be omitted, thereby reducing the material and cost of the array substrate.
  • FIG. 1 is a schematic cross-sectional structure diagram of an array substrate display area according to an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional structure diagram of a non-display area of a display panel according to an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a method for manufacturing an array substrate according to an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a method for manufacturing a liquid crystal display panel according to another embodiment of the present application.
  • an embodiment of the present application provides an array substrate including a substrate 10, an active switch 20 formed on the substrate 10, a color filter layer 30 formed on the active switch 20, and The spacer unit layer 50 on the color filter layer 30 and the electrode layer 60 formed on the color filter layer 30 and the spacer unit layer 50.
  • the array substrate provided in this embodiment may be further configured to be made into a display panel, such as a liquid crystal display panel.
  • the substrate 10 is made of a glass material and includes a display area and a non-display area.
  • the active switch 20 is a thin film transistor (thin film).
  • transistor (TFT) layer which is mainly set to control the standing angle of the liquid crystal.
  • the thin film transistor layer is a thin film layer deposited on the substrate 10 as a channel region, and includes a gate 210, a source 220, and a drain 230.
  • the gate 210 is provided with a gate insulating layer 211, a source 220 and The drain electrodes 230 are all disposed on the gate insulating layer 211.
  • a thin film transistor is an insulated gate field effect transistor, and its working principle is roughly as follows: When a positive voltage is applied to the gate 210, a positive gate voltage generates an electric field in the gate insulating layer 211, and a power line is directed from the gate 210 to the semiconductor active source. The surface of the layer 212 generates induced charges at the surface. As the gate voltage increases, an inversion layer is formed in the semiconductor active layer 212. When a strong inversion is reached (that is, when the turn-on voltage is reached), a voltage is applied between the source 220 and the drain 230 and carriers will pass through the channel.
  • the conductive channel is approximately a constant resistance, and the leakage current increases linearly with the increase of the source-drain voltage.
  • the source-drain voltage When the source-drain voltage is large, it will affect the gate voltage, which makes the electric field in the gate insulating layer 211 gradually weaken from source to drain, and the electrons in the surface inversion layer of the thin film transistor layer gradually change from source to drain As it decreases, the channel resistance increases as the source-drain voltage increases. The leakage current increases slowly, corresponding to the transition from the linear region to the saturated region.
  • the thickness of the drain inversion layer decreases to zero, the voltage increases, and the device enters the saturation region.
  • most of the thin film transistor layers use hydrogenated amorphous silicon (a-Si: H) as the main material, which is mainly used
  • a-Si: H hydrogenated amorphous silicon
  • the on-state (greater than the on-voltage) of the a-Si: H TFT charges the electrode layer 60 quickly, and the off-state is used to maintain the voltage of the electrode layer 60, thereby achieving the unity of fast response and good storage.
  • the thin film transistor layer uses indium tin oxide (ITO) for the electrodes and internal wiring.
  • ITO indium tin oxide
  • the substrate 10 further includes a first passivation layer 41 disposed on the thin film transistor layer.
  • the first passivation layer 41 is disposed over the source 220 and the drain 230 and completely covers the source 220 and the drain. 230.
  • the first passivation layer 41 is provided with a via hole 411, and the drain 230 is connected to the electrode layer 60 through the via hole 411.
  • a color filter layer 30 is formed on the first passivation layer 41.
  • the role of the color filter layer 30 is mainly to form white light into colored light.
  • the color filter layer 30 includes a plurality of color resist units 310, and the plurality of color resist units 310 are arranged in an array on the substrate 10.
  • the color filter layer 30 may include, for example, first, second, and third color resistance units.
  • the first, second, and third color resistance units may be red, green, and blue color resistance units, for example.
  • each pixel region corresponds to a color resist unit 310 of one color.
  • the substrate 10 further includes a light shielding layer (such as a black matrix black matrix (BM), which is located on the color filter layer 30.
  • a light shielding layer such as a black matrix black matrix (BM)
  • BM black matrix black matrix
  • the color filter layer 30 is further provided with a second passivation layer 42, and the second passivation layer 42 completely covers the color filter layer 30.
  • the second passivation layer 42 is provided with a via hole 421 at a position corresponding to the via hole 411, and is provided so that the electrode layer 60 extends into the via hole 411 and is connected to the drain electrode 230.
  • the substrate 10 further includes a light shielding layer (such as a black matrix black matrix (BM), which is located on the color filter layer 30.
  • a light shielding layer such as a black matrix black matrix (BM)
  • BM black matrix black matrix
  • a second passivation layer 42 is further provided on the light shielding layer, and the second passivation layer 42 completely covers the light shielding layer.
  • the second passivation layer 42 is provided with a via hole 421 at a position corresponding to the via hole 411, and is configured so that the electrode layer 60 extends into the via hole 411 and is connected to the drain electrode 230.
  • the spacer unit layer 50 includes a plurality of spacer units 510 made of an insulating material.
  • the spacing unit 510 is disposed on the substrate 10, and a plurality of platforms (not labeled) corresponding to the spacing unit 510 are provided on the substrate 10, so that the spacing unit 510 can maintain the panel pitch more stably.
  • the spacing unit 510 is disposed on at least a portion of the color resistance units 310.
  • the spacing unit 510 is formed only on a portion of the color resistance units 310, instead of forming the spacing unit 510 on each of the color resistance units 310.
  • the spacer unit 510 includes a lower end surface 501 facing the color filter layer 30 and an upper surface on the array substrate 100.
  • the upper surface of the spacer unit 510 includes an upper end surface 502 opposite to the lower end surface 501 and connecting the upper end surface 502 and the lower end surface. 501 side 503.
  • the spacing unit 510 has a trapezoidal column shape, and an area of an upper end surface 502 thereof is smaller than an area of a lower end surface 501.
  • the electrode layer 60 includes a first electrode layer 601 and a second electrode layer 602.
  • the first electrode layer 601 is located in a display area
  • the second electrode layer 602 is located in a non-display area
  • the first electrode layer 601 and the second The electrode layers 602 are insulated, that is, the first electrode layer 601 and the second electrode layer 602 are not electrically connected.
  • the first electrode layer 601 is a pixel electrode layer
  • the material of the pixel electrode layer is a metal or a metal oxide, such as indium tin oxide (Indium tin oxide (ITO).
  • the second electrode layer 602 is a conductive electrode layer, and the material is also a metal or a metal oxide.
  • a preferred material is indium tin oxide (Indium tin oxide). oxide (ITO).
  • the first electrode layer 601 is formed on the color filter layer 30 and the spacer unit layer 50 and is patterned. Specifically, the first electrode layer 601 includes a plurality of first electrode regions 610 and a second electrode region 620. The first electrode region 610 covers at least a part of the spacer unit 510, and includes: the first electrode region 610 covers the spacer unit 510. On the side and / or the upper end surface, the second electrode region 620 covers the color resist unit 310.
  • a portion of the first electrode region 610 covering the side surface 503 of the spacing unit 510 is defined as a first portion 611, and a portion of the first electrode region 610 covering the upper end surface 502 of the spacing unit 510 is a second portion 612. Because the electrode layer 60 is patterned, only the second electrode region 620 is formed on a portion of the color-resistance unit 310 for the array substrate to be finally formed; and the first electrode region is also formed on the portion of the color-resistance unit 310. 610 and the second electrode region 620, and the first electrode region 610 and the second electrode region 620 are connected. The first electrode region 610 covers the side surface and / or the upper end surface of the spacing unit 510.
  • the first electrode region only covers the side surface 503 of the spacing unit 510, that is, the first electrode region 610 only includes The first part 611, the first part 611 is connected to the second electrode region 620; on the partial spacing unit 510, the first electrode region 610 covers both the side surface 503 and the upper end surface 502 of the spacing unit 510.
  • the first portion 611 connects the second electrode region 620 and the second portion 612.
  • the second electrode layer 602 is formed on the color filter layer 30 and the spacer unit layer 50 in the non-display area and is patterned.
  • an upper surface of a platform (not labeled) corresponding to the spacer unit 510 provided on the substrate 10 is an upper surface of the second passivation layer 42, and the spacer unit 510 is formed on the second passivation layer 42.
  • the second electrode region 620 is formed on the upper surface of the second passivation layer 42.
  • the electrode layer 60 By forming the electrode layer 60 on the spacer unit layer 50 in the array substrate provided in this application, the distance between the signal line and the electrode layer 60 is increased, so that the capacitance becomes smaller, thereby reducing the signal line of the substrate 10 ( (Not shown). Since the load on the signal line is reduced, the requirements on the material of the signal line are reduced, so that the material and cost of the liquid crystal display panel can be reduced.
  • FIG. 2 another embodiment of the present application provides a liquid crystal display panel including an upper substrate 70, a lower substrate (not labeled), and a liquid crystal layer (not shown), where the lower substrate is the same as in the above embodiment.
  • the provided array substrate is made with the upper substrate 70 and the lower substrate facing each other, the spacing unit 501 is configured to stably maintain the distance between the upper substrate 70 and the lower substrate, and define a liquid crystal space.
  • the liquid crystal space is filled by a liquid crystal layer.
  • a rubber frame (not shown) is provided around the lower substrate.
  • a spacer unit 501 is provided near the rubber frame.
  • a second electrode layer 602 covers the spacer unit 501.
  • the second electrode layer 602 is electrically connected to the common electrode layer 71 of the upper substrate 70, thereby omitting the gold ball material and the coating process, thereby further reducing the material and cost of the liquid crystal display panel.
  • the liquid crystal display panel provided in this embodiment can be further applied as a flat-type or curved-type display panel.
  • an embodiment of the present application further provides a method for manufacturing an array substrate, including the following steps:
  • S11 Provide a substrate 10 on which a plurality of active switches 20 are formed;
  • the active switch 20 is a thin film transistor (thin film).
  • transistor (TFT) layer which is mainly set to control the standing angle of the liquid crystal.
  • the thin film transistor layer is a thin film deposited on the substrate 10 as a channel region, which includes a gate 210, a source 220, and a drain 230.
  • the gate 210 is provided with a gate insulating layer 211, a source 220, and a drain.
  • the electrodes 230 are all disposed on the gate insulating layer 211.
  • a plurality of color resist units 310 are formed on the substrate 10 in the form of an array, and the plurality of color resist units 310 constitute a color filter layer 30.
  • the color filter layer 30 may include, for example, first, second, third, and fourth color photoresist layers.
  • the first, second, third, and fourth color photoresist layers may be red, green, etc. , Blue and white photoresist layers, and the material of one of the first, second, third and fourth color photoresist layers is the same as the spacer unit.
  • each pixel region corresponds to a color resist unit 310 of one color.
  • the substrate 10 further includes a light shielding layer (such as a black matrix black matrix (BM), which is located on the color filter layer 30.
  • a light shielding layer such as a black matrix black matrix (BM)
  • BM black matrix black matrix
  • a first passivation layer 41 is formed on the substrate 10, and a color filter layer 30 is formed on the first passivation layer 41.
  • the substrate 10 further includes a light shielding layer (such as a black matrix black matrix (BM), which is located on the color filter layer 30.
  • a light shielding layer such as a black matrix black matrix (BM)
  • BM black matrix black matrix
  • a second passivation layer 42 is further disposed on the color filter layer 30, and the second passivation layer 42 completely covers the color filter layer 30.
  • the spacer unit layer 50 includes a plurality of spacer units 510 made of an insulating material.
  • a plurality of platforms (not labeled) corresponding to the spacing unit 510 are provided on the substrate 10, so that the spacing unit 510 can more stably maintain the panel pitch.
  • the spacing unit 510 is formed on the color resistance unit 310.
  • the spacing unit 510 is formed only on a part of the color resistance unit 310, instead of forming the spacing unit 510 on each of the color resistance units 310.
  • the spacing unit 510 has a trapezoidal column shape, and an area of an upper end surface 502 thereof is smaller than an area of a lower end surface 501.
  • Forming the electrode layer 60 on the color filter layer 30 and the spacer unit layer 50 includes forming a first electrode layer 601 on a display area of the substrate 10, and forming a second electrode layer 602 on a non-display area of the substrate 10.
  • the first electrode layer 601 is a pixel electrode layer.
  • the material of the pixel electrode layer is a metal or a metal oxide.
  • a preferred material is indium tin oxide. oxide (ITO).
  • the second electrode layer 602 is a conductive electrode layer, and the material is also a metal or a metal oxide.
  • a preferred material is indium tin oxide (Indium tin oxide). oxide (ITO).
  • the first electrode layer 601 and the second electrode layer 602 may be patterned by a photoresist exposure development process and an etching process. Specifically, the first electrode layer 601 and the second electrode layer 602 may be formed with a preset pattern through a same mask, or may be patterned successively through different masks.
  • the first electrode layer 601 and the second electrode layer 602 are insulated.
  • the first electrode layer 601 is formed on the color filter layer 30 and the spacer unit layer 50.
  • the first electrode layer 601 includes a plurality of first electrode regions 610 and a second electrode region 620.
  • the first electrode region 610 covers the spacer unit 510, and includes: the first electrode region 610 covers a side of the spacer unit 510 and / Or the upper end surface, the second electrode region 620 is formed on the color resist unit 310.
  • a portion of the first electrode region 610 covering the side surface 503 of the spacing unit 510 is defined as a first portion 611, and a portion of the first electrode region 610 covering the upper end surface 502 of the spacing unit 510 is a second portion 612. Since the first electrode layer 601 and the second electrode layer 602 are formed by patterning, for the finally formed array substrate, only a second electrode region 620 is formed on a part of the color resistive unit 310; on the part of the color resistive unit 310 A first electrode region 610 and a second electrode region 620 are simultaneously formed, and the first electrode region 610 and the second electrode region 620 are connected. The first electrode region 610 is formed on a side surface and / or an upper end surface of the spacer unit 510.
  • the first electrode region 610 is formed only on a side surface 503 of the spacer unit 510, that is, the first electrode region 610 includes only The first portion 611 is connected to the second electrode region 620.
  • the first electrode region 610 is simultaneously formed on the side surface 503 and the upper end surface 502 of the spacing unit 510.
  • the first electrode region 610 includes the first portion 611 With the second portion 612, the first portion 611 connects the second electrode region 620 and the second portion 612.
  • the second electrode layer 602 is formed on the color filter layer 30 and the spacer unit layer 50 in the non-display area, and is obtained by patterning.
  • an upper surface of a platform (not labeled) corresponding to the spacer unit 510 provided on the substrate 10 is an upper surface of the second passivation layer 42, and the spacer unit 510 is formed on the second passivation layer 42.
  • the second electrode region 620 is formed on the upper surface of the second passivation layer 42.
  • FIG. 1, FIG. 2, and FIG. 4 another embodiment of the present application further provides a method for manufacturing a liquid crystal display panel, including the following steps:
  • S21 Provide a substrate 10, and form an active switch 20 on the substrate 10;
  • the substrate 10 includes a display area and a non-display area.
  • the active switch 20 is a thin film transistor layer, which has the function of controlling the standing angle of the liquid crystal.
  • the thin film transistor layer is a thin film deposited on the substrate 10 as a channel region, which includes a gate 210, a source 220, and a drain 230.
  • the gate 210 is provided with a gate insulating layer 211, a source 220, and a drain.
  • the electrodes 230 are all disposed on the gate insulating layer 211.
  • the thin film transistor layer uses hydrogenated amorphous silicon (a-Si: H) as the main material, which mainly uses a-Si: H TFT
  • a-Si: H hydrogenated amorphous silicon
  • the on-state charges the electrode layer 60 quickly, and the off-state is used to maintain the voltage of the electrode layer 60, thereby achieving the unity of fast response and good storage.
  • the thin film transistor layer uses indium tin oxide (ITO) for the electrodes and internal wiring.
  • ITO indium tin oxide
  • the first passivation layer 41 is formed on the source 220 and the drain 230 and completely covers the source.
  • a via 411 is formed in the first passivation layer 41.
  • the plurality of color resist units 310 are arranged in an array.
  • the color filter layer 30 may include, for example, first, second, and third color resistance units.
  • the first, second, and third color resistance units may be red, green, and blue color resistance units, for example.
  • each pixel region corresponds to a color resist unit 310 of one color.
  • the substrate 10 further includes a light shielding layer (such as a black matrix black matrix (BM), which is formed on the color filter layer 30.
  • a light shielding layer such as a black matrix black matrix (BM)
  • BM black matrix black matrix
  • the second passivation layer 42 is completely covered on the color filter layer 30.
  • the spacer unit layer 50 includes a plurality of spacer units 510.
  • the spacer units 510 are used to define a liquid crystal spacer space, which is made of an insulating material.
  • a plurality of platforms (not labeled) corresponding to the spacing unit 510 are provided on the substrate 10, so that the spacing unit 510 can more stably maintain the panel pitch.
  • the spacing unit 510 is disposed on the color resistance unit 310, and the spacing unit 510 is formed only on a part of the color resistance unit 310, instead of forming the spacing unit 510 on each of the color resistance units 310.
  • the spacing unit 510 is trapezoidal, and the area of the upper surface is smaller than the area of the lower surface.
  • Forming an electrode layer 60 on the second passivation layer 42 and the spacer unit layer 50 includes: forming a first electrode layer 601 on the second passivation layer 42 and the spacer unit layer 50 in the display area; A second electrode layer 602 is formed on the passivation layer 42 and the spacer unit layer 50.
  • the first electrode layer 601 and the second electrode layer 602 are insulated. Both the first electrode layer 601 and the second electrode layer 60 are formed by patterning.
  • the first electrode layer 601 includes a plurality of first electrode regions 610 and a second electrode region 620.
  • the first electrode region 610 is formed on the spacer unit 510.
  • the first electrode region 610 is formed on a side surface of the spacer unit 510 and / Or the upper end surface, the second electrode region 620 is formed on the color resist unit 310.
  • a portion defining the first electrode region 610 formed on the side surface 503 of the spacer unit 510 is a first portion 611, and a portion formed on the upper end surface 502 of the spacer unit 510 is a second portion 612. Since the first electrode layer 601 and the second electrode layer 602 are formed by patterning, for the finally formed array substrate, only a second electrode region 620 is formed on a part of the color resistive unit 310; on the part of the color resistive unit 310 A first electrode region 610 and a second electrode region 620 are simultaneously formed, and the first electrode region 610 and the second electrode region 620 are connected. The first electrode region 610 is formed on a side surface and / or an upper end surface of the spacer unit 510.
  • the first electrode region 610 is formed only on a side surface 503 of the spacer unit 510, that is, the first electrode region 610 includes The first portion 611 is connected to the second electrode region 620.
  • the first electrode region 610 is simultaneously formed on the side surface 503 and the upper end surface 502 of the spacing unit 510.
  • the first electrode region 610 includes the first portion 611 With the second portion 612, the first portion 611 connects the second electrode region 620 and the second portion 612.
  • the upper surface of the platform (not labeled) corresponding to the spacer unit 510 provided on the substrate 10 is the upper surface of the second passivation layer 42, and the spacer unit 510 is formed on the upper surface of the second passivation layer 42.
  • the electrode region 620 is formed on the upper surface of the second passivation layer 42.
  • the second electrode layer 602 is formed on the second passivation layer 42 and the spacer unit layer 50 in the non-display region.
  • An upper substrate 70 is provided, and the upper substrate 70 and the lower substrate are oppositely arranged.
  • the spacer unit layer 50 is located between the upper substrate 70 and the lower substrate.
  • the spacer unit layer 50 defines a liquid crystal spacer space.
  • the spacer unit layer 50 is stably formed between the upper substrate 70 and the lower substrate, and the distance between the upper substrate 70 and the lower substrate is maintained constant.
  • the upper substrate 70 includes a common electrode layer 71, and the active switch 20 supplies power to the electrode layer 60.
  • the common electrode layer 71 of the upper substrate 70 and the electrode layer 60 of the lower substrate Form an electric field.
  • a plastic frame (not shown) is provided on the lower substrate.
  • a spacer unit 510 is provided near the plastic frame.
  • a second electrode layer 71 covers the spacer unit 510, and a second electrode layer 602. It is electrically connected to the common electrode layer 71 of the upper substrate 70, thereby omitting the gold ball material and the coating process, thereby further reducing the material and cost of the liquid crystal display panel.
  • the array substrate or the liquid crystal display panel manufactured by the manufacturing method provided in this application forms the electrode layer 60 on the spacer unit layer 50, so that the distance between the signal line and the electrode layer 60 becomes larger, the capacitance becomes smaller, and the electrode layer 60 is reduced. This reduces the load on the signal line (not shown) of the substrate 10. Because the load on the signal line is reduced, the requirements for the material of the signal line are reduced. At the same time, the gold ball material and the coating process can be omitted, thereby further reducing the material and cost of the array substrate or the liquid crystal display panel.

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Abstract

一种阵列基板、显示面板及其制造方法。该阵列基板包括基板（10）、多个主动开关（20）、彩色滤光层（30）、间隔单元层（50）及形成于彩色滤光层（30）与间隔单元层（50）上的电极层（60）。该基板（10）包括显示区和非显示区；该多个主动开关（20）阵列于该基板（10）上；该彩色滤光层（30）阵列于该基板（10）上且形成于该多个主动开关（20）上；该间隔单元层（50）形成于该彩色滤光层（30）上；该电极层（60）包括第一电极层（601）和第二电极层（602），其中第一电极层（601）位于显示区，第二电极层（602）位于非显示区。

Description

阵列基板、显示面板及其制造方法
相关申请
本申请要求2018年7月16日申请的，申请号201810779922.5，名称为“ 阵列基板、显示面板及其制造方法”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及显示技术领域，尤其涉及阵列基板、显示面板及其制造方法。
背景技术
液晶显示面板通常包括上基板、下基板及配置于两基板间的液晶层，其工作原理是通过在两个基板上施加驱动电压来控制液晶层的液晶分子的旋转。
液晶显示面板容易因上下板错位而导致色彩不均、显示效果不佳等不良现象，行业内常采用在阵列上的彩色滤光膜技术（COA，Color Filter on Array)及在阵列上的间隔物技术（POA，PS on Array)来改善这些不良现象，并且将COA和POA制程工艺中的工序集中在下基板，以更加简化上基板的结构，降低不良现象出现的机率。
传统的COA+POA技术中的阵列工艺，按照的是薄膜晶体管（TFT，thin film transistor）制程、彩色滤光层（color filter）制程、电极层（PE，Pixel Electrode制程、间隔单元层（PS，Photo Spacer）制程的顺序，其中，PS制程会安排在PE制程完成之后。由于PS制程在PE制程的后面，间隔单元形成于电极层上，这种结构下所对应的下基板的讯号线（未图示）负载较大，从而增加了液晶显示面板的材料及成本。
发明内容
本申请目的在于提供阵列基板、显示面板及其制造方法，降低基板讯号线的负载。
本申请提供一种阵列基板，包括：
基板，包括显示区和非显示区；
多个主动开关，阵列在所述基板上；
彩色滤光层，阵列于所述基板上且形成于所述多个主动开关上；
间隔单元层，形成于所述彩色滤光层上；
电极层，形成于所述彩色滤光层及所述间隔单元层上，所述电极层包括第一电极层和第二电极层，所述第一电极层位于所述显示区，所述第二电极层位于所述非显示区。
在一个实施例中，所述间隔单元层包括多个间隔单元，所述第一电极层包括覆盖于所述间隔单元上的第一电极区域。
在一个实施例中，所述第一电极区域覆盖所述间隔单元包括：所述第一电极区域覆盖于所述间隔单元的侧面和/或上端面。
在一个实施例中，所述第一电极区域形成于至少部分所述间隔单元上。
在一个实施例中，所述第一电极层还包括形成于所述色阻单元上的第二电极区域，所述第二电极区域和所述第一电极区域连接。
在一个实施例中，所述第二电极层和所述第一电极层之间绝缘。
本申请还提供一种显示面板，包括：
第一基板，包括公共电极层；
第二基板，包括上述阵列基板，所述第二基板与所述第一基板对向设置；
所述第二电极层与所述公共电极层连接导通。
本申请还提供一种阵列基板的制造方法，包括如下步骤：
提供一基板，在所述基板上形成多个主动开关；
在所述基板上形成彩色滤光层；
形成间隔单元层于所述彩色滤光层上；
形成电极层于所述彩色滤光层及所述间隔单元层上，包括：在所述基板的显示区形成第一电极层，在所述基板的非显示区形成第二电极层。
在一实施例中，在所述基板上形成多个色阻单元构成所述彩色滤光层，在至少部分所述色阻单元上形成间隔单元，多个所述间隔单元构成所述间隔单元层。
在一个实施例中，所述第一电极层包括形成于所述间隔单元上的第一电极区域，所述第一电极区域形成于所述间隔单元的侧面和/或上端面。
为解决上述技术问题，本申请提供了阵列基板、显示面板及其制造方法，通过将电极层形成于间隔单元层上，增大了讯号线与电极层之间的距离，使得电容变小，降低了下基板的讯号线的负载，同时，可省略金球材料及涂布制程，以此降低阵列基板的材料及成本。
附图说明
图1为本申请一实施例提供的阵列基板显示区的剖面结构示意图。
图2为本申请一实施例提供的显示面板非显示区的剖面结构示意图。
图3为本申请一实施例提供的一阵列基板的制造方法的流程示意图。
图4为本申请另一实施例提供的一液晶显示面板的制造方法的流程示意图。
具体实施方式
下面详细描述本申请的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在解释本申请，而不能理解为对本申请的限制。
本申请所提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”、“侧面”等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度。在附图中，为了理解和便于描述，夸大了一些层和区域的厚度。将理解的是，当例如层、膜、区域或基底的组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在……上”意指位于目标组件上方或者下方，而不意指必须位于基于重力上方的顶部上。
为更进一步阐述本申请为达成预定申请目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本申请提出的一种阵列基板、显示面板及制造方法其具体实施方式、结构、特征及其功效，详细说明如后。
如图1和图2所示，本申请一实施例提供了一种阵列基板，包括一基板10、形成于基板10上的主动开关20、形成于主动开关20上的彩色滤光层30、形成于彩色滤光层30上的间隔单元层50，及形成于彩色滤光层30及间隔单元层50上的电极层60。本实施例提供的阵列基板可进一步设置为制成显示面板，比如液晶显示面板。
以下针对本申请实施例提供的阵列基板内的各个组件及组件之间的位置关系作具体说明。
在一实施例中，基板10由玻璃材料制成，包括显示区和非显示区。
在本实施例中，主动开关20为薄膜晶体管（thin film transistor，TFT）层，其主要设置为控制液晶的站立角度。具体的，薄膜晶体管层是在基板10上沉积一层薄膜当作通道区，其包括栅极210、源极220及漏极230，栅极210上设置有栅极绝缘层211，源极220和漏极230均设置在栅极绝缘层211上。
薄膜晶体管是一种绝缘栅场效应晶体管，其工作原理大致如下：当栅极210施以正电压时，栅极正电压在栅极绝缘层211中产生电场，电力线由栅极210指向半导体有源层212的表面，并在表面处产生感应电荷。随着栅电压增加，半导体有源层212中形成反型层。当达到强反型时(即达到开启电压时)，源极220、漏极230间加上电压就会有载流子通过沟道。当源极220、漏极230间电压（以下简称源漏电压）很小时，导电沟道近似为一恒定电阻，漏电流随源漏电压增加而线性增大。当源漏电压很大时，它会对栅电压产生影响，使得栅极绝缘层211中电场由源端到漏端逐渐减弱，薄膜晶体管层的表面反型层中电子由源端到漏端逐渐减少，沟道电阻随着源漏电压增大而增加。漏电流增加变得缓慢，对应线性区向饱和区过渡。当源漏电压增到一定程度，漏端反型层厚度减为零，电压在增加，器件进入饱和区。在实际液晶显示面板的生产中，薄膜晶体管层大多使用氢化非晶硅(a-Si:H)作为主要材料，其主要利用 a-Si:H TFT 的开态(大于开启电压)对电极层60快速充电，利用关态来保持电极层60的电压，从而实现快速响应和良好存储的统一。
在一实施例中，薄膜晶体管层在电极及内部接线使用铟锡氧化物(ITO)。
在一实施例中，基板10还包括设置在薄膜晶体管层上的第一钝化层41，第一钝化层41设置在源极220和漏极230之上并且完全覆盖源极220和漏极230。第一钝化层41上设置有导通孔411，漏极230通过导通孔411与电极层60相连。
彩色滤光层30形成在第一钝化层41上。彩色滤光层30的作用主要是将白光形成彩色光。在一实施例中，彩色滤光层30包括多个色阻单元310，多个色阻单元310在基板10上以阵列的形式排布。彩色滤光层30可例如有第一、第二及第三色阻单元，在一些实施例中，第一、第二及第三色阻单元可例如为红色、绿色及蓝色色阻单元。在一实施例中，在每一个像素区域对应一种颜色的色阻单元310。
在一实施例中，基板10还包括一遮光层（比如黑色矩阵black matrix，BM），其位于彩色滤光层30上。
在一实施例中，彩色滤光层30上还设置有第二钝化层42，第二钝化层42完全覆盖在彩色滤光层30上。第二钝化层42在与导通孔411对应的位置，设置有过孔421，设置为电极层60延伸至导通孔411内与漏极230相连。
在一实施例中，基板10还包括一遮光层（比如黑色矩阵black matrix，BM），其位于彩色滤光层30上。在遮光层上还设置有第二钝化层42，第二钝化层42完全覆盖在遮光层上。第二钝化层42上在与导通孔411对应的位置，设置有过孔421，配置为电极层60延伸至导通孔411内与漏极230相连。
间隔单元层50包括多个间隔单元510，间隔单元510由绝缘材料制成。在一实施例中，间隔单元510设置在基板10上，并且，在基板10上设置有多个与间隔单元510相对应的平台（未标示），使得间隔单元510能够更稳定地维持面板间距。具体的，间隔单元510设置在至少部分色阻单元310上，在一实施例中，仅在部分色阻单元310上形成间隔单元510，而不是每个色阻单元310上均形成间隔单元510。间隔单元510包括朝向彩色滤光层30的下端面501、及朝向阵列基板100上的上表面，间隔单元510的上表面包括与下端面501相背的上端面502以及连接上端面502和下端面501的侧面503。在一实施例中，间隔单元510呈梯形柱状，其上端面502的面积小于下端面501的面积。
在本实施例中，电极层60包括第一电极层601和第二电极层602，第一电极层601位于显示区，第二电极层602位于非显示区，且第一电极层601和第二电极层602之间绝缘，即第一电极层601和第二电极层602之间未电性连接。第一电极层601为像素电极层，像素电极层的材料为金属或金属氧化物，例如铟锡氧化物（Indium tin oxide，ITO）。第二电极层602为导电电极层，其材料也为金属或金属氧化物，优选材料为铟锡氧化物（Indium tin oxide，ITO）。
第一电极层601形成于彩色滤光层30及间隔单元层50上且图案化设置。具体的，第一电极层601包括多个第一电极区域610和第二电极区域620，第一电极区域610覆盖于至少部分间隔单元510上，包括：第一电极区域610覆盖于间隔单元510的侧面和/或上端面，第二电极区域620覆盖于色阻单元310上。
定义第一电极区域610覆盖于间隔单元510的侧面503的部分为第一部分611，第一电极区域610覆盖于间隔单元510的上端面502的部分为第二部分612。由于电极层60为图案化设置，所以，对于最终形成的阵列基板，在部分色阻单元310上，仅形成有第二电极区域620；在部分色阻单元310上，同时形成有第一电极区域610和第二电极区域620，并且第一电极区域610和第二电极区域620连接。第一电极区域610覆盖于间隔单元510的侧面和/或上端面，具体的，于部分间隔单元510上，第一电极区域仅覆盖于间隔单元510的侧面503，即第一电极区域610仅包括第一部分611，第一部分611与第二电极区域620连接；于部分间隔单元510上，第一电极区域610同时覆盖于间隔单元510的侧面503及上端面502，第一电极区域610包括第一部分611和第二部分612，第一部分611连接第二电极区域620和第二部分612。
第二电极层602形成于非显示区的彩色滤光层30及间隔单元层50上且图案化设置。
在一实施例中，在基板10上所设置的与间隔单元510相对应的平台（未标示）的上表面为第二钝化层42的上表面，间隔单元510形成于第二钝化层42的上表面，第二电极区域620形成于第二钝化层42的上表面。
本申请提供的阵列基板，通过将电极层60形成于间隔单元层50上，增大了讯号线与电极层60之间的距离，从而使得电容变小，以此降低了基板10的讯号线（未图示）的负载。由于降低了对于讯号线的负载，对讯号线的材料的要求便降低了，从而可以降低液晶显示面板的材料及成本。
如图2所示，本申请另一实施例提供了一种液晶显示面板，包括上基板70、下基板（未标示）以及一液晶层（未图示），其中，下基板由上述实施例中所提供的阵列基板制成，上基板70与下基板对向设置，间隔单元501设置为稳定地维持上基板70和下基板之间的间距，并定义一液晶间隔空间。该液晶间隔空间由液晶层填满，下基板的周边设置有胶框（未图示），胶框附近设置有间隔单元501，第二电极层602覆盖在该间隔单元501上，第二电极层602与上基板70的公共电极层71连接导通，以此省略金球材料及涂布制程，从而可进一步降低液晶显示面板的材料及成本。本实施例所提供的液晶显示面板可进一步应用为平面型或曲面型的显示面板。
参考图1至图3所示，本申请一实施例还提供一种阵列基板的制造方法，包括以下步骤：
S11：提供一基板10，在基板10上形成多个主动开关20；
在本实施例中，主动开关20为薄膜晶体管（thin film transistor，TFT）层，其主要设置为控制液晶的站立角度。具体的，薄膜晶体管层是在基板10上沉积一层薄膜当做通道区，其包括栅极210、源极220及漏极230，栅极210上设置有栅极绝缘层211，源极220和漏极230均设置在栅极绝缘层211上。
S12：在基板10上形成彩色滤光层30；
在一实施例中，以阵列的形式在基板10上形成多个色阻单元310，多个色阻单元310构成彩色滤光层30。彩色滤光层30可例如包括有第一、第二、第三及第四色光阻层，在一些实施例中，第一、第二、第三及第四色光阻层可例如为红色、绿色、蓝色及白色光阻层，且第一、第二、第三及第四色光阻层之一的材料相同于间隔单元。在一实施例中，在每一个像素区域对应一种颜色的色阻单元310。
在一实施例中，基板10还包括一遮光层（比如黑色矩阵black matrix，BM），其位于彩色滤光层30上。
在一实施例中，基板10上形成有第一钝化层41，彩色滤光层30形成在第一钝化层41上。
在一实施例中，基板10还包括一遮光层（比如黑色矩阵black matrix，BM），其位于彩色滤光层30上。
在一实施例中，彩色滤光层30上还设置有第二钝化层42，第二钝化层42完全覆盖于彩色滤光层30上。
S13:形成间隔单元层50于彩色滤光层30上；
间隔单元层50包括多个间隔单元510，间隔单元510由绝缘材料制成。在一实施例中，在基板10上设置有多个与间隔单元510相对应的平台（未标示），使得间隔单元510能够更稳定地维持面板间距。具体的，间隔单元510形成于色阻单元310上，在一实施例中，仅在一部分色阻单元310上形成间隔单元510，而不是在每个色阻单元310上均形成间隔单元510。在一实施例中，间隔单元510呈梯形柱状，其上端面502的面积小于下端面501的面积。
S14：形成电极层60于彩色滤光层30及间隔单元层50上，包括：在基板10的显示区形成第一电极层601，在基板10的非显示区形成第二电极层602。
第一电极层601为像素电极层，像素电极层的材料为金属或金属氧化物，优选材料为铟锡氧化物（Indium tin oxide，ITO）。第二电极层602为导电电极层，其材料也为金属或金属氧化物，优选材料为铟锡氧化物（Indium tin oxide，ITO）。第一电极层601和第二电极层602可通过光刻胶曝光显影工艺及刻蚀工艺进行图案化。具体的，第一电极层601和第二电极层602可通过同一道光罩形成预设图案，也可以通过不同的光罩先后形成图案化。在本实施例中，第一电极层601和第二电极层602之间绝缘。第一电极层601形成于彩色滤光层30及间隔单元层50上。具体的，第一电极层601包括多个第一电极区域610和第二电极区域620，第一电极区域610覆盖于间隔单元510上，包括：第一电极区域610覆盖于间隔单元510的侧面和/或上端面，第二电极区域620形成于色阻单元310上。
定义第一电极区域610覆盖于间隔单元510的侧面503的部分为第一部分611，第一电极区域610覆盖于间隔单元510的上端面502的部分为第二部分612。由于第一电极层601和第二电极层602通过图案化形成，所以，对于最终形成的阵列基板，在部分色阻单元310上，仅形成有第二电极区域620；在部分色阻单元310上，同时形成有第一电极区域610和第二电极区域620，并且第一电极区域610和第二电极区域620连接。第一电极区域610形成于间隔单元510的侧面和/或上端面，具体的，于部分间隔单元510上，第一电极区域仅形成于间隔单元510的侧面503，即第一电极区域610仅包括第一部分611，第一部分611与第二电极区域620连接；于部分间隔单元510上，第一电极区域610同时形成于间隔单元510的侧面503及上端面502，第一电极区域610包括第一部分611和第二部分612，第一部分611连接第二电极区域620和第二部分612。
第二电极层602形成于非显示区的彩色滤光层30及间隔单元层50上，且通过图案化获得。
在一实施例中，在基板10上所设置的与间隔单元510相对应的平台（未标示）的上表面为第二钝化层42的上表面，间隔单元510形成于第二钝化层42的上表面，第二电极区域620形成于第二钝化层42的上表面。
参考图1、图2和图4所示，本申请另一实施例还提供一种液晶显示面板的制造方法，包括以下步骤：
S21：提供一基板10，在基板10上形成主动开关20；
基板10包括显示区和非显示区。在本实施例中，主动开关20为薄膜晶体管层，其具有控制液晶站立角度的作用。具体的，薄膜晶体管层是在基板10上沉积一层薄膜当做通道区，其包括栅极210、源极220及漏极230，栅极210上设置有栅极绝缘层211，源极220和漏极230均设置在栅极绝缘层211上。
薄膜晶体管层使用氢化非晶硅(a-Si:H)作为主要材料，其主要利用 a-Si:H TFT 的开态(大于开启电压)对电极层60快速充电，利用关态来保持电极层60的电压，从而实现快速响应和良好存储的统一。
在一实施例中，薄膜晶体管层在电极及内部接线使用铟锡氧化物(ITO)。
S22：在主动开关20上形成第一钝化层41；
具体的，第一钝化层41形成在源极220和漏极230之上并且完全覆盖源
极220和漏极230。第一钝化层41上形成有导通孔411。
S23：在第一钝化层41上形成彩色滤光层30；
多个色阻单元310以阵列的形式排布。彩色滤光层30可例如有第一、第二及第三色阻单元，在一些实施例中，第一、第二及第三色阻单元可例如为红色、绿色及蓝色色阻单元。在一实施例中，在每一个像素区域对应一种颜色的色阻单元310。
在一实施例中，基板10还包括一遮光层（比如黑色矩阵black matrix，BM），将其形成于彩色滤光层30上。
S24：在彩色滤光层30上形成第二钝化层42；
具体的，第二钝化层42完全覆盖在彩色滤光层30上。
S25：在第二钝化层42上形成间隔单元层50；
间隔单元层50包括多个间隔单元510，间隔单元510用以定义一液晶间隔空间，其由绝缘材料制成。在一实施例中，在基板10上设置有多个与间隔单元510相对应的平台（未标示），使得间隔单元510能够更稳定地维持面板间距。具体的，间隔单元510设置在色阻单元310上，且仅在一部分色阻单元310上形成间隔单元510，而不是每个色阻单元310上均形成间隔单元510。在一实施例中，间隔单元510呈梯形，其上表面的面积小于下表面的面积。
S26：将电极层60形成于第二钝化层42和间隔单元层50上，以得到下基板；
在第二钝化层42及间隔单元层50上形成电极层60，包括：在显示区的第二钝化层42及间隔单元层50上形成第一电极层601，在非显示区的第二钝化层42及间隔单元层50上形成第二电极层602。在本实施例中，第一电极层601和第二电极层602之间绝缘。第一电极层601和第二电极层60均通过图案化形成。具体的，第一电极层601包括多个第一电极区域610和第二电极区域620，第一电极区域610形成于间隔单元510上，包括：第一电极区域610形成于间隔单元510的侧面和/或上端面，第二电极区域620形成于色阻单元310上。
定义第一电极区域610形成于间隔单元510的侧面503的部分为第一部分611，第一电极区域610形成于间隔单元510的上端面502的部分为第二部分612。由于第一电极层601和第二电极层602通过图案化形成，所以，对于最终形成的阵列基板，在部分色阻单元310上，仅形成有第二电极区域620；在部分色阻单元310上，同时形成有第一电极区域610和第二电极区域620，并且第一电极区域610和第二电极区域620连接。第一电极区域610形成于间隔单元510的侧面和/或上端面，具体的，于部分间隔单元510上，第一电极区域仅形成于间隔单元510的侧面503，即第一电极区域610仅包括第一部分611，第一部分611与第二电极区域620连接；于部分间隔单元510上，第一电极区域610同时形成于间隔单元510的侧面503及上端面502，第一电极区域610包括第一部分611和第二部分612，第一部分611连接第二电极区域620和第二部分612。在基板10上所设置的与间隔单元510相对应的平台（未标示）的上表面为第二钝化层42的上表面，间隔单元510形成于第二钝化层42的上表面，第二电极区域620形成于第二钝化层42的上表面。
第二电极层602形成于非显示区的第二钝化层42及间隔单元层50上。
S27：提供一上基板70，将上基板70和下基板对向设置，间隔单元层50位于上基板70和下基板之间，间隔单元层50定义一液晶间隔空间；
间隔单元层50稳定地形成于上基板70和下基板之间，维持上基板70和下基板之间的间距不变。
在一实施例中，上基板70包括公共电极层71，主动开关20为电极层60进行供电，在液晶显示面板的显示区，上基板70的公共电极层71和下基板的电极层60之间形成电场。在液晶显示面板的非显示区，于下基板上设置有胶框（未图示），胶框附近设置有间隔单元510，第二电极层71覆盖在该间隔单元510上，第二电极层602与上基板70的公共电极层71连接导通，以此省略金球材料及涂布制程，从而可进一步降低液晶显示面板的材料及成本。
S28：在上述的液晶间隔空间内灌满液晶，制成液晶显示面板。
通过本申请提供的制造方法制成的阵列基板或液晶显示面板，将电极层60形成于间隔单元层50上，使得讯号线与电极层60的距离变大，电容变小，降低了电极层60的电阻，以此降低了基板10的讯号线（未图示）的负载。由于降低了对于讯号线的负载，对讯号线的材料的要求便降低了，同时，可省略金球材料及涂布制程，从而进一步降低阵列基板或液晶显示面板的材料及成本。
以上所述，仅是本申请的最佳实施例而已，并非对本申请作任何形式上的限制，任何熟悉本领域的技术人员，在不脱离本申请技术方案范围情况下，利用上述揭示的方法内容对本申请技术方案做出许多可能的变动和修饰，均属于权利要求保护的范围。

Claims (20)

  1. 一种阵列基板，包括：
    基板，包括显示区和非显示区；
    多个主动开关，阵列于所述基板上；
    彩色滤光层，阵列于所述基板上且形成于所述多个主动开关上；
    间隔单元层，形成于所述彩色滤光层上；以及，
    电极层，形成于所述彩色滤光层及所述间隔单元层上，所述电极层包括第一电极层和第二电极层，所述第一电极层位于所述显示区，所述第二电极层位于所述非显示区。
  2. 根据权利要求1所述的阵列基板，其中，所述间隔单元层包括多个间隔单元，所述第一电极层包括覆盖于所述间隔单元上的第一电极区域。
  3. 根据权利要求2所述的阵列基板，其中，所述第一电极区域覆盖所述间隔单元包括：所述第一电极区域覆盖于所述间隔单元的侧面和/或上端面。
  4. 根据权利要求2所述的阵列基板，其中，所述第一电极区域形成于至少部分所述间隔单元上。
  5. 根据权利要求2所述的阵列基板，其中，在所述基板上形成多个色阻单元阵列排布构成所述彩色滤光层，所述第一电极层还包括形成于所述色阻单元上的第二电极区域，所述第二电极区域和所述第一电极区域连接。
  6. 根据权利要求1所述的阵列基板，其中，所述第二电极层和所述第一电极层之间绝缘。
  7. 根据权利要求1所述的阵列基板，其中，所述主动开关为薄膜晶体管层，其包括栅极、源极及漏极。
  8. 根据权利要求7所述的阵列基板，其中，所述薄膜晶体管层在电极及内部接线时为铟锡氧化物。
  9. 根据权利要求7所述的阵列基板，其中，所述基板还包括设置在所述薄膜晶体管层上的第一钝化层，所述第一钝化层设置在所述源极和漏极之上并且完全覆盖所述源极和漏极，所述第一钝化层上设置有导通孔，所述漏极通过所述导通孔与所述电极层相连。
  10. 根据权利要求7所述的阵列基板，其中，所述基板还包括一遮光层，所述遮光层位于所述彩色滤光层上。
  11. 一种显示面板，包括：
    第一基板，包括公共电极层；
    第二基板，包括阵列基板，所述第二基板与所述第一基板对向设置；
    所述第二电极层与所述公共电极层连接导通，所述阵列基板包括：
    基板，包括显示区和非显示区；
    多个主动开关，阵列于所述基板上；
    彩色滤光层，阵列于所述基板上且形成于所述多个主动开关上；
    间隔单元层，形成于所述彩色滤光层上；以及，
    电极层，形成于所述彩色滤光层及所述间隔单元层上，所述电极层包括第一电极层和第二电极层，所述第一电极层位于所述显示区，所述第二电极层位于所述非显示区。
  12. 一种阵列基板的制造方法，包括如下步骤：
    提供一基板，在所述基板上形成多个主动开关；
    在所述基板上形成彩色滤光层；
    形成间隔单元层于所述彩色滤光层上；以及
    形成电极层于所述彩色滤光层及所述间隔单元层上，包括：在所述基板的显示区形成第一电极层，在所述基板的非显示区形成第二电极层。
  13. 根据权利要求12所述的阵列基板的制造方法，其中，所述基板还包括一遮光层，将其形成于所述彩色滤光层上。
  14. 根据权利要求12所述的阵列基板的制造方法，其中，在所述主动开关上形成第一钝化层；在所述第一钝化层上形成所述彩色滤光层。
  15. 根据权利要求12所述的阵列基板的制造方法，其中，在所述基板上形成多个色阻单元阵列排布构成所述彩色滤光层，在至少部分所述色阻单元上形成间隔单元，多个所述间隔单元构成所述间隔单元层。
  16. 根据权利要求15所述的阵列基板的制造方法，其中，所述第一电极层包括形成于所述间隔单元上的第一电极区域，所述第一电极区域形成于所述间隔单元的侧面和/或上端面。
  17. 根据权利要求12所述的阵列基板的制造方法，其中，在所述彩色滤光层上形成第二钝化层；在所述第二钝化层上形成所述间隔单元层。
  18. 根据权利要求17所述的阵列基板的制造方法，其中，将所述电极层形成于所述第二钝化层和间隔单元层上。
  19. 根据权利要求17所述的阵列基板的制造方法，其中，在显示区的第二钝化层及间隔单元层上形成所述第一电极层，在非显示区的第二钝化层及间隔单元层上形成所述第二电极层。
  20. 根据权利要求12所述的阵列基板的制造方法，其中，所述第二电极层和所述第一电极层之间绝缘。
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