WO2019056529A1 - 一种液晶显示面板及阵列基板 - Google Patents

一种液晶显示面板及阵列基板 Download PDF

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Publication number
WO2019056529A1
WO2019056529A1 PCT/CN2017/110323 CN2017110323W WO2019056529A1 WO 2019056529 A1 WO2019056529 A1 WO 2019056529A1 CN 2017110323 W CN2017110323 W CN 2017110323W WO 2019056529 A1 WO2019056529 A1 WO 2019056529A1
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Prior art keywords
gate
layer
drain
tin oxide
array substrate
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PCT/CN2017/110323
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English (en)
French (fr)
Inventor
郝思坤
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/574,226 priority Critical patent/US20190086751A1/en
Publication of WO2019056529A1 publication Critical patent/WO2019056529A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a liquid crystal display panel and an array substrate.
  • Liquid crystal display is one of the most widely used flat panel displays, and has gradually become a widely used electronic device such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptop screens with high-resolution color screens. monitor.
  • PDAs personal digital assistants
  • monitor computer screens or laptop screens with high-resolution color screens. monitor.
  • a vertical electric field mode display such as TN (Twist) can be formed. Nematic) mode, VA (Vertical Alignment) mode, and MVA (Multi-domain Vertical) developed to solve narrow viewing angles Alignment).
  • IPS In-plane
  • FFS Frringe Field Switching
  • the VA mode thin film transistor display is adopted for a large-sized panel such as a liquid crystal television with its high opening, high resolution, wide viewing angle, etc., and the pixel liquid crystal designed by the conventional method is low in efficiency.
  • the horseshoe-shaped TFT takes up too much space, increases the width in the horizontal direction, and reduces the aperture ratio of the pixel, thereby reducing the light transmittance of the liquid crystal panel.
  • the invention provides a liquid crystal display panel and an array substrate, which can increase the aperture ratio of the pixel electrode and increase the optical transmittance of the liquid crystal display.
  • the invention provides an array substrate of a liquid crystal display, the array substrate comprising:
  • a gate electrode formed on the first substrate and connected to the gate line
  • a gate insulating layer formed on the first substrate and covering the gate line and the gate;
  • a data line formed on the gate insulating layer and perpendicular to the gate line, wherein the data line and the gate line are used to jointly define a pixel region;
  • a semiconductor active layer formed on the gate insulating layer corresponding to the gate, and a cross-sectional width of the semiconductor active layer is smaller than a cross-sectional width of the gate;
  • a drain formed on a surface of the gate insulating layer and in contact with one end of the semiconductor active layer
  • a source formed on the surface of the gate insulating layer and in contact with the opposite end of the semiconductor active layer, the source being connected to the indium tin oxide pixel electrode;
  • the data line covers at least a portion of the semiconductor active layer; the source portion is used to connect the indium tin oxide pixel electrode, and the other portion is extended as a metal light blocking layer.
  • the area of the data line covering the semiconductor active layer is equal to the area of the corresponding portion of the drain parallel to the data line.
  • the shape of the longitudinal section of the drain is a horseshoe shape
  • the longitudinal section is a section parallel to the first substrate
  • the side of the drain with respect to the source is In the horseshoe-shaped recess
  • the source is insulated from the drain corresponding to the recess.
  • the source first portion covers the semiconductor active layer, and the remaining second portion extends outward to a position corresponding to the gate, the second portion shape being the Metal light barrier layer pattern.
  • the second portion is in the same layer as the first portion and is arranged parallel to the data line.
  • the array substrate further includes an indium tin oxide common electrode, and the indium tin oxide common electrode covers a region other than the indium tin oxide pixel electrode.
  • the indium tin oxide common electrode covers the switching unit.
  • the invention also provides a display panel, the display panel comprising:
  • a gate insulating layer formed on the first substrate and covering the gate line
  • a data line formed on the gate insulating layer and perpendicular to the gate line, wherein the data line and the gate line are used to jointly define a pixel region;
  • the thin film transistor layer formed on the gate insulating layer, the thin film transistor layer including a switching unit;
  • the switching unit includes a source and a drain, and at least a portion of the drain multiplexes part of the data line,
  • the source portion is used to connect the indium tin oxide pixel electrode, and the other portion is extended as a metal light blocking layer.
  • the second substrate comprises a black matrix, the black matrix covering the data lines and the switching unit.
  • the invention also provides an array substrate of a liquid crystal display, the array substrate comprising:
  • a gate electrode formed on the first substrate and connected to the gate line
  • a gate insulating layer formed on the first substrate and covering the gate line and the gate;
  • a data line formed on the gate insulating layer and perpendicular to the gate line, wherein the data line and the gate line are used to jointly define a pixel region;
  • a semiconductor active layer formed on the gate insulating layer corresponding to the gate, and a cross-sectional width of the semiconductor active layer is smaller than a cross-sectional width of the gate;
  • a drain formed on a surface of the gate insulating layer and in contact with one end of the semiconductor active layer
  • a source formed on the surface of the gate insulating layer and in contact with the opposite end of the semiconductor active layer, the source being connected to the indium tin oxide pixel electrode;
  • the source portion is used to connect the indium tin oxide pixel electrode, and the other portion is extended as a metal light blocking layer.
  • the area of the data line covering the semiconductor active layer is equal to the area of the corresponding portion of the drain parallel to the data line.
  • the shape of the longitudinal section of the drain is a horseshoe shape
  • the longitudinal section is a section parallel to the first substrate
  • the side of the drain with respect to the source is In the horseshoe-shaped recess
  • the source is insulated from the drain corresponding to the recess.
  • the source first portion covers the semiconductor active layer, and the remaining second portion extends outward to a position corresponding to the gate, the second portion shape being the Metal light barrier layer pattern.
  • the second portion is in the same layer as the first portion and is arranged parallel to the data line.
  • the array substrate further includes an indium tin oxide common electrode, and the indium tin oxide common electrode covers a region other than the indium tin oxide pixel electrode.
  • the indium tin oxide common electrode covers the switching unit.
  • the horseshoe-shaped TFT of the liquid crystal display panel of the present invention reduces the horizontal width by the drain half structure by means of the data line, so that the horseshoe TFT The occupied space is reduced;
  • the metal light blocking layer in the vicinity of the TFT of the present invention is made of a second layer of metal, which can function as a light blocking function and is a source of the TFT, and functions as a conducting TFT and a pixel electrode.
  • the regions other than the ITO pixel electrode are covered with the ITO common electrode, which greatly reduces the capacitive coupling between the Array substrate and the CF substrate.
  • FIGS. 1a-1d are schematic diagrams showing the structure of an array substrate film layer according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a pixel in a display panel according to an embodiment of the present invention.
  • the present invention is directed to the prior art liquid crystal display panel, in which the horseshoe-shaped TFT takes up too much space and reduces the aperture ratio of the pixel, thereby reducing the optical transmittance of the liquid crystal panel.
  • This embodiment can solve the defect.
  • a schematic diagram of a first metal film layer structure of an array substrate includes: a first substrate 101; a gate line 102 formed on the first substrate 101; a gate electrode 103 is formed on the first substrate 101 and connected to the gate line 102.
  • the common electrode line 104 is prepared in the same layer as the gate line 102 and is spaced apart from the gate line 102.
  • a gate insulating layer is formed on the first substrate 101 and covers the gate line 102 and the gate electrode 103 and the common electrode line 104.
  • a schematic structural diagram of a second metal film layer of an array substrate includes: a data line 105 formed on the gate insulating layer and perpendicular to the gate line 102.
  • the data line 105 and the gate line 102 are used to jointly define a pixel region;
  • a semiconductor active layer 106 is formed on the gate insulating layer corresponding to the gate 103, and the semiconductor active layer 106
  • the cross-sectional width is smaller than the cross-sectional width of the gate 103
  • the side of the drain 107 opposite to the source 108 is the horseshoe-shaped recess, and the source 108 is insulated from the drain 107 corresponding to the recess.
  • the first portion 1081 of the source 108 is used to connect the indium tin oxide pixel electrode, and the second portion 1082 extends from the first portion 1081 as a metal light blocking layer.
  • the first portion 1081 of the source 108 covers the semiconductor active layer 106, and the remaining second portion 1082 extends outward to a position corresponding to the gate 103, the second portion 1082 shape
  • the metal light blocking layer pattern is used to cover the pixel electrode edge region.
  • the second portion 1082 is in the same layer as the first portion 1081 and is disposed parallel to the data line 105.
  • the drain 107 and the source 108 cause the semiconductor active layer 106 to form a corresponding channel region.
  • the drain 107, the source 108, and the data line 105 are all the second metal film layer, and at least a portion of the drain 107 multiplexes part of the data line 105,
  • the source 108 is extended and multiplexed into the metal light shielding layer, which greatly simplifies the process, shortens the time, reduces the overall proportion of the TFT, and utilizes the space more reasonably.
  • FIG. 1c a schematic diagram of a color tone layer structure of an array substrate is provided in an embodiment of the present invention.
  • a color group layer 109 is formed on a second metal layer, and the color group layer 109 is disposed at a corresponding position corresponding to the source.
  • a via layer is formed on the color group layer 109, and the via layer is provided with a second via hole corresponding to the position of the first via hole 110, and then the pixel electrode layer is prepared on the via layer.
  • the array substrate includes an indium tin oxide pixel electrode 111, and the indium tin oxide pixel electrode 111 includes a cross-shaped main electrode and a plurality of branches. a dry electrode, the main electrode is divided into four regions, the branch electrode is connected to the trunk electrode in a fishbone shape; one end of the indium tin oxide pixel electrode 111 is passed through The second via and the first via are connected to the source; the second portion 1082 of the source covers the edge of the indium tin oxide pixel electrode 111.
  • An insulating layer is prepared on the indium tin oxide pixel electrode 111, and an indium tin oxide common electrode 112 is prepared on the insulating layer, and the indium tin oxide common electrode 112 covers an area other than the indium tin oxide pixel electrode 111.
  • the indium tin oxide common electrode 112 covers the switching unit. In this embodiment, the region other than the indium tin oxide pixel electrode 111 is covered with the indium tin oxide common electrode 112, and the capacitive coupling between the array substrate and the color filter substrate is greatly reduced.
  • the present invention also provides a display panel, the display panel comprising: a first substrate; a gate line formed on the first substrate; a gate insulating layer formed on the first substrate and covering the gate a data line formed on the gate insulating layer and perpendicular to the gate line, wherein the data line and the gate line are used to jointly define a pixel region; a thin film transistor layer formed on the gate insulating layer On the layer, the thin film transistor layer includes a switching unit; an indium tin oxide pixel electrode formed on the thin film transistor layer; a liquid crystal layer; and a second substrate disposed opposite to the first substrate; wherein the switching unit comprises a source and a drain, at least a portion of the drain multiplexing a portion of the data line, The source portion is used to connect the indium tin oxide pixel electrode, and the other portion is extended as a metal light blocking layer.
  • the second substrate includes a black matrix 201 covering the data line and the switch unit; the black matrix 201 covers a frame region of the indium tin oxide pixel electrode 202, and a phase A gap region between the two indium tin oxide pixel electrodes 202 is adjacent.
  • the spacing between the TFT and the data line is reduced to be connected, and a portion of the drain multiplexes the data line, so that the occupied area of the TFT in the horizontal direction is greatly reduced, thereby correspondingly reducing
  • the cover area of the black matrix 201 on the indium tin oxide pixel electrode 202 is increased, and the effective display area of the indium tin oxide pixel electrode 202 is increased, thereby increasing the aperture ratio. Increase the optical transmittance of the liquid crystal display.
  • the horseshoe-shaped TFT of the liquid crystal display panel of the present invention reduces the horizontal width by the drain half structure by means of the data line, so that the space of the horseshoe TFT is reduced;
  • the metal light blocking layer near the TFT is made of a second layer of metal, which functions as both a light blocking function and a source of the TFT, and functions to turn on the TFT and the pixel electrode.
  • the regions other than the ITO pixel electrode are covered with the ITO common electrode, which greatly reduces the capacitive coupling between the Array substrate and the CF substrate.

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  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
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Abstract

一种液晶显示面板及阵列基板，阵列基板包括：第一基板(101)、栅极线(102)、栅极(103)、栅绝缘层、数据线(105)、半导体有源层(106)，以及漏极(107)，与半导体有源层(106)的一端接触；源极(108)，与半导体有源层(106)的另一端接触；其中，漏极(107)的至少一部分复用部分数据线(105)，源极(108)一部分(1082)延伸作为金属挡光层。

Description

一种液晶显示面板及阵列基板 技术领域
本发明涉及显示技术领域，尤其涉及一种液晶显示面板及阵列基板。
 背景技术
液晶显示器是目前使用最广泛的一种平板显示器，已经逐渐成为各种电子设备如移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕所广泛应用具有高分辨率彩色屏幕的显示器。
目前普遍采用的液晶显示器，通常有上下衬底和中间液晶层组成，衬底有玻璃和电极等组成。如果上下衬底都有电极，可以形成纵向电场模式的显示器，如TN（Twist Nematic）模式，VA（Vertical Alignment）模式，以及为了解决视角过窄开发的MVA（Multi-domain Vertical Alignment）。另外一类与上述显示器不同，电极只位于衬底的一侧，形成横向电场模式的显示器，如IPS（In-plane switching）模式、FFS（Fringe Field Switching）模式等。
VA模式薄膜晶体管显示器，以其高开口、高分辨率、广视角等特点为液晶电视等大尺寸面板采用，使用传统方法设计的像素液晶效率低。
综上所述，现有技术的VA模式液晶显示器中，马蹄形TFT占用空间过大，增加了其水平方向的宽度，降低了像素的开口率，从而使液晶面板的光穿透率降低。
 技术问题
本发明提供一种液晶显示面板及阵列基板，能够提升像素电极的开口率，增加液晶显示器的光学穿透率。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种液晶显示器的阵列基板，所述阵列基板包括：
第一基板；
栅极线，形成于所述第一基板上；
栅极，形成于所述第一基板上，并连接于所述栅极线；
栅绝缘层，形成在所述第一基板上并覆盖所述栅极线与所述栅极；
数据线，形成于所述栅绝缘层上面，与所述栅极线相互垂直，所述数据线和所述栅极线用以共同界定像素区域；
半导体有源层，形成在所述栅极对应的所述栅极绝缘层上，且所述半导体有源层的截面宽度小于所述栅极的截面宽度 ；以及
漏极，形成在所述栅极绝缘层表面，且与所述半导体有源层的一端接触；
源极，形成在所述栅极绝缘层表面，且与所述半导体有源层的相对另一端接触，所述源极与氧化铟锡像素电极相连；
其中，所述漏极的至少一部分复用部分所述数据线, 所述数据线覆盖所述半导体有源层至少一部分；所述源极一部分用以连接所述氧化铟锡像素电极，相对另一部分延伸作为金属挡光层。
根据本发明一优选实施例，所述数据线覆盖所述半导体有源层的面积等于与所述数据线平行的所述漏极相应部分的面积。
根据本发明一优选实施例，所述漏极的纵截面的形状为马蹄状，所述纵截面为平行于所述第一基板的截面，所述漏极相对所述源极的一侧为所述马蹄状的凹部，所述源极对应所述凹部与所述漏极绝缘设置。
根据本发明一优选实施例，所述源极第一部分覆盖所述半导体有源层，其余的第二部分向外延伸至对应所述栅极之外的位置，所述第二部分形状为所述金属挡光层图形。
根据本发明一优选实施例，所述第二部分与所述第一部分同层，且平行于所述数据线设置。
根据本发明一优选实施例，所述阵列基板还包括氧化铟锡公共电极，所述氧化铟锡公共电极覆盖所述氧化铟锡像素电极以外的区域。
根据本发明一优选实施例，所述氧化铟锡公共电极覆盖所述开关单元。
本发明还提供一种显示面板，所述显示面板包括：
第一基板；
栅极线，形成于所述第一基板上；
栅绝缘层，形成在所述第一基板上并覆盖所述栅极线；
数据线，形成于所述栅绝缘层上面，与所述栅极线相互垂直，所述数据线和所述栅极线用以共同界定像素区域；
薄膜晶体管层，形成于所述栅绝缘层上，所述薄膜晶体管层包括开关单元；
氧化铟锡像素电极，形成于所述薄膜晶体管层上；
液晶层；
第二基板，与所述第一基板相对设置；
其中，所述开关单元包括源极与漏极，所述漏极的至少一部分复用部分所述数据线, 所述源极一部分用以连接所述氧化铟锡像素电极，相对另一部分延伸作为金属挡光层。
根据本发明一优选实施例，所述第二基板包括黑色矩阵，所述黑色矩阵遮盖所述数据线以及所述开关单元。
本发明还提供一种液晶显示器的阵列基板，所述阵列基板包括：
第一基板；
栅极线，形成于所述第一基板上；
栅极，形成于所述第一基板上，并连接于所述栅极线；
栅绝缘层，形成在所述第一基板上并覆盖所述栅极线与所述栅极；
数据线，形成于所述栅绝缘层上面，与所述栅极线相互垂直，所述数据线和所述栅极线用以共同界定像素区域；
半导体有源层，形成在所述栅极对应的所述栅极绝缘层上，且所述半导体有源层的截面宽度小于所述栅极的截面宽度；以及
漏极，形成在所述栅极绝缘层表面，且与所述半导体有源层的一端接触；
源极，形成在所述栅极绝缘层表面，且与所述半导体有源层的相对另一端接触，所述源极与氧化铟锡像素电极相连；
其中，所述漏极的至少一部分复用部分所述数据线, 所述源极一部分用以连接所述氧化铟锡像素电极，相对另一部分延伸作为金属挡光层。
根据本发明一优选实施例，所述数据线覆盖所述半导体有源层的面积等于与所述数据线平行的所述漏极相应部分的面积。
根据本发明一优选实施例，所述漏极的纵截面的形状为马蹄状，所述纵截面为平行于所述第一基板的截面，所述漏极相对所述源极的一侧为所述马蹄状的凹部，所述源极对应所述凹部与所述漏极绝缘设置。
根据本发明一优选实施例，所述源极第一部分覆盖所述半导体有源层，其余的第二部分向外延伸至对应所述栅极之外的位置，所述第二部分形状为所述金属挡光层图形。
根据本发明一优选实施例，所述第二部分与所述第一部分同层，且平行于所述数据线设置。
根据本发明一优选实施例，所述阵列基板还包括氧化铟锡公共电极，所述氧化铟锡公共电极覆盖所述氧化铟锡像素电极以外的区域。
根据本发明一优选实施例，所述氧化铟锡公共电极覆盖所述开关单元。
 有益效果
本发明的有益效果为：相较于现有技术的液晶显示面板，本发明的液晶显示面板的马蹄形TFT，通过将漏极半边结构借助数据线，减小了其水平方向的宽度，使马蹄形TFT占用空间减小；本发明的TFT附近的金属挡光层，使用第二层金属制作，该部分结构既可以起到挡光的作用，又是TFT的源极，起到导通TFT和像素电极的作用。在ITO像素电极以外的区域，均使用ITO公共电极覆盖，大幅降低了Array基板和CF基板间的电容耦合。通过使用本发明的TFT、遮光结构、ITO公共电极，使显示面板水平方向的不透光区域宽度大幅变窄，像素的开口率增加，光学穿透率提升。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a-图1d为本发明实施例提供的一种阵列基板膜层结构示意图；
图2 为本发明实施例提供的显示面板中像素结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有技术的液晶显示面板，马蹄形TFT占用空间过大，降低了像素的开口率，从而使液晶面板的光穿透率降低的技术问题，本实施例能够解决该缺陷。
下面结合附图详细介绍本发明具体实施例提供的液晶显示面板及阵列基板。
如图1a所示，本发明实施例提供的一种阵列基板第一金属膜层结构示意图，所述阵列基板包括：第一基板101；栅极线102，形成于所述第一基板101上；栅极103，形成于所述第一基板101上，并连接于所述栅极线102；公共电极线104，与所述栅极线102同层制备，且与所述栅极线102间隔设置；栅绝缘层，形成在所述第一基板101上并覆盖所述栅极线102与所述栅极103以及所述公共电极线104。
如图1b所示，本发明实施例提供的一种阵列基板第二金属膜层结构示意图，包括：数据线105，形成于所述栅绝缘层上面，与所述栅极线102相互垂直，所述数据线105和所述栅极线102用以共同界定像素区域；半导体有源层106，形成在所述栅极103对应的所述栅极绝缘层上，且所述半导体有源层106的截面宽度小于所述栅极103的截面宽度 ；以及漏极107，形成在所述栅极绝缘层表面，且与所述半导体有源层106的一端接触；具体地，所述漏极107可位于所述半导体有源层106的覆盖范围内；源极108，形成在所述栅极绝缘层表面，且与所述半导体有源层106的相对另一端接触，所述源极108与氧化铟锡像素电极相连；其中，所述漏极107的至少一部分复用部分所述数据线105, 所述数据线105覆盖所述半导体有源层106至少一部分；所述漏极107的纵截面的形状为马蹄状，所述纵截面为平行于所述第一基板101的截面，所述数据线105覆盖所述半导体有源层106的面积等于与所述数据线105平行的所述漏极107相应部分的面积。所述漏极107相对所述源极108的一侧为所述马蹄状的凹部，所述源极108对应所述凹部与所述漏极107绝缘设置。所述源极108的第一部分1081用以连接所述氧化铟锡像素电极，由所述第一部分1081延伸出第二部分1082，作为金属挡光层。所述源极108的所述第一部分1081覆盖所述半导体有源层106，其余的所述第二部分1082向外延伸至对应所述栅极103之外的位置，所述第二部分1082形状为所述金属挡光层图形，用于遮盖所述像素电极边缘区域。其中，所述第二部分1082与所述第一部分1081同层，且平行于所述数据线105设置。所述漏极107与所述源极108使所述半导体有源层106形成相应的沟道区域。
所述漏极107、所述源极108、所述数据线105均为所述第二金属膜层，所述漏极107的至少一部分复用部分所述数据线105, 且所述源极108延伸复用为所述金属遮光层，大大简化了制程，缩短了时间，使TFT的整体占比缩小，更合理的利用了空间。
如图1c所示，本发明实施例提供的一种阵列基板色组层结构示意图，在第二金属层上制作一色组层109，所述色组层109在对应所述源极的相应位置设置一第一通孔110，所述第一通孔110用于将像素电极连接与TFT开关。之后在所述色组层109上制备一层过孔层，所述过孔层对应所述第一通孔110的位置设置有第二通孔，之后在所述过孔层上制备像素电极层。
如图1d所示，本发明实施例提供的一种阵列基板电极层结构示意图，所述阵列基板包括氧化铟锡像素电极111，所述氧化铟锡像素电极111包括十字形主干电极与多个支干电极，所述主干电极将所述氧化铟锡像素电极111分为四个区域，所述支干电极呈鱼骨形与所述主干电极连接；所述氧化铟锡像素电极111的一端通过所述第二过孔以及所述第一过孔与源极连接；所述源极的第二部分1082遮盖所述氧化铟锡像素电极111的边缘。在所述氧化铟锡像素电极111上制备一层绝缘层，在所述绝缘层上制备氧化铟锡公共电极112，所述氧化铟锡公共电极112覆盖所述氧化铟锡像素电极111以外的区域；所述氧化铟锡公共电极112覆盖所述开关单元。本实施例通过在所述氧化铟锡像素电极111以外的区域，均使用所述氧化铟锡公共电极112覆盖，大幅降低了所述阵列基板和彩膜基板间的电容耦合。
本发明还提供一种显示面板，所述显示面板包括：第一基板；栅极线，形成于所述第一基板上；栅绝缘层，形成在所述第一基板上并覆盖所述栅极线；数据线，形成于所述栅绝缘层上面，与所述栅极线相互垂直，所述数据线和所述栅极线用以共同界定像素区域；薄膜晶体管层，形成于所述栅绝缘层上，所述薄膜晶体管层包括开关单元；氧化铟锡像素电极，形成于所述薄膜晶体管层上；液晶层；第二基板，与所述第一基板相对设置；其中，所述开关单元包括源极与漏极，所述漏极的至少一部分复用部分所述数据线, 所述源极一部分用以连接所述氧化铟锡像素电极，相对另一部分延伸作为金属挡光层。如图2所示，所述第二基板包括黑色矩阵201，所述黑色矩阵201遮盖所述数据线以及所述开关单元；所述黑色矩阵201遮盖氧化铟锡像素电极202的边框区域，以及相邻两所述氧化铟锡像素电极202的间隙区域。由于本实施例中TFT与所述数据线之间的间距缩小至相连，所述漏极的一部分复用所述数据线，使所述TFT在水平方向上占用面积大大减小，从而相应的减小了所述黑色矩阵201在所述氧化铟锡像素电极202上的遮盖面积，增加了所述氧化铟锡像素电极202的有效显示面积，进而增大了开口率, 增加液晶显示器的光学穿透率。
相较于现有技术的液晶显示面板，本发明的液晶显示面板的马蹄形TFT，通过将漏极半边结构借助数据线，减小了其水平方向的宽度，使马蹄形TFT占用空间减小；本发明的TFT附近的金属挡光层，使用第二层金属制作，该部分结构既可以起到挡光的作用，又是TFT的源极，起到导通TFT和像素电极的作用。在ITO像素电极以外的区域，均使用ITO公共电极覆盖，大幅降低了Array基板和CF基板间的电容耦合。通过使用本发明的TFT、遮光结构、ITO公共电极，使显示面板水平方向的不透光区域宽度大幅变窄，像素的开口率增加，光学穿透率提升。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种液晶显示器的阵列基板，其包括：
    第一基板；
    栅极线，形成于所述第一基板上；
    栅极，形成于所述第一基板上，并连接于所述栅极线；
    栅绝缘层，形成在所述第一基板上并覆盖所述栅极线与所述栅极；
    数据线，形成于所述栅绝缘层上面，与所述栅极线相互垂直，所述数据线和所述栅极线用以共同界定像素区域；
    半导体有源层，形成在所述栅极对应的所述栅极绝缘层上，且所述半导体有源层的截面宽度小于所述栅极的截面宽度 ；以及
    漏极，形成在所述栅极绝缘层表面，且与所述半导体有源层的一端接触；
    源极，形成在所述栅极绝缘层表面，且与所述半导体有源层的相对另一端接触，所述源极与氧化铟锡像素电极相连；
    其中，所述漏极的至少一部分复用部分所述数据线, 所述数据线覆盖所述半导体有源层至少一部分；所述源极一部分用以连接所述氧化铟锡像素电极，相对另一部分延伸作为金属挡光层。
  2. 根据权利要求1所述的阵列基板，其中，所述数据线覆盖所述半导体有源层的面积等于与所述数据线平行的所述漏极相应部分的面积。
  3. 根据权利要求1所述的阵列基板，其中，所述漏极的纵截面的形状为马蹄状，所述纵截面为平行于所述第一基板的截面，所述漏极相对所述源极的一侧为所述马蹄状的凹部，所述源极对应所述凹部与所述漏极绝缘设置。
  4. 根据权利要求3所述的阵列基板，其中，所述源极第一部分覆盖所述半导体有源层，其余的第二部分向外延伸至对应所述栅极之外的位置，所述第二部分形状为所述金属挡光层图形。
  5. 根据权利要求4所述的阵列基板，其中，所述第二部分与所述第一部分同层，且平行于所述数据线设置。
  6. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括氧化铟锡公共电极，所述氧化铟锡公共电极覆盖所述氧化铟锡像素电极以外的区域。
  7. 根据权利要求6所述的阵列基板，其中，所述氧化铟锡公共电极覆盖所述开关单元。
  8. 一种显示面板，其包括：
    第一基板；
    栅极线，形成于所述第一基板上；
    栅绝缘层，形成在所述第一基板上并覆盖所述栅极线；
    数据线，形成于所述栅绝缘层上面，与所述栅极线相互垂直，所述数据线和所述栅极线用以共同界定像素区域；
    薄膜晶体管层，形成于所述栅绝缘层上，所述薄膜晶体管层包括开关单元；
    氧化铟锡像素电极，形成于所述薄膜晶体管层上；
    液晶层；
    第二基板，与所述第一基板相对设置；
    其中，所述开关单元包括源极与漏极，所述漏极的至少一部分复用部分所述数据线, 所述源极一部分用以连接所述氧化铟锡像素电极，相对另一部分延伸作为金属挡光层。
  9. 根据权利要求8所述的显示面板，其中，所述第二基板包括黑色矩阵，所述黑色矩阵遮盖所述数据线以及所述开关单元。
  10. 一种液晶显示器的阵列基板，其包括：
    第一基板；
    栅极线，形成于所述第一基板上；
    栅极，形成于所述第一基板上，并连接于所述栅极线；
    栅绝缘层，形成在所述第一基板上并覆盖所述栅极线与所述栅极；
    数据线，形成于所述栅绝缘层上面，与所述栅极线相互垂直，所述数据线和所述栅极线用以共同界定像素区域；
    半导体有源层，形成在所述栅极对应的所述栅极绝缘层上，且所述半导体有源层的截面宽度小于所述栅极的截面宽度 ；以及
    漏极，形成在所述栅极绝缘层表面，且与所述半导体有源层的一端接触；
    源极，形成在所述栅极绝缘层表面，且与所述半导体有源层的相对另一端接触，所述源极与氧化铟锡像素电极相连；
    其中，所述漏极的至少一部分复用部分所述数据线, 所述源极一部分用以连接所述氧化铟锡像素电极，相对另一部分延伸作为金属挡光层。
  11. 根据权利要求10所述的阵列基板，其中，所述数据线覆盖所述半导体有源层的面积等于与所述数据线平行的所述漏极相应部分的面积。
  12. 根据权利要求10所述的阵列基板，其中，所述漏极的纵截面的形状为马蹄状，所述纵截面为平行于所述第一基板的截面，所述漏极相对所述源极的一侧为所述马蹄状的凹部，所述源极对应所述凹部与所述漏极绝缘设置。
  13. 根据权利要求12所述的阵列基板，其中，所述源极第一部分覆盖所述半导体有源层，其余的第二部分向外延伸至对应所述栅极之外的位置，所述第二部分形状为所述金属挡光层图形。
  14. 根据权利要求13所述的阵列基板，其中，所述第二部分与所述第一部分同层，且平行于所述数据线设置。
  15. 根据权利要求10所述的阵列基板，其中，所述阵列基板还包括氧化铟锡公共电极，所述氧化铟锡公共电极覆盖所述氧化铟锡像素电极以外的区域。
  16. 根据权利要求15所述的阵列基板，其中，所述氧化铟锡公共电极覆盖所述开关单元。
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