WO2020113687A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2020113687A1
WO2020113687A1 PCT/CN2018/122143 CN2018122143W WO2020113687A1 WO 2020113687 A1 WO2020113687 A1 WO 2020113687A1 CN 2018122143 W CN2018122143 W CN 2018122143W WO 2020113687 A1 WO2020113687 A1 WO 2020113687A1
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WO
WIPO (PCT)
Prior art keywords
gate
chip
flip
substrate
display panel
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PCT/CN2018/122143
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English (en)
French (fr)
Inventor
黄北洲
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惠科股份有限公司
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Publication of WO2020113687A1 publication Critical patent/WO2020113687A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a display device.
  • the gate control signal sent from the printed circuit board is routed through the array (WOA, Wire On Array) to thin film transistor (TFT, Thin Film Transistor) gate to control the thin film transistors to turn on line by line.
  • WA Wire On Array
  • TFT Thin Film Transistor
  • H-block phenomenon Horizontal Block, bad horizontal block.
  • the main purpose of the present application is to provide a display panel and a display device to achieve uniform brightness display of the display panel and avoid H-block phenomenon.
  • a display panel proposed by the present application wherein the display panel includes: a first substrate, and a data flip-chip film is provided on one side of the first substrate;
  • a second substrate which is spaced apart from the first substrate
  • a plurality of gate flip-chip films, the gate flip-chip films are disposed on the first substrate on a side different from the data flip-chip film;
  • array traces are provided on the first substrate and are electrically connected to the data flip chip and the plurality of gate flip chip films;
  • the lengths of the array traces connected from the data flip-chip film to different gate flip-chip films are equal.
  • the array traces are arranged in a zigzag shape.
  • the array traces are arranged in a curved shape.
  • the array wiring includes:
  • An extension section extending from the data flip chip to the side where the gate flip chip is located;
  • a plurality of connecting segments each of the connecting segments is connected to each gate flip-chip film from the extending segment;
  • the lengths of the connecting segments in multiple segments are equal.
  • the first substrate includes a display area and a wiring area provided around the display area, and the data flip chip and the gate flip chip are provided on the wiring area.
  • the data flip chip and the gate flip chip are respectively disposed on different sides of the wiring area perpendicular to each other.
  • the display area is provided with a plurality of gate lines arranged in parallel, and the wiring area is further provided with a plurality of sets of fan-shaped leads corresponding to the number of gate flip-chip films.
  • Each set of the fan-shaped leads includes A plurality of gate signal lines, each of the gate signal lines is connected to the gate line from the gate flip-chip film.
  • each gate signal line is equal or the impedance of each gate signal line is equal.
  • the first substrate includes a display area and a wiring area provided around the display area, and the data flip chip and the gate flip chip are provided on the wiring area; the data overlay The crystal film and the gate flip-chip film are respectively arranged on different sides of the wiring area perpendicular to each other; the display area is provided with a plurality of parallel grid lines, and the wiring area is also provided with A plurality of groups of fan-shaped leads corresponding to the number of gate flip-chip films, each group of the fan-shaped leads includes a plurality of gate signal lines, and each of the gate signal lines is connected from the gate flip-chip film to the gate line.
  • the gate signal lines are arranged linearly.
  • the gate signal lines are arranged in a zigzag shape.
  • the gate signal lines are arranged in a curved shape.
  • the display panel further includes a printed circuit board, and the printed circuit board is electrically connected to the data flip chip to control signals generated by the printed circuit board in sequence through the data flip chip and the array wiring Passed to a plurality of the gate flip chip.
  • the present application also proposes a display panel, the display panel including: a first substrate, the first substrate includes a display area and a wiring area disposed around the display area, the wiring area is provided on one side Flip chip with data;
  • a second substrate which is spaced apart from the first substrate
  • a plurality of gate flip-chip films, the gate flip-chip films are disposed on the wiring area different from the sides of the data flip chip;
  • the array wiring is disposed on the wiring area and electrically connects the data flip chip and a plurality of the gate flip chip; wherein, the data flip chip is connected to different The array traces of the gate flip-chip film are equal;
  • the display area is provided with a plurality of gate lines arranged in parallel, and the wiring area is also provided with a plurality of sets of fan-shaped leads corresponding to the number of gate flip-chip films, and each set of the fan-shaped leads includes a plurality of gates Signal lines, each of the gate signal lines is connected from the gate flip-chip film to the gate lines;
  • each gate signal line is equal or the impedance of each gate signal line is equal.
  • the array traces and gate signal lines are arranged in a zigzag shape.
  • the array traces and gate signal lines are arranged in a curved shape.
  • the array wiring includes:
  • An extension section extending from the data flip chip to the side where the gate flip chip is located;
  • a plurality of connecting segments each of the connecting segments is connected to each gate flip-chip film from the extending segment;
  • the lengths of the connecting segments in multiple segments are equal.
  • the present application also proposes a display device, including a display panel, the display panel including: a first substrate, a data flip chip is provided on one side of the first substrate;
  • a second substrate which is spaced apart from the first substrate
  • a plurality of gate flip-chip films, the gate flip-chip films are disposed on the first substrate on a side different from the data flip-chip film;
  • array traces are provided on the first substrate and are electrically connected to the data flip chip and the plurality of gate flip chip films;
  • the lengths of the array traces connected from the data flip-chip film to different gate flip-chip films are equal.
  • the array wiring includes:
  • An extension section extending from the data flip chip to the side where the gate flip chip is located;
  • a plurality of connecting segments each of the connecting segments is connected to each gate flip-chip film from the extending segment;
  • the lengths of the connecting segments in multiple segments are equal.
  • the first substrate includes a display area and a wiring area provided around the display area, and the data flip chip and the gate flip chip are provided on the wiring area; the data overlay The crystal thin film and the gate flip chip are respectively disposed on different sides of the wiring area perpendicular to each other;
  • the display area is provided with a plurality of gate lines arranged in parallel, and the wiring area is also provided with a plurality of sets of fan-shaped leads corresponding to the number of gate flip-chip films, and each set of the fan-shaped leads includes a plurality of gates Signal lines, each of the gate signal lines is connected from the gate flip chip to the gate line
  • each gate signal line is equal or the impedance of each gate signal line is equal.
  • the lengths of the array traces connected from the data flip-chip film to different gate flip-chip films are equal.
  • the material of each array trace is the same, such as aluminum or copper, all The impedance of each array trace from the data flip chip to the gate flip chip is equal, so when the gate control signal is sent from the data flip chip to a different gate flip chip, Different gate control signals received by the gate flip-chip film have no resistance capacitance delay, eliminating the waveform difference of the gate driving signal, thereby solving the problem of bad horizontal blocks due to different impedances of the array traces and improving The display effect of the display panel.
  • FIG. 1 is a schematic structural diagram of an embodiment of a display panel of this application.
  • FIG. 2 is a schematic structural view of an embodiment of the data flip-chip film, gate flip-chip film and array wiring of this application;
  • FIG. 3 is a schematic structural view of another embodiment of the data flip chip, gate flip chip and array wiring of the present application.
  • FIG. 4 is a structural schematic diagram of yet another embodiment of the data flip chip, gate flip chip and array wiring of this application;
  • FIG. 5 is a schematic structural diagram of another embodiment of a display panel of this application.
  • FIG. 6 is a structural schematic diagram of yet another embodiment of the data flip chip, gate flip chip and array wiring of the present application.
  • a display panel 100 proposed by the present application includes: a first substrate 10, a data flip chip 20 is provided on one side of the first substrate 10; Two substrates (not shown), the second substrate is spaced apart from the first substrate 10; a plurality of gate flip-chip films 30, the gate flip-chip films 30 are disposed on the first substrate 10 different On the side of the data flip-chip film 20; an array trace 40, which is disposed on the first substrate 10 and electrically connects the data flip-chip film 20 and a plurality of the gate electrodes Crystal film 30; wherein, the lengths of the array traces 40 connected from the data flip chip 20 to different gate flip chip 30 are equal.
  • the first substrate may be an array substrate, and the second substrate may be a color filter substrate.
  • the second substrate is disposed above the first substrate 10 and spaced apart from the first substrate 10, and a liquid crystal layer (not shown) is disposed in front of the second substrate and the first substrate 10.
  • the first substrate 10 is provided with a plurality of thin film transistors (not shown) arranged in an array, and the gates of the plurality of thin film transistors in the same row are connected to the same gate scanning line 101 (hereinafter referred to as gate line) 101), when receiving the gate control signal, the thin film transistors on the first substrate 10 are turned on line by line.
  • gate line gate scanning line
  • the gate scan line 101 is generated by the printed circuit board 50 in the display panel 100 and sent to the plurality of gate flip-chip films 30 through the data flip-chip film 20, where the gate The flip chip 30 is forwarded to each gate line 101 to control the thin film transistors to be turned on row by row, and at the same time, the data flip chip 20 inputs data signals to the opened row of thin film transistors, thereby realizing picture display.
  • the data flip chip 20 forwards the received gate control signal generated by the printed circuit board 50 to the gate flip chip through the array trace 40 provided on the first substrate 10 ⁇ 30 ⁇ The film 30.
  • the number of array traces 40 drawn from the data flip chip 20 may correspond to the number of gate flip chip 30, so that each gate flip chip 30 is connected to an array Line 40, the gate trace is connected from the data flip-chip film 20 to the gate flip-chip film 30 from beginning to end without extending or diverging branches in the middle.
  • the lengths of the array traces 40 connected from the data flip-chip film 20 to different gate flip-chip films 30 are equal, and the material of each array trace 40 is the same as aluminum Or in the case of copper, the impedance of each array trace 40 from the data flip-chip film 20 to the gate flip-chip film 30 is equal, so when the gate control signal goes from the data flip-chip film 20 When sent to different gate flip-chip films 30, the gate control signals received by different gate flip-chip films 30 have no resistance capacitance delay (RC Delay) to eliminate the difference in the waveform of the gate drive signal, thereby solving the problem of poor horizontal blocks due to the different impedance of the array trace 40, and improving the display effect of the display panel 100.
  • RC Delay resistance capacitance delay
  • the array trace 40 is arranged in a zigzag shape and/or a curved shape.
  • the array traces 40 can be arranged in a zigzag shape and/or a curved shape to ensure that the actual lengths of different array traces 40 are equal.
  • the array trace 40 may be arranged in a rectangular wave, sine wave, sawtooth wave, or the like.
  • the array trace 40 where the data flip-chip film 20 is farthest from the gate flip-chip film 30 can be set as a straight line, while other data flip-chip films 20 are closer to the gate flip-chip film 30
  • the array traces 40 are arranged in a zigzag shape and/or a curved shape to ensure that the actual lengths of different array traces 40 are equal.
  • the array trace 40 includes: an extension section 41 (arc segment in FIG. 4), the extension section 41 extends from the data flip chip 20 to the side where the gate flip chip 30 is located; multiple segments In the connection section 42 (broken line section in FIG. 4 ), each connection section 42 is connected from the extension section 41 to each gate chip on film 30; wherein, the lengths of the connection sections 42 in multiple sections are equal.
  • the extension section 41 is drawn from the data flip chip 20 and extends to the side where the gate flip chip 30 is located, and a plurality of connection sections 42 are diverged from the extension section 41, the connection The number of the segments 42 corresponds to the number of the gate flip-chip films 30 to ensure that each of the connection segments 42 is connected to each gate flip-chip film 30 from the extending section 41.
  • the lengths of the connecting segments 42 in multiple segments are equal, so the sum of the lengths of each connecting segment 42 and the extension segment 41 is also equal, so as to ensure that each of the gate flip chip 30 and the data flip chip 20
  • the array traces 40 between are equal.
  • the multiple connecting segments 42 share an extension segment 41 to be connected to the data flip chip 20, the consumables consumed during the production of the array traces 40 can be reduced, and at the same time the array traces 40 can be reduced
  • the wiring area on the first substrate 10 is described.
  • the first substrate 10 includes a display area 11 and a wiring area 12 disposed around the display area 11, the data flip chip 20 and the gate flip chip 30 are provided On the wiring area 12.
  • the wiring area 12 may be surrounded around the display area 11, or the wiring area 12 may be provided only on the two adjacent sides of the wiring area 12, or the wiring area 12 may be provided Any three sides of the display area 11 are not limited here.
  • the data flip chip 20 and the gate flip chip 30 are respectively disposed on different sides of the wiring area 12 that are perpendicular to each other.
  • the data flip-chip film 20 is disposed on the lateral side of the wiring area 12, and the plurality of gate flip-chip films 30 are disposed in the vertical direction of the wiring area 12
  • the data flip-chip film 20 and the gate flip-chip film 30 are respectively disposed on different sides of the wiring area 12 that are perpendicular to each other, so that the data flip-chip film 20 and The gate flip-chip thin film 30 inputs data signals and gate drive signals from the thin film transistors in the display area 11 in two mutually perpendicular directions, respectively, to realize picture display.
  • the gate flip chip 30 may be provided on two vertical sides, so that each gate line 101 Can receive the gate control signal.
  • the display area 11 is provided with a plurality of gate lines 101 arranged in parallel, and the wiring area 12 is further provided with a plurality of sets of sectors corresponding to the number of the gate chip 30 Lead wires 50, each of the fan-shaped lead wires 50 includes a plurality of gate signal lines 51, and each of the gate signal lines 51 is connected from the gate flip chip 30 to the gate line 101.
  • the multiple sets of fan-shaped leads 50 are disposed between the gate flip chip 30 and the plurality of flat gate lines 101, and each of the gate signal lines 51 is from the gate flip chip
  • the thin film 30 is connected to each of the gate lines 101 to transmit the gate control signal received by the gate flip-chip thin film 30 to each of the gate lines 101 through the gate signal line 51, thereby controlling and
  • the thin film transistors connected to the gate line 101 are turned on row by row.
  • each gate signal line 51 is equal or the impedance of each gate signal line 51 is equal.
  • the gate signal lines 51 are arranged in a linear shape, a fold line shape or a curved shape, so as to ensure that the actual lengths of different gate signal lines 51 are equal.
  • the array trace 40 may be arranged in a rectangular wave, sine wave, sawtooth wave, or the like.
  • the gate signal line 51 which is the farthest from the gate flip-chip film 30 to the gate line 101 can be set as a straight line, while the other gate signal lines 51 which are closer to the gate flip-chip film 30 are set to a zigzag shape and /Or curved to ensure that the actual lengths of different gate signal lines 51 are equal, thereby ensuring that the impedance of each gate signal line 51 is equal, and that there is no delay in the gate control signal transmitted to each gate line 101, thereby The waveform difference of the gate driving signal is eliminated, and the display effect of the display panel 100 is improved.
  • different gate signal lines 51 may also be formed by using different conductive materials, for example, a longer gate signal line 51 uses a conductive material with a lower resistivity such as copper, and a shorter gate signal line 51 uses a conductive material with a large resistivity, such as aluminum, to ensure that the impedance of each gate signal line 51 is equal.
  • the display panel 100 further includes a printed circuit board 50 that is electrically connected to the data flip chip 20 to sequentially pass the gate control signals generated by the printed circuit board 50 through the data
  • the flip chip 20 and the array trace 40 are transferred to the plurality of gate flip chips 30.
  • the gate control signal is sequentially transmitted to the plurality of gate flip-chip films 30 through the data flip-chip film 20 and the array trace 40, and the gate flip-chip film 30 passes through the gate signal lines 51 is transmitted to the gate line 101, because the impedances of the different array traces 40 are equal, and the impedances of the different gate signal lines 51 are also equal, thereby eliminating the difference in the waveform of the gate driving signal, thereby solving The problem of defective horizontal blocks due to the different impedance of the line 40 improves the display effect of the display panel 100.
  • a binary tree wiring structure as shown in FIG. 6 may be used to ensure that each One array wiring 40 has the same length.
  • the present application also proposes a display device including the display panel 100 as described above.
  • the display device includes the above-mentioned display panel 100, the lengths of the array traces 40 connected from the data flip chip 20 to different gate flip chip 30 are equal, and the material of each array trace 40 In the case where both are aluminum or copper, the impedance of each array trace 40 of the data flip chip 20 to the gate flip chip 30 is equal, so when the gate control signal When the data flip chip 20 is sent to different gate flip chip 30, the gate control signal received by the different gate flip chip 30 has no resistance capacitance delay (RC Delay) to eliminate the difference in the waveform of the gate drive signal, thereby solving the problem of poor horizontal blocks due to the different impedance of the array trace 40, and improving the display effect of the display panel 100.
  • RC Delay resistance capacitance delay
  • the display device further includes a second substrate disposed opposite to the first substrate 10, a liquid crystal disposed between the first substrate 10 and the second substrate, and a backlight module as a backlight , Used for setting the rear case of the rear case backlight module and the middle frame that fixes the first substrate 10 and the second substrate, which will not be repeated here.

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Abstract

一种显示面板（100）及显示装置，显示面板（100）包括：第一基板（10），第一基板（10）一侧边上设置有数据覆晶薄膜（20）；第二基板，第二基板与第一基板（10）间隔设置；多个栅极覆晶薄膜（30），栅极覆晶薄膜（30）设置于第一基板（10）上异于数据覆晶薄膜（20）的侧边；阵列走线（40），阵列走线（40）设置于第一基板（10）上并电连接数据覆晶薄膜（20）及多个栅极覆晶薄膜（30）；其中，自数据覆晶薄膜（20）连接至不同栅极覆晶薄膜（30）的阵列走线（40）的长度相等。

Description

显示面板及显示装置
本申请要求于2018年12月04日提交中国专利局，申请号为201822040011.9，申请名称为“显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别涉及一种显示面板及显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成示例性技术。
液晶面板中，从印刷电路板发出的栅极控制信号经阵列走线（WOA，Wire On Array）传输至薄膜晶体管（TFT，Thin Film Transistor）的栅极以控制薄膜晶体管逐行打开，由于不同阵列走线的阻抗不同，在传输栅极控制信号过程中存在信号延迟，导致液晶面板画面亮度分布不均匀，从而影响面板整体显示效果，即所谓的H-block现象（Horizontal Block，水平区块不良）。
申请内容
本申请的主要目的是提供一种显示面板及显示装置，实现显示面板画面亮度显示均匀，避免出现的H-block现象。
为实现上述目的，本申请提出的一种显示面板，其中，所述显示面板包括：第一基板，所述第一基板一侧边上设置有数据覆晶薄膜；
第二基板，所述第二基板与所述第一基板间隔设置；
多个栅极覆晶薄膜，所述栅极覆晶薄膜设置于所述第一基板上异于所述数据覆晶薄膜的侧边；
阵列走线，所述阵列走线设置于所述第一基板上并电连接所述数据覆晶薄膜及多个所述栅极覆晶薄膜；
其中，自所述数据覆晶薄膜连接至不同所述栅极覆晶薄膜的阵列走线的长度相等。
可选地，所述阵列走线呈折线形设置。
可选地，所述阵列走线呈曲线形设置。
可选地，所述阵列走线包括：
延伸段，所述延伸段自所述数据覆晶薄膜延伸至栅极覆晶薄膜所在侧边；
多段连接段，每一所述连接段自所述延伸段连接至每一栅极覆晶薄膜；
其中，多段所述连接段的长度相等。
可选地，所述第一基板包括显示区及设置于所述显示区周边的布线区，所述数据覆晶薄膜及所述栅极覆晶薄膜设置于所述布线区上。
可选地，所述数据覆晶薄膜及所述栅极覆晶薄膜分别设置于所述布线区上相互垂直的不同侧边上。
可选地，所述显示区内设置有多条平行设置的栅线，所述布线区上还设置有与所述栅极覆晶薄膜数量对应的多组扇形引线，每组所述扇形引线包括多条栅极信号线，每一所述栅极信号线自所述栅极覆晶薄膜连接至所述栅线。
可选地，每条所述栅极信号线的长度相等或者每条所述栅极信号线的阻抗相等。
可选地，所述第一基板包括显示区及设置于所述显示区周边的布线区，所述数据覆晶薄膜及所述栅极覆晶薄膜设置于所述布线区上；所述数据覆晶薄膜及所述栅极覆晶薄膜分别设置于所述布线区上相互垂直的不同侧边上；所述显示区内设置有多条平行设置的栅线，所述布线区上还设置有与所述栅极覆晶薄膜数量对应的多组扇形引线，每组所述扇形引线包括多条栅极信号线，每一所述栅极信号线自所述栅极覆晶薄膜连接至所述栅线。
可选地，所述栅极信号线呈直线形设置。
可选地，所述栅极信号线呈折线形设置。
可选地，所述栅极信号线呈曲线形设置。
可选地，所述显示面板还包括印刷电路板，所述印刷电路板与所述数据覆晶薄膜电连接，以将印刷电路板产生的控制信号依次经所述数据覆晶薄膜、阵列走线传递给多个所述栅极覆晶薄膜。
此外，本申请还提出一种显示面板，所述显示面板包括：第一基板，所述第一基板包括显示区及设置于所述显示区周边的布线区，所述布线区一侧边上设置有数据覆晶薄膜；
第二基板，所述第二基板与所述第一基板间隔设置；
多个栅极覆晶薄膜，所述栅极覆晶薄膜设置于所述布线区上异于所述数据覆晶薄膜的侧边；
阵列走线，所述阵列走线设置于所述布线区上并电连接所述数据覆晶薄膜及多个所述栅极覆晶薄膜；其中，自所述数据覆晶薄膜连接至不同所述栅极覆晶薄膜的阵列走线的长度相等；
所述显示区内设置有多条平行设置的栅线，所述布线区上还设置有与所述栅极覆晶薄膜数量对应的多组扇形引线，每组所述扇形引线包括多条栅极信号线，每一所述栅极信号线自所述栅极覆晶薄膜连接至所述栅线；
其中，每条所述栅极信号线的长度相等或者每条所述栅极信号线的阻抗相等。
可选地，所述阵列走线及栅极信号线呈折线形设置。
可选地，所述阵列走线及栅极信号线呈曲线形设置。
可选地，所述阵列走线包括：
延伸段，所述延伸段自所述数据覆晶薄膜延伸至栅极覆晶薄膜所在侧边；
多段连接段，每一所述连接段自所述延伸段连接至每一栅极覆晶薄膜；
其中，多段所述连接段的长度相等。
此外，本申请还提出一种显示装置，包括显示面板，所述显示面板包括；第一基板，所述第一基板一侧边上设置有数据覆晶薄膜；
第二基板，所述第二基板与所述第一基板间隔设置；
多个栅极覆晶薄膜，所述栅极覆晶薄膜设置于所述第一基板上异于所述数据覆晶薄膜的侧边；
阵列走线，所述阵列走线设置于所述第一基板上并电连接所述数据覆晶薄膜及多个所述栅极覆晶薄膜；
其中，自所述数据覆晶薄膜连接至不同所述栅极覆晶薄膜的阵列走线的长度相等。
可选地，所述阵列走线包括：
延伸段，所述延伸段自所述数据覆晶薄膜延伸至栅极覆晶薄膜所在侧边；
多段连接段，每一所述连接段自所述延伸段连接至每一栅极覆晶薄膜；
其中，多段所述连接段的长度相等。
可选地，所述第一基板包括显示区及设置于所述显示区周边的布线区，所述数据覆晶薄膜及所述栅极覆晶薄膜设置于所述布线区上；所述数据覆晶薄膜及所述栅极覆晶薄膜分别设置于所述布线区上相互垂直的不同侧边上；
所述显示区内设置有多条平行设置的栅线，所述布线区上还设置有与所述栅极覆晶薄膜数量对应的多组扇形引线，每组所述扇形引线包括多条栅极信号线，每一所述栅极信号线自所述栅极覆晶薄膜连接至所述栅线
其中，每条所述栅极信号线的长度相等或者每条所述栅极信号线的阻抗相等。
本申请中自所述数据覆晶薄膜连接至不同所述栅极覆晶薄膜的阵列走线的长度相等，在每条所述阵列走线的材料相同如都为铝或者铜的情形下，所述数据覆晶薄膜至所述栅极覆晶薄膜的每条阵列走线的阻抗都相等，故当所述栅极控制信号从所述数据覆晶薄膜发送至不同的栅极覆晶薄膜时，不同的所述栅极覆晶薄膜接收到的栅极控制信号没有电阻电容延迟，消除了栅极驱动信号的波形差异，从而解决由于阵列走线的阻抗不同产生的水平区块不良的问题，改善显示面板的显示效果。
附图说明
为了更清楚地说明本申请实施例或示例性技术中的技术方案，下面将对实施例或示例性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请显示面板的一实施例的结构示意图；
图2为本申请数据覆晶薄膜、栅极覆晶薄膜及阵列走线一实施例的结构示意图；
图3为本申请数据覆晶薄膜、栅极覆晶薄膜及阵列走线另一实施例的结构示意图的结构示意图；
图4为本申请数据覆晶薄膜、栅极覆晶薄膜及阵列走线再一实施例的结构示意图的结构示意图；
图5为本申请显示面板的另一实施例的结构示意图；
图6为本申请数据覆晶薄膜、栅极覆晶薄膜及阵列走线又一实施例的结构示意图的结构示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图进行说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，本申请实施例中所有方向性指示（诸如上、下、左、右、前、后……）仅设置为解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，在本申请中涉及“第一”、“第二”等的描述仅设置为描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
请一并参阅图1-5，本申请提出的一种显示面板100，所述显示面板100包括：第一基板10，所述第一基板10一侧边上设置有数据覆晶薄膜20；第二基板（图未示），所述第二基板与所述第一基板10间隔设置；多个栅极覆晶薄膜30，所述栅极覆晶薄膜30设置于所述第一基板10上异于所述数据覆晶薄膜20的侧边；阵列走线40，所述阵列走线40设置于所述第一基板10上并电连接所述数据覆晶薄膜20及多个所述栅极覆晶薄膜30；其中，自所述数据覆晶薄膜20连接至不同所述栅极覆晶薄膜30的阵列走线40的长度相等。
可选地，所述第一基板可为阵列基板，所述第二基板可为彩膜基板。所述第二基板设置于所述第一基板10上方位置并与所述第一基板10间隔设置，所述第二基板与所述第一基板10之前设置有液晶层（图未示）。所述第一基板10上设置有阵列排布的多个薄膜晶体管（图未示），同一行的所述多个薄膜晶体管的栅极共同连接至同一条栅极扫描线101（以下简称栅线101），在接收到栅极控制信号时，所述第一基板10上的薄膜晶体管逐行打开。可选地，所述栅极扫描线101由显示面板100中的印刷电路板50产生，并经过所述数据覆晶薄膜20发送至多个所述栅极覆晶薄膜30，在由所述栅极覆晶薄膜30转发至每条栅线101控制薄膜晶体管逐行打开，同时，所述数据覆晶薄膜20向打开行的薄膜晶体管中输入数据信号，从而实现画面显示。
可选地，所述数据覆晶薄膜20将接收到的所述印刷电路板50产生的栅极控制信号通过设置于所述第一基板10上的阵列走线40转发至所述栅极覆晶薄膜30。可选地，自所述数据覆晶薄膜20引出的阵列走线40可以只有一条，在该一条阵列走线40延伸至多个所述栅极覆晶薄膜30所在侧边时，再发散出多条与所述栅极覆晶薄膜30数量对应的阵列走线40，以使每一所述栅极覆晶薄膜30连接至一条阵列走线40。可选地，自所述数据覆晶薄膜20引出的阵列走线40的数量可与所述栅极覆晶薄膜30数量对应，以使每一所述栅极覆晶薄膜30连接至一条阵列走线40，该栅极走线自始至终从所述数据覆晶薄膜20连接至所述栅极覆晶薄膜30，中间没有延伸或者发散出支路。
需要特别强调的是，自所述数据覆晶薄膜20连接至不同所述栅极覆晶薄膜30的阵列走线40的长度相等，在每条所述阵列走线40的材料相同如都为铝或者铜的情形下，所述数据覆晶薄膜20至所述栅极覆晶薄膜30的每条阵列走线40的阻抗都相等，故当所述栅极控制信号从所述数据覆晶薄膜20发送至不同的栅极覆晶薄膜30时，不同的所述栅极覆晶薄膜30接收到的栅极控制信号没有电阻电容延迟（RC Delay），消除栅极驱动信号的波形差异，从而解决由于阵列走线40的阻抗不同产生的水平区块不良的问题，改善显示面板100的显示效果。
请参阅图2，可选地，所述阵列走线40呈折线形及/或曲线形设置。
可选地，由于所述数据覆晶薄膜20与不同所述栅极覆晶薄膜30的直线距离是不同的，有的栅极覆晶薄膜30距离数据覆晶薄膜20较近，有的栅极覆晶薄膜30距离数据覆晶薄膜20较远，可将阵列走线40设置成折线形及/或曲线形，以保证不同阵列走线40的实际长度相等。具体地，例如，可将所述阵列走线40设置成矩形波、正弦波、锯齿波等形状。
请参阅图3，可以理解，可以将数据覆晶薄膜20距离栅极覆晶薄膜30最远的阵列走线40设置为直线，而其他数据覆晶薄膜20距离栅极覆晶薄膜30较近的阵列走线40设置为折线形及/或曲线形，以保证不同阵列走线40的实际长度相等。
可选地，所述阵列走线40包括：延伸段41（图4中弧线段），所述延伸段41自所述数据覆晶薄膜20延伸至栅极覆晶薄膜30所在侧边；多段连接段42（图4中折线段），每一所述连接段42自所述延伸段41连接至每一栅极覆晶薄膜30；其中，多段所述连接段42的长度相等。
可选地，自所述数据覆晶薄膜20引出所述延伸段41并延伸至所述栅极覆晶薄膜30所在侧边，并自所述延伸段41发散出多段连接段42，所述连接段42的数量与所述栅极覆晶薄膜30数量相对应，以保证每一所述连接段42自所述延伸段41连接至每一栅极覆晶薄膜30。
可选地，多段所述连接段42的长度相等，故每段连接段42与所述延伸段41的长度之和也相等，从而保证每一栅极覆晶薄膜30与数据覆晶薄膜20之间的阵列走线40相等。
可选地，由于多段连接段42共用一条延伸段41连接至所述数据覆晶薄膜20，可以减少所述阵列走线40生产时所消耗的耗材，同时减小所述阵列走线40在所述第一基板10上的布线面积。
请参阅图1，可选地，所述第一基板10包括显示区11及设置于所述显示区11周边的布线区12，所述数据覆晶薄膜20及所述栅极覆晶薄膜30设置于所述布线区12上。
可选地，所述布线区12可围设于所述显示区11的四周，或者所述布线区12也可以仅设置于所述布线区12相邻两侧边，或者所述布线区12设置于所述显示区11任意三个侧边，此处不以此为限。
可选地，所述数据覆晶薄膜20及所述栅极覆晶薄膜30分别设置于所述布线区12上相互垂直的不同侧边上。
可选地，例如图1所示，所述数据覆晶薄膜20设置于所述布线区12的横向侧边上，所述多个栅极覆晶薄膜30设置于所述布线区12的竖向侧边上，此时，所述数据覆晶薄膜20及所述栅极覆晶薄膜30分别设置于所述布线区12上相互垂直的不同侧边上，以使所述数据覆晶薄膜20及栅极覆晶薄膜30分别从两个相互垂直的方向所述显示区11内的薄膜晶体管输入数据信号以及栅极驱动信号，实现画面显示。
请参阅图5，可选地，当所述显示区11内栅线101很多时，可在两条竖向侧边上均设置所述栅极覆晶薄膜30，以使每一条栅线101均能接收到栅极控制信号。
请参阅图1，可选地，所述显示区11内设置有多条平行设置的栅线101，所述布线区12上还设置有与所述栅极覆晶薄膜30数量对应的多组扇形引线50，每组所述扇形引线50包括多条栅极信号线51，每一所述栅极信号线51自所述栅极覆晶薄膜30连接至所述栅线101。
可选地，所述多组扇形引线50设置于所述栅极覆晶薄膜30与所述多条平栅线101之间，且每一所述栅极信号线51自所述栅极覆晶薄膜30连接至每一所述栅线101，以通过所述栅极信号线51将所述栅极覆晶薄膜30接收到的栅极控制信号传输给每一所述栅线101，从而控制与所述栅线101连接的薄膜晶体管逐行打开。
可选地，每条所述栅极信号线51的长度相等或者每条所述栅极信号线51的阻抗相等。
可选地，由于所述栅极覆晶薄膜30与不同的栅线101的直线距离是不同的，有的栅线101距离栅极覆晶薄膜30较近，有的栅线101距离栅极覆晶薄膜30较远，可选地，所述栅极信号线51呈直线形、折线形或曲线形设置，以保证不同栅极信号线51的实际长度相等。具体地，例如，可将所述阵列走线40设置成矩形波、正弦波、锯齿波等形状。
可选地，可以将栅极覆晶薄膜30距离栅线101最远的栅极信号线51设置为直线，而其他距离栅极覆晶薄膜30较近的栅极信号线51设置为折线形及/或曲线形，以保证不同栅极信号线51的实际长度相等，从而保证每条栅极信号线51的阻抗相等，保证传输到每条所述栅线101的栅极控制信号没有延迟，从而消除栅极驱动信号的波形差异，改善显示面板100的显示效果。
可选地，还可以通过使用不同导电材料形成不同的所述栅极信号线51，例如，较长的栅极信号线51使用电阻率较小的导电材料如铜，较短的栅极信号线51使用电阻率较大的导电材料如铝，以保证每条栅极信号线51的阻抗相等。
可选地，所述显示面板100还包括印刷电路板50，所述印刷电路板50与所述数据覆晶薄膜20电连接，以将印刷电路板50产生的栅极控制信号依次经所述数据覆晶薄膜20、阵列走线40传递给多个所述栅极覆晶薄膜30。
可选地，栅极控制信号依次经所述数据覆晶薄膜20、阵列走线40传递给多个所述栅极覆晶薄膜30，所述栅极覆晶薄膜30经所述栅极信号线51传输给所述栅线101，由于所述不同阵列走线40的阻抗相等，且不同所述栅极信号线51的阻抗也相等，从而消除栅极驱动信号的波形差异，从而解决由于阵列走线40的阻抗不同产生的水平区块不良的问题，改善显示面板100的显示效果。
请参阅图6，可选地，当所述布线区102的竖向侧边包括2个以上的所述栅极覆晶薄膜30时，可采用如图6所示的二叉树布线结构，以保证每一条所述阵列布线40的长度相等。
此外，本申请还提出一种显示装置，包括如上述所述的显示面板100。
由于所述显示装置包括上述显示面板100，自所述数据覆晶薄膜20连接至不同所述栅极覆晶薄膜30的阵列走线40的长度相等，在每条所述阵列走线40的材料相同如都为铝或者铜的情形下，所述数据覆晶薄膜20至所述栅极覆晶薄膜30的每条阵列走线40的阻抗都相等，故当所述栅极控制信号从所述数据覆晶薄膜20发送至不同的栅极覆晶薄膜30时，不同的所述栅极覆晶薄膜30接收到的栅极控制信号没有电阻电容延迟（RC Delay），消除栅极驱动信号的波形差异，从而解决由于阵列走线40的阻抗不同产生的水平区块不良的问题，改善显示面板100的显示效果。
此外，所述显示装置还包括与所述第一基板10相对设置的第二基板及设置于所述述第一基板10与所述第二基板之间的液晶，以及作为背光源的背光模组，用于设置所述后壳背光模组的后壳及固定所述第一基板10、第二基板的中框等结构，在此不再赘述。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的申请构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域都包括在本申请的专利保护范围内。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括：第一基板，所述第一基板一侧边上设置有数据覆晶薄膜；
    第二基板，所述第二基板与所述第一基板间隔设置；
    多个栅极覆晶薄膜，所述栅极覆晶薄膜设置于所述第一基板上异于所述数据覆晶薄膜的侧边；
    阵列走线，所述阵列走线设置于所述第一基板上并电连接所述数据覆晶薄膜及多个所述栅极覆晶薄膜；
    其中，自所述数据覆晶薄膜连接至不同所述栅极覆晶薄膜的阵列走线的长度相等。
  2. 根据权利要求1所述的显示面板，其中，所述阵列走线呈折线形设置。
  3. 根据权利要求1所述的显示面板，其中，所述阵列走线呈曲线形设置。
  4. 根据权利要求1所述的显示面板，其中，所述阵列走线包括：
    延伸段，所述延伸段自所述数据覆晶薄膜延伸至栅极覆晶薄膜所在侧边；
    多段连接段，每一所述连接段自所述延伸段连接至每一栅极覆晶薄膜；
    其中，多段所述连接段的长度相等。
  5. 根据权利要求1所述的显示面板，其中，所述第一基板包括显示区及设置于所述显示区周边的布线区，所述数据覆晶薄膜及所述栅极覆晶薄膜设置于所述布线区上。
  6. 根据权利要求5所述的显示面板，其中，所述数据覆晶薄膜及所述栅极覆晶薄膜分别设置于所述布线区上相互垂直的不同侧边上。
  7. 根据权利要求5所述的显示面板，其中，所述显示区内设置有多条平行设置的栅线，所述布线区上还设置有与所述栅极覆晶薄膜数量对应的多组扇形引线，每组所述扇形引线包括多条栅极信号线，每一所述栅极信号线自所述栅极覆晶薄膜连接至所述栅线。
  8. 根据权利要求7所述的显示面板，其中，每条所述栅极信号线的长度相等或者每条所述栅极信号线的阻抗相等。
  9. 根据权利要求1所述的显示面板，其中，所述第一基板包括显示区及设置于所述显示区周边的布线区，所述数据覆晶薄膜及所述栅极覆晶薄膜设置于所述布线区上；所述数据覆晶薄膜及所述栅极覆晶薄膜分别设置于所述布线区上相互垂直的不同侧边上；所述显示区内设置有多条平行设置的栅线，所述布线区上还设置有与所述栅极覆晶薄膜数量对应的多组扇形引线，每组所述扇形引线包括多条栅极信号线，每一所述栅极信号线自所述栅极覆晶薄膜连接至所述栅线。
  10. 根据权利要求8所述的显示面板，其中，所述栅极信号线呈直线形设置。
  11. 根据权利要求8所述的显示面板，其中，所述栅极信号线呈折线形设置。
  12. 根据权利要求8所述的显示面板，其中，所述栅极信号线呈曲线形设置。
  13. 根据权利要求1所述的显示面板，其中，所述显示面板还包括印刷电路板，所述印刷电路板与所述数据覆晶薄膜电连接，以将印刷电路板产生的控制信号依次经所述数据覆晶薄膜、阵列走线传递给多个所述栅极覆晶薄膜。
  14. 一种显示面板，其中，所述显示面板包括：第一基板，所述第一基板包括显示区及设置于所述显示区周边的布线区，所述布线区一侧边上设置有数据覆晶薄膜；
    第二基板，所述第二基板与所述第一基板间隔设置；
    多个栅极覆晶薄膜，所述栅极覆晶薄膜设置于所述布线区上异于所述数据覆晶薄膜的侧边；
    阵列走线，所述阵列走线设置于所述布线区上并电连接所述数据覆晶薄膜及多个所述栅极覆晶薄膜；其中，自所述数据覆晶薄膜连接至不同所述栅极覆晶薄膜的阵列走线的长度相等；
    所述显示区内设置有多条平行设置的栅线，所述布线区上还设置有与所述栅极覆晶薄膜数量对应的多组扇形引线，每组所述扇形引线包括多条栅极信号线，每一所述栅极信号线自所述栅极覆晶薄膜连接至所述栅线；
    其中，每条所述栅极信号线的长度相等或者每条所述栅极信号线的阻抗相等。
  15. 根据权利要求14所述的显示面板，其中，所述阵列走线及栅极信号线呈折线形设置。
  16. 根据权利要求14所述的显示面板，其中，所述阵列走线及栅极信号线呈曲线形设置。
  17. 根据权利要求14所述的显示面板，其中，所述阵列走线包括：
    延伸段，所述延伸段自所述数据覆晶薄膜延伸至栅极覆晶薄膜所在侧边；
    多段连接段，每一所述连接段自所述延伸段连接至每一栅极覆晶薄膜；
    其中，多段所述连接段的长度相等。
  18. 一种显示装置，其中，包括显示面板，所述显示面板包括；第一基板，所述第一基板一侧边上设置有数据覆晶薄膜；
    第二基板，所述第二基板与所述第一基板间隔设置；
    多个栅极覆晶薄膜，所述栅极覆晶薄膜设置于所述第一基板上异于所述数据覆晶薄膜的侧边；
    阵列走线，所述阵列走线设置于所述第一基板上并电连接所述数据覆晶薄膜及多个所述栅极覆晶薄膜；
    其中，自所述数据覆晶薄膜连接至不同所述栅极覆晶薄膜的阵列走线的长度相等。
  19. 根据权利要求18所述的显示装置，其中，所述阵列走线包括：
    延伸段，所述延伸段自所述数据覆晶薄膜延伸至栅极覆晶薄膜所在侧边；
    多段连接段，每一所述连接段自所述延伸段连接至每一栅极覆晶薄膜；
    其中，多段所述连接段的长度相等。
  20. 根据权利要求18所述的显示装置，其中，所述第一基板包括显示区及设置于所述显示区周边的布线区，所述数据覆晶薄膜及所述栅极覆晶薄膜设置于所述布线区上；所述数据覆晶薄膜及所述栅极覆晶薄膜分别设置于所述布线区上相互垂直的不同侧边上；
    所述显示区内设置有多条平行设置的栅线，所述布线区上还设置有与所述栅极覆晶薄膜数量对应的多组扇形引线，每组所述扇形引线包括多条栅极信号线，每一所述栅极信号线自所述栅极覆晶薄膜连接至所述栅线
    其中，每条所述栅极信号线的长度相等或者每条所述栅极信号线的阻抗相等。
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