CN110729308A - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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CN110729308A
CN110729308A CN201910922443.9A CN201910922443A CN110729308A CN 110729308 A CN110729308 A CN 110729308A CN 201910922443 A CN201910922443 A CN 201910922443A CN 110729308 A CN110729308 A CN 110729308A
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capacitor
thin film
film transistor
display panel
layer
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杜鹏
宋乔乔
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to PCT/CN2019/126628 priority patent/WO2021056867A1/zh
Priority to US16/626,359 priority patent/US11437414B2/en
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/1362—Active matrix addressed cells
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    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

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Abstract

本揭示提供一种显示面板及显示装置，显示面板包括衬底基板、薄膜晶体管器件层、钝化层以及导电膜层，导电膜层通过第一过孔与薄膜晶体管器件层中薄膜晶体管的栅极电连接，导电膜层与薄膜晶体管的源/漏极相对应的区域至少部分重叠并用以形成第一电容结构，同时薄膜晶体管的源/漏极与薄膜晶体管的栅极相对应的重叠区域形成第二电容，第一电容与第二电容形成并联结构，从而提升了驱动电路中的升压电容的电容值，压缩了驱动电路的设计空间，实现窄边框产品的设计。

Description

显示面板及显示装置
技术领域
本揭示涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
在液晶显示器不断向着低成本高品质方向发展的背景下，阵列基板行驱动(GateDriver On Array，GOA)技术以其低成本和高集成度等优点得到了广泛的应用。
显示面板中包括多个GOA驱动电路，在典型的GOA电路中，如时钟信号(CK)线上第二列第一个(T21)TFT分别连接时钟信号和像素的栅极(Gate)线，电路在工作时，往往会在T21的栅极和源极(Source)之间增加一个电容，即升压(Boost)电容，当GOA电路在输出时，由于耦合的作用，Boost电容会使T21的Gate的电位进一步的升高，从而提升了电路的输出能力。但是，一般的Boost电容值比较大，在电路设计时，Boost电容会占用很大的空间，使得GOA区域的宽度难以压缩，这样对窄边框产品的设计是非常不利的，也不利于产品成本的控制。
综上所述，现有的GOA电路中，存在着Boost电容所占据的设计空间较大，GOA区域的宽度难以压缩，不利于窄边框产品的设计，并且生产成本高等问题。
发明内容
本揭示提供一种显示面板及显示装置，以解决现有的GOA电路中，GOA区域较宽难以压缩，Boost电容所占据的设计空间较大，产品生产成本高等问题。
为解决上述技术问题，本揭示实施例提供的技术方案如下：
根据本揭示实施例的第一方面，提供了一种显示面板，包括：
衬底基板；
薄膜晶体管器件层，所述薄膜晶体管器件层设置在所述衬底基板上；
钝化层，所述钝化层设置在所述薄膜晶体管器件层上；以及
导电膜层，所述导电膜层设置在所述钝化层上；
其中，所述导电膜层通过第一过孔与所述薄膜晶体管器件层中薄膜晶体管的栅极电连接，所述导电膜层与所述薄膜晶体管的源/漏极相对应的区域至少部分重叠并用以形成第一电容结构。
根据本揭示一实施例，所述第一过孔位于所述薄膜晶体管源极的一侧，所述第一过孔贯穿所述薄膜晶体管器件层和所述钝化层。
根据本揭示一实施例，所述导电膜层完全覆盖所述钝化层。
根据本揭示一实施例，所述导电膜层设置在所述钝化层上并覆盖部分所述薄膜晶体管的源极。
根据本揭示一实施例，所述显示面板还包括第二电容，所述薄膜晶体管的源/漏极与所述薄膜晶体管的栅极相对应的重叠区域形成所述第二电容。
根据本揭示一实施例，所述第一电容与所述第二电容并联设置。
根据本揭示一实施例，所述第一电容的电容值大于所述第二电容的电容值。
根据本揭示一实施例，所述导电膜层为像素电极膜层。
根据本揭示一实施例，所述钝化层的厚度为
Figure BDA0002217984820000021
根据本揭示的第二方面，还提供了一种显示装置，所述显示装置包括本揭示提供的显示面板。
综上所述，本揭示实施例的有益效果为：
本揭示提供一种新的薄膜晶体管及GOA驱动电路，通过在薄膜晶体管的结构中设置钝化层及氧化铟锡膜层，增加的钝化层及氧化铟锡膜层与其他膜层构成新的电容，使得GOA电路中的电容值进一步增大，进而将GOA区域的宽度进行压缩，减小其设计空间，实现窄边框产品的设计。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是揭示的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有设计的显示面板中的一级GOA电路的等效电路图；
图2为图1中GOA电路图的部分平面设计图；
图3为本揭示实施例的GOA电路的部分平面设计图；
图4为图3中本揭示实施例的显示面板的截面结构示意图；
图5为本揭示另一种实施例的GOA电路的部分平面设计图；
图6为图5中本揭示另一种实施例的显示面板的截面结构示意图；
图7为本揭示实施例的显示装置示意图。
具体实施方式
下面将结合本揭示实施例中的附图，对本揭示实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本揭示一部分实施例，而不是全部的实施例。基于本揭示中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本揭示保护的范围。
在本揭示的实施例中，如图1所示，图1为现有设计中的显示面板的一级GOA电路的等效电路图。图中时钟信号线上第二列第一个(T21)薄膜晶体管是GOA电路输出中最重要的器件，根据图中T21的连接关系，T21的TFT的源极与时钟信号线相连接，T21的TFT的漏极与栅极扫描线G(n)相连接，同时，为了提升GOA电路的输出能力，会在T21的栅极和源极之间增加一个电容，即图中的升压(Boost)电容100，在电路工作时，由于耦合作用，升压电容100会使T21的栅极上的电位进一步升高，使得GOA的电路的输出能力提高。
如图2所示，图2为图1中GOA电路的部分平面设计图。其中包括第一时钟信号线(CK1)201、栅极扫描线200以及薄膜晶体管区域中的T21薄膜晶体管203。第一时钟信号线201与薄膜晶体管的漏极相连接。同时，图2中还包括GOA区域202，一般情况下，GOA电路中的升压电容100的电容值Cboost比较大，为了满足升压电容100的电容值，在设计时，GOA区域202的宽度D就会设置的较宽，而宽度D的数值越大，占据的设计空间就越大，这样对于窄边框产品的设计时非常不利的，因此，在设计时，需要尽可能的提高升压电容100的电容值，升压电容100的电容越大，所对应在GOA区域中的宽度D就越小，当宽度D的数值越小，面板的边框也变得较小，最终实现显示面板的窄边框设计。
本揭示提供一种薄膜晶体管，在不改变现有GOA电路结构设计图的条件下，通过改变显示面板内部的结构来提高所述升压电容100的电容值，达到减小GOA宽度的效果。
如图3所示，图3为本揭示实施例GOA电路的部分平面设计图。GOA电路中包括第一时钟信号线(CK1)301、栅极扫描线300以及T21薄膜晶体管303，其中还包括GOA区域302和设置在GOA区域302内的导电膜层304，所述导电膜层304可为像素电极膜层，所述像素电极膜层为氧化铟锡膜。以及T21薄膜晶体管303的栅极层305，多晶硅层306，设置在多晶硅层306上的源极307。在本实施例中，通过在GOA区域302内设置导电膜层304，以此来增大图1中的升压电容100的电容值Cboost。
具体的，如图4所示，图4为图3中对应的本揭示实施例的显示面板的截面结构示意图。显示面板的结构包括：衬底基板400，设置在衬底基板400之上的栅极401，设置在栅极401之上的栅极绝缘层402，设置在栅极绝缘层402之上的多晶硅层405，以及薄膜晶体管的漏极406、源极407、设置在漏极405与源极407之间的沟道408。所述源极407和所述漏极406具有相同的材质，薄膜晶体管的栅极401、源/漏极、栅极绝缘层402以及多晶硅层405共同构成了一薄膜晶体管器件层。
所述显示面板的结构中还包括钝化层403和导电膜层404。钝化层403设置在栅极绝缘层402之上，并且所述钝化层403完全覆盖所述多晶硅层405、源极407以及漏极406，在本揭示实施例中，导电膜层404位于钝化层403的一侧，只覆盖钝化层403的部分区域，未将钝化层403全部覆盖，钝化层403的材料包括绝缘材质。
在本揭示实施例中，所述栅极绝缘层402上还设置有第一过孔409。所述第一过孔409位于所述薄膜晶体管漏极406的一侧，所述第一过孔409贯穿所述薄膜晶体管器件层和所述钝化层403。所述导电膜层404通过所述第一过孔409与所述薄膜晶体管的栅极401相连接，所述导电膜层404包括氧化铟锡膜层。
在制备时，所述第一过孔409经过涂胶、曝光、显影、刻蚀等光刻工艺流程制备形成，所述栅极绝缘层402通过沉积工艺设置在栅极401上，栅极绝缘层402可以是SiOx、SiNx薄膜或叠层结构的薄膜。
由于导电膜层404与源极407均为导电膜层，此时就相当于一个电容的上、下电极板，而钝化层403为绝缘介质，因此在导电膜层404与源极407两者相对应的重叠区域410之间会形成一个第一电容C1，同理，薄膜晶体管的栅极401、源极407与其栅极401三者相对应的重叠区域膜层之间会形成一个第二电容C2。第一电容C1与第二电容C2在连接上为并联的形式，此时，结合图1中的电路图，电路中的总的升压电容100的就变为第一电容C1与第二电容C2之和，升压电容100的电容值也变为两者电容值的和。从而使得整个显示面板内的电容值变大。由于电容值变大，因此，在设计时，其边框处的宽度D值就可相应的进行缩小。
由于钝化层403的厚度较薄，钝化层403的膜厚在
Figure BDA0002217984820000061
优选为
Figure BDA0002217984820000062
栅极绝缘层402的厚度较大，膜厚在
Figure BDA0002217984820000063
之间，优选为
Figure BDA0002217984820000064
即所述第一电容值大于第二电容的电容值。
同时，电容值的大小会取决于导电膜层404与源极407之间相对的重叠区域410的面积，相对重叠区域410的面积越大，升压电容也会越大。
由于本揭示实施例中的电容值要大于现有设计的显示面板中的电容值。因此，对应于图3中GOA电路平面图中，相对于现有设计，本揭示实施例中升压电容的上下两个电极的面积就可以变小，即GOA区域302中的宽度能进行压缩，进一步的减小D1的宽度值，从而实现了窄边框的产品设计。
如图5所示，图5为本揭示另一种实施例的GOA电路的部分平面设计图。在本揭示实施例中，如图5所示，第一时钟信号线(CK1)501与薄膜晶体管的源极相连接、栅极扫描线500与薄膜晶体管的漏极相连接，保证薄膜晶体管信号的正常输入和输出。像素电极504覆盖整个GOA电路的设计空间。
具体的，如图6所示，图6为图5中本揭示另一种实施例的显示面板的截面结构示意图。像素电极604完全覆盖整个钝化层603。显示面板的其他膜层结构设置同图4中的结构，自下而上依次设置衬底基板600、栅极601、栅极绝缘层602以及多晶硅层605、源极607和漏极606，具体结构这里不再详细描述。根据图4中形成升压电容的原理，同理可知，在本揭示实施例中，在显示面板内形成的第一重叠区域610以及第二重叠区域611，第一重叠区域610为像素电极604与像素电极604相对应的薄膜晶体管的源极607形成的重叠区域，这一第一重叠区域610构成了第一电容C1，上下两导电膜层分别为第一电容C1的上下极板，同理，薄膜晶体管的源极607与薄膜晶体管的栅极601相对应的第二重叠区域611构成了显示面板的第二电容C2，图中第一重叠区域610与第二重叠区域611只是整个显示面板的一部分示意，其它区域内的相对应的膜层之间形成的重叠部分均为本揭示实施例中的第一电容C1和第二电容C2。
在结构以及连接关系上，实施例中的第一电容C1与第二电容C2为并联的结构，因此，显示面板内的总电容值就变为C＝C 1+C2，进而，通过增加一层导电膜层，增加了显示面板内的整个电容值，具体的对应到其平面布置图5上，由于此时像素电极604的面积变得更大，当像素电极604与栅极601以及钝化层603三者形成第一电容时，相互间相对应的重叠面积会更多，第一电容的电容值会变得更大。
因此，其侧边处的宽度D2的值就会进一步变小，在较小的宽度D2情况下，就可满足显示面板的电容值。对应于图5中的GOA电路设计时，GOA区域能再进一步的压缩，宽度D2变得更小，更有利于窄边框产品的设计。因此，根据上述各个不同的实施例，其GOA区域的宽度大小关系为D>D 1>D2，即当导电膜层覆盖的钝化层的区域越多，其边缘处的宽度D就会越小。
本揭示实施例还提供一种显示装置，所述显示装置中包括本揭示实施例提供的显示面板。如图7所示，图7为本揭示实施例的显示装置示意图。在本揭示实施例的显示装置700中，显示装置700内部包括本揭示实施例提供的显示面板701，其中，显示面板701中驱动电路的升压电容的电容值比现有设计中的升压电容的电容值都大，这样，在GOA电路布局时，GOA区域所占据的设计空间更小。
以上对本揭示实施例所提供的一种显示面板及显示装置进行了详细介绍，以上实施例的说明只是用于帮助理解本揭示的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，而这些修改或者替换，并不使相应技术方案的本质脱离本揭示各实施例的技术方案的范围。

Claims (10)

1.一种显示面板，其特征在于，包括：
衬底基板；
薄膜晶体管器件层，所述薄膜晶体管器件层设置在所述衬底基板上；
钝化层，所述钝化层设置在所述薄膜晶体管器件层上；以及
导电膜层，所述导电膜层设置在所述钝化层上；
其中，所述导电膜层通过第一过孔与所述薄膜晶体管器件层中薄膜晶体管的栅极电连接，所述导电膜层与所述薄膜晶体管的源/漏极相对应的区域至少部分重叠并用以形成第一电容结构。
2.根据权利要求1所述的显示面板，其特征在于，所述第一过孔位于所述薄膜晶体管源极的一侧，所述第一过孔贯穿所述薄膜晶体管器件层和所述钝化层。
3.根据权利要求1所述的显示面板，其特征在于，所述导电膜层完全覆盖所述钝化层。
4.根据权利要求1所述的显示面板，其特征在于，所述导电膜层设置在所述钝化层上并覆盖部分所述薄膜晶体管的所述源极。
5.根据权利要求1所述的显示面板，其特征在于，所述显示面板还包括第二电容，所述薄膜晶体管的源/漏极与所述薄膜晶体管的栅极相对应的重叠区域形成所述第二电容。
6.根据权利要求5所述的显示面板，其特征在于，所述第一电容与所述第二电容并联设置。
7.根据权利要求5所述的显示面板，其特征在于，所述第一电容的电容值大于所述第二电容的电容值。
8.根据权利要求1所述的显示面板，其特征在于，所述导电膜层为像素电极膜层。
9.根据权利要求1所述的显示面板，其特征在于，所述钝化层的厚度为
10.一种显示装置，其特征在于，包括如权利要求1-9中任一项所述的显示面板。
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