WO2021056867A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

Info

Publication number
WO2021056867A1
WO2021056867A1 PCT/CN2019/126628 CN2019126628W WO2021056867A1 WO 2021056867 A1 WO2021056867 A1 WO 2021056867A1 CN 2019126628 W CN2019126628 W CN 2019126628W WO 2021056867 A1 WO2021056867 A1 WO 2021056867A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
thin film
film transistor
display panel
capacitor
Prior art date
Application number
PCT/CN2019/126628
Other languages
English (en)
French (fr)
Inventor
杜鹏
宋乔乔
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US16/626,359 priority Critical patent/US11437414B2/en
Publication of WO2021056867A1 publication Critical patent/WO2021056867A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present disclosure relates to the field of display technology, and more particularly to a display panel and a display device.
  • the display panel includes multiple GOA driving circuits.
  • the first (T21) TFT in the second column of the clock signal (CK) line is connected to the clock signal and the pixel gate (Gate) line respectively.
  • a capacitor is often added between the gate and the source of T21, that is, a boost capacitor.
  • the Boost capacitor will cause the gate of T21 to be coupled. The potential is further increased, thereby enhancing the output capability of the circuit.
  • the general Boost capacitor value is relatively large. In the circuit design, the Boost capacitor will take up a lot of space, making the width of the GOA area difficult to compress, which is very detrimental to the design of narrow-frame products, and it is also detrimental to the cost of the product. control.
  • the design space occupied by the Boost capacitor is relatively large, the width of the GOA area is difficult to compress, which is not conducive to the design of narrow-frame products, and the production cost is high.
  • the present disclosure provides a display panel and a display device to solve the problems of the existing GOA circuit, where the GOA area is wider and difficult to compress, the design space occupied by the Boost capacitor is relatively large, and the production cost of the product is high.
  • a display panel including:
  • a thin film transistor device layer, the thin film transistor device layer is disposed on the base substrate;
  • a passivation layer, the passivation layer is disposed on the thin film transistor device layer;
  • a conductive film layer, the conductive film layer is disposed on the passivation layer;
  • the conductive film layer is electrically connected to the gate of the thin film transistor in the thin film transistor device layer through a first via hole, and the conductive film layer at least partially overlaps with the region corresponding to the source/drain of the thin film transistor And used to form a first capacitor structure;
  • the first via hole is located on one side of the source of the thin film transistor, and the first via hole penetrates the thin film transistor device layer and the passivation layer; the conductive film layer includes a pixel electrode film layer.
  • the conductive film layer completely covers the passivation layer.
  • the conductive film layer is disposed on the passivation layer and covers a part of the source electrode of the thin film transistor.
  • the display panel further includes a second capacitor, and an overlapping area corresponding to the source/drain of the thin film transistor and the gate of the thin film transistor forms the second capacitor.
  • the first capacitor and the second capacitor are arranged in parallel.
  • the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.
  • the thickness of the passivation layer is 1500 ⁇ to 2500 ⁇ .
  • a display panel including:
  • a thin film transistor device layer, the thin film transistor device layer is disposed on the base substrate;
  • a passivation layer, the passivation layer is disposed on the thin film transistor device layer;
  • a conductive film layer, the conductive film layer is disposed on the passivation layer;
  • the conductive film layer is electrically connected to the gate of the thin film transistor in the thin film transistor device layer through a first via hole, and the conductive film layer at least partially overlaps with the region corresponding to the source/drain of the thin film transistor And used to form a first capacitor structure.
  • the first via hole is located on one side of the source of the thin film transistor, and the first via hole penetrates the thin film transistor device layer and the passivation layer.
  • the conductive film layer completely covers the passivation layer.
  • the conductive film layer is disposed on the passivation layer and covers part of the source electrode of the thin film transistor.
  • the display panel further includes a second capacitor, and an overlapping area corresponding to the source/drain of the thin film transistor and the gate of the thin film transistor forms the second capacitor.
  • the first capacitor and the second capacitor are arranged in parallel.
  • the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.
  • the conductive film layer is a pixel electrode film layer.
  • the thickness of the passivation layer is 1500 ⁇ to 2500 ⁇ .
  • a display device comprising:
  • a thin film transistor device layer, the thin film transistor device layer is disposed on the base substrate;
  • a passivation layer, the passivation layer is disposed on the thin film transistor device layer;
  • a conductive film layer, the conductive film layer is disposed on the passivation layer;
  • the conductive film layer is electrically connected to the gate of the thin film transistor in the thin film transistor device layer through a first via hole, and the conductive film layer at least partially overlaps with the region corresponding to the source/drain of the thin film transistor And used to form a first capacitor structure.
  • the first via hole is located on one side of the source of the thin film transistor, and the first via hole penetrates the thin film transistor device layer and the passivation layer.
  • the conductive film layer completely covers the passivation layer.
  • the conductive film layer is disposed on the passivation layer and covers a part of the source electrode of the thin film transistor.
  • the present disclosure provides a new thin film transistor and GOA driving circuit.
  • a passivation layer and an indium tin oxide film layer in the structure of the thin film transistor, the increased passivation layer and the indium tin oxide film layer and other film layers constitute a new
  • the capacitance further increases the capacitance value in the GOA circuit, thereby compressing the width of the GOA area, reducing its design space, and realizing the design of narrow-frame products.
  • Fig. 1 is an equivalent circuit diagram of a first-level GOA circuit in a display panel of a conventional design
  • Figure 2 is a partial plan view of the GOA circuit diagram in Figure 1;
  • FIG. 3 is a partial plan design diagram of the GOA circuit of the disclosed embodiment
  • FIG. 4 is a schematic diagram of a cross-sectional structure of the display panel of the embodiment of the present disclosure in FIG. 3;
  • FIG. 5 is a partial plan view of a GOA circuit according to another embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of a cross-sectional structure of a display panel according to another embodiment of the present disclosure in FIG. 5;
  • FIG. 7 is a schematic diagram of a display device according to an embodiment of the disclosure.
  • FIG. 1 is an equivalent circuit diagram of a first-level GOA circuit of a display panel in an existing design.
  • the first (T21) thin film transistor in the second column of the clock signal line in the figure is the most important device in the GOA circuit output.
  • the source of the TFT of T21 is connected to the clock signal line, and the source of T21 is connected to the clock signal line.
  • the drain of the TFT is connected to the gate scan line G(n).
  • a capacitor will be added between the gate and source of T21, which is the boost in the figure.
  • the capacitor 100 will further increase the potential on the gate of the T21 due to the coupling effect, so that the output capability of the GOA circuit will be improved.
  • Figure 2 is a partial plan view of the GOA circuit in Figure 1. It includes the first clock signal line (CK1) 201, the gate scan line 200, and the T21 thin film transistor 203 in the thin film transistor area.
  • the first clock signal line 201 is connected to the drain of the thin film transistor.
  • FIG. 2 also includes the GOA area 202.
  • the capacitance value Cboost of the boost capacitor 100 in the GOA circuit is relatively large.
  • the width D of the GOA area 202 is It will be set wider, and the larger the value of the width D, the larger the design space occupied, which is very unfavorable for the design of narrow-frame products.
  • the present disclosure provides a thin film transistor, which improves the capacitance value of the boost capacitor 100 by changing the internal structure of the display panel without changing the existing GOA circuit structure design drawing, so as to achieve the effect of reducing the GOA width.
  • FIG. 3 is a partial plan design diagram of the GOA circuit according to the embodiment of the disclosure.
  • the GOA circuit includes a first clock signal line (CK1) 301, a gate scan line 300, and a T21 thin film transistor 303. It also includes a GOA area 302 and a conductive film layer 304 disposed in the GOA area 302.
  • the conductive film layer 304 It may be a pixel electrode film layer, and the pixel electrode film layer is an indium tin oxide film.
  • the conductive film layer 304 is provided in the GOA area 302 to increase the capacitance value Cboost of the boost capacitor 100 in FIG. 1.
  • FIG. 4 is a schematic cross-sectional structure diagram of the display panel according to the embodiment of the present disclosure corresponding to FIG. 3.
  • the structure of the display panel includes: a base substrate 400, a gate 401 disposed on the base substrate 400, a gate insulating layer 402 disposed on the gate 401, and a polysilicon layer disposed on the gate insulating layer 402 405, and the drain 406, the source 407 of the thin film transistor, and the channel 408 provided between the drain 405 and the source 407.
  • the source electrode 407 and the drain electrode 406 have the same material.
  • the gate electrode 401, source/drain electrode, gate insulating layer 402 and polysilicon layer 405 of the thin film transistor together constitute a thin film transistor device layer.
  • the structure of the display panel further includes a passivation layer 403 and a conductive film layer 404.
  • the passivation layer 403 is disposed on the gate insulating layer 402, and the passivation layer 403 completely covers the polysilicon layer 405, the source electrode 407, and the drain electrode 406.
  • the conductive film layer 404 is located on the passivation layer.
  • One side of the passivation layer 403 only covers a part of the passivation layer 403 without covering all the passivation layer 403.
  • the material of the passivation layer 403 includes an insulating material.
  • the gate insulating layer 402 is further provided with a first via 409.
  • the first via hole 409 is located at one side of the drain electrode 406 of the thin film transistor, and the first via hole 409 penetrates the thin film transistor device layer and the passivation layer 403.
  • the conductive film layer 404 is connected to the gate 401 of the thin film transistor through the first via 409, and the conductive film layer 404 includes an indium tin oxide film layer.
  • the first via 409 is prepared and formed by photolithography processes such as glue coating, exposure, development, and etching.
  • the gate insulating layer 402 is disposed on the gate 401 through a deposition process.
  • the gate insulating layer 402 may be a SiOx, SiNx film or a laminated structure film.
  • the conductive film layer 404 and the source electrode 407 are both conductive film layers, they are equivalent to the upper and lower electrode plates of a capacitor at this time, and the passivation layer 403 is an insulating medium. Therefore, the conductive film layer 404 and the source electrode 407 are both conductive film layers.
  • a first capacitor C1 is formed between the corresponding overlapping regions 410.
  • a second capacitor is formed between the film layers of the overlapping regions corresponding to the gate 401, source 407 and gate 401 of the thin film transistor. C2.
  • the first capacitor C1 and the second capacitor C2 are connected in parallel. At this time, in conjunction with the circuit diagram in FIG. 1, the total boost capacitor 100 in the circuit becomes the difference between the first capacitor C1 and the second capacitor C2.
  • the capacitance value of the boost capacitor 100 also becomes the sum of the two capacitance values. As a result, the capacitance value in the entire display panel becomes larger. As the capacitance value becomes larger, the width D value of the frame can be reduced accordingly during design.
  • the thickness of the passivation layer 403 is relatively thin, the thickness of the passivation layer 403 is 1500 ⁇ to 2500 ⁇ , preferably 2000 ⁇ ; the thickness of the gate insulating layer 402 is relatively large, and the film thickness is between 3500 ⁇ to 4050 ⁇ , preferably 4000 ⁇ . That is, the first capacitance value is greater than the capacitance value of the second capacitance.
  • the capacitance value depends on the area of the overlapping area 410 between the conductive film layer 404 and the source electrode 407. The larger the area of the overlapping area 410, the larger the boost capacitance.
  • the capacitance value in the embodiment of the present disclosure is larger than the capacitance value in the display panel of the existing design. Therefore, corresponding to the plan view of the GOA circuit in FIG. 3, compared to the existing design, the area of the upper and lower electrodes of the boost capacitor in the embodiment of the present disclosure can be reduced, that is, the width of the GOA region 302 can be compressed, and further The width value of D1 is reduced to realize the product design of narrow bezel.
  • FIG. 5 is a partial plan design diagram of a GOA circuit according to another embodiment of the disclosure.
  • the first clock signal line (CK1) 501 is connected to the source of the thin film transistor
  • the gate scan line 500 is connected to the drain of the thin film transistor to ensure the signal of the thin film transistor. Normal input and output.
  • the pixel electrode 504 covers the entire design space of the GOA circuit.
  • FIG. 6 is a schematic cross-sectional structure diagram of the display panel according to another embodiment of the present disclosure in FIG. 5.
  • the pixel electrode 604 completely covers the entire passivation layer 603.
  • the other film structure of the display panel is the same as the structure in FIG. 4, the base substrate 600, the gate 601, the gate insulating layer 602, the polysilicon layer 605, the source electrode 607 and the drain electrode 606 are arranged in order from bottom to top.
  • the specific structure It will not be described in detail here. According to the principle of forming the boost capacitor in FIG.
  • the first overlap area 610 and the second overlap area 611 are formed in the display panel, and the first overlap area 610 is the pixel electrode 604 and the second overlap area 611.
  • the overlapping area formed by the source 607 of the thin film transistor corresponding to the pixel electrode 604, this first overlapping area 610 constitutes the first capacitor C1, and the upper and lower conductive film layers are the upper and lower plates of the first capacitor C1.
  • the second overlap area 611 corresponding to the source 607 of the thin film transistor and the gate 601 of the thin film transistor constitutes the second capacitor C2 of the display panel.
  • the first overlap area 610 and the second overlap area 611 in the figure are only a part of the entire display panel. For illustration, the overlapping portions formed between the corresponding film layers in other regions are both the first capacitor C1 and the second capacitor C2 in the embodiment of the present disclosure.
  • the film layer increases the entire capacitance value in the display panel, which specifically corresponds to its plan layout in Figure 5. Because the area of the pixel electrode 604 becomes larger at this time, when the pixel electrode 604 and the gate 601 and the passivation layer 603 When the three forms the first capacitor, the overlap area corresponding to each other will be larger, and the capacitance value of the first capacitor will become larger.
  • the value of the width D2 at the side will be further reduced.
  • the capacitance value of the display panel can be satisfied.
  • the GOA area can be further compressed, and the width D2 becomes smaller, which is more conducive to the design of narrow-frame products. Therefore, according to the various embodiments described above, the relationship between the width of the GOA area is D>D1>D2, that is, when the conductive film layer covers more areas of the passivation layer, the width D at the edges thereof will be smaller.
  • the embodiment of the present disclosure also provides a display device, and the display device includes the display panel provided by the embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a display device according to an embodiment of the disclosure.
  • the display device 700 includes the display panel 701 provided in the embodiment of the present disclosure.
  • the capacitance value of the boost capacitor of the driving circuit in the display panel 701 is higher than that of the boost capacitor in the conventional design.
  • the capacitance values are large, so that in the GOA circuit layout, the design space occupied by the GOA area is smaller.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种显示面板及显示装置，显示面板中的导电膜层（404）通过第一过孔（409）与薄膜晶体管的栅极（401）电连接，导电膜层（404）与薄膜晶体管的源级（407）/漏极（406）相对应的区域至少部分重叠并用以形成第一电容结构，同时薄膜晶体管的源级（407）/漏极（406）与薄膜晶体管的栅极（401）相对应的重叠区域形成第二电容，进而提升了面板的升压电容值，压缩了驱动电路的设计空间。

Description

显示面板及显示装置
本申请要求于2019年09月27日提交中国专利局、申请号为201910922443.9、发明名称为“显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本揭示涉及显示技术领域，尤其涉及一种显示面板及显示装置。
 背景技术
在液晶显示器不断向着低成本高品质方向发展的背景下，阵列基板行驱动（Gate Driver On Array，GOA）技术以其低成本和高集成度等优点得到了广泛的应用。
显示面板中包括多个GOA驱动电路，在典型的GOA电路中，如时钟信号（CK）线上第二列第一个（T21）TFT分别连接时钟信号和像素的栅极（Gate）线，电路在工作时，往往会在T21的栅极和源极（Source）之间增加一个电容，即升压（Boost）电容，当GOA电路在输出时，由于耦合的作用，Boost电容会使T21的Gate的电位进一步的升高，从而提升了电路的输出能力。但是，一般的Boost电容值比较大，在电路设计时，Boost电容会占用很大的空间，使得GOA区域的宽度难以压缩，这样对窄边框产品的设计是非常不利的，也不利于产品成本的控制。
因此需要对现有技术中的问题提出解决方法。
 技术问题
综上所述，现有的GOA电路中，存在着Boost电容所占据的设计空间较大，GOA区域的宽度难以压缩，不利于窄边框产品的设计，并且生产成本高等问题。
 技术解决方案
本揭示提供一种显示面板及显示装置，以解决现有的GOA电路中，GOA区域较宽难以压缩，Boost电容所占据的设计空间较大，产品生产成本高等问题。
为解决上述技术问题，本揭示实施例提供的技术方案如下：
根据本揭示实施例的第一方面，提供了一种显示面板，包括：
衬底基板；
薄膜晶体管器件层，所述薄膜晶体管器件层设置在所述衬底基板上；
钝化层，所述钝化层设置在所述薄膜晶体管器件层上；以及
导电膜层，所述导电膜层设置在所述钝化层上；
其中，所述导电膜层通过第一过孔与所述薄膜晶体管器件层中薄膜晶体管的栅极电连接，所述导电膜层与所述薄膜晶体管的源/漏极相对应的区域至少部分重叠并用以形成第一电容结构；
所述第一过孔位于所述薄膜晶体管源极的一侧，所述第一过孔贯穿所述薄膜晶体管器件层和所述钝化层；所述导电膜层包括像素电极膜层。
根据本揭示一实施例，所述导电膜层完全覆盖所述钝化层。
根据本揭示一实施例，所述导电膜层设置在所述钝化层上并覆盖部分所述薄膜晶体管的所述源极。
根据本揭示一实施例，所述显示面板还包括第二电容，所述薄膜晶体管的源/漏极与所述薄膜晶体管的栅极相对应的重叠区域形成所述第二电容。
根据本揭示一实施例，所述第一电容与所述第二电容并联设置。
根据本揭示一实施例，所述第一电容的电容值大于所述第二电容的电容值。
根据本揭示一实施例，所述钝化层的厚度为1500Å~2500Å。
根据本揭示实施例的第二方面，提供了一种显示面板，包括：
衬底基板；
薄膜晶体管器件层，所述薄膜晶体管器件层设置在所述衬底基板上；
钝化层，所述钝化层设置在所述薄膜晶体管器件层上；以及
导电膜层，所述导电膜层设置在所述钝化层上；
其中，所述导电膜层通过第一过孔与所述薄膜晶体管器件层中薄膜晶体管的栅极电连接，所述导电膜层与所述薄膜晶体管的源/漏极相对应的区域至少部分重叠并用以形成第一电容结构。
根据本揭示一实施例，所述第一过孔位于所述薄膜晶体管源极的一侧，所述第一过孔贯穿所述薄膜晶体管器件层和所述钝化层。
根据本揭示一实施例，所述导电膜层完全覆盖所述钝化层。
根据本揭示一实施例，所述导电膜层设置在所述钝化层上并覆盖部分所述薄膜晶体管的源极。
根据本揭示一实施例，所述显示面板还包括第二电容，所述薄膜晶体管的源/漏极与所述薄膜晶体管的栅极相对应的重叠区域形成所述第二电容。
根据本揭示一实施例，所述第一电容与所述第二电容并联设置。
根据本揭示一实施例，所述第一电容的电容值大于所述第二电容的电容值。
根据本揭示一实施例，所述导电膜层为像素电极膜层。
根据本揭示一实施例，所述钝化层的厚度为1500Å~2500Å。
根据本揭示的第三方面，还提供了一种显示装置，所述显示装置包括：
衬底基板；
薄膜晶体管器件层，所述薄膜晶体管器件层设置在所述衬底基板上；
钝化层，所述钝化层设置在所述薄膜晶体管器件层上；以及
导电膜层，所述导电膜层设置在所述钝化层上；
其中，所述导电膜层通过第一过孔与所述薄膜晶体管器件层中薄膜晶体管的栅极电连接，所述导电膜层与所述薄膜晶体管的源/漏极相对应的区域至少部分重叠并用以形成第一电容结构。
根据本揭示一实施例，所述第一过孔位于所述薄膜晶体管源极的一侧，所述第一过孔贯穿所述薄膜晶体管器件层和所述钝化层。
根据本揭示一实施例，所述导电膜层完全覆盖所述钝化层。
根据本揭示一实施例，所述导电膜层设置在所述钝化层上并覆盖部分所述薄膜晶体管的所述源极。
 有益效果
综上所述，本揭示实施例的有益效果为：
本揭示提供一种新的薄膜晶体管及GOA驱动电路，通过在薄膜晶体管的结构中设置钝化层及氧化铟锡膜层，增加的钝化层及氧化铟锡膜层与其他膜层构成新的电容，使得GOA电路中的电容值进一步增大，进而将GOA区域的宽度进行压缩，减小其设计空间，实现窄边框产品的设计。
 附图说明
图1为现有设计的显示面板中的一级GOA电路的等效电路图；
图2为图1中GOA电路图的部分平面设计图；
图3为本揭示实施例的GOA电路的部分平面设计图；
图4为图3中本揭示实施例的显示面板的截面结构示意图；
图5为本揭示另一种实施例的GOA电路的部分平面设计图；
图6为图5中本揭示另一种实施例的显示面板的截面结构示意图；
图7为本揭示实施例的显示装置示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
在本揭示的实施例中，如图1所示，图1为现有设计中的显示面板的一级GOA电路的等效电路图。图中时钟信号线上第二列第一个（T21）薄膜晶体管是GOA电路输出中最重要的器件，根据图中T21的连接关系，T21的TFT的源极与时钟信号线相连接，T21的TFT的漏极与栅极扫描线G（n）相连接，同时，为了提升GOA电路的输出能力，会在T21的栅极和源极之间增加一个电容，即图中的升压（Boost）电容100，在电路工作时，由于耦合作用，升压电容100会使T21的栅极上的电位进一步升高，使得GOA的电路的输出能力提高。
如图2所示，图2为图1中GOA电路的部分平面设计图。其中包括第一时钟信号线（CK1）201、栅极扫描线200以及薄膜晶体管区域中的T21薄膜晶体管203。第一时钟信号线201与薄膜晶体管的漏极相连接。同时，图2中还包括GOA区域202，一般情况下，GOA电路中的升压电容100的电容值Cboost比较大，为了满足升压电容100的电容值，在设计时，GOA区域202的宽度D就会设置的较宽，而宽度D的数值越大，占据的设计空间就越大，这样对于窄边框产品的设计时非常不利的，因此，在设计时，需要尽可能的提高升压电容100的电容值，升压电容100的电容越大，所对应在GOA区域中的宽度D就越小，当宽度D的数值越小，面板的边框也变得较小，最终实现显示面板的窄边框设计。
本揭示提供一种薄膜晶体管，在不改变现有GOA电路结构设计图的条件下，通过改变显示面板内部的结构来提高所述升压电容100的电容值，达到减小GOA宽度的效果。
如图3所示，图3为本揭示实施例GOA电路的部分平面设计图。GOA电路中包括第一时钟信号线（CK1）301、栅极扫描线300以及T21薄膜晶体管303，其中还包括GOA区域302和设置在GOA区域302内的导电膜层304，所述导电膜层304可为像素电极膜层，所述像素电极膜层为氧化铟锡膜。以及T21薄膜晶体管303的栅极层305，多晶硅层306，设置在多晶硅层306上的源极307。在本实施例中，通过在GOA区域302内设置导电膜层304，以此来增大图1中的升压电容100的电容值Cboost。
具体的，如图4所示，图4为图3中对应的本揭示实施例的显示面板的截面结构示意图。显示面板的结构包括：衬底基板400，设置在衬底基板400之上的栅极401，设置在栅极401之上的栅极绝缘层402，设置在栅极绝缘层402之上的多晶硅层405，以及薄膜晶体管的漏极406、源极407、设置在漏极405与源极407之间的沟道408。所述源极407和所述漏极406具有相同的材质，薄膜晶体管的栅极401、源/漏极、栅极绝缘层402以及多晶硅层405共同构成了一薄膜晶体管器件层。
所述显示面板的结构中还包括钝化层403和导电膜层404。钝化层403设置在栅极绝缘层402之上，并且所述钝化层403完全覆盖所述多晶硅层405、源极407以及漏极406，在本揭示实施例中，导电膜层404位于钝化层403的一侧，只覆盖钝化层403的部分区域，未将钝化层403全部覆盖，钝化层403的材料包括绝缘材质。
在本揭示实施例中，所述栅极绝缘层402上还设置有第一过孔409。所述第一过孔409位于所述薄膜晶体管漏极406的一侧，所述第一过孔409贯穿所述薄膜晶体管器件层和所述钝化层403。所述导电膜层404通过所述第一过孔409与所述薄膜晶体管的栅极401相连接，所述导电膜层404包括氧化铟锡膜层。
在制备时，所述第一过孔409经过涂胶、曝光、显影、刻蚀等光刻工艺流程制备形成，所述栅极绝缘层402通过沉积工艺设置在栅极401上，栅极绝缘层402可以是SiOx、SiNx薄膜或叠层结构的薄膜。
由于导电膜层404与源极407均为导电膜层，此时就相当于一个电容的上、下电极板，而钝化层403为绝缘介质，因此在导电膜层404与源极407两者相对应的重叠区域410之间会形成一个第一电容C1，同理，薄膜晶体管的栅极401、源极407与其栅极401三者相对应的重叠区域膜层之间会形成一个第二电容C2。第一电容C1与第二电容C2在连接上为并联的形式，此时，结合图1中的电路图，电路中的总的升压电容100的就变为第一电容C1与第二电容C2之和，升压电容100的电容值也变为两者电容值的和。从而使得整个显示面板内的电容值变大。由于电容值变大，因此，在设计时，其边框处的宽度D值就可相应的进行缩小。
由于钝化层403的厚度较薄，钝化层403的膜厚在1500Å~2500Å，优选为2000Å；栅极绝缘层402的厚度较大，膜厚在3500Å~4050Å之间，优选为4000Å。即所述第一电容值大于第二电容的电容值。
同时，电容值的大小会取决于导电膜层404与源极407之间相对的重叠区域410的面积，相对重叠区域410的面积越大，升压电容也会越大。
由于本揭示实施例中的电容值要大于现有设计的显示面板中的电容值。因此，对应于图3中GOA电路平面图中，相对于现有设计，本揭示实施例中升压电容的上下两个电极的面积就可以变小，即GOA区域302中的宽度能进行压缩，进一步的减小D1的宽度值，从而实现了窄边框的产品设计。
如图5所示，图5为本揭示另一种实施例的GOA电路的部分平面设计图。在本揭示实施例中，如图5所示，第一时钟信号线（CK1）501与薄膜晶体管的源极相连接、栅极扫描线500与薄膜晶体管的漏极相连接，保证薄膜晶体管信号的正常输入和输出。像素电极504覆盖整个GOA电路的设计空间。
具体的，如图6所示，图6为图5中本揭示另一种实施例的显示面板的截面结构示意图。像素电极604完全覆盖整个钝化层603。显示面板的其他膜层结构设置同图4中的结构，自下而上依次设置衬底基板600、栅极601、栅极绝缘层602以及多晶硅层605、源极607和漏极606，具体结构这里不再详细描述。根据图4中形成升压电容的原理，同理可知，在本揭示实施例中，在显示面板内形成的第一重叠区域610以及第二重叠区域611，第一重叠区域610为像素电极604与像素电极604相对应的薄膜晶体管的源极607形成的重叠区域，这一第一重叠区域610构成了第一电容C1，上下两导电膜层分别为第一电容C1的上下极板，同理，薄膜晶体管的源极607与薄膜晶体管的栅极601相对应的第二重叠区域611构成了显示面板的第二电容C2，图中第一重叠区域610与第二重叠区域611只是整个显示面板的一部分示意，其它区域内的相对应的膜层之间形成的重叠部分均为本揭示实施例中的第一电容C1和第二电容C2。
在结构以及连接关系上，实施例中的第一电容C1与第二电容C2为并联的结构，因此，显示面板内的总电容值就变为C=C1+C2，进而，通过增加一层导电膜层，增加了显示面板内的整个电容值，具体的对应到其平面布置图5上，由于此时像素电极604的面积变得更大，当像素电极604与栅极601以及钝化层603三者形成第一电容时，相互间相对应的重叠面积会更多，第一电容的电容值会变得更大。
因此，其侧边处的宽度D2的值就会进一步变小，在较小的宽度D2情况下，就可满足显示面板的电容值。对应于图5中的GOA电路设计时，GOA区域能再进一步的压缩，宽度D2变得更小，更有利于窄边框产品的设计。因此，根据上述各个不同的实施例，其GOA区域的宽度大小关系为D>D1>D2，即当导电膜层覆盖的钝化层的区域越多，其边缘处的宽度D就会越小。
本揭示实施例还提供一种显示装置，所述显示装置中包括本揭示实施例提供的显示面板。如图7所示，图7为本揭示实施例的显示装置示意图。在本揭示实施例的显示装置700中，显示装置700内部包括本揭示实施例提供的显示面板701，其中，显示面板701中驱动电路的升压电容的电容值比现有设计中的升压电容的电容值都大，这样，在GOA电路布局时，GOA区域所占据的设计空间更小。
以上对本揭示实施例所提供的一种显示面板及显示装置进行了详细介绍，以上实施例的说明只是用于帮助理解本揭示的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，而这些修改或者替换，并不使相应技术方案的本质脱离本揭示各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，包括：
    衬底基板；
    薄膜晶体管器件层，所述薄膜晶体管器件层设置在所述衬底基板上；
    钝化层，所述钝化层设置在所述薄膜晶体管器件层上；以及
    导电膜层，所述导电膜层设置在所述钝化层上；
    其中，所述导电膜层通过第一过孔与所述薄膜晶体管器件层中薄膜晶体管的栅极电连接，所述导电膜层与所述薄膜晶体管的源/漏极相对应的区域至少部分重叠并用以形成第一电容结构；
    所述第一过孔位于所述薄膜晶体管源极的一侧，所述第一过孔贯穿所述薄膜晶体管器件层和所述钝化层；所述导电膜层包括像素电极膜层。
  2. 根据权利要求1所述的显示面板，其中所述导电膜层完全覆盖所述钝化层。
  3. 根据权利要求1所述的显示面板，其中所述导电膜层设置在所述钝化层上并覆盖部分所述薄膜晶体管的所述源极。
  4. 根据权利要求1所述的显示面板，其中所述显示面板还包括第二电容，所述薄膜晶体管的源/漏极与所述薄膜晶体管的栅极相对应的重叠区域形成所述第二电容。
  5. 根据权利要求4所述的显示面板，其中所述第一电容与所述第二电容并联设置。
  6. 根据权利要求4所述的显示面板，其中所述第一电容的电容值大于所述第二电容的电容值。
  7. 根据权利要求1所述的显示面板，其中所述钝化层的厚度为1500Å~2500Å。
  8. 一种显示面板，包括：
    衬底基板；
    薄膜晶体管器件层，所述薄膜晶体管器件层设置在所述衬底基板上；
    钝化层，所述钝化层设置在所述薄膜晶体管器件层上；以及
    导电膜层，所述导电膜层设置在所述钝化层上；
    其中，所述导电膜层通过第一过孔与所述薄膜晶体管器件层中薄膜晶体管的栅极电连接，所述导电膜层与所述薄膜晶体管的源/漏极相对应的区域至少部分重叠并用以形成第一电容结构。
  9. 根据权利要求8所述的显示面板，其中所述第一过孔位于所述薄膜晶体管源极的一侧，所述第一过孔贯穿所述薄膜晶体管器件层和所述钝化层。
  10. 根据权利要求8所述的显示面板，其中所述导电膜层完全覆盖所述钝化层。
  11. 根据权利要求8所述的显示面板，其中所述导电膜层设置在所述钝化层上并覆盖部分所述薄膜晶体管的所述源极。
  12. 根据权利要求8所述的显示面板，其中所述显示面板还包括第二电容，所述薄膜晶体管的源/漏极与所述薄膜晶体管的栅极相对应的重叠区域形成所述第二电容。
  13. 根据权利要求12所述的显示面板，其中所述第一电容与所述第二电容并联设置。
  14. 根据权利要求12所述的显示面板，其中所述第一电容的电容值大于所述第二电容的电容值。
  15. 根据权利要求8所述的显示面板，其中所述导电膜层为像素电极膜层。
  16. 根据权利要求8所述的显示面板，其中所述钝化层的厚度为1500Å~2500Å。
  17. 一种显示装置，包括：
    衬底基板；
    薄膜晶体管器件层，所述薄膜晶体管器件层设置在所述衬底基板上；
    钝化层，所述钝化层设置在所述薄膜晶体管器件层上；以及
    导电膜层，所述导电膜层设置在所述钝化层上；
    其中，所述导电膜层通过第一过孔与所述薄膜晶体管器件层中薄膜晶体管的栅极电连接，所述导电膜层与所述薄膜晶体管的源/漏极相对应的区域至少部分重叠并用以形成第一电容结构。
  18. 根据权利要求17所述的显示装置，其中所述第一过孔位于所述薄膜晶体管源极的一侧，所述第一过孔贯穿所述薄膜晶体管器件层和所述钝化层。
  19. 根据权利要求17所述的显示装置，其中所述导电膜层完全覆盖所述钝化层。
  20. 根据权利要求17所述的显示装置，其中所述导电膜层设置在所述钝化层上并覆盖部分所述薄膜晶体管的所述源极。
PCT/CN2019/126628 2019-09-27 2019-12-19 显示面板及显示装置 WO2021056867A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/626,359 US11437414B2 (en) 2019-09-27 2019-12-19 Display panel and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910922443.9A CN110729308A (zh) 2019-09-27 2019-09-27 显示面板及显示装置
CN201910922443.9 2019-09-27

Publications (1)

Publication Number Publication Date
WO2021056867A1 true WO2021056867A1 (zh) 2021-04-01

Family

ID=69218462

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/126628 WO2021056867A1 (zh) 2019-09-27 2019-12-19 显示面板及显示装置

Country Status (3)

Country Link
US (1) US11437414B2 (zh)
CN (1) CN110729308A (zh)
WO (1) WO2021056867A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116249394A (zh) * 2023-02-28 2023-06-09 惠科股份有限公司 显示面板、显示装置和显示面板的制备方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112701127A (zh) * 2019-10-23 2021-04-23 群创光电股份有限公司 电子装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120218485A1 (en) * 2009-11-09 2012-08-30 Sharp Kabushiki Kaisha Active matrix substrate and liquid crystal display panel including the same, and method for manufacturing active matrix substrate
CN104536223A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 液晶显示面板及其阵列基板
CN204314578U (zh) * 2014-12-23 2015-05-06 京东方科技集团股份有限公司 一种显示基板和显示装置
CN107527599A (zh) * 2017-08-16 2017-12-29 深圳市华星光电半导体显示技术有限公司 扫描驱动电路、阵列基板与显示面板
CN108020971A (zh) * 2017-12-22 2018-05-11 武汉华星光电技术有限公司 阵列基板、液晶面板以及液晶显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080022245A (ko) * 2006-09-06 2008-03-11 삼성전자주식회사 게이트 구동회로 및 이를 갖는 표시 장치
CN103018991B (zh) * 2012-12-24 2015-01-28 京东方科技集团股份有限公司 一种阵列基板及其制造方法、显示装置
CN108873514A (zh) * 2018-06-11 2018-11-23 深圳市华星光电半导体显示技术有限公司 阵列基板及其制作方法
CN208861649U (zh) * 2018-11-08 2019-05-14 惠科股份有限公司 阵列基板、显示面板以及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120218485A1 (en) * 2009-11-09 2012-08-30 Sharp Kabushiki Kaisha Active matrix substrate and liquid crystal display panel including the same, and method for manufacturing active matrix substrate
CN204314578U (zh) * 2014-12-23 2015-05-06 京东方科技集团股份有限公司 一种显示基板和显示装置
CN104536223A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 液晶显示面板及其阵列基板
CN107527599A (zh) * 2017-08-16 2017-12-29 深圳市华星光电半导体显示技术有限公司 扫描驱动电路、阵列基板与显示面板
CN108020971A (zh) * 2017-12-22 2018-05-11 武汉华星光电技术有限公司 阵列基板、液晶面板以及液晶显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116249394A (zh) * 2023-02-28 2023-06-09 惠科股份有限公司 显示面板、显示装置和显示面板的制备方法
CN116249394B (zh) * 2023-02-28 2024-05-03 惠科股份有限公司 显示面板、显示装置和显示面板的制备方法

Also Published As

Publication number Publication date
CN110729308A (zh) 2020-01-24
US20210408084A1 (en) 2021-12-30
US11437414B2 (en) 2022-09-06

Similar Documents

Publication Publication Date Title
US9933664B2 (en) Display panel and encapsulation method thereof, and liquid crystal display device
KR101896377B1 (ko) 베젤이 최소화된 액정표시소자
JP3433779B2 (ja) アクティブマトリクス基板およびその製造方法
TWI299099B (en) Active matrix type liquid crystal display apparatus
TWI464882B (zh) 薄膜電晶體基板及其製造方法
WO2018119932A1 (zh) 一种显示面板及其阵列基板
WO2011030583A1 (ja) 液晶表示装置及びその製造方法
WO2010071160A1 (ja) アクティブマトリクス基板の製造方法、および、液晶表示装置の製造方法
KR20150078248A (ko) 표시소자
WO2005029450A1 (ja) 電極配線基板および表示装置
WO2013149467A1 (zh) 阵列基板及其制作方法和显示装置
WO2009081633A1 (ja) アクティブマトリクス基板、これを備えた液晶表示装置、及びアクティブマトリクス基板の製造方法
WO2021056867A1 (zh) 显示面板及显示装置
WO2021035847A1 (zh) 液晶显示面板及其制作方法与无边框液晶显示装置
WO2010071159A1 (ja) 絶縁ゲート型トランジスタ、アクティブマトリクス基板、液晶表示装置及びそれらの製造方法
JPH0728089A (ja) 液晶表示パネル
TWI401497B (zh) 顯示面板
JP4381691B2 (ja) 液晶表示装置用基板及びそれを備えた液晶表示装置及びその製造方法
CN113985662B (zh) 显示面板、阵列基板及其制造方法
US20040125293A1 (en) Integrated color filter and fabricating method thereof
JP4747911B2 (ja) 液晶パネル用アレイ基板および液晶パネルならびにこれらの製造方法
JPH06160901A (ja) 液晶表示装置
JPH0444014A (ja) アクティブマトリクス型液晶表示装置
JPH1195255A (ja) 液晶表示装置のアレイ基板、およびこれを備えた液晶表示装置
WO2020206785A1 (zh) 显示面板及显示模组

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19946921

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19946921

Country of ref document: EP

Kind code of ref document: A1