CN106684037B - 优化4m制程的tft阵列制备方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 67
- 238000012545 processing Methods 0.000 title claims abstract description 38
- 238000002360 preparation method Methods 0.000 title claims abstract description 27
- 230000003287 optical effect Effects 0.000 claims abstract description 28
- 238000004380 ashing Methods 0.000 claims abstract description 20
- 239000001301 oxygen Substances 0.000 claims abstract description 20
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 20
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 238000001312 dry etching Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000001039 wet etching Methods 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 238000002161 passivation Methods 0.000 claims abstract description 10
- 206010019133 Hangover Diseases 0.000 claims abstract description 8
- 238000011161 development Methods 0.000 claims abstract description 6
- 239000011521 glass Substances 0.000 claims abstract description 6
- 238000005457 optimization Methods 0.000 claims description 16
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 9
- 229910044991 metal oxide Inorganic materials 0.000 claims description 7
- 150000004706 metal oxides Chemical class 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 239000010409 thin film Substances 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 238000007639 printing Methods 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims 1
- 238000007740 vapor deposition Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000002926 oxygen Chemical class 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
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- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1292—Multistep manufacturing methods using liquid deposition, e.g. printing
-
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Abstract
本发明提供一种优化4M制程的TFT阵列制备方法。该方法包括：步骤10、在第一道光罩制程中，在玻璃基板上制备栅极层，并图形化栅极层；步骤20、在第二道光罩制程中，对光刻胶层进行曝光显影；第一次湿刻，图形化源漏极层；第一次氧气灰化，减少源漏金属层边的有源层拖尾大小；第一次干刻，形成有源层岛状结构；第二次氧气灰化，露出沟道区域的源漏极层；第二次湿刻，图形化源漏极；第三次氧气灰化，减少接触层拖尾；第二次干刻，刻蚀有源层；步骤30、在第三道光罩制程中，制备钝化层并图案化；步骤40、在第四道光罩制程中，制备透明电极层并图案化。本发明可以在原制程基础上，成功在沟道区消除重掺杂残留(减少约0.9um)，在不定形硅区减少约1um。
Description
技术领域
本发明涉及液晶显示器领域，尤其涉及一种优化4M制程的TFT阵列制备方法。
背景技术
液晶显示器(LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
为了降低成本、提高良率，各家显示阵列基板制备和研究厂商和机构不断开发新的制程工艺和技术，其中，4M(四道光罩)代替5M(五道光罩)为业内研发和制程趋势。在4M制程中存在第二层金属边缘有不定形硅和重掺杂硅残留问题，第二层金属即源漏极层金属。该问题影响TFT(薄膜晶体管)光学稳定性和电学性能，开口率，功耗和可靠性，这是由于其采用HTM(半色调光罩)或GTM(灰阶光罩)曝光图形化过程引起。
参见图1，其为现有4M制程示意图，显示了现有4M制程中的第二道光罩制程。现有4M制程一般包括：
在第一道光罩制程中，在玻璃基板11上制备栅极层12，并图形化栅极层12；然后制备栅极绝缘层13、有源层、源漏极层16、光刻胶层17，有源层可以包括沟道层14、接触层15；
在第二道光罩制程中，此示例中第二道光罩为灰阶光罩，对光刻胶层17进行曝光显影；第一次湿刻，图形化源漏极层16，形成源漏极区域和有源区域的金属导线结构；第一次干刻，形成有源层岛状结构，也就是图形化沟道层14、接触层15；氧气灰化，降低光刻胶层17厚度以露出沟道区域的源漏极层16；第二次湿刻，图形化源漏极；第二次干刻，刻蚀有源层，也就是刻蚀开沟道层14、接触层15，形成薄膜晶体管结构；
在第三道光罩制程中，制备钝化层，并图案化钝化层；
在第四道光罩制程中，制备透明电极层，并图案化透明电极层。
针对现有4M制程中存在的第二层金属边缘有不定形硅和重掺杂硅残留的问题，亟需一种优化4M制程的TFT阵列制备方法。
发明内容
本发明的目的在于通过制程方法变更，减少或消除第二层金属边缘有不定形硅和重掺杂硅残留问题。
为实现上述目的，本发明提供一种优化4M制程的TFT阵列制备方法，包括：
步骤10、在第一道光罩制程中，在玻璃基板上制备栅极层，并图形化栅极层；然后制备栅极绝缘层、有源层、源漏极层、光刻胶层；
步骤20、在第二道光罩制程中，对光刻胶层进行曝光显影；第一次湿刻，图形化源漏极层，形成源漏极区域和有源区域的金属导线结构；第一次氧气灰化，减少源漏金属层边的有源层拖尾大小；第一次干刻，形成有源层岛状结构；第二次氧气灰化，降低光刻胶层厚度以露出沟道区域的源漏极层；第二次湿刻，图形化源漏极；第三次氧气灰化，减少接触层拖尾；第二次干刻，刻蚀有源层，形成薄膜晶体管结构；
步骤30、在第三道光罩制程中，制备钝化层，并图案化钝化层；
步骤40、在第四道光罩制程中，制备透明电极层，并图案化透明电极层。
其中，所述TFT阵列为显示区或GOA电路区的TFT阵列。
其中，该第二道光罩为灰阶光罩或半色调光罩。
其中，通过溅射，溶胶凝胶，原子层沉积，蒸发，或者打印方式制备所述栅极层。
其中，所述栅极层的材料为Cu，Cu/Mo，Mo/Cu/Mo，MoNb/Cu/MoNb，Ti/Cu/Ti，Al，Al/Mo，或者Mo/Al/Mo。
其中，通过等离子体化学气相沉积，常压化学气相沉积，或者溅射制备所述栅绝缘层。
其中，所述栅绝缘层的材料为氮化硅，氧化硅，氮氧化硅，氧化铝，或者氧化铪。
其中，所述有源层包括沟道层和接触层。
其中，所述沟道层和接触层通过沉积硅基，溅射金属氧化物半导体层，或者原子层沉积金属氧化物半导体层形成。
其中，所述金属氧化物为IGZO，IZO，或者ITZO。
综上，本发明优化4M制程的TFT阵列制备方法在原制程基础上添加两步氧气灰化步骤，该步骤会在原制程的同个腔室中进行，不额外增加单独的机台使用，有利于降低成本，提高良率；达到提高TFT光学稳定性和电学性能，开口率，可靠性以及减低功耗目的，提高阵列基板的整体性能，可以在原制程基础上，成功在沟道区消除重掺杂残留(减少约0.9um)，在不定形硅区减少约1um。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有4M制程示意图；
图2为本发明优化4M制程的TFT阵列制备方法的制程示意图；
图3为本发明优化4M制程的TFT阵列制备方法的流程图。
具体实施方式
图3为本发明优化4M制程的TFT阵列制备方法的流程图。该制备方法主要包括：
步骤10、在第一道光罩制程中，在玻璃基板上制备栅极层，并图形化栅极层；然后制备栅极绝缘层、有源层、源漏极层、光刻胶层；
步骤20、在第二道光罩制程中，对光刻胶层进行曝光显影；第一次湿刻，图形化源漏极层，形成源漏极区域和有源区域的金属导线结构；第一次氧气灰化，减少源漏金属层边的有源层拖尾大小；第一次干刻，形成有源层岛状结构；第二次氧气灰化，降低光刻胶层厚度以露出沟道区域的源漏极层；第二次湿刻，图形化源漏极；第三次氧气灰化，减少接触层拖尾；第二次干刻，刻蚀有源层，形成薄膜晶体管结构；
步骤30、在第三道光罩制程中，制备钝化层，并图案化钝化层；
步骤40、在第四道光罩制程中，制备透明电极层，并图案化透明电极层。
本发明具体涉及一种优化的4M制程工艺背板开发，可用于包括显示区和GOA电路区TFT阵列开发和显示以及电路性能优化。本发明包括栅电极制备，可通过溅射，溶胶凝胶，原子层沉积，蒸发，打印等方式制备Cu，Cu/Mo，Mo/Cu/Mo，MoNb/Cu/MoNb，Ti/Cu/Ti，Al，Al/Mo，Mo/Al/Mo等电极材料，并图形化。本发明包括栅绝缘层制备，具体包括等离子体化学气相沉积，常压化学气相沉积，溅射等制备的氮化硅，氧化硅，氮氧化硅，氧化铝，氧化铪等介质材料。本发明包括沉积硅基，溅射和原子层沉积金属氧化物半导体层，如IGZO，IZO，ITZO等做为沟道层和接触层。第二道光罩可采用灰阶光罩或半色调光罩。步骤30及40中钝化层沉积，接触孔刻蚀，和透明电极如ITO引出等，可采用现有技术，在此不再赘述。
参见图2，其为本发明优化4M制程的TFT阵列制备方法的制程示意图，显示了第二道光罩制程，也就是本发明对现有制程优化的部分。
在第二道光罩制程前的第一道光罩制程中，在玻璃基板21上制备栅极层22，并图形化栅极层22；然后制备栅极绝缘层23、有源层、源漏极层26、光刻胶层27，有源层可以包括沟道层24、接触层25。然后，在应用灰阶光罩的第二道光罩制程中：
应用灰阶光罩，对光刻胶层27进行曝光显影；
第一次湿刻，图形化源漏极层26，形成源漏极区域和有源区域的金属导线结构；
第一次氧气灰化，减少源漏金属层26边的有源层拖尾大小；增加此次氧气灰化主要作用是减少不定形硅残留；
第一次干刻，形成有源层岛状结构，也就是图形化沟道层24、接触层25；
第二次氧气灰化，降低光刻胶层27厚度以露出沟道区域的源漏极层16；
第二次湿刻，图形化源漏极；
第三次氧气灰化，减少接触层拖尾；增加此次氧气灰化主要作用为减少重掺杂硅残留；
第二次干刻，刻蚀有源层，也就是刻蚀开沟道层24、接触层25，形成薄膜晶体管结构。
综上，本发明优化4M制程的TFT阵列制备方法在原制程基础上添加两步氧气灰化步骤，该步骤会在原制程的同个腔室中进行，不额外增加单独的机台使用，有利于降低成本，提高良率；达到提高TFT光学稳定性和电学性能，开口率，可靠性以及减低功耗目的，提高阵列基板的整体性能，可以在原制程基础上，成功在沟道区消除重掺杂残留(减少约0.9um)，在不定形硅区减少约1um。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。
Claims (10)
1.一种优化4M制程的TFT阵列制备方法，所述4M指代四道光罩，其特征在于，包括：
步骤10、在第一道光罩制程中，在玻璃基板上制备栅极层，并图形化栅极层；然后制备栅极绝缘层、有源层、源漏极层、光刻胶层；
步骤20、在第二道光罩制程中，对光刻胶层进行曝光显影；第一次湿刻，图形化源漏极层，形成源漏极区域和有源区域的金属导线结构；第一次氧气灰化，减少源漏金属层边的有源层拖尾大小；第一次干刻，形成有源层岛状结构；第二次氧气灰化，降低光刻胶层厚度以露出沟道区域的源漏极层；第二次湿刻，图形化源漏极；第三次氧气灰化，减少接触层拖尾；第二次干刻，刻蚀有源层，形成薄膜晶体管结构；
步骤30、在第三道光罩制程中，制备钝化层，并图案化钝化层；
步骤40、在第四道光罩制程中，制备透明电极层，并图案化透明电极层。
2.如权利要求1所述的优化4M制程的TFT阵列制备方法，其特征在于，所述TFT阵列为显示区或GOA电路区的TFT阵列。
3.如权利要求1所述的优化4M制程的TFT阵列制备方法，其特征在于，该第二道光罩为灰阶光罩或半色调光罩。
4.如权利要求1所述的优化4M制程的TFT阵列制备方法，其特征在于，通过溅射，溶胶凝胶，原子层沉积，蒸发，或者打印方式制备所述栅极层。
5.如权利要求4所述的优化4M制程的TFT阵列制备方法，其特征在于，所述栅极层的材料为Cu，Cu/Mo，Mo/Cu/Mo，MoNb/Cu/MoNb，Ti/Cu/Ti，Al，Al/Mo，或者Mo/Al/Mo。
6.如权利要求1所述的优化4M制程的TFT阵列制备方法，其特征在于，通过等离子体化学气相沉积，常压化学气相沉积，或者溅射制备所述栅极绝缘层。
7.如权利要求6所述的优化4M制程的TFT阵列制备方法，其特征在于，所述栅绝缘层的材料为氮化硅，氧化硅，氮氧化硅，氧化铝，或者氧化铪。
8.如权利要求1所述的优化4M制程的TFT阵列制备方法，其特征在于，所述有源层包括沟道层和接触层。
9.如权利要求8所述的优化4M制程的TFT阵列制备方法，其特征在于，所述沟道层和接触层通过沉积硅基，溅射金属氧化物半导体层，或者原子层沉积金属氧化物半导体层形成。
10.如权利要求9所述的优化4M制程的TFT阵列制备方法，其特征在于，所述金属氧化物为IGZO，IZO，或者ITZO。
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