CN105655391A - Tft阵列基板及其制作方法 - Google Patents

Tft阵列基板及其制作方法 Download PDF

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Publication number
CN105655391A
CN105655391A CN201610060834.0A CN201610060834A CN105655391A CN 105655391 A CN105655391 A CN 105655391A CN 201610060834 A CN201610060834 A CN 201610060834A CN 105655391 A CN105655391 A CN 105655391A
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China
Prior art keywords
layer
aluminium lamination
electrode
burr
insulating film
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CN201610060834.0A
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CN105655391B (zh
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李安石
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to CN201610060834.0A priority Critical patent/CN105655391B/zh
Priority to PCT/CN2016/082413 priority patent/WO2017128561A1/zh
Priority to US15/114,848 priority patent/US9885933B1/en
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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    • G02F2202/104—Materials and properties semiconductor poly-Si

Abstract

本发明提供一种TFT阵列基板及其制作方法，该TFT阵列基板中的源极(801)与漏极(802)包括自下而上层叠设置的第一钼层(811)、第一铝层(812)、第二铝层(813)、及第二钼层(814)，所述第一铝层(812)与第二铝层(813)的表面均分布有多个毛刺(8120)，且所述第二铝层(813)上的毛刺(8120)的高度大于所述第一铝层(812)上的毛刺(8120)的高度，使得所述源极(801)与漏极(802)的上表面呈现为凹凸不平的粗糙表面，相比于现有技术中的光滑的平整面，该凹凸不平的粗糙表面能够增大漏极(802)与像素电极(1200)的接触面积，进而减小TFT与像素电极的接触阻抗，提升液晶显示面板的性能。

Description

TFT阵列基板及其制作方法
技术领域
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板及其制作方法。
背景技术
液晶显示器(LiquidCrystalDisplay，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlightmodule)。液晶显示面板的工作原理是在薄膜晶体管阵列基板(ThinFilmTransistorArraySubstrate，TFTArraySubstrate)与彩色滤光片基板(ColorFilter，CF)之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
TFT阵列基板包括：多条栅极线和数据线，相互垂直的多条栅极线和多条数据线形成了多个像素单元，且每个像素单元内均设置有TFT、像素电极及存储电容等。TFT包括一栅极连接至栅极线，源极连接至数据线，漏极连接至像素电极。当栅极线被驱动时，TFT处于导通状态，对应的数据线送入灰阶电压信号并将其加载至像素电极，从而使得像素电极与公共电极之间产生相应的电场，液晶层中的液晶分子则在电场的作用下发生取向变化，以实现不同的图像显示。
请参阅图1，图1为现有的TFT阵列基板的剖面结构示意图，该TFT阵列基板包括：衬底基板1、设于所述衬底基板1上的遮光层2、覆盖所述遮光层2及衬底基板1的缓冲层3、对应所述遮光层2上方设于所述缓冲层3上的多晶硅半导体层4、覆盖所述多晶硅半导体层4及缓冲层3的栅极绝缘层5、对应所述多晶硅半导体层4上方设于所述栅极绝缘层5上的栅极6、覆盖所述栅极6及栅极绝缘层5的层间绝缘层7、设于所述层间绝缘层7上的源极81与漏极82、覆盖所述源极81、漏极82、及层间绝缘层7的平坦层9、设于所述平坦层9上的公共电极10、设于所述公共电极10上的保护层11、以及设于所述保护层11上方的像素电极12。所述源极81与漏极82均采用两层钼(Mo)夹设一层铝(Al)的结构，所述像素电极12通过贯穿所述保护层11、公共电极10、及平坦层9的过孔91与所述漏极82相接触，如图2所示，所述像素电极12与漏极82的接触面均为光滑的平整面，两者接触面积等于过孔91的底面面积，接触阻抗较高，影响液晶显示面板的性能。
发明内容
本发明的目的在于提供一种TFT阵列基板，能够减小TFT与像素电极的接触阻抗，提升液晶显示面板性能。
本发明的目的还在于提供一种TFT阵列基板的制作方法，能够减小TFT与像素电极的接触阻抗，提升液晶显示面板性能。
为实现上述目的，本发明提供了一种TFT阵列基板，包括：衬底基板、设于所述衬底基板上的遮光层、覆盖所述遮光层及衬底基板的缓冲层、对应所述遮光层上方设于所述缓冲层上的多晶硅半导体层、覆盖所述多晶硅半导体层及缓冲层的栅极绝缘层、对应所述多晶硅半导体层上方设于所述栅极绝缘层上的栅极、覆盖所述栅极及栅极绝缘层的层间绝缘层、设于所述层间绝缘层上的源极与漏极、覆盖所述源极、漏极、及层间绝缘层的平坦层、设于所述平坦层上的公共电极、设于所述公共电极上的保护层、以及设于所述保护层上方的像素电极；
所述源极与漏极均包括自下而上层叠设置的第一钼层、第一铝层、第二铝层、及第二钼层，其中，所述第一钼层的表面平滑，所述第一铝层与第二铝层的表面均分布有多个毛刺，且所述第二铝层上的毛刺的高度大于所述第一铝层上的毛刺的高度，所述第二钼层的表面平滑，其包覆于所述第二铝层的毛刺上，使所述第二铝层的毛刺的锋利度降低，最终使所述源极与漏极的上表面呈现为凹凸不平的粗糙表面；
所述像素电极通过贯穿所述保护层、公共电极、以及平坦层的过孔与所述漏极的上表面相接触。
所述源极和漏极分别通过贯穿层间绝缘层和栅极绝缘层的过孔与多晶硅半导体层的两端相接触。
所述遮光层的材料为钼。
所述缓冲层包括自下而上层叠设置的第一氮化硅层和第一氧化硅层；
所述栅极绝缘层包括自下而上层叠设置的第二氧化硅层和第二氮化硅层；
所述层间绝缘层包括自下而上层叠设置的第三氮化硅层和第三氧化硅层；
所述保护层的材料为氮化硅。
所述像素电极与公共电极的材料均为ITO。
本发明还提供一种TFT阵列基板的制作方法，包括如下步骤：
步骤1、提供一衬底基板，在所述衬底基板自下而上依次形成遮光层、缓冲层、多晶硅半导体层、栅极绝缘层、栅极、及层间绝缘层；
步骤2、在所述层间绝缘层上沉积第一钼层，所述第一钼层的表面平滑；
步骤3、在所述第一钼层上沉积第一铝层，所述第一铝层的表面分布有多个毛刺；
步骤4、在所述第一铝层上沉积第二铝层，所述第二铝层的表面也分布有多个毛刺，且所述第二铝层上的毛刺的高度大于所述第一铝层上的毛刺的高度；
步骤5、在所述第二铝层上沉积第二钼层，所述第二钼层的表面平滑，其包覆于所述第二铝层的毛刺上，使毛刺的锋利度降低，对第一钼层、第一铝层、第二铝层、及第二钼层进行图形化处理，得到位于所述层间绝缘层上的源极与漏极，所述源极与漏极的上表面呈现为凹凸不平的粗糙表面；
步骤6、在所述源极、漏极、及层间绝缘层上自下而上依次形成平坦层、公共电极、保护层、及像素电极；
所述像素电极通过贯穿所述保护层、公共电极、以及平坦层的过孔与所述漏极的上表面相接触。
所述源极和漏极分别通过贯穿层间绝缘层和栅极绝缘层的过孔与多晶硅半导体层的两端相接触。
所述遮光层的材料为钼。
所述缓冲层包括自下而上层叠设置的第一氮化硅层和第一氧化硅层；
所述栅极绝缘层包括自下而上层叠设置的第二氧化硅层和第二氮化硅层；
所述层间绝缘层包括自下而上层叠设置的第三氮化硅层和第三氧化硅层；
所述保护层的材料为氮化硅。
所述像素电极与公共电极的材料均为ITO。
本发明的有益效果：本发明提供了一种TFT阵列基板，该TFT阵列基板中的源极与漏极包括自下而上层叠设置的第一钼层、第一铝层、第二铝层、及第二钼层，所述第一铝层与第二铝层的表面均分布有多个毛刺，且所述第二铝层上的毛刺的高度大于所述第一铝层上的毛刺的高度，使得所述源极与漏极的上表面呈现为有凹凸不平的粗糙表面，相比于现有技术中的光滑的平整面，该凹凸不平的粗糙表面能够增大漏极与像素电极的接触面积，进而减小TFT与像素电极的接触阻抗，提升液晶显示面板的性能。本发明还提供一种TFT阵列基板的制作方法，能够减小TFT与像素电极的接触阻抗，提升液晶显示面板的性能。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的TFT阵列基板的剖面结构示意图；
图2为图1所示TFT阵列基板的漏极与像素电极的接触面的示意图；
图3为本发明的TFT阵列基板的制作方法的示意流程图；
图4为本发明的TFT阵列基板的制作方法的步骤1-步骤5的示意图；
图5为本发明的TFT阵列基板的制作方法的步骤5制得的源极与漏极的结构示意图；
图6为本发明的TFT阵列基板的制作方法的步骤6的示意图暨本发明的TFT阵列基板的剖面结构示意图；
图7为本发明的TFT阵列基板的漏极与像素电极的接触面的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图6和图5，本发明首先提供一种TFT阵列基板，包括：衬底基板100、设于所述衬底基板100上的遮光层200、覆盖所述遮光层200及衬底基板100的缓冲层300、对应所述遮光层200上方设于所述缓冲层300上的多晶硅半导体层400、覆盖所述多晶硅半导体层400及缓冲层300的栅极绝缘层500、对应所述多晶硅半导体层400上方设于所述栅极绝缘层500上的栅极600、覆盖所述栅极600及栅极绝缘层500的层间绝缘层700、设于所述层间绝缘层700上的源极801与漏极802、覆盖所述源极801、漏极802、及层间绝缘层700的平坦层900、设于所述平坦层900上的公共电极1000、设于所述公共电极1000上的保护层1100、以及设于所述保护层1100上方的像素电极1200；
所述源极801与漏极802均包括自下而上层叠设置的第一钼层811、第一铝层812、第二铝层813、及第二钼层814，其中，所述第一钼层811的表面平滑，所述第一铝层812与第二铝层813的表面均分布有多个毛刺8120，且所述第二铝层813上的毛刺8120的高度大于所述第一铝层812上的毛刺8120的高度，所述第二钼层814的表面平滑，其包覆于所述第二铝层813的毛刺8120上，使所述第二铝层813的毛刺8120的锋利度降低，最终使所述源极801与漏极802的上表面呈现为凹凸不平的粗糙表面；
所述像素电极1200通过贯穿所述保护层1100、公共电极1000、以及平坦层900的过孔901与所述漏极802的上表面相接触。
具体的，本发明通过设置粗糙度较高的第二铝层813，可保证所述源极801与漏极802的上表面具有足够的粗糙度，同时在第二铝层813下方设置粗糙度较低的第一铝层812，可保证所述源极801与漏极802的粗糙面下方的平整部分具有足够的厚度。
所述源极801和漏极802分别通过贯穿层间绝缘层700和栅极绝缘层500的过孔703与多晶硅半导体层400的两端相接触。
特别的，请参阅图2与图7，在现有技术中像素电极与漏极接触面为光滑的平整面，两者的接触面积等于过孔的底面积，而本发明中通过层叠设置粗糙度不同的第一铝层812与第二铝层813使得漏极802的上表面(即与像素电极的接触面)呈现为凹凸不平的粗糙表面，像素电极1200与漏极802接触面由平面接触变为了曲面接触，大大增加了接触面积，进而减小TFT与像素电极的接触阻抗，提升液晶显示面板的性能。
优选地，所述遮光层200的材料为钼。
优选地，所述缓冲层300包括自下而上层叠设置的第一氮化硅层301和第一氧化硅层302；所述栅极绝缘层500包括自下而上层叠设置的第二氧化硅层501和第二氮化硅层502；所述层间绝缘层700包括自下而上层叠设置的第三氮化硅层701和第三氧化硅层702；
优选地，所述保护层1100的材料为氮化硅。
优选地，所述像素电极1200与公共电极1000的材料均为ITO。
请参阅图3并结合图4至图7，本发明还提供一种TFT阵列基板的制作方法，包括如下步骤：
步骤1、请参阅图4，提供一衬底基板100，在所述衬底基板100自下而上依次形成遮光层200、缓冲层300、多晶硅半导体层400、栅极绝缘层500、栅极600、及层间绝缘层700。
具体的，该步骤1具体包括：
步骤11、在衬底基板100上沉积一金属薄膜，图案化该金属薄膜形成遮光层200，优选的，所述金属薄膜的材料为钼；
步骤12、在所述遮光层200及衬底基板100上成膜第一氮化硅层301，在所述第一氮化硅层301上成膜第一氧化硅层302，形成缓冲层300；
步骤13、在所述缓冲层300上沉积一非晶硅层，对所述非晶硅层进行晶化处理形成多晶硅层，在对所述多晶硅层进行图案化和离子掺杂制程，形成位于缓冲层300上且对应所述遮光层200的多晶硅半导体层400；
步骤14、在所述多晶硅半导体层400及缓冲层300上成膜并图案化第二氧化硅层501，在所述第二氧化硅层501上成膜并图案化第二氮化硅层502，形成栅极绝缘层500；
步骤15、在所述栅极绝缘层500上沉积并图案化一金属薄膜，形成位于所述栅极绝缘层500上且对应所述多晶硅半导体层400的栅极600；
步骤16、在所述栅极600、及栅极绝缘层500上依次沉积第三氮化硅层701与第三氧化硅层702，形成层间绝缘层700，对所述层间绝缘层700和栅极绝缘层500同时进行图案化处理，形成贯穿所述层间绝缘层700和栅极绝缘层500且暴露出所述多晶硅半导体层400两端的过孔703。
步骤2、在所述层间绝缘层700上沉积第一钼层811，所述第一钼层811的表面平滑。
步骤3、在所述第一钼层811上沉积第一铝层812，所述第一铝层812的表面分布有多个毛刺8120。
步骤4、在所述第一铝层811上沉积第二铝层813，所述第二铝层813的表面也分布有多个毛刺8120，且所述第二铝层813上的毛刺8120的高度大于所述第一铝层812上的毛刺8120的高度，即所述第二铝层813的粗糙度大于所述第一铝层812上的粗糙度。
具体的，所述步骤3和步骤4通过溅射法形成所述第一铝层812与第二铝层813，并通过控制沉积时间的长短或者调整溅射靶材的组分(如微量元素的含量)等措施来控制沉积得到的铝层的粗糙度(毛刺的高度)。
步骤5、在所述第二铝层813上沉积第二钼层814，所述第二钼层814的表面平滑，其包覆于所述第二铝层813的毛刺8120上，使所述第二铝层813的毛刺8120的锋利度降低，对第一钼层811、第一铝层812、第二铝层813、及第二钼层814进行图形化处理，得到位于所述层间绝缘层700上的源极801与漏极802，所述源极801与漏极802的上表面呈现为凹凸不平的粗糙表面。
具体的，所述源极801和漏极802分别通过贯穿层间绝缘层700和栅极绝缘层500的过孔703与多晶硅半导体层400的两端相接触。
步骤6、请参阅图6，在所述源极801、漏极802、及层间绝缘层700上自下而上依次形成平坦层900、公共电极1000、保护层1000、及像素电极1200；
具体的，所述像素电极1200通过贯穿所述保护层1100、公共电极1000、以及平坦层900的过孔901与所述漏极802的上表面相接触。
优选地，所述像素电极1200与公共电极1000的材料均为ITO。
特别的，请参阅图2与图7，在现有技术中像素电极与漏极接触面为光滑的平整面，两者的接触面积等于过孔的底面积，而本发明中通过依次沉积粗糙度不同的第一铝层812与第二铝层813使得漏极802的上表面(即与像素电极的接触面)呈现为凹凸不平的粗糙表面，像素电极1200与漏极802接触面由平面接触变为了曲面接触，大大增加了接触面积，进而减小TFT与像素电极的接触阻抗，提升液晶显示面板的性能。
综上所述，本发明提供了一种TFT阵列基板，该TFT阵列基板中的源极与漏极包括自下而上层叠设置的第一钼层、第一铝层、第二铝层、及第二钼层，所述第一铝层与第二铝层的表面均分布有多个毛刺，且所述第二铝层的毛刺的高度大于所述第一铝层的毛刺的高度，使得所述源极与漏极的上表面呈现为凹凸不平的粗糙表面，相比于现有技术中的光滑的平整面，该凹凸不平的粗糙表面能够增大漏极与像素电极的接触面积，进而减小TFT与像素电极的接触阻抗，提升液晶显示面板的性能。本发明还提供一种TFT阵列基板的制作方法，能够减小TFT与像素电极的接触阻抗，提升液晶显示面板的性能。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

1.一种TFT阵列基板，其特征在于，包括：衬底基板(100)、设于所述衬底基板(100)上的遮光层(200)、覆盖所述遮光层(200)及衬底基板(100)的缓冲层(300)、对应所述遮光层(200)上方设于所述缓冲层(300)上的多晶硅半导体层(400)、覆盖所述多晶硅半导体层(400)及缓冲层(300)的栅极绝缘层(500)、对应所述多晶硅半导体层(400)上方设于所述栅极绝缘层(500)上的栅极(600)、覆盖所述栅极(600)及栅极绝缘层(500)的层间绝缘层(700)、设于所述层间绝缘层(700)上的源极(801)与漏极(802)、覆盖所述源极(801)、漏极(802)、及层间绝缘层(700)的平坦层(900)、设于所述平坦层(900)上的公共电极(1000)、设于所述公共电极(1000)上的保护层(1100)、以及设于所述保护层(1100)上方的像素电极(1200)；
所述源极(801)与漏极(802)均包括自下而上层叠设置的第一钼层(811)、第一铝层(812)、第二铝层(813)、及第二钼层(814)，其中，所述第一钼层(811)的表面平滑，所述第一铝层(812)与第二铝层(813)的表面均分布有多个毛刺(8120)，且所述第二铝层(813)上的毛刺(8120)的高度大于所述第一铝层(812)上的毛刺(8120)的高度，所述第二钼层(814)的表面平滑，其包覆于所述第二铝层(813)的毛刺(8120)上，使所述第二铝层(813)的毛刺(8120)的锋利度降低，最终使所述源极(801)与漏极(802)的上表面呈现为凹凸不平的粗糙表面；
所述像素电极(1200)通过贯穿所述保护层(1100)、公共电极(1000)、以及平坦层(900)的过孔(901)与所述漏极(802)的上表面相接触。
2.如权利要求1所述的TFT阵列基板，其特征在于，所述源极(801)和漏极(802)分别通过贯穿层间绝缘层(700)和栅极绝缘层(500)的过孔(703)与多晶硅半导体层(400)的两端相接触。
3.如权利要求1所述的TFT阵列基板，其特征在于，所述遮光层(200)的材料为钼。
4.如权利要求1所述的TFT阵列基板，其特征在于，所述缓冲层(300)包括自下而上层叠设置的第一氮化硅层(301)和第一氧化硅层(302)；
所述栅极绝缘层(500)包括自下而上层叠设置的第二氧化硅层(501)和第二氮化硅层(502)；
所述层间绝缘层(700)包括自下而上层叠设置的第三氮化硅层(701)和第三氧化硅层(702)；
所述保护层(1100)的材料为氮化硅。
5.如权利要求1所述的TFT阵列基板，其特征在于，所述像素电极(1200)与公共电极(1000)的材料均为ITO。
6.一种TFT阵列基板的制作方法，其特征在于，包括如下步骤：
步骤1、提供一衬底基板(100)，在所述衬底基板(100)自下而上依次形成遮光层(200)、缓冲层(300)、多晶硅半导体层(400)、栅极绝缘层(500)、栅极(600)、及层间绝缘层(700)；
步骤2、在所述层间绝缘层(700)上沉积第一钼层(811)，所述第一钼层(811)的表面平滑；
步骤3、在所述第一钼层(811)上沉积第一铝层(812)，所述第一铝层(812)的表面分布有多个毛刺(8120)；
步骤4、在所述第一铝层(812)上沉积第二铝层(813)，所述第二铝层(813)的表面也分布有多个毛刺(8120)，且所述第二铝层(813)上的毛刺(8120)的高度大于所述第一铝层(812)上的毛刺(8120)的高度；
步骤5、在所述第二铝层(813)上沉积第二钼层(814)，所述第二钼层(814)的表面平滑，其包覆于所述第二铝层(813)的毛刺(8120)上，使所述第二铝层(813)的毛刺(8120)的锋利度降低，对第一钼层(811)、第一铝层(812)、第二铝层(813)、及第二钼层(814)进行图形化处理，得到位于所述层间绝缘层(700)上的源极(801)与漏极(802)，所述源极(801)与漏极(802)的上表面呈现为凹凸不平的粗糙表面；
步骤6、在所述源极(801)、漏极(802)、及层间绝缘层(700)上自下而上依次形成平坦层(900)、公共电极(1000)、保护层(1000)、及像素电极(1200)；
所述像素电极(1200)通过贯穿所述保护层(1100)、公共电极(1000)、以及平坦层(900)的过孔(901)与所述漏极(802)的上表面相接触。
7.如权利要求6所述的TFT阵列基板的制作方法，其特征在于，所述源极(801)和漏极(802)分别通过贯穿层间绝缘层(700)和栅极绝缘层(500)的过孔(703)与多晶硅半导体层(400)的两端相接触。
8.如权利要求6的TFT阵列基板的制作方法，其特征在于，所述遮光层(200)的材料为钼。
9.如权利要求6的TFT阵列基板的制作方法，其特征在于，所述缓冲层(300)包括自下而上层叠设置的第一氮化硅层(301)和第一氧化硅层(302)；
所述栅极绝缘层(500)包括自下而上层叠设置的第二氧化硅层(501)和第二氮化硅层(502)；
所述层间绝缘层(700)包括自下而上层叠设置的第三氮化硅层(701)和第三氧化硅层(702)；
所述保护层(1100)的材料为氮化硅。
10.如权利要求6的TFT阵列基板的制作方法，其特征在于，所述像素电极(1200)与公共电极(1000)的材料均为ITO。
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