WO2017128561A1 - Tft阵列基板及其制作方法 - Google Patents

Tft阵列基板及其制作方法 Download PDF

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Publication number
WO2017128561A1
WO2017128561A1 PCT/CN2016/082413 CN2016082413W WO2017128561A1 WO 2017128561 A1 WO2017128561 A1 WO 2017128561A1 CN 2016082413 W CN2016082413 W CN 2016082413W WO 2017128561 A1 WO2017128561 A1 WO 2017128561A1
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Prior art keywords
layer
aluminum
drain
molybdenum
insulating layer
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PCT/CN2016/082413
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English (en)
French (fr)
Inventor
李安石
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武汉华星光电技术有限公司
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Priority to US15/114,848 priority Critical patent/US9885933B1/en
Publication of WO2017128561A1 publication Critical patent/WO2017128561A1/zh

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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT array substrate and a method of fabricating the same.
  • LCD Liquid Crystal Display
  • advantages such as thin body, power saving, no radiation, etc., such as: LCD TV, mobile phone, personal digital assistant (PDA), digital camera, computer screen or Laptop screens, etc., dominate the field of flat panel display.
  • PDA personal digital assistant
  • liquid crystal displays which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to fill liquid crystal molecules between a Thin Film Transistor Array Substrate (TFT Array Substrate) and a Color Filter (CF), and apply driving on the two substrates.
  • TFT Array Substrate Thin Film Transistor Array Substrate
  • CF Color Filter
  • the TFT array substrate includes: a plurality of gate lines and data lines, a plurality of gate lines and a plurality of data lines perpendicular to each other form a plurality of pixel units, and each of the pixel units is provided with a TFT, a pixel electrode, and a storage capacitor Wait.
  • the TFT includes a gate connected to the gate line, a source connected to the data line, and a drain connected to the pixel electrode.
  • the TFT When the gate line is driven, the TFT is in an on state, and the corresponding data line is fed with a gray scale voltage signal and loaded to the pixel electrode, thereby generating a corresponding electric field between the pixel electrode and the common electrode, in the liquid crystal layer
  • the liquid crystal molecules undergo orientation changes under the action of an electric field to achieve different image display.
  • FIG. 1 is a cross-sectional structural view of a conventional TFT array substrate.
  • the TFT array substrate includes a base substrate 1 and a light shielding layer 2 disposed on the base substrate 1 and covering the light shielding layer 2 .
  • the source 81 and the drain 82 are both formed by sandwiching a layer of aluminum (Al) with two layers of molybdenum (Mo), and the pixel electrode 12 passes through The protective layer 11, the common electrode 10, and the via 91 of the planar layer 9 are in contact with the drain 82.
  • the contact surfaces of the pixel electrode 12 and the drain 82 are smooth and flat.
  • the contact area of the two faces is equal to the area of the bottom surface of the via 91, and the contact resistance is high, which affects the performance of the liquid crystal display panel.
  • An object of the present invention is to provide a TFT array substrate capable of reducing the contact resistance between a TFT and a pixel electrode and improving the performance of the liquid crystal display panel.
  • Another object of the present invention is to provide a method for fabricating a TFT array substrate, which can reduce the contact resistance between the TFT and the pixel electrode and improve the performance of the liquid crystal display panel.
  • the present invention provides a TFT array substrate, comprising: a base substrate, a light shielding layer disposed on the base substrate, a buffer layer covering the light shielding layer and the base substrate, corresponding to the light shielding a polysilicon semiconductor layer disposed on the buffer layer, a gate insulating layer covering the polysilicon semiconductor layer and the buffer layer, a gate corresponding to the gate insulating layer above the polysilicon semiconductor layer, and a cover
  • the source and the drain each include a first molybdenum layer, a first aluminum layer, a second aluminum layer, and a second molybdenum layer, which are stacked from bottom to top, wherein the surface of the first molybdenum layer is smooth, a surface of the first aluminum layer and the second aluminum layer are distributed with a plurality of burrs, and a height of the burrs on the second aluminum layer is greater than a height of the burrs on the first aluminum layer, the second molybdenum layer
  • the surface is smooth, which is coated on the burrs of the second aluminum layer, so that the sharpness of the burrs of the second aluminum layer is lowered, and finally the upper surfaces of the source and the drain are rough and rough. surface;
  • the pixel electrode is in contact with an upper surface of the drain through a via hole penetrating the protective layer, the common electrode, and the flat layer.
  • the source and the drain are respectively in contact with both ends of the polysilicon semiconductor layer through via holes penetrating the interlayer insulating layer and the gate insulating layer.
  • the material of the light shielding layer is molybdenum.
  • the buffer layer includes a first silicon nitride layer and a first silicon oxide layer stacked from bottom to top;
  • the gate insulating layer includes a second silicon oxide layer and a second silicon nitride layer stacked from bottom to top;
  • the interlayer insulating layer includes a third silicon nitride layer and a third silicon oxide layer which are stacked from bottom to top;
  • the material of the protective layer is silicon nitride.
  • the material of the pixel electrode and the common electrode is ITO.
  • the invention also provides a method for fabricating a TFT array substrate, comprising the following steps:
  • Step 1 Providing a base substrate on which a light shielding layer, a buffer layer, a polysilicon semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer insulating layer are sequentially formed from bottom to top;
  • Step 2 depositing a first molybdenum layer on the interlayer insulating layer, the surface of the first molybdenum layer being smooth;
  • Step 3 depositing a first aluminum layer on the first molybdenum layer, the surface of the first aluminum layer is distributed with a plurality of burrs;
  • Step 4 depositing a second aluminum layer on the first aluminum layer, the surface of the second aluminum layer is also distributed with a plurality of burrs, and the height of the burrs on the second aluminum layer is greater than the first aluminum The height of the burr on the layer;
  • Step 5 depositing a second molybdenum layer on the second aluminum layer, the surface of the second molybdenum layer is smooth, and is coated on the burr of the second aluminum layer to reduce the sharpness of the burr, a molybdenum layer, a first aluminum layer, a second aluminum layer, and a second molybdenum layer are patterned to obtain a source and a drain on the interlayer insulating layer, and upper surfaces of the source and the drain Appears as a rough surface that is uneven;
  • Step 6 forming a flat layer, a common electrode, a protective layer, and a pixel electrode from bottom to top on the source, the drain, and the interlayer insulating layer;
  • the pixel electrode is in contact with an upper surface of the drain through a via hole penetrating the protective layer, the common electrode, and the flat layer.
  • the source and the drain are respectively in contact with both ends of the polysilicon semiconductor layer through via holes penetrating the interlayer insulating layer and the gate insulating layer.
  • the material of the light shielding layer is molybdenum.
  • the buffer layer includes a first silicon nitride layer and a first silicon oxide layer stacked from bottom to top;
  • the gate insulating layer includes a second silicon oxide layer and a second silicon nitride layer stacked from bottom to top;
  • the interlayer insulating layer includes a third silicon nitride layer and a third silicon oxide layer which are stacked from bottom to top;
  • the material of the protective layer is silicon nitride.
  • the material of the pixel electrode and the common electrode is ITO.
  • the present invention also provides a TFT array substrate, comprising: a base substrate, a light shielding layer disposed on the base substrate, a buffer layer covering the light shielding layer and the base substrate, and corresponding to the light shielding layer a polysilicon semiconductor layer on the buffer layer, a gate insulating layer covering the polysilicon semiconductor layer and the buffer layer, a gate corresponding to the gate insulating layer above the polysilicon semiconductor layer, covering the gate and
  • An interlayer insulating layer of the gate insulating layer is disposed on the interlayer insulating layer a source and a drain, a flat layer covering the source, the drain, and the interlayer insulating layer, a common electrode provided on the flat layer, a protective layer disposed on the common electrode, and a a pixel electrode above the protective layer;
  • the source and the drain each include a first molybdenum layer, a first aluminum layer, a second aluminum layer, and a second molybdenum layer, which are stacked from bottom to top, wherein the surface of the first molybdenum layer is smooth, a surface of the first aluminum layer and the second aluminum layer are distributed with a plurality of burrs, and a height of the burrs on the second aluminum layer is greater than a height of the burrs on the first aluminum layer, the second molybdenum layer
  • the surface is smooth, which is coated on the burrs of the second aluminum layer, so that the sharpness of the burrs of the second aluminum layer is lowered, and finally the upper surfaces of the source and the drain are rough and rough. surface;
  • the pixel electrode is in contact with an upper surface of the drain through a via hole penetrating the protective layer, the common electrode, and the flat layer;
  • source and the drain are respectively in contact with both ends of the polysilicon semiconductor layer through via holes penetrating the interlayer insulating layer and the gate insulating layer;
  • the material of the light shielding layer is molybdenum.
  • the present invention provides a TFT array substrate, wherein the source and the drain in the TFT array substrate comprise a first molybdenum layer, a first aluminum layer, a second aluminum layer, which are stacked from bottom to top, And a second molybdenum layer, the surface of the first aluminum layer and the second aluminum layer are distributed with a plurality of burrs, and the height of the burrs on the second aluminum layer is greater than the height of the burrs on the first aluminum layer
  • the upper surface of the source and the drain are rendered as a rough surface having irregularities, and the rough surface of the uneven surface can increase the contact between the drain and the pixel electrode compared to the smooth flat surface in the prior art.
  • the area reduces the contact resistance between the TFT and the pixel electrode, and improves the performance of the liquid crystal display panel.
  • the invention also provides a method for fabricating a TFT array substrate, which can reduce the contact resistance between the TFT and the pixel electrode and improve the performance of the liquid crystal display panel.
  • FIG. 1 is a schematic cross-sectional structural view of a conventional TFT array substrate
  • FIG. 2 is a schematic view showing a contact surface of a drain electrode and a pixel electrode of the TFT array substrate shown in FIG. 1;
  • FIG. 3 is a schematic flow chart of a method of fabricating a TFT array substrate of the present invention.
  • FIG. 4 is a schematic view showing steps 1 to 5 of the method for fabricating a TFT array substrate of the present invention
  • step 5 is a source and a drain obtained in step 5 of the method for fabricating a TFT array substrate of the present invention. Schematic diagram of the structure;
  • FIG. 6 is a schematic view showing a step 6 of a method for fabricating a TFT array substrate of the present invention and a schematic cross-sectional structure of the TFT array substrate of the present invention;
  • Fig. 7 is a schematic view showing a contact surface of a drain electrode and a pixel electrode of a TFT array substrate of the present invention.
  • the present invention firstly provides a TFT array substrate, comprising: a substrate substrate 100 , a light shielding layer 200 disposed on the substrate substrate 100 , covering the light shielding layer 200 and the substrate substrate 100 .
  • a buffer layer 300 a buffer layer 300, a polysilicon semiconductor layer 400 disposed on the buffer layer 300 above the light shielding layer 200, a gate insulating layer 500 covering the polysilicon semiconductor layer 400 and the buffer layer 300, and a corresponding polysilicon semiconductor layer a gate 600 disposed on the gate insulating layer 500, an interlayer insulating layer 700 covering the gate 600 and the gate insulating layer 500, and a source 801 disposed on the interlayer insulating layer 700 And a drain 802, a flat layer 900 covering the source 801, the drain 802, and the interlayer insulating layer 700, a common electrode 1000 provided on the flat layer 900, and protection provided on the common electrode 1000 a layer 1100, and a pixel electrode 1200 disposed above the protective layer 1100;
  • the source 801 and the drain 802 each include a first molybdenum layer 811, a first aluminum layer 812, a second aluminum layer 813, and a second molybdenum layer 814 stacked from bottom to top, wherein the first molybdenum
  • the surface of the layer 811 is smooth, and the surface of the first aluminum layer 812 and the second aluminum layer 813 are distributed with a plurality of burrs 8120, and the height of the burrs 8120 on the second aluminum layer 813 is greater than the first aluminum layer.
  • the height of the burr 8120 on the 812, the surface of the second molybdenum layer 814 is smooth, and it is coated on the burr 8120 of the second aluminum layer 813, so that the sharpness of the burr 8120 of the second aluminum layer 813 is lowered.
  • the upper surface of the source 801 and the drain 802 are rendered as a rough surface;
  • the pixel electrode 1200 is in contact with the upper surface of the drain 802 through a via 901 penetrating through the protective layer 1100, the common electrode 1000, and the planarization layer 900.
  • the present invention can ensure that the upper surface of the source 801 and the drain 802 has sufficient roughness by providing the second aluminum layer 813 having a higher roughness, and the roughness is set under the second aluminum layer 813.
  • the low first aluminum layer 812 ensures that the flat portion under the rough surface of the source 801 and the drain 802 has a sufficient thickness.
  • the source electrode 801 and the drain electrode 802 are in contact with both ends of the polysilicon semiconductor layer 400 through via holes 703 penetrating through the interlayer insulating layer 700 and the gate insulating layer 500, respectively.
  • the pixel electrode and the drain contact surface are light.
  • the sliding flat surface, the contact area of the two is equal to the bottom area of the via hole, and in the present invention, the first aluminum layer 812 and the second aluminum layer 813 having different roughness are laminated by lamination so that the upper surface of the drain 802 (ie, the pixel)
  • the contact surface of the electrode appears as a rough surface with unevenness, and the contact surface of the pixel electrode 1200 and the drain 802 is changed into a curved surface contact by the planar contact, which greatly increases the contact area, thereby reducing the contact resistance between the TFT and the pixel electrode, and improving the liquid crystal display. Panel performance.
  • the material of the light shielding layer 200 is molybdenum.
  • the buffer layer 300 includes a first silicon nitride layer 301 and a first silicon oxide layer 302 stacked from bottom to top;
  • the gate insulating layer 500 includes a second silicon dioxide layered from bottom to top.
  • the interlayer insulating layer 700 includes a third silicon nitride layer 701 and a third silicon oxide layer 702 stacked from bottom to top;
  • the material of the protective layer 1100 is silicon nitride.
  • the material of the pixel electrode 1200 and the common electrode 1000 are both ITO.
  • the present invention further provides a method for fabricating a TFT array substrate, including the following steps:
  • Step 1 please refer to FIG. 4, a substrate substrate 100 is provided, and a light shielding layer 200, a buffer layer 300, a polysilicon semiconductor layer 400, a gate insulating layer 500, and a gate electrode 600 are sequentially formed on the substrate substrate 100 from bottom to top. And an interlayer insulating layer 700.
  • the step 1 specifically includes:
  • Step 11 depositing a metal film on the base substrate 100, patterning the metal film to form the light shielding layer 200, preferably, the material of the metal film is molybdenum;
  • Step 12 forming a first silicon nitride layer 301 on the light shielding layer 200 and the substrate 100, forming a first silicon oxide layer 302 on the first silicon nitride layer 301, forming a buffer layer 300;
  • Step 13 Deposit an amorphous silicon layer on the buffer layer 300, crystallize the amorphous silicon layer to form a polysilicon layer, and pattern and ion doping the polysilicon layer to form a buffer.
  • Step 14 Form and pattern a second silicon oxide layer 501 on the polysilicon semiconductor layer 400 and the buffer layer 300, and form a second silicon nitride layer 502 on the second silicon oxide layer 501. Forming a gate insulating layer 500;
  • Step 15 depositing and patterning a metal film on the gate insulating layer 500, forming a gate 600 on the gate insulating layer 500 corresponding to the polysilicon semiconductor layer 400;
  • Step 16 sequentially depositing a third silicon nitride layer 701 and a third silicon oxide layer 702 on the gate electrode 600 and the gate insulating layer 500 to form an interlayer insulating layer 700, and the interlayer insulating layer 700 and The gate insulating layer 500 is simultaneously patterned to form via holes 703 penetrating the interlayer insulating layer 700 and the gate insulating layer 500 and exposing both ends of the polysilicon semiconductor layer 400.
  • Step 2 depositing a first molybdenum layer 811 on the interlayer insulating layer 700, the surface of the first molybdenum layer 811 being smooth.
  • Step 3 depositing a first aluminum layer 812 on the first molybdenum layer 811, and a surface of the first aluminum layer 812 is distributed with a plurality of burrs 8120.
  • Step 4 depositing a second aluminum layer 813 on the first aluminum layer 811, the surface of the second aluminum layer 813 is also distributed with a plurality of burrs 8120, and the height of the burrs 8120 on the second aluminum layer 813 The height of the burr 8120 on the first aluminum layer 812 is greater than the roughness of the second aluminum layer 812.
  • the steps 3 and 4 form the first aluminum layer 812 and the second aluminum layer 813 by a sputtering method, and adjust the composition of the sputtering target by adjusting the length of the deposition time (such as trace elements). (Measurement) and other measures to control the roughness of the deposited aluminum layer (the height of the burr).
  • Step 5 depositing a second molybdenum layer 814 on the second aluminum layer 813, the surface of the second molybdenum layer 814 is smooth, and is coated on the burr 8120 of the second aluminum layer 813, so that the first The sharpness of the burr 8120 of the two-aluminum layer 813 is reduced, and the first molybdenum layer 811, the first aluminum layer 812, the second aluminum layer 813, and the second molybdenum layer 814 are patterned to obtain the interlayer insulating layer.
  • the source 801 and the drain 802 on the 700, the upper surfaces of the source 801 and the drain 802 appear as rough surfaces.
  • the source electrode 801 and the drain electrode 802 are in contact with both ends of the polysilicon semiconductor layer 400 through via holes 703 penetrating through the interlayer insulating layer 700 and the gate insulating layer 500, respectively.
  • Step 6 please refer to FIG. 6, on the source 801, the drain 802, and the interlayer insulating layer 700, forming a flat layer 900, a common electrode 1000, a protective layer 1000, and a pixel electrode 1200 from bottom to top;
  • the pixel electrode 1200 is in contact with the upper surface of the drain 802 through the via 901 penetrating through the protective layer 1100, the common electrode 1000, and the planarization layer 900.
  • the material of the pixel electrode 1200 and the common electrode 1000 are both ITO.
  • the pixel electrode and the drain contact surface are smooth flat surfaces, and the contact area of the two is equal to the bottom area of the via hole, and in the present invention, the roughness is sequentially deposited.
  • the different first aluminum layer 812 and the second aluminum layer 813 make the upper surface of the drain 802 (ie, the contact surface with the pixel electrode) appear as a rough surface, and the contact surface of the pixel electrode 1200 and the drain 802 is changed by planar contact.
  • the contact area is greatly increased, thereby reducing the contact resistance between the TFT and the pixel electrode, and improving the performance of the liquid crystal display panel.
  • the present invention provides a TFT array substrate
  • the source and the drain in the TFT array substrate include a first molybdenum layer, a first aluminum layer, a second aluminum layer, and a second molybdenum layer, a surface of the first aluminum layer and the second aluminum layer are distributed with a plurality of burrs, and the second The height of the burr of the aluminum layer is greater than the height of the burrs of the first aluminum layer, such that the upper surfaces of the source and the drain appear as rough surfaces, compared to the smooth flat surface of the prior art.
  • the uneven surface can increase the contact area between the drain and the pixel electrode, thereby reducing the contact resistance between the TFT and the pixel electrode, and improving the performance of the liquid crystal display panel.
  • the invention also provides a method for fabricating a TFT array substrate, which can reduce the contact resistance between the TFT and the pixel electrode and improve the performance of the liquid crystal display panel.

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Abstract

一种TFT阵列基板，该TFT阵列基板中源极(801)与漏极(802)均包括自下而上层叠设置的第一钼层(811)、第一铝层(812)、第二铝层(813)及第二钼层(814)，其中，所述第一钼层(811)的表面平滑，所述第一铝层(812)与第二铝层(813)的表面均分布有多个毛刺(8120)，且所述第二铝层(813)上的毛刺(8120)的高度大于所述第一铝层(812)上的毛刺(8120)的高度，所述第二钼层(814)的表面平滑，其包覆于所述第二铝层(813)的毛刺(8120)上，使所述第二铝层(813)的毛刺(8120)的锋利度降低，最终使所述源极(801)与漏极(802)的上表面呈现为凹凸不平的粗糙表面。该凹凸不平的粗糙表面能够增大漏极(802)与像素电极(1200)的接触面积，进而减小TFT与像素电极(1200)的接触阻抗，提升液晶显示面板的性能。还提供了一种TFT阵列基板的制作方法。

Description

TFT阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板及其制作方法。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片基板(Color Filter，CF)之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
TFT阵列基板包括：多条栅极线和数据线，相互垂直的多条栅极线和多条数据线形成了多个像素单元，且每个像素单元内均设置有TFT、像素电极及存储电容等。TFT包括一栅极连接至栅极线，源极连接至数据线，漏极连接至像素电极。当栅极线被驱动时，TFT处于导通状态，对应的数据线送入灰阶电压信号并将其加载至像素电极，从而使得像素电极与公共电极之间产生相应的电场，液晶层中的液晶分子则在电场的作用下发生取向变化，以实现不同的图像显示。
请参阅图1，图1为现有的TFT阵列基板的剖面结构示意图，该TFT阵列基板包括：衬底基板1、设于所述衬底基板1上的遮光层2、覆盖所述遮光层2及衬底基板1的缓冲层3、对应所述遮光层2上方设于所述缓冲层3上的多晶硅半导体层4、覆盖所述多晶硅半导体层4及缓冲层3的栅极绝缘层5、对应所述多晶硅半导体层4上方设于所述栅极绝缘层5上的栅极6、覆盖所述栅极6及栅极绝缘层5的层间绝缘层7、设于所述层间绝缘层7上的源极81与漏极82、覆盖所述源极81、漏极82、及层间绝缘层7的平坦层9、设于所述平坦层9上的公共电极10、设于所述公共电极10上的保护层11、以及设于所述保护层11上方的像素电极12。所述源极81与漏极82均采用两层钼(Mo)夹设一层铝(Al)的结构，所述像素电极12通过贯穿 所述保护层11、公共电极10、及平坦层9的过孔91与所述漏极82相接触，如图2所示，所述像素电极12与漏极82的接触面均为光滑的平整面，两者接触面积等于过孔91的底面面积，接触阻抗较高，影响液晶显示面板的性能。
发明内容
本发明的目的在于提供一种TFT阵列基板，能够减小TFT与像素电极的接触阻抗，提升液晶显示面板性能。
本发明的目的还在于提供一种TFT阵列基板的制作方法，能够减小TFT与像素电极的接触阻抗，提升液晶显示面板性能。
为实现上述目的，本发明提供了一种TFT阵列基板，包括：衬底基板、设于所述衬底基板上的遮光层、覆盖所述遮光层及衬底基板的缓冲层、对应所述遮光层上方设于所述缓冲层上的多晶硅半导体层、覆盖所述多晶硅半导体层及缓冲层的栅极绝缘层、对应所述多晶硅半导体层上方设于所述栅极绝缘层上的栅极、覆盖所述栅极及栅极绝缘层的层间绝缘层、设于所述层间绝缘层上的源极与漏极、覆盖所述源极、漏极、及层间绝缘层的平坦层、设于所述平坦层上的公共电极、设于所述公共电极上的保护层、以及设于所述保护层上方的像素电极；
所述源极与漏极均包括自下而上层叠设置的第一钼层、第一铝层、第二铝层、及第二钼层，其中，所述第一钼层的表面平滑，所述第一铝层与第二铝层的表面均分布有多个毛刺，且所述第二铝层上的毛刺的高度大于所述第一铝层上的毛刺的高度，所述第二钼层的表面平滑，其包覆于所述第二铝层的毛刺上，使所述第二铝层的毛刺的锋利度降低，最终使所述源极与漏极的上表面呈现为凹凸不平的粗糙表面；
所述像素电极通过贯穿所述保护层、公共电极、以及平坦层的过孔与所述漏极的上表面相接触。
所述源极和漏极分别通过贯穿层间绝缘层和栅极绝缘层的过孔与多晶硅半导体层的两端相接触。
所述遮光层的材料为钼。
所述缓冲层包括自下而上层叠设置的第一氮化硅层和第一氧化硅层；
所述栅极绝缘层包括自下而上层叠设置的第二氧化硅层和第二氮化硅层；
所述层间绝缘层包括自下而上层叠设置的第三氮化硅层和第三氧化硅层；
所述保护层的材料为氮化硅。
所述像素电极与公共电极的材料均为ITO。
本发明还提供一种TFT阵列基板的制作方法，包括如下步骤：
步骤1、提供一衬底基板，在所述衬底基板自下而上依次形成遮光层、缓冲层、多晶硅半导体层、栅极绝缘层、栅极、及层间绝缘层；
步骤2、在所述层间绝缘层上沉积第一钼层，所述第一钼层的表面平滑；
步骤3、在所述第一钼层上沉积第一铝层，所述第一铝层的表面分布有多个毛刺；
步骤4、在所述第一铝层上沉积第二铝层，所述第二铝层的表面也分布有多个毛刺，且所述第二铝层上的毛刺的高度大于所述第一铝层上的毛刺的高度；
步骤5、在所述第二铝层上沉积第二钼层，所述第二钼层的表面平滑，其包覆于所述第二铝层的毛刺上，使毛刺的锋利度降低，对第一钼层、第一铝层、第二铝层、及第二钼层进行图形化处理，得到位于所述层间绝缘层上的源极与漏极，所述源极与漏极的上表面呈现为凹凸不平的粗糙表面；
步骤6、在所述源极、漏极、及层间绝缘层上自下而上依次形成平坦层、公共电极、保护层、及像素电极；
所述像素电极通过贯穿所述保护层、公共电极、以及平坦层的过孔与所述漏极的上表面相接触。
所述源极和漏极分别通过贯穿层间绝缘层和栅极绝缘层的过孔与多晶硅半导体层的两端相接触。
所述遮光层的材料为钼。
所述缓冲层包括自下而上层叠设置的第一氮化硅层和第一氧化硅层；
所述栅极绝缘层包括自下而上层叠设置的第二氧化硅层和第二氮化硅层；
所述层间绝缘层包括自下而上层叠设置的第三氮化硅层和第三氧化硅层；
所述保护层的材料为氮化硅。
所述像素电极与公共电极的材料均为ITO。
本发明还提供一种TFT阵列基板，包括：衬底基板、设于所述衬底基板上的遮光层、覆盖所述遮光层及衬底基板的缓冲层、对应所述遮光层上方设于所述缓冲层上的多晶硅半导体层、覆盖所述多晶硅半导体层及缓冲层的栅极绝缘层、对应所述多晶硅半导体层上方设于所述栅极绝缘层上的栅极、覆盖所述栅极及栅极绝缘层的层间绝缘层、设于所述层间绝缘层上 的源极与漏极、覆盖所述源极、漏极、及层间绝缘层的平坦层、设于所述平坦层上的公共电极、设于所述公共电极上的保护层、以及设于所述保护层上方的像素电极；
所述源极与漏极均包括自下而上层叠设置的第一钼层、第一铝层、第二铝层、及第二钼层，其中，所述第一钼层的表面平滑，所述第一铝层与第二铝层的表面均分布有多个毛刺，且所述第二铝层上的毛刺的高度大于所述第一铝层上的毛刺的高度，所述第二钼层的表面平滑，其包覆于所述第二铝层的毛刺上，使所述第二铝层的毛刺的锋利度降低，最终使所述源极与漏极的上表面呈现为凹凸不平的粗糙表面；
所述像素电极通过贯穿所述保护层、公共电极、以及平坦层的过孔与所述漏极的上表面相接触；
其中，所述源极和漏极分别通过贯穿层间绝缘层和栅极绝缘层的过孔与多晶硅半导体层的两端相接触；
其中，所述遮光层的材料为钼。
本发明的有益效果：本发明提供了一种TFT阵列基板，该TFT阵列基板中的源极与漏极包括自下而上层叠设置的第一钼层、第一铝层、第二铝层、及第二钼层，所述第一铝层与第二铝层的表面均分布有多个毛刺，且所述第二铝层上的毛刺的高度大于所述第一铝层上的毛刺的高度，使得所述源极与漏极的上表面呈现为有凹凸不平的粗糙表面，相比于现有技术中的光滑的平整面，该凹凸不平的粗糙表面能够增大漏极与像素电极的接触面积，进而减小TFT与像素电极的接触阻抗，提升液晶显示面板的性能。本发明还提供一种TFT阵列基板的制作方法，能够减小TFT与像素电极的接触阻抗，提升液晶显示面板的性能。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的TFT阵列基板的剖面结构示意图；
图2为图1所示TFT阵列基板的漏极与像素电极的接触面的示意图；
图3为本发明的TFT阵列基板的制作方法的示意流程图；
图4为本发明的TFT阵列基板的制作方法的步骤1-步骤5的示意图；
图5为本发明的TFT阵列基板的制作方法的步骤5制得的源极与漏极 的结构示意图；
图6为本发明的TFT阵列基板的制作方法的步骤6的示意图暨本发明的TFT阵列基板的剖面结构示意图；
图7为本发明的TFT阵列基板的漏极与像素电极的接触面的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图6和图5，本发明首先提供一种TFT阵列基板，包括：衬底基板100、设于所述衬底基板100上的遮光层200、覆盖所述遮光层200及衬底基板100的缓冲层300、对应所述遮光层200上方设于所述缓冲层300上的多晶硅半导体层400、覆盖所述多晶硅半导体层400及缓冲层300的栅极绝缘层500、对应所述多晶硅半导体层400上方设于所述栅极绝缘层500上的栅极600、覆盖所述栅极600及栅极绝缘层500的层间绝缘层700、设于所述层间绝缘层700上的源极801与漏极802、覆盖所述源极801、漏极802、及层间绝缘层700的平坦层900、设于所述平坦层900上的公共电极1000、设于所述公共电极1000上的保护层1100、以及设于所述保护层1100上方的像素电极1200；
所述源极801与漏极802均包括自下而上层叠设置的第一钼层811、第一铝层812、第二铝层813、及第二钼层814，其中，所述第一钼层811的表面平滑，所述第一铝层812与第二铝层813的表面均分布有多个毛刺8120，且所述第二铝层813上的毛刺8120的高度大于所述第一铝层812上的毛刺8120的高度，所述第二钼层814的表面平滑，其包覆于所述第二铝层813的毛刺8120上，使所述第二铝层813的毛刺8120的锋利度降低，最终使所述源极801与漏极802的上表面呈现为凹凸不平的粗糙表面；
所述像素电极1200通过贯穿所述保护层1100、公共电极1000、以及平坦层900的过孔901与所述漏极802的上表面相接触。
具体的，本发明通过设置粗糙度较高的第二铝层813，可保证所述源极801与漏极802的上表面具有足够的粗糙度，同时在第二铝层813下方设置粗糙度较低的第一铝层812，可保证所述源极801与漏极802的粗糙面下方的平整部分具有足够的厚度。
所述源极801和漏极802分别通过贯穿层间绝缘层700和栅极绝缘层500的过孔703与多晶硅半导体层400的两端相接触。
特别的，请参阅图2与图7，在现有技术中像素电极与漏极接触面为光 滑的平整面，两者的接触面积等于过孔的底面积，而本发明中通过层叠设置粗糙度不同的第一铝层812与第二铝层813使得漏极802的上表面(即与像素电极的接触面)呈现为凹凸不平的粗糙表面，像素电极1200与漏极802接触面由平面接触变为了曲面接触，大大增加了接触面积，进而减小TFT与像素电极的接触阻抗，提升液晶显示面板的性能。
优选地，所述遮光层200的材料为钼。
优选地，所述缓冲层300包括自下而上层叠设置的第一氮化硅层301和第一氧化硅层302；所述栅极绝缘层500包括自下而上层叠设置的第二氧化硅层501和第二氮化硅层502；所述层间绝缘层700包括自下而上层叠设置的第三氮化硅层701和第三氧化硅层702；
优选地，所述保护层1100的材料为氮化硅。
优选地，所述像素电极1200与公共电极1000的材料均为ITO。
请参阅图3并结合图4至图7，本发明还提供一种TFT阵列基板的制作方法，包括如下步骤：
步骤1、请参阅图4，提供一衬底基板100，在所述衬底基板100自下而上依次形成遮光层200、缓冲层300、多晶硅半导体层400、栅极绝缘层500、栅极600、及层间绝缘层700。
具体的，该步骤1具体包括：
步骤11、在衬底基板100上沉积一金属薄膜，图案化该金属薄膜形成遮光层200，优选的，所述金属薄膜的材料为钼；
步骤12、在所述遮光层200及衬底基板100上成膜第一氮化硅层301，在所述第一氮化硅层301上成膜第一氧化硅层302，形成缓冲层300；
步骤13、在所述缓冲层300上沉积一非晶硅层，对所述非晶硅层进行晶化处理形成多晶硅层，在对所述多晶硅层进行图案化和离子掺杂制程，形成位于缓冲层300上且对应所述遮光层200的多晶硅半导体层400；
步骤14、在所述多晶硅半导体层400及缓冲层300上成膜并图案化第二氧化硅层501，在所述第二氧化硅层501上成膜并图案化第二氮化硅层502，形成栅极绝缘层500；
步骤15、在所述栅极绝缘层500上沉积并图案化一金属薄膜，形成位于所述栅极绝缘层500上且对应所述多晶硅半导体层400的栅极600；
步骤16、在所述栅极600、及栅极绝缘层500上依次沉积第三氮化硅层701与第三氧化硅层702，形成层间绝缘层700，对所述层间绝缘层700和栅极绝缘层500同时进行图案化处理，形成贯穿所述层间绝缘层700和栅极绝缘层500且暴露出所述多晶硅半导体层400两端的过孔703。
步骤2、在所述层间绝缘层700上沉积第一钼层811，所述第一钼层811的表面平滑。
步骤3、在所述第一钼层811上沉积第一铝层812，所述第一铝层812的表面分布有多个毛刺8120。
步骤4、在所述第一铝层811上沉积第二铝层813，所述第二铝层813的表面也分布有多个毛刺8120，且所述第二铝层813上的毛刺8120的高度大于所述第一铝层812上的毛刺8120的高度，即所述第二铝层813的粗糙度大于所述第一铝层812上的粗糙度。
具体的，所述步骤3和步骤4通过溅射法形成所述第一铝层812与第二铝层813，并通过控制沉积时间的长短或者调整溅射靶材的组分(如微量元素的含量)等措施来控制沉积得到的铝层的粗糙度(毛刺的高度)。
步骤5、在所述第二铝层813上沉积第二钼层814，所述第二钼层814的表面平滑，其包覆于所述第二铝层813的毛刺8120上，使所述第二铝层813的毛刺8120的锋利度降低，对第一钼层811、第一铝层812、第二铝层813、及第二钼层814进行图形化处理，得到位于所述层间绝缘层700上的源极801与漏极802，所述源极801与漏极802的上表面呈现为凹凸不平的粗糙表面。
具体的，所述源极801和漏极802分别通过贯穿层间绝缘层700和栅极绝缘层500的过孔703与多晶硅半导体层400的两端相接触。
步骤6、请参阅图6，在所述源极801、漏极802、及层间绝缘层700上自下而上依次形成平坦层900、公共电极1000、保护层1000、及像素电极1200；
具体的，所述像素电极1200通过贯穿所述保护层1100、公共电极1000、以及平坦层900的过孔901与所述漏极802的上表面相接触。
优选地，所述像素电极1200与公共电极1000的材料均为ITO。
特别的，请参阅图2与图7，在现有技术中像素电极与漏极接触面为光滑的平整面，两者的接触面积等于过孔的底面积，而本发明中通过依次沉积粗糙度不同的第一铝层812与第二铝层813使得漏极802的上表面(即与像素电极的接触面)呈现为凹凸不平的粗糙表面，像素电极1200与漏极802接触面由平面接触变为了曲面接触，大大增加了接触面积，进而减小TFT与像素电极的接触阻抗，提升液晶显示面板的性能。
综上所述，本发明提供了一种TFT阵列基板，该TFT阵列基板中的源极与漏极包括自下而上层叠设置的第一钼层、第一铝层、第二铝层、及第二钼层，所述第一铝层与第二铝层的表面均分布有多个毛刺，且所述第二 铝层的毛刺的高度大于所述第一铝层的毛刺的高度，使得所述源极与漏极的上表面呈现为凹凸不平的粗糙表面，相比于现有技术中的光滑的平整面，该凹凸不平的粗糙表面能够增大漏极与像素电极的接触面积，进而减小TFT与像素电极的接触阻抗，提升液晶显示面板的性能。本发明还提供一种TFT阵列基板的制作方法，能够减小TFT与像素电极的接触阻抗，提升液晶显示面板的性能。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (13)

  1. 一种TFT阵列基板，包括：衬底基板、设于所述衬底基板上的遮光层、覆盖所述遮光层及衬底基板的缓冲层、对应所述遮光层上方设于所述缓冲层上的多晶硅半导体层、覆盖所述多晶硅半导体层及缓冲层的栅极绝缘层、对应所述多晶硅半导体层上方设于所述栅极绝缘层上的栅极、覆盖所述栅极及栅极绝缘层的层间绝缘层、设于所述层间绝缘层上的源极与漏极、覆盖所述源极、漏极、及层间绝缘层的平坦层、设于所述平坦层上的公共电极、设于所述公共电极上的保护层、以及设于所述保护层上方的像素电极；
    所述源极与漏极均包括自下而上层叠设置的第一钼层、第一铝层、第二铝层、及第二钼层，其中，所述第一钼层的表面平滑，所述第一铝层与第二铝层的表面均分布有多个毛刺，且所述第二铝层上的毛刺的高度大于所述第一铝层上的毛刺的高度，所述第二钼层的表面平滑，其包覆于所述第二铝层的毛刺上，使所述第二铝层的毛刺的锋利度降低，最终使所述源极与漏极的上表面呈现为凹凸不平的粗糙表面；
    所述像素电极通过贯穿所述保护层、公共电极、以及平坦层的过孔与所述漏极的上表面相接触。
  2. 如权利要求1所述的TFT阵列基板，其中，所述源极和漏极分别通过贯穿层间绝缘层和栅极绝缘层的过孔与多晶硅半导体层的两端相接触。
  3. 如权利要求1所述的TFT阵列基板，其中，所述遮光层的材料为钼。
  4. 如权利要求1所述的TFT阵列基板，其中，所述缓冲层包括自下而上层叠设置的第一氮化硅层和第一氧化硅层；
    所述栅极绝缘层包括自下而上层叠设置的第二氧化硅层和第二氮化硅层；
    所述层间绝缘层包括自下而上层叠设置的第三氮化硅层和第三氧化硅层；
    所述保护层的材料为氮化硅。
  5. 如权利要求1所述的TFT阵列基板，其中，所述像素电极与公共电极的材料均为ITO。
  6. 一种TFT阵列基板的制作方法，包括如下步骤：
    步骤1、提供一衬底基板，在所述衬底基板自下而上依次形成遮光层、缓冲层、多晶硅半导体层、栅极绝缘层、栅极、及层间绝缘层；
    步骤2、在所述层间绝缘层上沉积第一钼层，所述第一钼层的表面平滑；
    步骤3、在所述第一钼层上沉积第一铝层，所述第一铝层的表面分布有多个毛刺；
    步骤4、在所述第一铝层上沉积第二铝层，所述第二铝层的表面也分布有多个毛刺，且所述第二铝层上的毛刺的高度大于所述第一铝层上的毛刺的高度；
    步骤5、在所述第二铝层上沉积第二钼层，所述第二钼层的表面平滑，其包覆于所述第二铝层的毛刺上，使所述第二铝层的毛刺的锋利度降低，对第一钼层、第一铝层、第二铝层、及第二钼层进行图形化处理，得到位于所述层间绝缘层上的源极与漏极，所述源极与漏极的上表面呈现为凹凸不平的粗糙表面；
    步骤6、在所述源极、漏极、及层间绝缘层上自下而上依次形成平坦层、公共电极、保护层、及像素电极；
    所述像素电极通过贯穿所述保护层、公共电极、以及平坦层的过孔与所述漏极的上表面相接触。
  7. 如权利要求6所述的TFT阵列基板的制作方法，其中，所述源极和漏极分别通过贯穿层间绝缘层和栅极绝缘层的过孔与多晶硅半导体层的两端相接触。
  8. 如权利要求6的TFT阵列基板的制作方法，其中，所述遮光层的材料为钼。
  9. 如权利要求6的TFT阵列基板的制作方法，其中，所述缓冲层包括自下而上层叠设置的第一氮化硅层和第一氧化硅层；
    所述栅极绝缘层包括自下而上层叠设置的第二氧化硅层和第二氮化硅层；
    所述层间绝缘层包括自下而上层叠设置的第三氮化硅层和第三氧化硅层；
    所述保护层的材料为氮化硅。
  10. 如权利要求6的TFT阵列基板的制作方法，其中，所述像素电极与公共电极的材料均为ITO。
  11. 一种TFT阵列基板，包括：衬底基板、设于所述衬底基板上的遮光层、覆盖所述遮光层及衬底基板的缓冲层、对应所述遮光层上方设于所述缓冲层上的多晶硅半导体层、覆盖所述多晶硅半导体层及缓冲层的栅极绝缘层、对应所述多晶硅半导体层上方设于所述栅极绝缘层上的栅极、覆盖所述栅极及栅极绝缘层的层间绝缘层、设于所述层间绝缘层上的源极与 漏极、覆盖所述源极、漏极、及层间绝缘层的平坦层、设于所述平坦层上的公共电极、设于所述公共电极上的保护层、以及设于所述保护层上方的像素电极；
    所述源极与漏极均包括自下而上层叠设置的第一钼层、第一铝层、第二铝层、及第二钼层，其中，所述第一钼层的表面平滑，所述第一铝层与第二铝层的表面均分布有多个毛刺，且所述第二铝层上的毛刺的高度大于所述第一铝层上的毛刺的高度，所述第二钼层的表面平滑，其包覆于所述第二铝层的毛刺上，使所述第二铝层的毛刺的锋利度降低，最终使所述源极与漏极的上表面呈现为凹凸不平的粗糙表面；
    所述像素电极通过贯穿所述保护层、公共电极、以及平坦层的过孔与所述漏极的上表面相接触；
    其中，所述源极和漏极分别通过贯穿层间绝缘层和栅极绝缘层的过孔与多晶硅半导体层的两端相接触；
    其中，所述遮光层的材料为钼。
  12. 如权利要求11所述的TFT阵列基板，其中，所述缓冲层包括自下而上层叠设置的第一氮化硅层和第一氧化硅层；
    所述栅极绝缘层包括自下而上层叠设置的第二氧化硅层和第二氮化硅层；
    所述层间绝缘层包括自下而上层叠设置的第三氮化硅层和第三氧化硅层；
    所述保护层的材料为氮化硅。
  13. 如权利要求11所述的TFT阵列基板，其中，所述像素电极与公共电极的材料均为ITO。
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