WO2017049842A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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WO2017049842A1
WO2017049842A1 PCT/CN2016/073627 CN2016073627W WO2017049842A1 WO 2017049842 A1 WO2017049842 A1 WO 2017049842A1 CN 2016073627 W CN2016073627 W CN 2016073627W WO 2017049842 A1 WO2017049842 A1 WO 2017049842A1
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Prior art keywords
common electrode
transparent common
array substrate
electrode
pixel
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PCT/CN2016/073627
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English (en)
French (fr)
Inventor
陈传宝
马俊才
Original Assignee
京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/519,370 priority Critical patent/US10466557B2/en
Priority to EP16847734.7A priority patent/EP3355110B1/en
Publication of WO2017049842A1 publication Critical patent/WO2017049842A1/zh

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • At least one embodiment of the present invention is directed to an array substrate, a method of fabricating the same, and a display device.
  • the pixel electrode and the common electrode are both disposed on the array substrate.
  • the pixel electrode may have a plate-like structure
  • the common electrode may have a slit-like structure
  • the pixel electrode is disposed on the substrate of the common electrode and the array substrate. Between the substrates.
  • a plurality of gate lines and a plurality of data lines are disposed on the array substrate, for example, the gate lines and the data lines cross each other to define a plurality of sub-pixel units.
  • image display can be achieved by sequentially applying a gate scan signal to the gate lines.
  • the voltage on the pixel electrode usually needs to be able to remain at a certain voltage value until the next frame gate scan signal arrives. If the voltage maintained on the pixel electrode drops prematurely, the display effect of the ADS liquid crystal display device is lowered. Therefore, generally, each sub-pixel unit in the array substrate of the ADS liquid crystal display device includes a storage capacitor to satisfy the requirement of maintaining the pixel electrode voltage stability.
  • At least one embodiment of the present invention provides an array substrate, a method of fabricating the same, and a display device to increase the storage capacitance of the array substrate while ensuring the aperture ratio of the sub-pixel unit.
  • At least one embodiment of the present invention provides an array substrate including a sub-pixel unit including a first transparent common electrode, a pixel electrode, and a second transparent common electrode; the pixel electrode being disposed on the first Above a transparent common electrode and insulated from the first transparent common electrode, an orthographic projection of the first transparent common electrode on a surface on which the pixel electrode is located overlaps with the pixel electrode; and the second transparent a common electrode is disposed above the pixel electrode and Insulated with the pixel electrode.
  • At least one embodiment of the present invention also provides a display device comprising the array substrate described above.
  • At least one embodiment of the present invention also provides a method of fabricating an array substrate, the method comprising forming a sub-pixel unit, further comprising: forming a first transparent common electrode; forming on the first transparent common electrode a pixel electrode, the pixel electrode is insulated from the first transparent common electrode, and an orthographic projection of the first transparent common electrode on a surface of the pixel electrode overlaps with the pixel electrode; A second transparent common electrode is formed on the pixel electrode, and the second transparent common electrode is insulated from the pixel electrode.
  • 1a is a top plan view of an ADS array substrate
  • Figure 1b is a cross-sectional view taken along line AA, line BB and line CC of Figure 1a;
  • FIG. 2a is a schematic top view of an array substrate according to an embodiment of the present invention.
  • FIG. 2b is a cross-sectional view of the array substrate along the aa line, the bb line, and the cc line in FIG. 2a according to an embodiment of the present invention
  • 3a is a top plan view showing an end portion of a gate line in which an electrically conductive structure is disposed in an array substrate according to an embodiment of the present invention
  • Figure 3b is a cross-sectional view along line EE of Figure 3a;
  • FIG. 4 is a cross-sectional view of another array substrate along the aa line, the bb line, and the cc line in FIG. 2a according to an embodiment of the present invention
  • FIG. 5 is a top plan view showing a first transparent common electrode provided with a hollow portion in an array substrate according to an embodiment of the invention
  • FIG. 6 is a cross-sectional view of a display device according to an embodiment of the present invention.
  • FIG. 7 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 8a and FIG. 8b are schematic diagrams showing fabrication of a first transparent common electrode by using a material forming an active layer according to an embodiment of the present invention
  • FIG. 9 is a top plan view showing a first transparent common electrode formed in the method for fabricating an array substrate according to an embodiment of the invention.
  • 9b is a schematic top plan view of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 9 is a top plan view showing a second transparent common electrode formed in the method for fabricating an array substrate according to an embodiment of the invention.
  • FIG. 1a is a top plan view of an ADS array substrate; and FIG. 1b is a cross-sectional view along line AA, line BB, and line CC of FIG. 1a.
  • the ADS array substrate includes a plurality of gate lines 101 and a plurality of data lines 102, and the gate lines 101 and the data lines 102 cross each other to define a plurality of sub-pixel units.
  • each of the sub-pixel units includes a thin film transistor 110 and a pixel electrode 160 and a common electrode 180 which are disposed on the flat layer 150 and insulated from each other by the insulating layer 170.
  • the thin film transistor 110 includes a gate electrode 111, a gate insulating layer 112, an active layer 113, a source 114, and a drain 115, the gate electrode 111 may be integrally formed or electrically connected to the gate line 101.
  • the source electrode 114 may be integrally formed or electrically connected to the data line 102, and the drain electrode 115 and the pixel electrode 160 may be electrically connected, for example, through the via hole 161.
  • the ADS array substrate may further include a common electrode line 130 electrically connected to the common electrode 180, which is disposed, for example, in the same layer as the gate line 101.
  • the inventors of the present application have noted that the storage capacitance in the ADS array substrate is usually generated by the overlapping portion between the common electrode 180 and the pixel electrode 160, but the size of the storage capacitor is often affected by the thickness of the insulating layer 170 or It is difficult to increase due to factors such as resolution.
  • At least one embodiment of the present invention provides an array substrate 20 including a sub-pixel unit 200 including a first transparent common electrode 290, a pixel electrode 260, and a second transparent
  • the common electrode 280 is disposed above the first transparent common electrode 290 (ie, disposed on a side of the first transparent common electrode 290 away from the base substrate 100) and is insulated from the first transparent common electrode 290 (ie, two An insulating layer is disposed between the first transparent common electrode 290 and the pixel electrode 260 on the surface of the pixel electrode 260, and the second transparent common electrode 280 is disposed above the pixel electrode 260 (ie, disposed on the pixel) The side of the electrode 260 that is away from the first transparent common electrode 290) and is insulated from the pixel electrode 260 (ie, an insulating layer is disposed therebetween).
  • a first transparent common electrode 290 overlapping the pixel electrode 260 is disposed, so that a capacitance is generated between the first transparent common electrode 290 and the pixel electrode 260 to obtain a larger storage capacitor.
  • a transparent common electrode 290 is disposed to be transparent, and the aperture ratio of the array substrate can be ensured. Further, the first transparent common electrode 290 is disposed on a side of the pixel electrode 260 away from the second transparent common electrode 280, and the pixel electrode 260 can be avoided as much as possible.
  • the electric field generated between the second transparent common electrodes 280 for controlling the liquid crystal exerts an influence.
  • the above-described orthographic projection of the first transparent common electrode 290 may be located in the region where the pixel electrode 260 is located. In this way, the influence of the first transparent common electrode 290 on the electric field for controlling the liquid crystal generated between the pixel electrode 260 and the second transparent common electrode 280 can be further prevented.
  • the material for preparing the first transparent common electrode 290 may include a transparent conductive metal oxide such as indium tin oxide, indium gallium zinc oxide, indium zinc oxide, or the like.
  • the material for preparing the pixel electrode 260 and the second transparent common electrode 280 may also include a transparent conductive metal oxide such as indium tin oxide, indium gallium zinc oxide, indium zinc oxide, or the like.
  • the orthographic projection of the second transparent common electrode 280 on the face of the pixel electrode 260 may overlap with the pixel electrode 260 or may be outside the region where the pixel electrode 260 is located.
  • the array substrate 20 may further include a flat layer 250 that may be disposed between the pixel electrode 260 and the second transparent common electrode 280 in a direction perpendicular to the base substrate 100.
  • the flat layer 250 provides a flat surface to serve as a flattening effect, and the flat layer 250 is usually made of an organic material such as a resin, so that the thickness thereof can be made thicker to lower the conductive layers on both sides of the flat layer (for example, The parasitic capacitance between the source/drain metal layer where the data line 202 is located and the layer where the second transparent common electrode 280 is located in 2b.
  • the pixel electrode 160 and the common electrode 180 are both disposed on the flat layer 150, and the pixel electrode 160 is electrically connected to the drain 115 of the thin film transistor 110 through the via 161 penetrating the flat layer 150. connection. Since the flat layer 150 is thick, if the via hole 161 is made too large, the aperture ratio of the sub-pixel unit is lowered; if the via hole 161 is made too small, the pixel electrode 160 is easily broken at the via hole 161, resulting in the pixel. An open circuit occurs between the electrode 160 and the drain 115.
  • the array substrate 20 provided by the embodiment of the present invention is disposed between the pixel electrode 260 and the second transparent common electrode 280 by the flat layer 250, so that the pixel electrode 260 does not need to pass through.
  • the via of the flat layer 250 can be electrically connected to the drain 215 of the thin film transistor 210, thereby improving the aperture ratio of the sub-pixel unit and avoiding an open circuit between the pixel electrode 260 and the drain 215 of the thin film transistor 210.
  • the gate electrode 211 is disposed under the active layer 213 (ie, disposed between the active layer 213 and the base substrate 100), the source 214 and the drain.
  • the pole 215 is disposed over the active layer 213 (ie, disposed on a side of the active layer 213 remote from the base substrate 100).
  • the thin film transistor 210 can also adopt other structures commonly used in the art, for example, the gate, the source and the drain are disposed on the active layer, or the gate, the source and the drain are disposed on the active layer. Lower, or the gate is disposed above the active layer and the source/drain is disposed below the active layer.
  • the flat layer 250 is disposed between the pixel electrode 260 and the second transparent common electrode 280.
  • the pixel electrode 260 may be in direct contact with the drain 215 of the thin film transistor 210, or
  • the vias in the insulating layer between the ones are electrically connected or electrically connected by other conductive members.
  • the embodiments of the present invention are not described herein.
  • the array substrate 20 further includes a gate line 201 and a data line 202.
  • the gate line 201 and the data line 202 cross each other to define the sub-pixel unit 200.
  • an orthographic projection of at least one of the gate line 201 and the data line 202 on the face of the first transparent common electrode 290 is outside the area where the first transparent common electrode 290 is located. This can avoid parasitic capacitance caused by the overlap of the first transparent common electrode 290 and the gate line 201 / data line 202 as much as possible.
  • FIG. 2a and 2b illustrate the case where the positive projections of the gate line 201 and the data line 202 on the surface of the first transparent common electrode 290 are located outside the area where the first transparent common electrode 290 is located.
  • Embodiments of the invention include, but are not limited to, the illustrated aspects.
  • the array substrate 20 may further include a common electrode line 230 that is electrically connected to the common electrode line 230.
  • the embodiments of the present invention include, but are not limited to, as long as a voltage difference between the first transparent common electrode 290 and the pixel electrode 260 can be realized to generate a capacitance therebetween.
  • the first transparent common electrode 290 may be in direct contact with the common electrode line 230 (ie, the two are not electrically connected through vias or other conductive members in the insulating layer), and the contact area between the two is transparent with the first transparent
  • the area of the electrode 290 where the orthographic projection of the surface on which the common electrode line 230 is located is substantially uniform. Since the first transparent common electrode 290 is in direct contact with the common electrode line 230, it is not necessary to add an insulating layer therebetween. Therefore, the structure and manufacturing process of the array substrate provided by the embodiments of the present invention are simple.
  • the common electrode line 230 may be disposed in the same layer as the gate line 201 or the data line 202.
  • the array substrate 20 may further include a conductive structure covering the end of the gate line 201, which The conductive structure may be disposed in the same layer as the first transparent common electrode 290 (ie, formed of the same film).
  • the conductive structure covers the end of the gate line 201 and is in direct contact with the end portion, and the end portion of the gate line 201 can be effectively protected; and, in a direction perpendicular to the plane of the array substrate, the conductive structure There is no insulating layer between the layer and the gate line, which makes the process of the embodiment of the invention simple.
  • the end of the gate line 201 is a portion of the gate line 201 outside the pixel region of the array substrate 20 (ie, the region surrounded by the outermost sub-pixel unit on the array substrate), that is, the wiring region outside the display region part.
  • a gate driver for example, a gate driving IC
  • the end portion of the gate line 201 is electrically connected to the gate driver.
  • the first transparent common electrode 290 is in direct contact with the common electrode line 230 and
  • the array substrate 20 may also include a conductive structure covering the end of the data line 202, and the conductive structure may be disposed in the same layer as the first transparent common electrode 290.
  • a source driver (eg, a source driver IC) may be disposed on the array substrate, and the end of the data line 202 is electrically connected to the source driver.
  • a conductive structure 209a is disposed on the end portion 012 of the gate line 201 or the data line 202.
  • a gate insulating layer 212 of the thin film transistor 210 may be disposed on the conductive structure 209a.
  • an insulating layer may also be disposed between the first transparent common electrode 290 and the common electrode 230, and both are electrically connected through via holes in the insulating layer.
  • the second transparent common electrode 280 and the first transparent common electrode 290 may be electrically connected to the same common electrode line 230 or may be electrically connected to different common electrode lines.
  • the second transparent common electrode 280 may be electrically connected to the common electrode line through a via hole penetrating the flat layer 250, and the via hole may be disposed outside the pixel region of the array substrate 20 to avoid the influence as much as possible.
  • the aperture ratio of the sub-pixel unit may be used to be electrically connected to the same common electrode line 230 or may be electrically connected to different common electrode lines.
  • the active layer 213 of the thin film transistor 210 may be disposed in the same layer as the first transparent common electrode 290. That is, the active layer 213 of the thin film transistor 210 may be formed through the same film as the first transparent common electrode 290.
  • the material of the active layer 213 may include a transparent conductive metal oxide (eg, indium gallium zinc oxide, etc.) or a doped low temperature.
  • the active layer 213 may be made of a material that is transparent and has good semiconductor properties.
  • the gate electrode 211, the source electrode 214, and the drain electrode 215 may be disposed on the active layer 213 away from the substrate substrate 100.
  • the source 214 and the drain 215 may be disposed between the layer where the gate 211 is located and the layer where the active layer 213 is located or may be disposed at a portion of the gate 211 away from the active layer 213. side.
  • the embodiments of the present invention include, but are not limited to, the following.
  • the first transparent common electrode can also be insulated and insulated from the gate line.
  • the gate line is made of a transparent conductive material; or, the first transparent common electrode may be disposed in the same layer and insulated from the data line, in which case the data line is made of a transparent conductive material.
  • the first transparent common electrode 290 may have a hollow portion 290b, and the orthographic projection of the hollow portion 290b on the surface of the pixel electrode 260 is located in the region where the pixel electrode 260 is located.
  • the area of the overlapping portion of the first transparent common electrode 290 and the pixel electrode 260 can be changed by setting the hollow portion 290, thereby adjusting the size of the capacitance between the two, that is, the added to the array substrate 20.
  • the size of the storage capacitor can be adjusted by the size and number of the hollow portions 290.
  • the planar shape of the hollow portion 290 may be any pattern.
  • the planar shape of the hollow portion 290b may be polygonal, circular or elliptical in the direction in which the first transparent common electrode 290 is located.
  • At least one embodiment of the present invention provides a display device comprising the array substrate 20 provided by any of the above embodiments.
  • the display device of the present embodiment may include an array substrate 20 and a counter substrate 30.
  • the array substrate 20 and the opposite substrate 30 are opposed to each other and pass through the sealant 35 to form a liquid crystal cell.
  • the liquid crystal material 40 is filled therein.
  • the counter substrate 30 is, for example, a color filter substrate.
  • the pixel electrode of each sub-pixel unit of the array substrate 20 and the second transparent common electrode are used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the display device may include any product or component having a display function such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a watch, and the like.
  • a display function such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a watch, and the like.
  • At least one embodiment of the present invention further provides a method of fabricating an array substrate, the method comprising forming a sub-pixel unit, as shown in FIG. 7, forming the sub-pixel unit further comprises: forming a first transparent common electrode; Forming a pixel electrode on the common electrode to insulate the pixel electrode from the first transparent common electrode, the front projection of the first transparent common electrode on the surface of the pixel electrode overlaps with the pixel electrode; and forming a second transparent common on the pixel electrode The electrode insulates the second transparent common electrode from the pixel electrode.
  • the first transparent common electrode overlapping the pixel electrode, a larger storage capacitor can be obtained under the premise of ensuring the aperture ratio of the sub-pixel unit, and the pixel electrode can be avoided as much as possible. Between the second transparent common electrodes The electric field has an effect.
  • the fabrication method provided by the embodiment of the present invention may further include: forming a planarization layer on the pixel electrode after forming the pixel electrode and before forming the second transparent common electrode. This can increase the aperture ratio of the obtained sub-pixel unit and avoid short circuit between the pixel electrode and the second transparent common electrode.
  • the sub-pixel unit may include a thin film transistor including an active layer.
  • the step of forming the first transparent common electrode may include: forming a transparent conductive film 213' as shown in FIG. 8a; As shown in FIG. 8b, the transparent conductive film 213' is patterned to form the active layer 213 and the first transparent common electrode 290. This saves the process of making the first transparent common electrode separately.
  • the patterning process may be a process of forming a set pattern by using a mask, for example, including photoresist coating, photoresist exposure, photoresist development, etching a thin film layer using a photoresist pattern.
  • the steps are the same; however, the embodiment is not limited thereto, and the patterning process may be another processing method of forming a set pattern.
  • the manufacturing process of the array substrate provided by the embodiment of the present invention includes the following steps 1 to 8.
  • Step 1 A gate metal layer including a gate electrode 211, a plurality of gate lines 201, and a common electrode line 230 is formed by a patterning process (for example, including exposure, development, etching, and the like).
  • Step 2 Forming a transparent conductive film on the gate metal layer, patterning it to form a first transparent common electrode 290, which is in direct contact with the common electrode line 230, as shown in FIG. 9a.
  • a portion of the transparent conductive film at the end of the gate line may be left to protect the end of the gate line.
  • Step 3 A gate insulating layer 212 is formed on the first transparent common electrode 290.
  • Step 4 An active layer 213 is formed on the gate insulating layer 212.
  • Step 5 Forming a source/drain metal layer including a source electrode 214, a drain electrode 215, and a data line 202 by a patterning process.
  • the source electrode 214 and the drain electrode 215 are electrically connected to the active layer 213, respectively, thereby forming the thin film transistor 210.
  • Step 6 The pixel electrode 260 is formed to be electrically connected to the drain 215 of the thin film transistor 210 as shown in FIG. 9b.
  • Step 7 Forming a flat layer 250 on the pixel electrode 250 and a via hole in the flat layer 250, the via hole exposing a part of the surface of the first transparent common electrode 290 or a part of the surface of the common electrode line 230.
  • Step 8 A second transparent common electrode 280 is formed on the flat layer 250 as shown in Fig. 9c.
  • the second transparent common electrode 280 may be electrically connected to the first transparent common electrode 290 or the common electrode line 230 through the via hole in the step 7.
  • each structure may refer to the embodiment of the above array substrate, and the repeated description is omitted.

Abstract

一种阵列基板及其制作方法、显示装置，该阵列基板(20)包括子像素单元(200)，所述子像素单元(200)包括：第一透明公共电极(290)；像素电极(260)，设置于所述第一透明公共电极(290)上方并且与所述第一透明公共电极(290)相绝缘，所述第一透明公共电极(290)在所述像素电极(260)所在面上的正投影与所述像素电极(260)有重叠部分；以及第二透明公共电极(280)，设置于所述像素电极(260)上方并且与所述像素电极(260)相绝缘。该阵列基板(20)可以在保证子像素单元(200)的开口率的前提下具有更大的存储电容。

Description

阵列基板及其制作方法、显示装置 技术领域
本发明的至少一个实施例涉及一种阵列基板及其制作方法、显示装置。
背景技术
高级超维场转换(AdvancedSuper Dimension Switch，ADS)技术由于具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差等优点而被广泛应用于各类显示装置中。在ADS液晶显示装置中，像素电极和公共电极都设置于阵列基板上，例如，像素电极可以具有板状结构，公共电极可以具有狭缝状结构，像素电极设置于公共电极和阵列基板的衬底基板之间。通过分别对公共电极和像素电极加载电压以在公共电极和像素电极之间形成电场，可以控制液晶分子的偏转，进而控制通过液晶面板的光线。
阵列基板上设置有多条栅线和多条数据线，例如，这些栅线和数据线彼此交叉以限定多个子像素单元。例如，可以通过对栅线依次施加栅扫描信号以实现图像显示。为更好地满足显示效果的需要，像素电极上的电压通常需要能够保持在某个电压值上，直到下一帧栅扫描信号到来。如果维持在像素电极上的电压过早下降，则会降低ADS液晶显示装置的显示效果。因此，通常ADS液晶显示装置的阵列基板中的每一子像素单元都包括一个存储电容来满足保持像素电极电压稳定的要求。
发明内容
本发明的至少一个实施例提供一种阵列基板及其制作方法、显示装置，以在保证子像素单元的开口率的前提下增大阵列基板的存储电容。
本发明的至少一个实施例提供了一种阵列基板，其包括子像素单元，所述子像素单元包括第一透明公共电极、像素电极和第二透明公共电极；所述像素电极设置于所述第一透明公共电极上方并且与所述第一透明公共电极相绝缘，所述第一透明公共电极在所述像素电极所在面上的正投影与所述像素电极有重叠部分；以及所述第二透明公共电极设置于所述像素电极上方并且 与所述像素电极相绝缘。
本发明的至少一个实施例还提供了一种显示装置，其包括以上所述的阵列基板。
本发明的至少一个实施例还提供了一种阵列基板的制作方法，该方法包括形成子像素单元，形成子像素单元进一步包括：形成第一透明公共电极；在所述第一透明公共电极上形成像素电极，使所述像素电极与所述第一透明公共电极相绝缘，所述第一透明公共电极在所述像素电极所在面上的正投影与所述像素电极有重叠部分；以及在所述像素电极上形成第二透明公共电极，所述第二透明公共电极与所述像素电极相绝缘。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1a为一种ADS阵列基板的俯视示意图；
图1b为沿图1a中AA线、BB线和CC线的剖视示意图；
图2a为本发明实施例提供的一种阵列基板的俯视示意图；
图2b为本发明实施例提供的一种阵列基板沿图2a中aa线、bb线和cc线的剖视示意图；
图3a为本发明实施例提供的阵列基板中栅线的端部设置有导电结构的俯视示意图；
图3b为沿图3a中EE线的剖视示意图；
图4为本发明实施例提供的另一种阵列基板沿图2a中aa线、bb线和cc线的剖视示意图；
图5a和图5b为本发明实施例提供的阵列基板中第一透明公共电极设置有镂空部的俯视示意图；
图6为本发明实施例提供的显示装置的剖视示意图；
图7为本发明实施例提供的阵列基板的制作方法的流程图；
图8a和图8b为本发明实施例提供的利用形成有源层的材料制作第一透明公共电极的示意图；
图9a为本发明实施例提供的阵列基板的制作方法中形成第一透明公共电极后的俯视示意图；
图9b为本发明实施例提供的阵列基板的制作方法中形成像素电极后的俯视示意图；
图9c为本发明实施例提供的阵列基板的制作方法中形成第二透明公共电极后的俯视示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1a为一种ADS阵列基板的俯视示意图；图1b为沿图1a中AA线、BB线和CC线的剖视示意图。如图1a和图1b所示，该ADS阵列基板包括多条栅线101和多条数据线102，这些栅线101和数据线102彼此交叉以限定多个子像素单元。例如，每个子像素单元包括薄膜晶体管110以及设置于平坦层150上且通过绝缘层170彼此绝缘的像素电极160和公共电极180。薄膜晶体管110包括栅极111、栅绝缘层112、有源层113、源极114和漏极 115，栅极111可以与栅线101一体形成或电连接，源极114可以与数据线102一体形成或电连接，漏极115与像素电极160例如通过过孔161电连接。该ADS阵列基板还可以包括与公共电极180电连接的公共电极线130，该公共电极线130例如与栅线101同层设置。
在研究中，本申请的发明人注意到，ADS阵列基板中的存储电容通常是通过公共电极180和像素电极160之间的交叠部分产生，但存储电容的大小往往受到绝缘层170的厚度或分辨率等因素的限制而很难增大。
如图2a和图2b所示，本发明的至少一个实施例提供了一种阵列基板20，其包括子像素单元200，子像素单元200包括第一透明公共电极290、像素电极260和第二透明公共电极280，像素电极260设置于第一透明公共电极290上方(即设置于第一透明公共电极290的远离衬底基板100的一侧)并且与第一透明公共电极290相绝缘(即，二者之间设置有绝缘层)，第一透明公共电极290在像素电极260所在面上的正投影与像素电极260有重叠部分，第二透明公共电极280设置于像素电极260上方(即设置于像素电极260的远离第一透明公共电极290的一侧)并且与像素电极260相绝缘(即，二者之间设置有绝缘层)。
本发明实施例提供的阵列基板，通过设置与像素电极260交叠的第一透明公共电极290，使得第一透明公共电极290和像素电极260之间产生电容，以获得更大的存储电容；第一透明公共电极290设置为透明，可以保证阵列基板的开口率；此外，第一透明公共电极290设置于像素电极260的远离第二透明公共电极280的一侧，可以尽量避免对像素电极260与第二透明公共电极280之间产生的用于控制液晶的电场造成影响。
例如，第一透明公共电极290的上述正投影(即，在像素电极260所在面上的正投影)可以位于像素电极260所在区域内。这样，可以进一步避免第一透明公共电极290对像素电极260与第二透明公共电极280之间产生的用于控制液晶的电场造成影响。
例如，制备第一透明公共电极290的材料可以包括透明的导电金属氧化物，例如，氧化铟锡、氧化铟镓锌、氧化铟锌等。
制备像素电极260和第二透明公共电极280的材料也可以包括透明的导电金属氧化物，例如，氧化铟锡、氧化铟镓锌、氧化铟锌等。
第二透明公共电极280在像素电极260所在面上的正投影可以与像素电极260有重叠部分或者可以位于像素电极260所在区域之外。
例如，阵列基板20还可以包括平坦层250，其在垂直于衬底基板100的方向上可以设置于像素电极260与第二透明公共电极280之间。平坦层250提供一个平坦的表面以起到平坦化作用，并且平坦层250通常采用树脂等有机材料制作，因而其厚度可以制作得较厚，以降低位于平坦层两侧的导电层(例如，图2b中数据线202所在的源漏金属层和第二透明公共电极280所在的层)之间的寄生电容。
在图1a和图1b所示的情形中，像素电极160和公共电极180都设置于平坦层150之上，并且像素电极160通过贯穿平坦层150的过孔161与薄膜晶体管110的漏极115电连接。由于平坦层150较厚，如果过孔161做得太大，则导致子像素单元的开口率降低；如果过孔161制作得太小，则像素电极160容易在过孔161处断开，导致像素电极160与漏极115之间发生断路。
与图1a和图1b所示的情形相比，本发明实施例提供的阵列基板20通过将平坦层250设置于像素电极260与第二透明公共电极280之间，使得像素电极260不需要通过贯穿平坦层250的过孔即可实现与薄膜晶体管210的漏极215的电连接，从而既可以提高子像素单元的开口率又可以避免像素电极260与薄膜晶体管210的漏极215之间发生断路。
本发明实施例不限定薄膜晶体管210的具体结构。例如，在图2a和图2b所示的薄膜晶体管210中，栅极211设置于有源层213之下(即，设置于有源层213与衬底基板100之间)，源极214和漏极215设置于有源层213之上(即，设置于有源层213的远离衬底基板100的一侧)。当然，薄膜晶体管210也可以采用本领域常用的其它结构，例如，栅极、源极和漏极都设置于有源层之上，或者栅极、源极和漏极都设置于有源层之下，或者栅极设置于有源层之上且源极/漏极设置于有源层之下。
本发明实施例中，平坦层250设置于像素电极260和第二透明公共电极280之间，在这种情况下，像素电极260与薄膜晶体管210的漏极215可以直接接触，或者通过设置于二者之间的绝缘层中的过孔电连接，或者通过其它导电部件电连接。本发明实施例不做赘述。
继续如图2a和图2b所示，阵列基板20还包括栅线201和数据线202， 栅线201和数据线202彼此交叉以限定子像素单元200。例如，栅线201和数据线202中的至少之一在第一透明公共电极290所在面上的正投影位于第一透明公共电极290所在区域之外。这样可以尽量避免第一透明公共电极290与栅线201/数据线202因交叠而产生寄生电容。图2a和图2b以栅线201和数据线202在第一透明公共电极290所在面上的正投影都位于第一透明公共电极290所在区域之外为例进行说明。本发明实施例包括、但不限于所示出的情形。
例如，在一个实施例中，阵列基板20还可以包括公共电极线230，第一透明公共电极290与公共电极线230电连接。本发明实施例包括、但不限于此，只要可以实现第一透明公共电极290与像素电极260之间具有电压差以在二者之间产生电容即可。
例如，第一透明公共电极290可以与公共电极线230直接接触(即，二者不是通过绝缘层中的过孔或者其它导电部件电连接)，并且二者之间的接触区域与第一透明公共电极290在公共电极线230所在面上的正投影所在的区域大致一致。由于第一透明公共电极290与公共电极线230直接接触，不需要在二者之间增加绝缘层，因此，本发明实施例提供的阵列基板的结构和制作工艺简单。
例如，公共电极线230可以栅线201或数据线202同层设置。
例如，在第一透明公共电极290与公共电极线230直接接触且公共电极线230与栅线201同层设置的情况下，阵列基板20还可以包括覆盖栅线201的端部的导电结构，该导电结构可以与第一透明公共电极290同层设置(即，由同一薄膜形成)。在本发明实施例中，导电结构覆盖栅线201的端部且与该端部直接接触，可以有效地保护栅线201的端部；并且，在垂直于阵列基板所在面的方向上，导电结构所在的层与栅线之间无绝缘层，使得本发明实施例的工艺简单。
栅线201的端部为栅线201的位于阵列基板20的像素区(即，阵列基板上的最外侧子像素单元围成的区域)之外的部分，即，位于显示区之外的布线区的部分。例如，阵列基板上还可以设置有栅极驱动器(例如，栅极驱动IC)，栅线201的上述端部与栅极驱动器电连接。
类似地，例如，在第一透明公共电极290与公共电极线230直接接触且 公共电极线230与数据线202同层设置的情况下，阵列基板20也可以包括覆盖数据线202的端部的导电结构，该导电结构可以与第一透明公共电极290同层设置。
例如，阵列基板上还可以设置有源极驱动器(例如，源极驱动IC)，数据线202的上述端部与源极驱动器电连接。
例如，如图3a和图3b所示，栅线201或数据线202的端部012上设置有导电结构209a。例如，在导电结构209a上还可以设置有薄膜晶体管210的栅绝缘层212。
以上实施例以第一透明公共电极290与公共电极线230直接接触为例进行说明。当然，本发明实施例包括、但不限于此。例如，在沿垂直于阵列基板所在面的方向上，第一透明公共电极290与公共电极230之间也可以设置有绝缘层，并且二者通过该绝缘层中的过孔电连接。
在本发明实施例中，第二透明公共电极280和第一透明公共电极290可以与同一公共电极线230电连接，也可以与不同的公共电极线电连接。当阵列基板20包括平坦层250时，第二透明公共电极280可以通过贯穿平坦层250的过孔与公共电极线电连接，该过孔可以设置于阵列基板20的像素区之外以尽量避免影响子像素单元的开口率。
为节省制作工艺，例如，如图4所示，薄膜晶体管210的有源层213可以与第一透明公共电极290同层设置。也就是说，薄膜晶体管210的有源层213可以与第一透明公共电极290通过同一薄膜形成。
例如，当薄膜晶体管210的有源层213与第一透明公共电极290同层设置时，有源层213的材料可以包括透明的导电金属氧化物(例如氧化铟镓锌等)或者掺杂的低温多晶硅等，只要有源层213采用透明且半导体性能好的材料即可。
例如，当有源层的材料包括掺杂的低温多晶硅时，为了便于制作有源层213，栅极211、源极214和漏极215可以都设置于有源层213的远离衬底基板100的一侧，在这种情况下，源极214和漏极215可以设置于栅极211所在的层和有源层213所在的层之间或者可以设置于栅极211的远离有源层213的一侧。当然，本发明实施例包括、但不限于此。
例如，为了节省制作工艺，第一透明公共电极也可以和栅线同层且绝缘 设置，在这种情况下，栅线采用透明导电材料制成；或者，第一透明公共电极也可以和数据线同层且绝缘设置，在这种情况下，数据线采用透明导电材料制成。
例如，如图5a和图5b所示，第一透明公共电极290可以具有镂空部290b，镂空部290b在像素电极260所在面上的正投影位于像素电极260所在区域中。本发明实施例通过设置镂空部290可以改变第一透明公共电极290与像素电极260的交叠部分的面积，从而调整二者之间的电容的大小，也就是说，对阵列基板20所增加的存储电容的大小可通过镂空部290的大小和数量来进行调整。
镂空部290的平面形状可以为任意图案。例如，沿第一透明公共电极290所在面方向，镂空部290b的平面形状可以为多边形、圆形或椭圆形。
本发明的至少一个实施例提供了一种显示装置，其包括上述任一实施例提供的阵列基板20。
例如，如图6所示，本实施例的显示装置可以包括阵列基板20与对置基板30，阵列基板20与对置基板30彼此对置且通过封框胶35以形成液晶盒，在液晶盒中填充有液晶材料40。该对置基板30例如为彩膜基板。阵列基板20的每个子像素单元的像素电极和第二透明公共电极(参见阵列基板的实施例中的相关描述)用于施加电场以对液晶材料的旋转程度进行控制从而进行显示操作。
例如，该显示装置可以包括：液晶面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、手表等任何具有显示功能的产品或部件。
本发明的至少一个实施例还提供了一种阵列基板的制作方法，该方法包括形成子像素单元，如图7所示，形成子像素单元进一步包括：形成第一透明公共电极；在第一透明公共电极上形成像素电极，使像素电极与第一透明公共电极相绝缘，第一透明公共电极在像素电极所在面上的正投影与像素电极有重叠部分；以及在像素电极上形成第二透明公共电极，使第二透明公共电极与像素电极相绝缘。本发明实施例提供的阵列基板，通过设置与像素电极交叠的第一透明公共电极，可以在保证子像素单元的开口率的前提下获得更大的存储电容，并且可以尽量避免对像素电极与第二透明公共电极之间的 电场造成影响。
例如，本发明实施例提供的制作方法还可以包括：在形成像素电极之后且在形成第二透明公共电极之前，在像素电极上形成平坦层。这样既可以提高所得到的子像素单元的开口率又可以避免像素电极与第二透明公共电极之间发生短路。
例如，子像素单元可以包括薄膜晶体管，薄膜晶体管包括有源层，在这种情况下，上述形成第一透明公共电极的步骤可以包括：如图8a所示，形成透明导电薄膜213’；如图8b所示，对透明导电薄膜213’进行图案化处理，以形成有源层213以及第一透明公共电极290。这样可以节省单独制作第一透明公共电极的工艺流程。
本公开之中，图案化处理可以是通过利用掩膜板形成设定图案的处理方式，例如包括光刻胶涂敷、光刻胶曝光、光刻胶显影、利用光刻胶图案刻蚀薄膜层等步骤；但实施方式不限于此，图案化处理还可以是其他的形成设定图案的处理方式。
以图2a和图2b所示的情形为例，本发明实施例提供的阵列基板的制作过程例如包括以下步骤1～步骤8。
步骤1：通过图案化处理(例如，包括曝光、显影、刻蚀等步骤)，形成包括栅极211、多条栅线201和公共电极线230的栅金属层。
步骤2：在栅金属层上形成透明导电薄膜，对其进行图案化处理以形成第一透明公共电极290，该第一透明公共电极290直接与公共电极线230接触，如图9a所示。
例如，在该步骤中，可以保留透明导电薄膜的位于栅线的端部的部分(即，上述的导电结构)，以对栅线的端部进行保护。
步骤3：在第一透明公共电极290上形成栅绝缘层212。
步骤4：在栅绝缘层212上形成有源层213。
步骤5：通过图案化处理，形成包括源极214、漏极215和数据线202的源漏金属层。源极214和漏极215分别与有源层213电连接，由此形成薄膜晶体管210。
步骤6：形成像素电极260，使其与薄膜晶体管210的漏极215电连接，如图9b所示。
步骤7：在像素电极250上形成平坦层250以及位于平坦层250中的过孔，该过孔暴露出第一透明公共电极290的部分表面或公共电极线230的部分表面。
步骤8：在平坦层250上形成第二透明公共电极280，如图9c所示。第二透明公共电极280可以通过步骤7中的过孔与第一透明公共电极290或公共电极线230电连接。
本发明实施例提供的制作方法中，各结构的设置可参考上述阵列基板的实施例，重复之处不再赘述。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2015年9月24日递交的中国专利申请第201510618081.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (14)

  1. 一种阵列基板，包括子像素单元，其中，所述子像素单元包括：
    第一透明公共电极；
    像素电极，设置于所述第一透明公共电极上方并且与所述第一透明公共电极相绝缘，所述第一透明公共电极在所述像素电极所在面上的正投影与所述像素电极有重叠部分；以及
    第二透明公共电极，设置于所述像素电极上方并且与所述像素电极相绝缘。
  2. 根据权利要求1所述的阵列基板，还包括平坦层，其设置于所述像素电极与所述第二透明公共电极之间。
  3. 根据权利要求1或2所述的阵列基板，其中，所述第一透明公共电极的所述正投影位于所述像素电极所在区域内。
  4. 根据权利要求1-3中任一项所述的阵列基板，还包括栅线和数据线，其中，所述栅线和所述数据线彼此交叉以限定所述子像素单元，所述栅线和所述数据线中的至少之一在所述第一透明公共电极所在面上的正投影位于所述第一透明公共电极所在区域之外。
  5. 根据权利要求4所述的阵列基板，还包括公共电极线，其中，所述第一透明公共电极与所述公共电极线直接接触，并且二者之间的接触区域与所述第一透明公共电极在所述公共电极线所在面上的正投影所在的区域一致。
  6. 根据权利要求5所述的阵列基板，其中，
    所述公共电极线与所述栅线同层设置，则所述阵列基板还包括覆盖所述栅线的端部的导电结构，所述导电结构与所述第一透明公共电极同层设置；或者
    所述公共电极线与所述数据线同层设置，则所述阵列基板还包括覆盖所述数据线的端部的导电结构，所述导电结构与所述第一透明公共电极同层设置。
  7. 根据权利要求1-6中任一项所述的阵列基板，其中，所述第一透明公共电极具有镂空部，所述镂空部在所述像素电极所在面上的正投影位于所述像素电极所在区域中。
  8. 根据权利要求7所述的阵列基板，其中，沿所述第一透明公共电极所在面方向，所述镂空部的平面形状为多边形、圆形或椭圆形。
  9. 根据权利要求1-3中任一项所述的阵列基板，还包括公共电极线，其中，所述第一透明公共电极与所述公共电极线接触，并且二者之间的接触区域与所述第一透明公共电极在所述公共电极线所在面上的正投影所在的区域一致。
  10. 根据权利要求1-9中任一项所述的阵列基板，其中，所述子像素单元还包括薄膜晶体管，所述薄膜晶体管包括有源层，所述有源层与所述第一透明公共电极同层设置。
  11. 一种显示装置，包括根据权利要求1-10任一项所述的阵列基板。
  12. 一种阵列基板的制作方法，包括形成子像素单元，其中，所述形成子像素单元进一步包括：
    形成第一透明公共电极；
    在所述第一透明公共电极上形成像素电极，其中，所述像素电极与所述第一透明公共电极相绝缘，所述第一透明公共电极在所述像素电极所在面上的正投影与所述像素电极有重叠部分；以及
    在所述像素电极上形成第二透明公共电极，所述第二透明公共电极与所述像素电极相绝缘。
  13. 根据权利要求12所述的制作方法，还包括：
    在形成所述像素电极之后且在形成所述第二透明公共电极之前，在像素电极上形成平坦层。
  14. 根据权利要求12或13所述的制作方法，其中，
    所述子像素单元包括薄膜晶体管，所述薄膜晶体管包括有源层；
    形成所述第一透明公共电极包括：
    形成透明导电薄膜；
    对所述透明导电薄膜进行图案化处理，以形成所述有源层以及所述第一透明公共电极。
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