WO2018068542A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2018068542A1
WO2018068542A1 PCT/CN2017/092488 CN2017092488W WO2018068542A1 WO 2018068542 A1 WO2018068542 A1 WO 2018068542A1 CN 2017092488 W CN2017092488 W CN 2017092488W WO 2018068542 A1 WO2018068542 A1 WO 2018068542A1
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WIPO (PCT)
Prior art keywords
common electrode
line
array substrate
display area
connection line
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PCT/CN2017/092488
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English (en)
French (fr)
Inventor
先建波
李盼
徐健
乔勇
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/750,984 priority Critical patent/US10546879B2/en
Publication of WO2018068542A1 publication Critical patent/WO2018068542A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode

Definitions

  • Embodiments of the present disclosure generally relate to the field of display technology, and in particular, to array substrates and display devices.
  • ADS Advanced-Super Dimensional Switching
  • the ADS technology forms a multi-dimensional electric field by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that all the aligned liquid crystal molecules are directly between the slit electrodes in the liquid crystal cell and above the electrode. Can produce rotation.
  • a common electrode located in a display region is connected to a common electrode lead line located in a non-display region through a common electrode line, and it is necessary to provide each common electrode for connection with a common electrode line. hole.
  • the present disclosure has been made in order to overcome at least one of the problems and disadvantages of the prior art.
  • an embodiment of the present disclosure provides an array substrate having a display area and a non-display area and comprising:
  • the pixel unit including a common electrode and a pixel electrode
  • the common electrodes of at least one row and/or at least one column of pixel units are connected to each other and to the common electrode lead-out line.
  • the array substrate further includes a common electrode connection line disposed on the base substrate, connecting at least one row and/or at least one column of pixel unit common electrodes to each other, and The common electrode lead wire is connected.
  • the common electrode is disposed in the same layer as the common electrode connection line.
  • the array substrate further includes a common electrode line disposed on the base substrate and electrically connected to the corresponding common electrode, the common electrode line being connected to the common electrode lead line.
  • the common electrode lead line is disposed in a non-same layer with the common electrode connection line and connected to the common electrode lead line through a first via hole; and/or the common electrode lead line and the common electrode The line is disposed in a non-same layer and is connected to the common electrode lead-out line through a second via.
  • the first via and the orthographic projection of the second via on the substrate substrate at least partially overlap.
  • an orthographic projection of the first via on the substrate substrate covers an orthographic projection of the second via on the substrate.
  • each row of pixel units includes a plurality of pixel unit groups, each pixel unit group includes at least two pixel units, and a common electrode of at least one of the pixel unit groups passes through the third via The common electrode lines are connected.
  • the common electrode of the at least two pixel units of the at least one pixel unit group is a single plate-like structure.
  • the common electrode connection line includes a first sub-connection line located in the display area and a second sub-connection line located in the non-display area, the common electrode line including the first in the display area a three sub-connection line and a fourth sub-connection line located in the non-display area, the second sub-connection line, the fourth sub-connection line and the common electrode are disposed in the same layer.
  • the common electrode connection line includes a first sub-connection line located in the display area and a second sub-connection line located in the non-display area, the common electrode line including the first in the display area a third sub-connection line and a fourth sub-connection line located in the non-display area, the second sub-connection line and the common electrode are disposed in a same layer, and the fourth sub-connection line and the pixel electrode are disposed at The same layer.
  • the pixel electrode is located above a plurality of data lines.
  • each pixel unit is provided with at least one thin film transistor, and a second passivation layer is disposed between the plurality of data lines and the pixel electrode, and the pixel electrode passes through the fourth via and at least A source or a drain of the thin film transistor is connected.
  • the pixel electrode spacing of each pixel unit is set, and the total of all pixel units
  • the common electrode is a single plate-like structure; or, the pixel electrodes of the respective pixel units are spaced apart, and the common electrode of each pixel unit is spaced apart.
  • the common electrode of all the pixel units is a single plate-like structure disposed in the display area or the non-display area, and the common electrode is placed above or below the common electrode lead line in the non-display area. Connected to the common electrode lead-out line.
  • the common electrode is located below the common electrode lead-out line
  • the pixel unit includes a common electrode line electrically connected to a corresponding common electrode, the common electrode line including a third sub-position located in the display area a connection line and a fourth sub-connection line located in the non-display area; the fourth sub-connection line and the pixel electrode are disposed in the same layer.
  • the common electrode is located above the common electrode lead line, and the pixel unit includes a common electrode line electrically connected to a corresponding common electrode, the common electrode line including a third sub-position located in the display area a connection line and a fourth sub-connection line located in the non-display area; the fourth sub-connection line and the common electrode are disposed in the same layer.
  • the pixel electrode is in the same layer as the common electrode.
  • the common electrode line is disposed in the same layer as the common electrode lead line and directly overlaps the common electrode lead-out line.
  • the common electrode includes a slit structure corresponding to at least one of the pixel units in a display region; and/or the common electrode includes a hollow structure, the hollow structure being The display area overlaps at least one of the gate line, the data line, and the thin film transistor.
  • a display device including the array substrate described in any of the embodiments.
  • 1 is a plan view showing an array substrate using ADS technology
  • FIG. 2A is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • 2B is a schematic structural diagram of an array substrate according to another embodiment of the present disclosure.
  • 3A is a schematic structural diagram of an array substrate according to still another embodiment of the present disclosure.
  • FIG. 3B is a schematic structural diagram of an array substrate according to still another embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view showing a film layer structure of a single pixel unit of an array substrate according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of an array substrate according to still another embodiment of the present disclosure.
  • FIG. 6 is a schematic cross-sectional view showing a film layer structure of a single pixel unit of an array substrate provided by still another embodiment of the present disclosure
  • FIG. 7 is a cross-sectional view showing a film layer structure of a single pixel unit of an array substrate according to still another embodiment of the present disclosure.
  • FIG. 1 is an array substrate adopting ADS technology, wherein the array substrate includes a display area 10 and a non-display area 20, and in the display area 10, any two adjacent gate lines 12 and any phase A pixel unit is disposed in a region surrounded by two adjacent data lines 11, each of the pixel units having a common electrode 131, and each common electrode 131 is connected to the common electrode line 15 through a third via hole 14, the common electrode line 15 extends from the display area 10 to the non-display area 20 and is connected to the common electrode lead line 21 through the second via 22 .
  • FIG. 2A is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • the array substrate has a display area 10 and a non-display area 20, and includes:
  • a base substrate for example, see the base substrate 01 in FIG. 4, 6 or 7;
  • the common electrode can be a bulk electrode.
  • the common electrodes of the individual pixel units can be spaced apart.
  • a plurality of data lines 11 and a plurality of gate lines 12 are further disposed on the array substrate, and the inter-interleaved gate lines 12 and data lines 11 define pixel units.
  • a pixel unit is disposed in an area surrounded by any two adjacent data lines 11 and any two adjacent gate lines 12.
  • a common electrode lead line 21 is further provided on the base substrate in the non-display area 20.
  • the common electrode lead line 21 may be parallel to the gate line 12 or the data line 11, and the common electrode lead line 21 is disposed on one side or both sides of the display area 10.
  • 2A shows a case where the common electrode lead line 21 is parallel to the data line 11 and is disposed on the display region 10 side.
  • At least one line of image is disposed on the substrate substrate.
  • the common electrode connection line 16 to which the common electrodes 131 of the element cells are connected and/or the common electrode connection line 16 which connects the common electrodes 131 of at least one column of the pixel units to each other, and the common electrode connection line 16 are electrically connected to the common electrode lead line 21.
  • FIG. 2A illustrates that in the array substrate, a common electrode connection line 16 connecting the common electrodes 131 of at least one row of pixel units to each other may be disposed; please refer to FIG. 2B, which is another embodiment of the present disclosure.
  • a common electrode connection line connecting the common electrodes of one, two, three or more rows of pixel units may be provided, or may be set
  • a common electrode connection line in which the common electrodes of one, two, three, or more columns of pixel units are connected to each other, or a common electrode connection line in which one row and a common electrode of one of the pixel units are connected to each other may be provided.
  • a common electrode connection line connecting at least one row of the common electrode and/or at least one column of the common electrode to each other and connected to the common electrode lead-out line is provided to realize the voltage to the common electrode Input.
  • Such an array substrate not only provides a new way of connecting the common electrode to the common electrode lead line, but also has at least other advantages, such as: no need or reduction for each common electrode is provided for connection with the common electrode line.
  • the via hole for example, no via hole is not required when the common electrode line is not provided
  • the process complexity is reduced
  • the transmittance of the display area is improved
  • the display effect of the image is optimized.
  • FIG. 3A is a schematic structural diagram of an array substrate according to another embodiment of the present disclosure.
  • a common electrode line 15 may be disposed on the substrate, and the common electrode line 15 is The common electrode lead wires 21 are connected.
  • FIG. 3A shows a case where the common electrode line 15 is parallel to the gate line 12. In practical applications, the common electrode line 15 may also be parallel to the data line 11.
  • the common electrode line and the common electrode lead line There are a plurality of methods for connecting the common electrode line and the common electrode lead line.
  • the common electrode line and the common electrode lead line can be directly electrically connected; when the common electrode When the line and the common electrode lead line are disposed in different layers, the common electrode line and the common electrode lead line need to be electrically connected through the via hole.
  • the common electrode voltage input can be realized by the common electrode connection line, the common electrode line is formed on the base substrate, and the common electrode line is electrically connected to the common electrode lead line.
  • the common electrode line can form a storage capacitor with the pixel electrode, which is beneficial to increasing the ability of the pixel electrode to hold a charge, thereby ensuring the display effect of the picture.
  • the common electrode and the common electrode connection line may be disposed in the same layer.
  • the common electrode connection line can be placed in the same layer as the common electrode.
  • the common electrode connection line may be a part or an integral part of the common electrode, or the common electrode connection line is formed of a material layer forming the common electrode and formed integrally with the common electrode, for example, the common electrode connection line may be directly from the display area
  • the internal common electrode extends to a portion of the non-display area.
  • the common electrode connection line may be directly formed on the base substrate on which the common electrode is formed such that the common electrode connection line directly contacts or overlaps the common electrode.
  • the common electrode connection line and the common electrode are electrically connected to each other without passing through the via hole, or there is no need to provide a via hole for realizing an electrical connection between the common electrode connection line and the common electrode, such as It can reduce the process complexity, improve the transmittance of the display area, and optimize the display effect of the image.
  • FIG. 3A and FIG. 4 are schematic cross-sectional views showing a film structure of a single pixel of an array substrate according to an embodiment of the present disclosure, wherein the array substrate may include: a substrate Substrate 01, gate 02, gate insulating layer 03, active layer 04, pixel electrode 05, source drain pattern 06, first passivation layer 07, and common electrode 08. At least one of the common electrode lead line 21 and the common electrode line 15 and the common electrode connection line 16 may be disposed in a non-same layer or a different layer.
  • the common electrode lead line 21 and the source drain pattern 06 may be disposed in the same layer, the common electrode line 15 and the gate 02 may be disposed in the same layer, and the common electrode connection line 16 may be disposed in the same layer as the common electrode 08.
  • a common electrode connection line 16 electrically connecting each row of the common electrodes 131 to each other and connected to the common electrode lead-out line 21 may be provided; each of the common electrode connection lines 16 passes The first via holes 23 provided in the first passivation layer 07 are electrically connected to the common electrode lead wires 21; each of the common electrode lines 15 passes through the second via holes 22 and the common electrode lead wires 21 provided in the gate insulating layer 03. connection.
  • the orthographic projections of the first via and the second via on the substrate may at least partially overlap.
  • the orthographic projection of the first via on the substrate may cover the orthographic projection of the second via on the substrate.
  • the orthographic projection of the first via on the substrate may not overlap with the orthographic projection of the second via on the substrate.
  • the embodiment of the present disclosure does not specifically limit the orthographic projection of the first via and the second via on the substrate.
  • FIG. 5 is a schematic structural diagram of an array substrate according to another embodiment of the present disclosure.
  • Each row of pixel units includes a plurality of pixel unit groups 13 and each pixel unit group 13 ( Indicated by the dashed box) includes at least two pixel units.
  • the pixel unit group 13 includes three pixel units.
  • the common electrode 131 of at least one of the pixel unit groups 13 is electrically connected to the common electrode line 15 through the third via hole 14.
  • the third via such that the common electrode line and the common electrode connection line are electrically connected to the common electrode at the same time, the voltage stability on the common electrode may be better.
  • the other line can also input a voltage to the common electrode.
  • the pixel unit group includes three pixel units, for example, the three pixel units are a red pixel unit, a green pixel unit, and a blue pixel unit. For the convenience of manufacturing the array substrate, only the blue pixel unit may be used. In the region, a third via that electrically connects the common electrode to the common electrode line is disposed.
  • the common electrode corresponding to a single pixel unit in the display area may be a plate-like or block-like structure (for example, see the array substrate shown in FIG. 3A) or a slit structure or a strip structure (for example) See the array substrate shown in Figure 4.
  • each row of pixel unit groups includes at least two pixel units, and the common electrodes of the at least two pixel units are formed in a single plate-like or block-like structure, which can simplify the patterning process when forming the common electrode.
  • the common electrode may be a unitary plate or block structure in the display area and/or the non-display area.
  • a common electrode connection line for connecting the common electrode and the common electrode lead line is provided; when the common electrode is disposed in the display area
  • FIG. 3B is a schematic structural diagram of another array substrate provided by the embodiment of the present disclosure.
  • the common electrode 131 and the common electrode lead line 21 are provided in the form of a plate or a block structure.
  • the first via 23 is electrically connected in the non-display area 20, that is, the portion of the common electrode 131 located in the non-display area 20 is electrically connected to the common electrode lead line 21 through the first via 23, and at this time, the common electrode is not required to be disposed. Connection line.
  • the common electrode 131 may include a slit structure 1311 and/or a hollow structure 1312, the slit structure 1311 corresponding to at least one pixel unit in the display region 10; the hollow structure 1312 and the gate At least one of the line 12, the data line 11, and the thin film transistor (see, for example, Figures 4, 6 or 7) overlap.
  • the shape of the common electrode is not specifically limited in the embodiment of the present disclosure.
  • the common electrode connection line 16 includes a first sub-connection line 161 located within the display area 10 and a second sub-connection line 162 located within the non-display area 20; the common electrode line 15 includes A third sub-connection line 151 located within the display area 10 and a fourth sub-connection line 152 located within the non-display area 20.
  • the second sub-connection line 162, the fourth sub-connection line 152, and the common electrode 131 may be disposed in the same layer.
  • the second sub-connection line 162 and the fourth sub-connection line 152 may be made of a material layer forming a common electrode, and the common electrode 131, the second sub-connection line 152, and the fourth sub-connection are formed by one patterning process.
  • Line 162 the first via 23 and the second via 22 can also be formed by one patterning process, which simplifies the number of patterning processes.
  • the second sub-connection line 162 and the common electrode 131 may be disposed in the same layer, the fourth sub-connection line 152 and the pixel electrode are disposed in the same layer, and the pixel electrode may directly overlap with the source-drain pattern.
  • the electrical connection is formed, and the common electrode lead line 21 may also be disposed in the same layer as the source drain pattern.
  • the fourth sub-connection line 152 is formed of a material layer formed by the pixel electrode, the second via 22 is not required at this time.
  • the common electrode line 15 is electrically connected to the common electrode lead line 21, and the common electrode line 15 can be directly overlapped with the common electrode lead line 21 to form an electrical connection, so that the patterning process can also be simplified.
  • FIG. 6 is a schematic cross-sectional view showing a structure of a film layer of a single pixel unit of an array substrate according to still another embodiment of the present disclosure.
  • Each pixel unit formed on the substrate substrate 01 may be provided with At least one thin film transistor (TFT), the data line in the array substrate is in the same layer as the source/drain pattern 06, and the pixel electrode 05 in the array substrate is located above the plurality of data lines, that is, the pixel electrode 05 is located Above the source drain pattern 06, a second passivation layer 09 may be disposed between the plurality of data lines and the pixel electrode 05.
  • the pixel electrode 05 passes through the fourth via 091 disposed in the second passivation layer 09.
  • a source or a drain in the source/drain pattern 06 of at least one of the TFTs is electrically connected.
  • the common electrode 08 includes a slit structure.
  • the array substrate is a case where the common electrode is above the pixel electrode.
  • the common electrode may also be located under the pixel electrode.
  • FIG. 7 is a schematic diagram of a film structure of another single pixel of an array substrate according to an embodiment of the present disclosure.
  • the common electrode 08 in the pixel unit is located under the pixel electrode 05, and the pixel electrode 05 may also have Slit structure.
  • the pixel electrodes 05 of the respective pixel units may be spaced apart, and the common electrodes 08 of all the pixel units are in a single plate-like structure; or the pixel electrodes 05 of the respective pixel units may also be spaced apart, and the common electrode 08 of each pixel unit Also Separate settings.
  • the common electrode 08 of all the pixel units is a single plate-like structure
  • the common electrode 08 is electrically connected to the common electrode line 15 through the fifth via 031 in the display region.
  • the common electrode lead line is in the same layer as the source/drain layer 06
  • the common electrode 08 and the common electrode lead line are directly overlapped to form an electrical connection, and it is not necessary to provide the common electrode and the common electrode line to be electrically connected.
  • the vias (that is, the third vias are not required to be provided) can realize the voltage input of the common electrode lines to the common electrodes.
  • the common electrode can be directly overlapped above or below the common electrode lead-out line in the non-display area to form an electrical connection.
  • the common electrode line may include a third sub-connection line located within the display area and a fourth sub-connection line located in the non-display area.
  • the common electrode When the common electrode is located below the common electrode lead line, the fourth sub-connection line and the pixel electrode are disposed in the same layer.
  • the common electrode When the common electrode is located above the common electrode lead line, the fourth sub-connection line and the common electrode are disposed in the same layer.
  • the patterning process when manufacturing the array substrate can be reduced, so that the process of manufacturing the array substrate is simplified.
  • the pixel electrode and the common electrode may also be located in the same layer.
  • the array substrate provided by the embodiment of the present disclosure may also be applied to an In-Plane Switching (referred to as IPS) structure.
  • IPS In-Plane Switching
  • the common electrode may be electrically connected to the common electrode lead-out line through the first via hole; the common electrode line is electrically connected to the common electrode lead-out line through the second via hole.
  • the embodiment of the present disclosure further provides a display device including the array substrate described in any one of the above embodiments.
  • the display device can be any product or component having a display function such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • At least one row of common electrodes and/or at least one column of common electrodes are connected to each other and connected to the common electrode lead wires, and at least one array substrate display region may be added.
  • the connection of the common electrode to the common electrode lead-out line in the non-display area enables voltage input to the common electrode, and the via hole for connecting to the common electrode line is not required or reduced on the array substrate ( For example, when a common electrode line is not provided, no via hole is required, the process complexity is reduced, the transmittance of the display area is improved, and the display effect of the image is optimized.
  • the common electrode line and the common electrode connection line simultaneously input a voltage to the common electrode, so that the voltage stability of the common electrode is better, and the common electrode can be combined with the pixel electrode A storage capacitor is formed to ensure the display of the picture.

Abstract

一种阵列基板及显示装置。阵列基板具有显示区域（10）和非显示区域（20）并包括：衬底基板（01）；在衬底基板（01）上、在显示区域（10）内设置的多个像素单元，像素单元包括公共电极（131）和像素电极（05）；和在衬底基板（01）上、在非显示区域（20）内设置的公共电极引出线（21）；至少一行和/或至少一列像素单元的公共电极（131）相互连接并与公共电极引出线（21）连接。

Description

阵列基板及显示装置
本申请主张在2016年10月14日在中国专利局提交的中国专利申请No.201621126476.0的优先权，其全部内容通过引用包含于此。
技术领域
本公开的实施例一般地涉及显示技术领域，并且特别地，涉及阵列基板及显示装置。
背景技术
目前的液晶显示器中，对于面板中公共电极的设置有多种情况，其中一种是将公共电极和像素电极都设置于阵列基板上的情况，例如高级超维场开关(Advanced-Super Dimensional Switching；简称：ADS)技术。ADS技术是通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场形成多维电场，使液晶盒内狭缝电极间、电极正上方所有取向液晶分子都能够产生旋转。
在采用ADS技术的常规阵列基板中，位于显示区域内的公共电极通过公共电极线与位于非显示区域内的公共电极引出线连接，需要为每个公共电极设置用于与公共电极线连接的过孔。
发明内容
为了克服现有技术存在的问题和缺陷中的至少一种，提出了本公开。
在一方面中，本公开的实施例提供了一种阵列基板，具有显示区域和非显示区域并包括：
衬底基板；
在所述衬底基板上、在显示区域内设置的多个像素单元，所述像素单元包括公共电极和像素电极；和
在所述衬底基板上、在非显示区域内设置的公共电极引出线；
至少一行和/或至少一列像素单元的公共电极相互连接并与所述公共电极引出线连接。
在一个实施例中，阵列基板还包括公共电极连接线，该公共电极连接线设置在在所述衬底基板上，将至少一行和/或至少一列像素单元的公共电极相互连接，并与所述公共电极引出线连接。
在一个实施例中，所述公共电极与所述公共电极连接线同层设置。
在一个实施例中，阵列基板还包括设置在在所述衬底基板上并与对应的公共电极电连接的公共电极线，所述公共电极线与所述公共电极引出线连接。
在一个实施例中，所述公共电极引出线与所述公共电极连接线非同层设置并通过第一过孔与所述公共电极引出线连接；和/或所述公共电极引出线与公共电极线非同层设置并通过第二过孔与所述公共电极引出线连接。
在一个实施例中，所述第一过孔与所述第二过孔在所述衬底基板上的正投影至少部分重叠。
在一个实施例中，所述第一过孔在所述衬底基板上的正投影覆盖所述第二过孔在所述衬底基板上的正投影。在一个实施例中，每行像素单元中包括多个像素单元组，每个像素单元组包括至少两个像素单元，每个像素单元组中的至少一个像素单元的公共电极通过第三过孔与所述公共电极线连接。
在一个实施例中，至少一个像素单元组的所述至少两个像素单元的公共电极为单个板状结构。
在一个实施例中，所述公共电极连接线包括位于显示区域内的第一子连接线和位于所述非显示区域内的第二子连接线，所述公共电极线包括位于显示区域内的第三子连接线和位于所述非显示区域内的第四子连接线，所述第二子连接线、所述第四子连接线和所述公共电极设置在同一层。
在一个实施例中，所述公共电极连接线包括位于显示区域内的第一子连接线和位于所述非显示区域内的第二子连接线，所述公共电极线包括位于显示区域内的第三子连接线和位于所述非显示区域内的第四子连接线，所述第二子连接线和所述公共电极设置在同一层，所述第四子连接线和所述像素电极设置在同一层。
在一个实施例中，所述像素电极位于多条数据线上方。
在一个实施例中，每个像素单元都设置有至少一个薄膜晶体管，所述多条数据线和所述像素电极之间设置有第二钝化层，所述像素电极通过第四过孔与至少一所述薄膜晶体管的源极或漏极连接。
在一些实施例中，各个像素单元的像素电极间隔设置，所有像素单元的公 共电极为单个板状结构；或者，各个像素单元的像素电极间隔设置，各个像素单元的公共电极间隔设置。
在一个实施例中，所有像素单元的公共电极为设置在显示区域或非显示区域内的单个板状结构，所述公共电极在所述非显示区域内在所述公共电极引出线的上方或者下方搭接在所述公共电极引出线上。
在一个实施例中，所述公共电极位于所述公共电极引出线下方，所述像素单元包括与对应的公共电极电连接的公共电极线，所述公共电极线包括位于显示区域内的第三子连接线和位于所述非显示区域内的第四子连接线；所述第四子连接线和所述像素电极设置在同一层。
在一个实施例中，所述公共电极位于所述公共电极引出线上方，所述像素单元包括与对应的公共电极电连接的公共电极线，所述公共电极线包括位于显示区域内的第三子连接线和位于所述非显示区域内的第四子连接线；所述第四子连接线和所述公共电极设置在同一层。
在一个实施例中，所述像素电极与所述公共电极位于同一层。
在一个实施例中，所述公共电极线与所述公共电极引出线同层设置并直接搭接在所述公共电极引出线上。
在一个实施例中，所述公共电极包括狭缝结构，所述狭缝结构在显示区域内对应至少一个所述像素单元；和/或所述公共电极包括镂空结构，所述镂空结构在所述显示区域内与栅线、数据线、薄膜晶体管中至少之一有交叠。
在另一方面中，提供了一种显示装置，包括任一实施例中描述的阵列基板。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为示出一种采用ADS技术的阵列基板的平面示意图；
图2A是本公开的一个实施例提供的阵列基板的结构示意图；
图2B是本公开的另一个实施例提供的阵列基板的结构示意图；
图3A是本公开的又一个实施例提供的阵列基板的结构示意图；
图3B是本公开的再一个实施例提供的阵列基板的结构示意图；
图4是示出本公开实施例提供的一种阵列基板的单个像素单元的膜层结构的剖面示意图；
图5是本公开的又一种实施例提供的阵列基板的结构示意图；
图6是示出本公开的又一种实施例提供的阵列基板的单个像素单元的膜层结构的剖面示意图；以及
图7是示出本公开的又一种实施例提供的阵列基板的单个像素单元的膜层结构的剖面示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
请参考图1，图1为一种采用ADS技术的阵列基板，其中，该阵列基板包括显示区域10和非显示区域20，在显示区域10中，任意相邻的两条栅线12和任意相邻的两条数据线11围成的区域内设置有一个像素单元，每个像素单元都具有公共电极131，每个公共电极131通过第三过孔14与公共电极线15相连，该公共电极线15从显示区域10延伸至非显示区域20并通过第二过孔22与公共电极引出线21连接。
图2A是本公开实施例提供的一种阵列基板的结构示意图。该阵列基板具有显示区域10和非显示区域20，并包括：
衬底基板(例如，参见图4、6或7中的衬底基板01)；和
在该衬底基板上、在显示区域10内设置的多个像素单元，每个像素单元都包括公共电极131和像素电极(例如，参见图4、6或7中的像素电极05)。示例性地，公共电极可以为块状电极。在一些示例中，各个像素单元的公共电极可以间隔设置。如图2A所示，在该阵列基板上还设置有多条数据线11和多条栅线12，相互交错的栅线12与数据线11限定出像素单元。例如，任意两条相邻的数据线11和任意两条相邻的栅线12围成的区域内设置有一个像素单元。
在该衬底基板上、在非显示区域20内还设置有公共电极引出线21。
在一个实施例中，公共电极引出线21可以平行于栅线12或者数据线11，且该公共电极引出线21设置在显示区域10的一侧或两侧。图2A为公共电极引出线21与数据线11平行且设置在显示区域10一侧的情况。
在一个实施例中，如图2A所示，在该衬底基板上，设置有将至少一行像 素单元的公共电极131相互连接的公共电极连接线16和/或将至少一列像素单元的公共电极131相互连接的公共电极连接线16，公共电极连接线16与公共电极引出线21电连接。
请参考图2A，图2A示出在该阵列基板中，可以设置有将至少一行像素单元的公共电极131相互连接的公共电极连接线16；请参考图2B，图2B是本公开的另一种实施例提供的阵列基板的结构示意图，示出在该阵列基板中，可以设置有将至少一列像素单元的公共电极131相互连接的公共电极连接线16；在本公开的其它实施例中，在该阵列基板中，可以设置将至少一行像素单元的公共电极和至少一列像素单元的公共电极相互连接的公共电极连接线。例如，当该阵列基板包括100行和90列像素单元时，则可以设置将其中的一行、两行、三行或更多行像素单元的公共电极相互连接的公共电极连接线，也可以设置将其中一列、两列、三列或更多列像素单元的公共电极相互连接的公共电极连接线，或者可以设置将其中的一行和其中的一列的像素单元的公共电极相互连接的公共电极连接线。
根据本公开实施例提供的阵列基板，在衬底基板上，设置将至少一行公共电极和/或至少一列公共电极相互连接并与公共电极引出线连接的公共电极连接线，实现对公共电极的电压输入。
发明人发现，这种阵列基板不仅提供了一种公共电极与公共电极引出线新的连接方式，而且至少还有其他优点，例如：无需或减少为每个公共电极设置用于与公共电极线连接的过孔(例如，不设置公共电极线时则不需要过孔)，降低了工艺复杂度，提高了显示区域的透过率，优化了图像的显示效果。
在一个实施例中，请参考图3A，图3A是本公开的另一种实施例提供的阵列基板的结构示意图，在衬底基板上还可以设置有公共电极线15，该公共电极线15与公共电极引出线21连接。图3A为公共电极线15平行于栅线12的情况，实际应用中，公共电极线15还可以平行于数据线11。
其中，该公共电极线与公共电极引出线连接的方法有多种，当公共电极线与公共电极引出线同层设置时，则可以直接将公共电极线与公共电极引出线电连接；当公共电极线与公共电极引出线非同层设置时，则需要通过过孔将该公共电极线与公共电极引出线电连接。
在本公开实施例中，通过公共电极连接线可以实现对公共电极电压输入，在衬底基板上形成公共电极线，且该公共电极线与公共电极引出线电连接，则 该公共电极线可以与像素电极之间形成存储电容，有利于增加像素电极保持电荷的能力，保证了画面的显示效果。
在一些实施例中，公共电极与公共电极连接线可以同层设置。
在本公开的实施例中，设置公共电极连接线的方法有多种。在一些示例中，可以将该公共电极连接线与公共电极同层设置。例如，公共电极连接线可以是公共电极的一部分或整体部分，或者公共电极连接线由形成公共电极的材料层形成并与公共电极形成为一体结构，例如，公共电极连接线可以是直接从显示区域内的公共电极延伸到非显示区域的部分。在另一些示例中，可以在形成公共电极的衬底基板上直接形成公共电极连接线，使得公共电极连接线直接接触或搭接在公共电极上。由此，在显示区域内，公共电极连接线与公共电极无需通过过孔而相互电连接，或者说不需要设置用于实现公共电极连接线和公共电极之间的电连接的过孔，这例如可以降低工艺复杂度，提高显示区域的透过率，优化图像的显示效果。
在一个实施例中，请参考图3A和图4，图4是示出本公开实施例提供的一种阵列基板的单个像素的膜层结构的剖面示意图，其中，该阵列基板可以包括：衬底基板01、栅极02、栅绝缘层03、有源层04、像素电极05、源漏极图形06、第一钝化层07和公共电极08。公共电极引出线21与公共电极线15和公共电极连接线16中的至少一个可以非同层或异层设置。例如，公共电极引出线21与源漏极图形06可以同层设置，公共电极线15与栅极02可以同层设置，公共电极连接线16可以与公共电极08同层设置。在本公开的一些实施例中，在衬底基板01上，可以设置将每行公共电极131相互电连接并与公共电极引出线21连接的公共电极连接线16；每条公共电极连接线16通过在第一钝化层07中设置的第一过孔23与公共电极引出线21电连接；每条公共电极线15通过栅绝缘层03中设置的第二过孔22与公共电极引出线21电连接。
在一个实施例中，该第一过孔与第二过孔在衬底基板上的正投影可以至少部分重叠。
在一个实施例中，该第一过孔在衬底基板上的正投影可以覆盖第二过孔在衬底基板上的正投影。
在一个实施例中，该第一过孔在衬底基板上的正投影，与该第二过孔在衬底基板上的正投影还可以不重叠。
本公开实施例对该第一过孔与第二过孔在衬底基板上的正投影重叠或者不重叠不做具体限定。
在一个实施例中，请参考图5，图5是本公开的另一种实施例提供的阵列基板的结构示意图，每行像素单元中包括多个像素单元组13，每个像素单元组13(由虚线框指示)包括至少两个像素单元，例如，当该阵列基板所制作的显示屏为三原色显示屏时，则该像素单元组13包括三个像素单元。每个像素单元组13中的至少一个像素单元的公共电极131通过第三过孔14与公共电极线15电连接。在本公开实施例中，通过设置第三过孔，使得公共电极线和公共电极连接线同时与公共电极电连接，则公共电极上的电压稳定性会更好。同时当公共电极线和公共电极连接线其中一根线损坏，另一根线也可以对公共电极输入电压。
实际应用中，当像素单元组包括三个像素单元时，例如：该三个像素单元为红色像素单元、绿色像素单元和蓝色像素单元，为了方便制造该阵列基板，可以只在蓝色像素单元区域中，设置公共电极与公共电极线电连接的第三过孔。
在本公开的一些实施例中，在显示区域内对应单个像素单元的公共电极可以为板状或块状结构(例如，参见图3A示出的阵列基板)或狭缝结构或条状结构(例如，参见图4示出的阵列基板)。
在一个实施例中，每行像素单元组包括至少两个像素单元，且该至少两个像素单元的公共电极形成为单个板状或块状结构，可以简化形成公共电极时的构图工艺。
在一些实施例中，公共电极在显示区域和/或非显示区域可以为整体的板状或块状结构。当各个像素单元的公共电极只设置在显示区域内且整体为单个板状或块状结构时，则设置用于公共电极与公共电极引出线连接的公共电极连接线；当公共电极设置在显示区域和非显示区域二者内且整体为板状或块状结构时，请参考图3B，图3B是本公开实施例提供的另一种阵列基板的结构示意图，公共电极131与公共电极引出线21在非显示区域20内通过第一过孔23电连接，即公共电极131位于非显示区域20内的部分与公共电极引出线21通过第一过孔23电连接，此时，不需要设置公共电极连接线。在一个实施例中，如图3B所示，公共电极131可以包括狭缝结构1311和/或镂空结构1312，该狭缝结构1311在显示区域10内至少对应一个像素单元；该镂空结构1312与栅线12、数据线11、薄膜晶体管(例如参见图4、6或7)中至少之一有交叠。 本公开实施例对公共电极的形状不做具体限定。
在一个实施例中，如图3A所示，公共电极连接线16包括位于显示区域10内的第一子连接线161和位于非显示区域20内的第二子连接线162；公共电极线15包括位于显示区域10内的第三子连接线151和位于非显示区域20内的第四子连接线152。在一个示例中，第二子连接线162、第四子连接线152和公共电极131可以设置在同一层。此时，该第二子连接线162和第四子连接线152可以采用由形成公共电极的材料层制成，则通过一次构图工艺形成公共电极131、第二子连接线152和第四子连接线162。当然，也可以通过一次构图工艺形成第一过孔23和第二过孔22，简化构图工艺次数。
在本公开的一个实施例中，第二子连接线162和公共电极131可以设置在同一层，第四子连接线152和像素电极设置在同一层，像素电极可以与源漏极图形直接搭接形成电连接，而公共电极引出线21也可以是与源漏极图形同层设置的，当第四子连接线152采用由形成像素电极的材料层制作时，此时不需要第二过孔22将公共电极线15与公共电极引出线21电连接，该公共电极线15可以与公共电极引出线21直接搭接形成电连接，因此同样可以简化构图工艺。
请参考图6，图6是示出本公开的又一种实施例提供的阵列基板的单个像素单元的膜层结构的剖面示意图，在衬底基板01上形成的每个像素单元都可以设置有至少一个薄膜晶体管(Thin Film Transistor；简称：TFT)，阵列基板中的数据线与源漏极图形06同层，当阵列基板中的像素电极05位于多条数据线上方，也即像素电极05位于源漏极图形06上方，此时可以在多条数据线和像素电极05之间设置有第二钝化层09，像素电极05通过设置在第二钝化层09中的第四过孔091与至少一个TFT的源漏极图形06中的源极或漏极电连接。在一些示例中，公共电极08包括狭缝结构。
上述阵列基板都是公共电极在像素电极上方时的情况，在本公开实施例中，公共电极还可以位于像素电极下方。
例如，请参考图7，图7是本公开实施例提供的另一种阵列基板单个像素的膜层结构的示意图，像素单元中公共电极08位于像素电极05下方，此时像素电极05也可以具有狭缝结构。在一些示例中，各个像素单元的像素电极05可以间隔设置，所有像素单元的公共电极08为单个板状结构；或者，各个像素单元的像素电极05也可以间隔设置，各个像素单元的公共电极08也可以间 隔设置。
在一个实施例中，如图7所示，当所有像素单元的公共电极08为单个板状结构时，公共电极08在显示区域内通过第五过孔031与公共电极线15电连接。此时，在非显示区内，当公共电极引出线与源漏极层06同层时，公共电极08与公共电极引出线直接搭接形成电连接，不需要设置公共电极与公共电极线电连接的过孔(也即不需要设置第三过孔)，便可以实现公共电极线对公共电极的电压输入。当然，公共电极在非显示区内可以在公共电极引出线的上方或下方直接搭接，形成电连接。
在一些示例中，公共电极线可以包括位于显示区域内的第三子连接线和位于非显示区域的第四子连接线。当公共电极位于公共电极引出线下方，第四子连接线和像素电极设置在同一层。当公共电极位于公共电极引出线上方，第四子连接线和公共电极设置在同一层。相应的可以减少制造该阵列基板时的构图工艺，使得制造该阵列基板的工艺简单化。
在一个实施例中，像素电极与公共电极还可以位于同一层。本公开实施例提供的阵列基板还可以适用于平面转换(In-Plane Switching；简称：IPS)结构。此时，公共电极可以通过第一过孔与公共电极引出线电连接；公共电极线通过第二过孔与公共电极引出线电连接。
本公开实施例还提供了一种显示装置，其包括上述任意一实施例中描述的阵列基板。显示装置可以为：液晶面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
综上所述，在本公开实施例提供的阵列基板和显示装置中，至少一行公共电极和/或至少一列公共电极相互连接并与公共电极引出线连接，至少可以增加一种阵列基板显示区域的公共电极与非显示区域内的公共电极引出线的连接方式，实现对公共电极的电压输入，并且在该阵列基板上无需或减少为每个公共电极设置用于与公共电极线连接的过孔(例如，不设置公共电极线时则不需要过孔)，降低了工艺复杂度，提高了显示区域的透过率，优化了图像的显示效果。同时，当该阵列基板上设置有公共电极线时，该公共电极线与公共电极连接线同时对公共电极输入电压，使得公共电极的电压稳定性会更好，并且该公共电极可以与像素电极之间形成存储电容，保证了画面的显示效果。
以上仅为本公开的较佳实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护 范围之内。

Claims (20)

  1. 一种阵列基板，具有显示区域和非显示区域并包括：
    衬底基板；
    在所述衬底基板上、在显示区域内设置的多个像素单元，所述像素单元包括公共电极和像素电极；和
    在所述衬底基板上、在非显示区域内设置的公共电极引出线；
    其中，至少一行和/或至少一列像素单元的公共电极相互连接并与所述公共电极引出线连接。
  2. 根据权利要求1所述的阵列基板，还包括公共电极连接线，该公共电极连接线设置在在所述衬底基板上，将至少一行和/或至少一列像素单元的公共电极相互连接，并与所述公共电极引出线连接。
  3. 根据权利要求2所述的阵列基板，所述公共电极与所述公共电极连接线同层设置。
  4. 根据权利要求2或3所述的阵列基板，还包括设置在在所述衬底基板上并与对应的公共电极电连接的公共电极线，所述公共电极线与所述公共电极引出线连接。
  5. 根据权利要求4所述的阵列基板，其中，所述公共电极引出线与所述公共电极连接线非同层设置并通过第一过孔与所述公共电极引出线连接；和/或
    所述公共电极引出线与公共电极线非同层设置并通过第二过孔与所述公共电极引出线连接。
  6. 根据权利要求4所述的阵列基板，其中，
    所述第一过孔与所述第二过孔在所述衬底基板上的正投影至少部分重叠。
  7. 根据权利要求4所述的阵列基板，其中，
    每行像素单元中包括多个像素单元组，每个像素单元组包括至少两个像素单元，每个像素单元组中的至少一个像素单元的公共电极通过第三过孔与所述公共电极线连接。
  8. 根据权利要求7所述的阵列基板，其中，
    至少一个像素单元组的所述至少两个像素单元的公共电极为单个板状结构。
  9. 根据权利要求4-8中任一项所述的阵列基板，其中，
    所述公共电极连接线包括位于显示区域内的第一子连接线和位于所述非显示区域内的第二子连接线；
    所述公共电极线包括位于显示区域内的第三子连接线和位于所述非显示区域内的第四子连接线；
    所述第二子连接线、所述第四子连接线和所述公共电极设置在同一层。
  10. 根据权利要求4-8中任一项所述的阵列基板，其中，
    所述公共电极连接线包括位于显示区域内的第一子连接线和位于所述非显示区域内的第二子连接线；
    所述公共电极线包括位于显示区域内的第三子连接线和位于所述非显示区域内的第四子连接线；
    所述第二子连接线和所述公共电极设置在同一层；
    所述第四子连接线和所述像素电极设置在同一层。
  11. 根据权利要求1-10中任一所述的阵列基板，其中，
    所述像素电极位于多条数据线上方。
  12. 根据权利要求11所述的阵列基板，其中，每个像素单元都设置有至少一个薄膜晶体管，
    所述多条数据线和所述像素电极之间设置有第二钝化层，所述像素电极通过第四过孔与至少一所述薄膜晶体管的源极或漏极连接。
  13. 根据权利要求1-12中任一项所述的阵列基板，其中，
    各个像素单元的像素电极间隔设置，所有像素单元的公共电极为单个板状结构；或者，
    各个像素单元的像素电极间隔设置，各个像素单元的公共电极间隔设置。
  14. 根据权利要求1所述的阵列基板，其中，
    所有像素单元的公共电极为设置在显示区域或非显示区域内的单个板状结构，
    所述公共电极在所述非显示区域内在所述公共电极引出线的上方或者下方搭接在所述公共电极引出线上。
  15. 根据权利要求14所述的阵列基板，其中，
    所述公共电极位于所述公共电极引出线下方，所述像素单元包括与对应的公共电极电连接的公共电极线，所述公共电极线包括位于显示区域内的第三子连接线和位于所述非显示区域内的第四子连接线；
    所述第四子连接线和所述像素电极设置在同一层。
  16. 根据权利要求14所述的阵列基板，其中，
    所述公共电极位于所述公共电极引出线上方，所述像素单元包括与对应的公共电极电连接的公共电极线，所述公共电极线包括位于显示区域内的第三子连接线和位于所述非显示区域内的第四子连接线；
    所述第四子连接线和所述公共电极设置在同一层。
  17. 根据权利要求1-16中任一所述的阵列基板，其中，
    所述像素电极与所述公共电极位于同一层。
  18. 根据权利要求4-10中任一项所述的阵列基板，其中，
    所述公共电极线与所述公共电极引出线同层设置并直接搭接在所述公共电极引出线上。
  19. 根据权利要求1-18中任一项所述的阵列基板，其中，
    所述公共电极包括狭缝结构，所述狭缝结构在显示区域内对应至少一个所述像素单元；和/或
    所述公共电极包括镂空结构，所述镂空结构在所述显示区域内与栅线、数据线、薄膜晶体管中至少之一有交叠。
  20. 一种显示装置，包括权利要求1-19中任一所述的阵列基板。
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US20190267400A1 (en) 2019-08-29

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