WO2013044783A1 - 阵列基板及其制备方法和显示装置 - Google Patents

阵列基板及其制备方法和显示装置 Download PDF

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Publication number
WO2013044783A1
WO2013044783A1 PCT/CN2012/081899 CN2012081899W WO2013044783A1 WO 2013044783 A1 WO2013044783 A1 WO 2013044783A1 CN 2012081899 W CN2012081899 W CN 2012081899W WO 2013044783 A1 WO2013044783 A1 WO 2013044783A1
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Prior art keywords
data line
common electrode
pixel
electrode
pixel electrode
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PCT/CN2012/081899
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English (en)
French (fr)
Inventor
李成
董学
陈东
木素真
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北京京东方光电科技有限公司
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Priority to US13/704,764 priority Critical patent/US9099356B2/en
Publication of WO2013044783A1 publication Critical patent/WO2013044783A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • Advanced Super Dimension Switch is a multi-dimensional electric field formed by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer. All of the aligned liquid crystal molecules between the inner slit electrodes and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field switching technology can improve the picture quality of thin film transistor liquid crystal display (TFT-LCD) products, resulting in high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, no extrusion Advantages such as Push Mura.
  • the common electrode and the pixel electrode are made of a transparent conductor, thereby increasing the aperture ratio and the light transmittance, and the space formed between the common electrode and the pixel electrode is larger than that between the upper and lower substrates.
  • the space is narrower, thereby forming a fringe electric field between the common electrode and the pixel electrode, so that the liquid crystal molecules are rotationally converted in a plane direction parallel to the substrate, thereby improving the light transmission efficiency of the liquid crystal layer.
  • the prior art provides a pixel structure. As shown in FIG. 1, the light-shielding area above the data line 1 is removed, and the data line 1 is set. Parallel strips of common electrode 2. A portion of the strip-shaped common electrode 2 is disposed above the pixel electrode 3, and another portion of the strip-shaped common electrode 2 covers over the data line 1, and has a width larger than the width of the data line 1. By forming the coverage of the common electrode 2 over the data line 1, the interference of the data line 1 with the liquid crystal electric field is suppressed, and adverse effects such as light leakage are prevented, thereby increasing the transmittance of the pixel.
  • the inventors have found that the load of the pixel structure of the prior art on the data line is too large, and the capacitance between the common electrode and the data line covering the data line accounts for the largest proportion of power consumption, resulting in the work of the entire liquid crystal panel. The consumption is greatly increased.
  • An embodiment of the present invention provides an array substrate, including: a base substrate; a gate line and a data line formed on the base substrate, the gate line and the data line crossing each other to define a pixel region; a thin film transistor and a pixel electrode disposed in the pixel region; a strip-shaped common electrode disposed above the pixel electrode and the data line, the common electrode including a cover over the data line and having a width greater than the data line a first common electrode of a width and a second common electrode disposed above the pixel electrode; an insulating layer disposed between the common electrode and the pixel electrode and between the common electrode and the data line, wherein The first common electrode is hollowed out corresponding to the area of the data line.
  • Another embodiment of the present invention provides a method of fabricating an array substrate, including: forming a gate line, a data line, a thin film transistor, and a pixel electrode on a base substrate, and a gate of the thin film transistor is connected to the gate line, a source of the thin film transistor is connected to the data line, a drain of the thin film transistor is connected to the pixel electrode; and a gate line, the data line, the thin film transistor, and the pixel are formed Forming an insulating layer on the base substrate of the electrode, and forming a strip-shaped common electrode on the insulating layer, the common electrode comprising: a first common electrode and a setting covering the data line and having a width larger than the data line a second common electrode above the pixel electrode, wherein the first common electrode is hollowed out corresponding to a region of the data line.
  • Still another embodiment of the present invention provides a display device including an array substrate according to any of the embodiments of the present invention.
  • FIG. 1 is a schematic cross-sectional structural view of a prior art array substrate
  • FIG. 2 is a schematic cross-sectional structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 3 is a second schematic cross-sectional view of an array substrate according to an embodiment of the present invention. detailed description
  • the embodiment of the invention provides an array substrate, a preparation method thereof and a display device, which can greatly reduce the data line load without affecting the transmittance of the pixel, thereby reducing the power consumption of the liquid crystal panel.
  • the array substrate includes: a pixel region defined by a gate line (not shown) and a data line 1 on the base substrate 100, the pixel region. a thin film transistor (not shown) and a pixel electrode 3 are disposed therein; a strip-shaped common electrode 2 that generates an electric field in cooperation with the pixel electrode 3, and the common electrode 2 is disposed above the pixel electrode 3 and the data line 1, And an insulating layer 4 is disposed between the common electrode 2 and the pixel electrode 3 and between the common electrode 2 and the data line 1; the common electrode 2 includes: covering the data line 1 and having a width larger than the data line 1 The first common electrode 21 of the width and the second common electrode 22 disposed above the pixel electrode 3, the first common electrode 21 being hollowed out corresponding to the area of the data line 1.
  • the strip-shaped common electrode 2 is electrically conductive as a whole, that is, the first common electrode 21 and the second common electrode 22 are conductive (not shown in the cross-sectional view).
  • the first common electrode 21 and the second common electrode 22 may be connected to each other at a portion other than the portion shown in the cross-sectional view.
  • any of the above-described pixel electrodes, thin film transistors, data lines, and gate lines may be of any suitable structure in the prior art.
  • the thin film transistor may include a gate, a source, and a drain. The gate of the thin film transistor is connected to the gate line, the source of the thin film transistor is connected to the data line 1, and the drain of the thin film transistor is connected to the pixel electrode 3.
  • the common electrode is completely covered above the data line, causing the load on the data line to be excessive, and the capacitance between the common electrode and the data line covering the data line accounts for power consumption.
  • the ratio is the largest, resulting in a significant increase in power consumption of the entire LCD panel.
  • the first common electrode covering the data line in the array substrate provided by the embodiment has a structure corresponding to the middle of the data line, which can greatly reduce the parasitic capacitance on the data line, thereby reducing power consumption.
  • the arrangement direction of the strip-shaped common electrodes is parallel to the arrangement direction of the data lines, that is, the arrangement direction of the first common electrode 21 and the second common electrode 22 is parallel to the arrangement direction of the data lines.
  • each pixel region (or above each pixel electrode 3) may be included A plurality of second common electrodes 22, as shown in Figures 2 and 3.
  • a plurality of second common electrodes 22 are equally spaced in each pixel region.
  • the strip-shaped common electrodes are formed equidistantly, so that a relatively uniform electric field can be formed with better optical characteristics.
  • the layer where the data line 1 is located and the layer where the common electrode 2 is located A resin layer 5 is provided between the resin layers 5 and a resin material.
  • the resin layer has a low dielectric constant and a relatively large thickness, which greatly improves the adverse effect of the data line on the liquid crystal electric field.
  • the resin material should be a transparent material; and, the above insulating layer 4 should also be a transparent material.
  • the resin layer 5 may be disposed at any layer between the layer where the data line 1 is located and the layer where the common electrode 2 is located; for example, the layer where the data line 1 is located and the pixel
  • the resin layer 5 is disposed between the layers in which the electrodes 3 are located, which can effectively reduce the interference of the data lines on the liquid crystal electric field and does not affect the storage capacitance between the common electrode 2 and the pixel electrodes 3. It will be understood by those skilled in the art that in various embodiments of the present invention, all suitable prior art techniques may be used in other portions, except that the common electrode and its associated design are different from the prior art.
  • the pixel design needs to have a via hole in the resin layer for the connection between the TFT drain and the pixel electrode 3; when the resin layer 5 is disposed at When the pixel electrode 3 and the common electrode 2 are arranged, the drain of the TFT can be directly overlapped with the pixel electrode 3 at the time of pixel design, and therefore, the via design can be omitted. Further, when the resin layer 5 is disposed between the pixel electrode 3 and the common electrode 2, the insulating layer 4 may be omitted.
  • an electric field is formed by the planar pixel electrode at the bottom and the strip-shaped common electrode of the upper portion, and the upper common electrode and the bottom pixel electrode are separated by an insulating layer, and the upper strip-shaped common electrode is included above the data line. And covering the hollowed first common electrode at the edge of the data line and the second common electrode above the pixel electrode.
  • Embodiments of the present invention provide a method for fabricating an array substrate according to the above embodiments. Includes:
  • Step 101 forming a gate line, a data line, a thin film transistor, and a pixel electrode on the base substrate, wherein a gate of the thin film transistor is connected to the gate line, and a source of the thin film transistor is connected to the data line. a drain of the thin film transistor is connected to the pixel electrode;
  • Step 102 forming a strip-shaped common electrode that generates an electric field in cooperation with the pixel electrode on a base substrate on which a gate line, a data line, a thin film transistor, and a pixel electrode are formed, and the common electrode and the pixel electrode are disposed between the pixel electrode Insulation. That is, an insulating layer is formed on the above-mentioned base substrate, and then a strip-shaped common electrode is formed on the insulating layer.
  • the common electrode includes: a first common electrode covering a data line and having a width greater than a width of the data line; and a second common electrode disposed above the pixel electrode, the first common electrode being hollowed out corresponding to a region of the data line.
  • the arrangement direction of the strip-shaped common electrodes is parallel to the arrangement direction of the data lines. That is, the arrangement direction of the first common electrode and the second common electrode is parallel to the arrangement direction of the data lines.
  • the second common electrode is arranged equidistantly in each pixel region. That is, a plurality of second common electrodes arranged equidistantly are disposed directly above each of the pixel electrodes. In the pixel region, the strip-shaped common electrodes are formed equidistantly, so that a relatively uniform electric field can be formed with better optical characteristics.
  • the edge of the first common electrode in order to suppress interference caused by the data line to the liquid crystal electric field, it is necessary to make the edge of the first common electrode sufficiently wide, and the edge of the first common electrode may be connected to the edge of the second common electrode adjacent thereto .
  • the method further includes: needing to be implemented in a corresponding specific step in step 101, such as after forming the data line, before forming the pixel electrode.
  • the resin layer is made of a resin material.
  • the resin layer has a low dielectric constant and a relatively large thickness, and has a great effect on reducing the adverse effect of the data line on the liquid crystal electric field. It will be understood by those skilled in the art that the resin material should be a transparent material; and, the above insulating layer should also be a transparent material.
  • the resin layer is disposed between the layer where the data line is located and the layer where the common electrode is located, specifically: A resin layer is disposed between the layer where the data line is located and the layer where the pixel electrode is located. In this way, the interference caused by the data line to the liquid crystal electric field can be effectively reduced, and the storage capacitance between the common electrode and the pixel electrode is not affected.
  • an electric field is formed by the planar pixel electrode at the bottom and the strip-shaped common electrode of the upper portion, and the upper common electrode and the bottom pixel electrode are separated by an insulating layer, and the upper strip-shaped common electrode is included above the data line. And covering the hollowed first common electrode at the edge of the data line and the second common electrode above the pixel electrode.
  • the embodiment of the invention provides a display device using the array substrate of the first embodiment.
  • the display device may be a liquid crystal panel, a mobile phone, a notebook computer, a liquid crystal display, a navigator or the like. Since the array substrate of the first embodiment is used, the display device can greatly reduce the data line load without affecting the transmittance of the pixel, thereby reducing power consumption.

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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

本发明的实施例提供一种阵列基板，包括：基底基板；形成于所述基底基板上的栅线和数据线，所述栅线和所述数据线相互交叉以限定像素区域；薄膜晶体管和像素电极，设置在所述像素区域内；条状的公共电极，设置在所述像素电极和所述数据线上方，所述公共电极包括覆盖在所述数据线上方且宽度大于所述数据线的宽度的第一公共电极和设置在像素电极上方的第二公共电极；绝缘层，设置在所述公共电极与所述像素电极之间以及所述公共电极和所述数据线之间，其中所述第一公共电极对应于数据线的区域镂空。

Description

阵列基板及其制备方法和显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制备方法和显示装置。 背景技术
高级超维场开关技术（ Advanced Super Dimension Switch, 简称为 ADS ) 是通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层 间产生的电场形成多维电场， 使液晶盒内狭缝电极间、 电极正上方所有取向 的液晶分子都能够产生旋转， 从而提高了液晶工作效率并增大了透光效率。 高级超维场开关技术可以提高薄膜晶体管液晶显示器（TFT-LCD )产品的画 面品质， 使之具有高分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低色 差、 无挤压水波紋（Push Mura )等优点。 在现有的 ADS模式液晶显示器中， 公共电极和像素电极由透明导体制成， 从而增加了开口率和透光率， 并且公 共电极和像素电极之间所形成的空间比上、 下基板间的空间更狭窄， 从而在 公共电极和像素电极之间形成边缘电场， 使得液晶分子在平行于基板的平面 方向上发生旋转转换， 从而提高液晶层的透光效率。
为了避免数据线上方的遮光区对开口率的影响， 提高像素的透过率， 现 有技术提供一种像素结构， 如图 1所示， 去掉数据线 1上方的遮光区， 设置 与数据线 1相平行的条状的公共电极 2。 一部分条状的公共电极 2设置在像 素电极 3上方， 另一部分条状的公共电极 2覆盖在数据线 1上方， 并且宽度 大于数据线 1的宽度。 通过在数据线 1上方形成公共电极 2的覆盖来抑制数 据线 1对液晶电场的干扰， 防止发生漏光等不利影响， 进而提高像素的透过 率。
然而， 发明人发现现有技术的像素结构在数据线上的负载过大， 并且覆 盖在数据线上的公共电极与数据线之间的电容在功耗方面占比最大， 造成整 个液晶面板的功耗大大增加。 发明内容 本发明的一个实施例提供一种阵列基板， 包括： 基底基板； 形成于所述 基底基板上的栅线和数据线， 所述栅线和所述数据线相互交叉以限定像素区 域； 薄膜晶体管和像素电极， 设置在所述像素区域内； 条状的公共电极， 设 置在所述像素电极和所述数据线上方， 所述公共电极包括覆盖在所述数据线 上方且宽度大于所述数据线的宽度的第一公共电极和设置在像素电极上方的 第二公共电极； 绝缘层， 设置在所述公共电极与所述像素电极之间以及所述 公共电极和所述数据线之间， 其中所述第一公共电极对应于数据线的区域镂 空。
本发明的另一个实施例提供一种阵列基板的制备方法， 包括： 在基底基 板上形成栅线、 数据线、 薄膜晶体管和像素电极， 且所述薄膜晶体管的栅极 与所述栅线连接、 所述薄膜晶体管的源极与所述数据线连接、 所述薄膜晶体 管的漏极与所述像素电极连接； 以及在形成有所述栅线、 所述数据线、 所述 薄膜晶体管和所述像素电极的基底基板上形成绝缘层， 并在所述绝缘层上形 成条状的公共电极， 所述公共电极包括： 覆盖在所述数据线上方且宽度大于 所述数据线的第一公共电极和设置在所述像素电极上方的第二公共电极， 其 中所述第一公共电极对应于数据线的区域镂空。
本发明的再一个实施例提供一种显示装置， 该显示装置包括根据本发明 任一实施例的阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术阵列基板的剖面结构示意图；
图 2为本发明实施例中阵列基板的剖面结构示意图之一；
图 3为本发明实施例中阵列基板的剖面结构示意图之二。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例提供一种阵列基板及其制备方法和显示装置， 能够在不影 响像素的透过率的前提下， 大大降低数据线负载，从而减小液晶面板的功耗。
实施例一
本发明实施例提供一种阵列基板， 如图 2所示， 该阵列基板包括： 在基 底基板 100上由栅线（图中未示出）和数据线 1交叉限定的像素区域， 所述 像素区域内设有薄膜晶体管（图中未示出）和像素电极 3; 与所述像素电极 3 配合产生电场的条状的公共电极 2, 所述公共电极 2设置在像素电极 3和数 据线 1上方， 且在所述公共电极 2与所述像素电极 3之间以及公共电极 2和 数据线 1之间设有绝缘层 4; 所述公共电极 2包括： 覆盖在数据线 1上方且 宽度大于数据线 1的宽度的第一公共电极 21和设置在像素电极 3上方的第二 公共电极 22, 所述第一公共电极 21对应于数据线 1的区域镂空。 也就是说， 第一公共电极 21在数据线 1正上方的部分被去除。本领域的技术人员可以理 解，条状的公共电极 2整体上是导通的， 即第一公共电极 21和第二公共电极 22是导通的 （截面图中未示出） 。 例如， 第一公共电极 21和第二公共电极 22可以在截面图所示部分之外的部分相互连接。
另外， 上述像素电极、 薄膜晶体管、 数据线和栅线等部分均可以釆用现 有技术中任何合适的结构。 例如， 薄膜晶体管可以包括栅极、 源极和漏极。 薄膜晶体管的栅极与栅线连接， 薄膜晶体管的源极与数据线 1连接， 而薄膜 晶体管的漏极与像素电极 3连接。
由于在现有技术提供的方案中， 将公共电极完全覆盖在数据线上方， 造 成数据线上的负载过大， 并且覆盖在数据线上的公共电极与数据线之间的电 容在功耗方面占比最大， 导致整个液晶面板的功耗大大增加。 本实施例提供 的阵列基板中覆盖在数据线上的第一公共电极釆用对应于数据线的区域是中 间镂空的结构， 这样能大大降低数据线上的寄生电容， 从而降低功耗。
优选地， 条状公共电极的排布方向平行于数据线的排布方向， 即所述第 一公共电极 21和第二公共电极 22的排布方向平行于数据线的排布方向。
进一步地， 在每个像素区域内 （或者在每个像素电极 3上方） 可以包括 多个第二公共电极 22, 如图 2和 3所示。 在每一个像素区域内多个第二公共 电极 22等距排布。在像素区域内，条状的公共电极形成等距排布， 因此能够 形成比较均匀的电场， 具有更好的光特性。
再进一步地， 如图 3所示， 为了抑制数据线 1对液晶电场造成的干扰， 需要将第一公共电极 21的边缘做的足够宽， 可以将所述第一公共电极 21的 边缘与与其相邻的第二公共电极 22的边缘相连接。
进一步地，如图 2和图 3所示，为了防止第一公共电极 21镂空后数据线 1对液晶电场造成的干扰， 在所述数据线 1所在的层与所述公共电极 2所在 的层之间设置一层树脂层 5, 该树脂层 5釆用树脂材料。 树脂层具有较低的 介电常数和比较大的厚度， 对于降低数据线对液晶电场的不利影响有很大的 改善作用。 本领域的技术人员可以理解， 所述树脂材料应为透明材料； 并且， 上述绝缘层 4也应为透明材料。
需要说明的是， 树脂层 5可以设置在所述数据线 1所在的层与所述公共 电极 2所在的层之间的任意一层； 例如， 在所述数据线 1所在的层与所述像 素电极 3所在的层之间设置树脂层 5, 能够有效减少数据线对液晶电场造成 的干扰， 并且不会影响到公共电极 2与像素电极 3之间的存储电容。 本领域 的技术人员可以理解， 本发明各实施例中， 除了公共电极及其关联设计与现 有技术不同之外， 其他部分均可以使用所有合适的现有技术。 比如： 当树脂 层 5设置在数据线 1和像素电极 3之间的时候， 像素设计上需要在树脂层上 开设过孔， 用于 TFT漏极与像素电极 3的连接； 当树脂层 5设置在像素电极 3和公共电极 2之间的时候， 在像素设计时， TFT的漏极可以跟像素电极 3 直接搭接， 因此， 可以不做过孔设计。 另外， 当树脂层 5设置在像素电极 3 和公共电极 2之间的时候， 也可以省略绝缘层 4。
在本实施例的技术方案中， 由底部的面状像素电极和上部的条状公共电 极形成电场， 上部公共电极和底部像素电极通过绝缘层隔开， 上部的条状公 共电极包括在数据线上方且覆盖数据线边缘的镂空的第一公共电极和像素电 极上方的第二公共电极。通过这样的设计方案，既能够不影响像素的透过率， 又能大大降低数据线负载， 从而减小液晶面板的功耗。
实施例二
本发明实施例提供一种上述实施例所述的阵列基板的制备方法， 该方法 包括：
步骤 101、 在基底基板上形成栅线、 数据线、 薄膜晶体管和像素电极， 且所述薄膜晶体管的栅极与所述栅线连接、 所述薄膜晶体管的源极与所述数 据线连接、 所述薄膜晶体管的漏极与所述像素电极连接；
步骤 102、 在形成有栅线、 数据线、 薄膜晶体管和像素电极的基底基板 上形成与所述像素电极配合产生电场的条状的公共电极， 所述公共电极与所 述像素电极之间设有绝缘层。 也就是说， 先在上述基底基板上形成绝缘层， 然后在绝缘层上形成条状的公共电极。 所述公共电极包括： 覆盖在数据线上 方且宽度大于数据线的宽度的第一公共电极和设置在像素电极上方的第二公 共电极， 所述第一公共电极对应于数据线的区域镂空。
进一步地， 所述条状的公共电极的排布方向平行于所述数据线的排布方 向。 即所述第一公共电极和第二公共电极的排布方向平行于数据线的排布方 向。
进一步地， 所述第二公共电极在每一个像素区域内为等距排布。 也就是 说， 在每个像素电极的正上方设置有等距排布的多个第二公共电极。 在像素 区域内， 条状的公共电极形成等距排布， 因此能够形成比较均匀的电场， 具 有更好的光特性。
进一步地， 为了抑制数据线对液晶电场造成的干扰， 需要将第一公共电 极的边缘做的足够宽， 可以将所述第一公共电极的边缘与与其相邻的第二公 共电极的边缘相连接。
进一步地，为了防止第一公共电极镂空后数据线对液晶电场造成的干扰， 该方法还包括： 骤需要在步骤 101中的相应具体步骤中实现， 比如形成数据线之后、 形成像 素电极之前。
该树脂层釆用树脂材料。该树脂层具有较低的介电常数和比较大的厚度， 对于降低数据线对液晶电场的不利影响有很大的改善作用。 本领域的技术人 员可以理解， 所述树脂材料应为透明材料； 并且， 上述绝缘层也应为透明材 料。
在数据线所在的层与公共电极所在的层之间设置树脂层具体为： 在数据线所在的层与像素电极所在的层之间设置树脂层。 这样， 能够有 效减少数据线对液晶电场造成的干扰， 并且不会影响到公共电极与像素电极 之间的存储电容。
在本实施例的技术方案中， 由底部的面状像素电极和上部的条状公共电 极形成电场， 上部公共电极和底部像素电极通过绝缘层隔开， 上部的条状公 共电极包括在数据线上方且覆盖数据线边缘的镂空的第一公共电极和像素电 极上方的第二公共电极。通过这样的设计方案，既能够不影响像素的透过率， 又能大大降低数据线负载， 从而减小液晶面板的功耗。
实施例三
本发明实施例提供一种显示装置， 使用了实施例一所述的阵列基板。 该 显示装置可以是液晶面板、 手机、 笔记本电脑、 液晶显示器、 导航仪等。 由 于釆用了实施例一中的阵列基板， 所述显示装置可以在不影响像素的透过率 的情况下， 大大降低数据线负载， 从而减小功耗。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护 范围应以所述权利要求的保护范围为准。

Claims

权利要求书
1、 一种阵列基板， 包括：
基底基板；
形成于所述基底基板上的栅线和数据线， 所述栅线和所述数据线相互交 叉以限定像素区域；
薄膜晶体管和像素电极， 设置在所述像素区域内；
条状的公共电极， 设置在所述像素电极和所述数据线上方， 所述公共电 极包括覆盖在所述数据线上方且宽度大于所述数据线的宽度的第一公共电极 和设置在像素电极上方的第二公共电极；
绝缘层， 设置在所述公共电极与所述像素电极之间以及所述公共电极和 所述数据线之间，
其中所述第一公共电极对应于数据线的区域镂空。
2、 根据权利要求 1所述的阵列基板， 其中，
3、 根据权利要求 2所述的阵列基板， 其中，
在每一个像素区域内包括多个第二公共电极， 所述多个第二公共电极在 每一个像素区域内等距排布。
4、 根据权利要求 3所述的阵列基板， 其中，
所述第一公共电极的边缘与与其相邻的第二公共电极的边缘相连接。
5、 根据权利要求 1所述的阵列基板， 其中，
置有树脂层 t
6、 根据权利要求 2所述的阵列基板， 其中,
置有树脂层 t
7、 根据权利要求 3所述的阵列基板， 其中,
置有树脂层 t
8、 根据权利要求 4所述的阵列基板， 其中,
置有树脂层 t
9、 根据权利要求 5所述的阵列基板， 其中，
所述树脂层设置在所述数据线所在的层与所述像素电极所在的层之间
10、 一种阵列基板的制备方法， 包括：
在基底基板上形成栅线、 数据线、 薄膜晶体管和像素电极， 且所述薄膜 晶体管的栅极与所述栅线连接、 所述薄膜晶体管的源极与所述数据线连接、 所述薄膜晶体管的漏极与所述像素电极连接； 以及
在形成有所述栅线、 所述数据线、 所述薄膜晶体管和所述像素电极的基 底基板上形成绝缘层， 并在所述绝缘层上形成条状的公共电极， 所述公共电 极包括： 覆盖在所述数据线上方且宽度大于所述数据线的宽度的第一公共电 极和设置在所述像素电极上方的第二公共电极，
其中所述第一公共电极对应于数据线的区域镂空。
11、 根据权利要求 10所述的方法， 其中，
12、 根据权利要求 11所述的方法， 其中，
在所述像素电极的正上方设置有等距排布的多个第二公共电极。
13、 根据权利要求 12所述的方法， 其中，
所述第一公共电极的边缘与与其相邻的第二公共电极的边缘相连接。
14、 根据权利要求 10所述的方法， 还包括：
15、根据权利要求 14所述的方法， 其中， 所述在所述数据线所在的层与 所述公共电极所在的层之间设置树脂层的步骤包括：
在形成所述数据线之后且在形成所述像素电极之前， 在所述基底基板上 形成所述树脂层， 以使得所述树脂层设置在所述数据线所在的层与所述像素 电极所在的层之间。
16、 一种显示装置， 包括阵列基板， 该阵列基板包括：
基底基板；
形成于所述基底基板上的栅线和数据线， 所述栅线和所述数据线相互交 叉以限定像素区域；
薄膜晶体管和像素电极， 设置在所述像素区域内；
条状的公共电极， 设置在所述像素电极和所述数据线上方， 所述公共电 极包括覆盖在所述数据线上方且宽度大于所述数据线的宽度的第一公共电极 和设置在像素电极上方的第二公共电极； 绝缘层， 设置在所述公共电极与所述像素电极之间以及所述公共电极和 所述数据线之间，
其中所述第一公共电极对应于数据线的区域镂空。
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