WO2016119344A1 - 阵列基板及其制造方法和显示面板 - Google Patents

阵列基板及其制造方法和显示面板 Download PDF

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Publication number
WO2016119344A1
WO2016119344A1 PCT/CN2015/079320 CN2015079320W WO2016119344A1 WO 2016119344 A1 WO2016119344 A1 WO 2016119344A1 CN 2015079320 W CN2015079320 W CN 2015079320W WO 2016119344 A1 WO2016119344 A1 WO 2016119344A1
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layer
array substrate
wire
conductive layer
metal
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PCT/CN2015/079320
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English (en)
French (fr)
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张洁
李付强
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US14/907,635 priority Critical patent/US20160372490A1/en
Publication of WO2016119344A1 publication Critical patent/WO2016119344A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display panel.
  • the display panel of the flat panel display has become the mainstream of current display products due to factors such as lightness, thinness and low radiation.
  • the display panel of the narrow bezel is beautiful in appearance and is advantageous for realizing the splicing of large-size display products. Therefore, the narrow bezel design of the display panel has become an important trend in the development of the display field.
  • the implementation of the narrow bezel of the display panel is mainly as follows: one is to reduce the line width and the line spacing of the signal lines in the non-display area of the display panel; the second is to reduce the number of components or the component size in the gate driving circuit. Thereby compressing the space occupied by the gate drive circuit.
  • the implementation is limited by the alignment error, the mura defect, and the process stability, it is difficult to achieve a large space saving of the signal line in the non-display area of the display panel;
  • reducing the number of components or the size of the components in the gate driving circuit requires consideration of signal stability and antistatic capability, and thus it is difficult to improve the gate driving circuit.
  • Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display panel, which can realize a display panel with a narrow bezel and are easy to implement, thereby reducing the manufacturing difficulty of the narrow bezel display panel.
  • an embodiment of the present invention provides an array substrate, including: a substrate substrate including a display region and a non-display region; and a metal conductive layer, an insulating layer over the metal conductive layer, and an auxiliary layer above the insulating layer a conductive layer, which is sequentially formed on the base substrate, wherein the metal conductive layer includes a plurality of first wires, the auxiliary conductive layer includes a plurality of second wires, and each of the plurality of first wires corresponds to At least one of the plurality of second wires, each of the plurality of second wires being electrically connected to the corresponding first wire via a connection structure in the insulating layer, the vertical projection of the connection structure being located The non-display area.
  • an embodiment of the present invention provides a display panel comprising: the array as provided above a substrate; and a counter substrate, the pair of the array substrate.
  • an embodiment of the present invention provides a method of fabricating an array substrate, comprising: preparing a substrate, wherein the substrate includes a display region and a non-display region; forming a metal conductive layer on the substrate
  • the metal conductive layer includes a plurality of first conductive lines; an insulating layer is formed over the metal conductive layer, a plurality of connection structures are formed in the insulating layer, and a vertical projection of the connection structure is located in the non-display area
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural view of an insulating layer according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a first specific array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a second specific array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a third specific array substrate according to an embodiment of the present invention.
  • an embodiment of the present invention provides an array substrate, including: a substrate substrate 1 including a display region and a non-display region; and a metal conductive layer sequentially formed on the substrate substrate 1 and an insulating layer above the metal conductive layer. 3 and an auxiliary conductive layer above the insulating layer 3; the metal conductive layer comprises a plurality of first wires 2, the auxiliary conductive layer comprises a plurality of second wires 4, each of the first wires 2 corresponding to at least one second wire 4; the second wire 4 electrically connected to the corresponding first wire 2 via the connecting structure 5 in the insulating layer 3
  • the vertical projection of the connection structure 5 is located in the non-display area of the array substrate.
  • vertical projection refers to projection in the thickness direction of the array substrate.
  • each of the first wires 2 may include at least a portion located in the non-display area, and further, the first conductive 2 may further include a portion located in the display area, and the second wire 4 is insulated.
  • the connection structure 5 in the layer 3 is electrically connected to the corresponding first wire 2, which may be a portion where the second wire 4 is electrically connected to the corresponding first wire 2 in the non-display area.
  • the first wire 2 of the metal conductive layer of the array substrate extends to the auxiliary conductive layer through the second wire 4 electrically connected thereto, so that the trace of the first wire 2 originally in the non-display area can be transferred to
  • the auxiliary conductive layer can reduce the area or width of the non-display area, and when the array substrate is applied to the display panel, the difficulty of realizing the display panel of the narrow bezel can be reduced.
  • the connecting structure 5 in FIG. 1 may be a via 51, and the second wire 4 is electrically connected to the corresponding first wire 2 through the hole 51; and/or, the connecting structure 5 may be a slit 52, and the second wire 4 is in the slit 52.
  • the corresponding first wire 2 is covered. 2 shows a schematic structural view of the insulating layer 3, which includes a via 51 and a slit 52, and of course may include only one of the via 51 and the slit 52.
  • a thin film transistor is generally formed on the array substrate.
  • the thin film transistor includes a source/drain metal layer and a gate metal layer.
  • the source and drain metal layers and the gate metal layer each include a large number of signal lines or components (such as a source of a thin film transistor). Electrode, drain electrode and gate electrode).
  • the source/drain metal layer may include a source electrode, a drain electrode, a data line, a power supply signal line, and the like
  • the gate metal layer may include a gate electrode, a gate line, a common electrode line, and the like.
  • the metal conductive layer in this embodiment is not limited to a single metal layer.
  • the metal conductive layer may be a single metal layer or a combination of multiple metal layers. When a plurality of metal layers are combined, each metal layer is insulated from each other; for example, the metal conductive layer may be a source/drain metal layer, and the first wire 2 may be at least one of a data line, a power signal line, and a ground line; Alternatively, the metal conductive layer may be a gate metal layer, and the first conductive line 2 may be at least one of a gate line and a common electrode line; or the metal conductive layer may be a combination of a source/drain metal layer and a gate metal layer.
  • a gate insulating layer is usually disposed between the source drain metal layer and the gate metal layer for insulation, and the first wire 2 may be at least one of a plurality of wires included in the source/drain metal layer and/or the gate metal layer.
  • the first wire 2 is a data line, a gate line, a power signal line, a ground line, a common electrode line, a clock signal line, a gate drive signal line, a DC control signal line, and an AC control signal line. At least one. After the first wire 2 is electrically connected to the second wire 4, the occupation of the first wire 2 in the non-display area of the source/drain metal layer and/or the gate metal layer can be reduced.
  • the insulating layer 3 above the metal conductive layer may be a passivation layer, a planarization layer, or a combination of a planarization layer and a passivation layer, and the passivation layer may be oxidized. Any one of a silicon film layer and a silicon nitride film layer or a composite film layer, and the planarization layer may be a polymethyl methacrylate film layer.
  • the insulating layer 3 above the metal conductive layer and the auxiliary conductive layer above the insulating layer 3 in the embodiment means that the insulating layer 3 may be formed on the metal conductive layer and contact each other, or may be the insulating layer 3 and the metal. There are other layers between the conductive layers.
  • the auxiliary conductive layers may be formed on the insulating layer 3 and contact each other, or the auxiliary conductive layer and the insulating layer 3 may have other layers; for example, the TFT on the array substrate is a bottom gate type, if The metal conductive layer includes only the gate metal layer, and the insulating layer 3 is a passivation layer, and the gate insulating layer, the active layer, and the source/drain metal layer may be sequentially disposed between the gate metal layer and the passivation layer; for example, The TFT on the array substrate is a bottom gate type.
  • the insulating layer 3 is a passivation layer, and the passivation layer is usually formed on the source and drain metal layers, the insulating layer 3 is formed on Above the metal conductive layer and in direct contact; for example, the TFT on the array substrate is a top gate type, if the metal conductive layer only includes a gate metal layer, the insulating layer 3 is a passivation layer, and the passivation layer is usually formed on the gate metal Above the layer, the insulating layer 3 Formed on the metal conductive layer and directly contact; for example, the TFT on the array substrate is a top gate type, if the metal conductive layer only includes the source and drain metal layers, the insulating layer 3 is a passivation layer, the source and drain metal layers and An active layer, a gate insulating layer and a gate metal layer are sequentially disposed between the passivation layers; for example, the TFT on the array substrate is a top gate type, and if the metal conductive layer
  • the insulating layer 3 is formed on the metal conductive layer and directly contacts.
  • the source and drain metal layers of the metal conductive layer here.
  • a gate insulating layer is required to be insulated from the gate metal layer.
  • the array substrate shown in FIGS. 3 to 5 is described in detail as follows:
  • the array substrate includes a TFT 6, and the TFT 6 includes a gate electrode 61, a source electrode 62, and a drain electrode. 63 and the active layer 64, the source electrode 62 and the drain electrode 63 are in the source-drain metal layer, the gate electrode 61 is in the gate metal layer, and the source-drain metal layer and the gate metal layer are disposed. Gate insulating layer 7.
  • the first wire 2 is disposed only on the source and drain metal layers, that is, the first wire 2 is disposed in the same layer as the source electrode 62 and the drain electrode 63.
  • the first wire 2 may be a data line, a power signal line, and a ground. At least one of a line, a clock signal line, and a common electrode line. Each of the first wires 2 is electrically connected to the corresponding second wire 4 through a via 51 and a slit 52, respectively.
  • the case where the first wire 2 is disposed only on the gate metal layer is similar to the structure of FIG. 3 and will not be described herein.
  • the structure of the TFT 6 is not limited to the bottom gate type shown in FIG. 3, and may also be a top gate type or other structure.
  • the TFT of the top gate type or other structure is also applicable to the embodiment, and the second wire 4 is
  • the material may be a transparent conductive material such as indium tin oxide (ITO), and thus does not affect the pixel aperture ratio of the array substrate.
  • ITO indium tin oxide
  • the array substrate includes a TFT 6, and the TFT 6 includes a gate electrode 61, a source electrode 62, and a drain electrode. 63 and the active layer 64, the source electrode 62 and the drain electrode 63 are in the source and drain metal layers, the gate electrode 61 is in the gate metal layer, and the gate insulating layer is provided between the source and drain metal layers and the gate metal layer.
  • Layer 7 the same reference numerals as in FIG. 3 have the same meanings
  • the first wire 2 is disposed on the source and drain metal layers and the gate metal layer, that is, a portion of the first wire 2 is disposed in the same layer as the source electrode 62 and the drain electrode 63, and the first wire 2 and the gate electrode 61 are partially disposed.
  • the second wire 4 may be at least one of a data line, a power signal line, a ground line, a gate line, a clock signal line, and a common electrode line.
  • Each of the first wires 2 is electrically connected to the corresponding second wire 4 through a via 51 and a slit 52, respectively. It is to be noted that the structure of the TFT 6 is not limited to the bottom gate type shown in FIG.
  • the material of the second wire 4 may be a transparent conductive material, for example, indium tin oxide (ITO), at the electrical connection of the second wire 4 and the first wire 2, the second wire 4 is opposite to the first wire 2
  • ITO indium tin oxide
  • the insulating layer 3 in the array substrate shown in FIG. 3 and FIG. 4 may be only a passivation layer or only a planarization layer, and may of course be a combination of a passivation layer and a planarization layer.
  • FIG. 5 a schematic structural view of a third specific array substrate is shown.
  • the array substrate shown in FIG. 5 has a similar structure to the array substrate shown in FIG. 4, except that the array substrate shown in FIG.
  • the insulating layer 3 includes a flat layer 31 and a passivation layer 32, although the order of lamination of the planarization layer 31 and the passivation layer 32 may be interchanged.
  • the second wire 4 may be designed as a hollow structure, and the pattern of the hollow structure may be flexible.
  • the second wire 4 may be formed with a square or circular hole or Cut off the part.
  • the beneficial effects of the embodiment of the present invention are as follows: the first conductive wire of the metal conductive layer of the array substrate extends to the auxiliary conductive layer through the second conductive wire electrically connected thereto, so that the trace of the first conductive wire originally in the non-display area can be transferred to the auxiliary conductive Layer, which can reduce the space occupied by the first wire in the non-display area of the metal conductive layer, thereby reducing the area or width of the non-display area, and facilitating the display panel of the narrow frame; meanwhile, the array substrate should be narrow When the display panel of the bezel is not required to adjust the line width or line spacing in the non-display area, there is no need to improve the gate driving circuit, which is easy to implement and low in cost.
  • the embodiment of the invention further provides a display panel comprising the array substrate provided in the above embodiments.
  • the beneficial effects of the embodiment of the present invention are as follows: the first conductive wire of the metal conductive layer of the array substrate extends to the auxiliary conductive layer through the second conductive wire electrically connected thereto, so that the trace of the first conductive wire originally in the non-display area can be transferred to the auxiliary conductive Layer, which can reduce the space occupied by the first wire in the non-display area of the metal conductive layer, thereby reducing the area or width of the non-display area, and facilitating the display panel of the narrow frame; meanwhile, the array substrate should be narrow When the display panel of the bezel is not required to adjust the line width or line spacing in the non-display area, there is no need to improve the gate driving circuit, which is easy to implement and low in cost.
  • the embodiment of the invention provides a display device, which comprises the display panel provided in the above embodiment.
  • the beneficial effects of the embodiment of the present invention are as follows: the first conductive wire of the metal conductive layer of the array substrate extends to the auxiliary conductive layer through the second conductive wire electrically connected thereto, so that the trace of the first conductive wire originally in the non-display area can be transferred to the auxiliary conductive Layer, which can reduce the space occupied by the first wire in the non-display area of the metal conductive layer, thereby reducing the area or width of the non-display area, and facilitating the display panel of the narrow frame; meanwhile, the array substrate should be narrow When the display panel of the bezel is not required to adjust the line width or line spacing in the non-display area, there is no need to improve the gate driving circuit, which is easy to implement and low in cost.
  • an embodiment of the present invention further provides a method for manufacturing an array substrate, including:
  • Step 601 preparing a substrate, wherein the substrate comprises a display area and a non-display area;
  • Step 602 forming a metal conductive layer on the base substrate, the metal conductive layer comprising a plurality of first wires.
  • the metal conductive layer may include any one or combination of a gate metal layer and a source/drain metal layer.
  • the metal conductive layer includes a combination of a gate metal layer and a source and drain metal layer, the gate metal layer There should be a gate insulating layer between the source and drain metal layers. This also means that the first wire may be formed only on the gate metal layer, or only on the source/drain metal layer, or on the gate metal layer and the source and drain metal layers.
  • Step 603 forming an insulating layer over the metal conductive layer, wherein a plurality of connection structures are formed in the insulating layer, and a vertical projection of the connection structure is located in the non-display area.
  • Step 604 forming an auxiliary conductive layer above the insulating layer, the auxiliary conductive layer includes a plurality of second wires, and the second wires are electrically connected to the corresponding first wires via the connection structure.
  • the insulating layer 3 above the metal conductive layer and the auxiliary conductive layer above the insulating layer 3 in the embodiment means that the insulating layer 3 may be formed on the metal conductive layer and contact each other, or may be an insulating layer. 3 There are other layers between the metal conductive layer, and the auxiliary conductive layer may be formed on the insulating layer 3 and in contact with each other, or the auxiliary conductive layer and the insulating layer 3 may have other layers. Therefore, according to different structures or hierarchical structures of the TFTs on the array substrate, some adjustments may be made on the basis of the manufacturing method provided in this embodiment, which is still within the protection scope of the embodiments of the present invention, and details are not described herein again.
  • the beneficial effects of the embodiments of the present invention are as follows: the first wire of the metal conductive layer of the array substrate extends to the auxiliary conductive layer through the second wire electrically connected thereto, so that the first wire is originally transferred to the auxiliary conductive layer in the non-display area In this way, the space occupied by the first wire in the non-display area of the metal conductive layer can be reduced, thereby reducing the area or width of the non-display area, and the display panel of the narrow frame is facilitated; meanwhile, the array substrate should be in a narrow frame. In the display panel, since it is not necessary to adjust the line width or line spacing in the non-display area, there is no need to improve the gate driving circuit, so it is easy to implement and low in cost.

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Abstract

一种阵列基板及其制备方法和显示面板被提供，该阵列基板，包括：衬底基板（1），包括显示区和非显示区；以及金属导电层、所述金属导电层上方的绝缘层（3）和所述绝缘层（3）上方的辅助导电层，依次形成于所述衬底基板（1）上，其中所述金属导电层包括多条第一导线（2），所述辅助导电层包括多条第二导线（4），所述多条第一导线（2）中每条对应所述多条第二导线（4）中至少之一，所述多条第二导线（4）中每条经所述绝缘层（3）中的连接结构（51，52）与相对应的所述第一导线（2）电连接，所述连接结构（51，52）的垂直投影位于所述非显示区内。上述结构能够实现窄边框的显示面板，从而降低窄边框显示面板的制造难度。

Description

阵列基板及其制造方法和显示面板 技术领域
本发明的实施例涉及一种阵列基板及其制造方法和显示面板。
背景技术
如今，平板显示器由于轻、薄、低辐射等因素，已经成为目前显示产品的主流。对于平板显示器的显示面板而言，窄边框的显示面板外形美观且有利于实现拼接大尺寸显示产品，因此，显示面板的窄边框设计已成为显示领域发展的重要趋势。
目前，显示面板的窄边框的实现主要有如下方式：一是减小显示面板的非显示区内的信号线的线宽和线间距；二是减少栅极驱动电路中的元件数量或元件尺寸，从而压缩栅极驱动电路所占用的空间。
但是，对于第一种方式，由于其实现受到对准误差、mura不良和工艺稳定性等方面的限制，实现大幅节省显示面板的非显示区内的信号线所占用的空间比较困难；第二种方式中，减少栅极驱动电路中的元件数量或元件尺寸需要考虑信号稳定性和抗静电能力，因此难以改进栅极驱动电路。
发明内容
本发明的实施例提供一种阵列基板及其制造方法和显示面板，能够实现窄边框的显示面板且易于实现，从而降低窄边框显示面板的制造难度。
一方面，本发明的实施例提供一种阵列基板，包括：衬底基板，包括显示区和非显示区；以及金属导电层、所述金属导电层上方的绝缘层和所述绝缘层上方的辅助导电层，依次形成于所述衬底基板上，其中所述金属导电层包括多条第一导线，所述辅助导电层包括多条第二导线，所述多条第一导线中每条对应所述多条第二导线中至少之一，所述多个第二导线中每条经所述绝缘层中的连接结构与相对应的所述第一导线电连接，所述连接结构的垂直投影位于所述非显示区内。
另一方面，本发明的实施例提供一种显示面板，包括：如上提供的阵列 基板；以及对置基板，与所述阵列基板对盒。
再一方面，本发明的实施例提供一种阵列基板的制造方法，包括：准备衬底基板，其中所述衬底基板包括显示区和非显示区；在所述衬底基板上形成金属导电层，所述金属导电层包括多条第一导线；在所述金属导电层上方形成绝缘层，所述绝缘层中形成有多个连接结构，所述连接结构的垂直投影位于所述非显示区内；以及在所述绝缘层上方形成辅助导电层，所述辅助导电层包括多条第二导线，所述第二导线经所述连接结构与相对应的所述第一导线电连接。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明实施例提供的阵列基板的结构示意图；
图2为本发明实施例提供绝缘层的结构示意图；
图3为本发明实施例提供的第一种具体的阵列基板的结构示意图；
图4为本发明实施例提供的第二种具体的阵列基板的结构示意图；以及
图5为本发明实施例提供的第三种具体的阵列基板的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
参见图1，本发明实施例提供一种阵列基板，包括：衬底基板1，包括显示区和非显示区；以及依次形成于衬底基板1上的金属导电层、金属导电层上方的绝缘层3和绝缘层3上方的辅助导电层；金属导电层包括多条第一导线2，辅助导电层包括多条第二导线4，每一条第一导线2对应至少一条第二导线4；第二导线4经绝缘层3中的连接结构5与相对应的第一导线2电连 接，连接结构5的垂直投影位于阵列基板的非显示区内。
这里，应注意的是，垂直投影是指在阵列基板的厚度方向上的投影。
在本发明的实施例中，每条第一导线2可以至少包括位于所述非显示区的部分，进一步地，所述第一导电2还可以包括位于显示区的部分，第二导线4经绝缘层3中的连接结构5与相对应的第一导线2电连接可以是第二导线4电连接到相对应的第一导线2位于所述非显示区的部分。
本发明实施例中，阵列基板的金属导电层的第一导线2通过与之电连接的第二导线4延伸至辅助导电层，这样，第一导线2原本在非显示区的走线可以转移至辅助导电层，从而可以减少非显示区的面积或宽度，该阵列基板应用于显示面板时，可以降低实现窄边框的显示面板的难度。
图1中的连接结构5可以为过孔51，第二导线4经过孔51与相对应的第一导线2电连接；和/或，连接结构5可以为切口52，第二导线4在切口52处覆盖相对应的第一导线2。图2示出了绝缘层3的结构示意图，绝缘层3包括过孔51和切口52，当然也可以仅包括过孔51和切口52中的一种。
阵列基板上通常形成有薄膜晶体管(TFT)，薄膜晶体管包括源漏极金属层和栅极金属层，源漏极金属层和栅极金属层均包括大量的信号线或元件(如薄膜晶体管的源电极、漏电极和栅电极)。源漏极金属层可以包括源电极、漏电极、数据线和电源信号线等，栅极金属层可以包括栅极、栅线和公共电极线等。本实施例中的金属导电层并非限定为单一的一个金属层，根据不同的阵列基板的结构或设计要求，金属导电层可以为单一的金属层或多个金属层的组合，当金属导电层为多个金属层的组合时，各个金属层是彼此绝缘的；例如：金属导电层可以是源漏极金属层，第一导线2可以为数据线、电源信号线和接地线中的至少一种；或者，金属导电层可以是栅极金属层，第一导线2可以为栅线和公共电极线中的至少一种；或者，金属导电层可以是源漏极金属层和栅极金属层的组合，当然源漏极金属层和栅极金属层之间通常设置有栅极绝缘层实现绝缘，第一导线2可以为源漏极金属层和/或栅极金属层所包括多种导线中的至少一种，例如第一导线2为数据线、栅线、电源信号线、接地线、公共电极线、时钟信号线、栅极驱动信号线、直流控制信号线和交流控制信号线中的至少一种。第一导线2与第二导线4电连接后，可以减少第一导线2在源漏极金属层和/或栅极金属层的非显示区的占用的 走线空间，同时，由第二导线4作为第一导线2的延伸线，能够增强第一导线2的抗静电能力。相应的，基于阵列基板的结构，在金属导电层上方的绝缘层3可以为钝化层，也可以为平坦化层，也可以为平坦化层和钝化层的组合，钝化层可以为氧化硅膜层和氮化硅膜层中的任意一种或复合膜层，平坦化层可以为聚甲基丙烯酸甲酯膜层。此外，本实施例中的金属导电层上方的绝缘层3和绝缘层3上方的辅助导电层，是指绝缘层3可以形成于金属导电层之上并相互接触，也可以是绝缘层3与金属导电层之间存在其他层，辅助导电层可以形成于绝缘层3之上并相互接触，也可以是辅助导电层与绝缘层3存在其他层；例如，阵列基板上的TFT为底栅型，如果金属导电层仅包括栅极金属层，绝缘层3为钝化层，则栅极金属层和钝化层之间可以依次设置栅极绝缘层、有源层和源漏极金属层；又例如，阵列基板上的TFT为底栅型，如果金属导电层仅包括源漏极金属层，绝缘层3为钝化层，钝化层通常形成于源漏极金属层之上，则绝缘层3形成于金属导电层之上并直接接触；又例如，阵列基板上的TFT为顶栅型，如果金属导电层仅包括栅极金属层，绝缘层3为钝化层，钝化层通常形成于栅极金属层之上，则绝缘层3形成于金属导电层之上并直接接触；又例如，阵列基板上的TFT为顶栅型，如果金属导电层仅包括源漏极金属层，绝缘层3为钝化层，源漏极金属层与钝化层之间依次设置有源层、栅极绝缘层和栅极金属层；又例如，阵列基板上的TFT为顶栅型，如果金属导电层包括源漏极金属层和栅极金属层，绝缘层3为钝化层，钝化层通常形成于栅极金属层之上，则绝缘层3形成于金属导电层之上并直接接触，当然，此处的金属导电层的源漏极金属层和栅极金属层之间需要设置有栅极绝缘层进行绝缘。本发明实施例中仅是对方案进行示例性说明，基于实际的TFT的结构，可以根据本实施例进行变型，其仍在本发明实施例的保护范围内。
为了更清楚的描述本发明实施例提供的阵列基板的结构，结合图3至5示出的阵列基板进行详细说明如下：
参见图3(与图1相同的附图标记具有相同含义)，示出的第一种具体的阵列基板的结构示意图，阵列基板包括TFT 6，TFT 6包括栅电极61、源电极62、漏电极63和有源层64，源电极62和漏电极63所在层为源漏极金属层，栅电极61所在层为栅极金属层，源漏极金属层和栅极金属层之间设置 栅极绝缘层7。在本实施例中，第一导线2仅设置于源漏极金属层，即第一导线2与源电极62和漏电极63同层设置，第一导线2可以为数据线、电源信号线、接地线、时钟信号线和公共电极线中的至少一种。各第一导线2分别通过过孔51和切口52与对应的第二导线4电连接。第一导线2仅设置于栅极金属层的情况与图3的结构相似，在此不再赘述。需要说明的是，TFT 6的结构不限于图3所示的底栅型，也可以为顶栅型或其他结构，顶栅型或其他结构的TFT同样适用于本实施例，第二导线4的材料可以为透明导电材料，例如，氧化铟锡(ITO)，因此不会影响阵列基板的像素开口率。
参见图4(与图3相同的附图标记具有相同含义)，示出的第二种具体的阵列基板的结构示意图，阵列基板包括TFT 6，TFT 6包括栅电极61、源电极62、漏电极63和有源层64，源电极62和漏电极63所在层为源漏极金属层，栅电极61所在层为栅极金属层，源漏极金属层和栅极金属层之间设置栅极绝缘层7。在本实施例中，第一导线2设置于源漏极金属层和栅极金属层，即部分第一导线2与源电极62和漏电极63同层设置，部分第一导线2与栅电极61同层设置，第二导线4可以为数据线、电源信号线、接地线、栅线、时钟信号线和公共电极线的至少一种。各第一导线2分别通过过孔51和切口52与对应的第二导线4电连接。需要说明的是，TFT 6的结构不限于图4所示的底栅型，也可以为顶栅型或其他结构，顶栅型或其他结构的TFT同样适用于本实施例。本实施例中，第二导线4的材料可以为透明导电材料，例如，氧化铟锡(ITO)，在第二导线4和第一导线2的电连接处，第二导线4对第一导线2进行覆盖保护，能够对电连接处的第一导线2进行防水保护和抗氧化保护。
图3和图4所示的阵列基板中的绝缘层3可以仅为钝化层或仅为平坦化层，当然也可以为钝化层和平坦化层的组合。参见图5，示出了第三种具体的阵列基板的结构示意图，图5所示的阵列基板与图4所示的阵列基板具有相似的结构，不同之处在于图5所示的阵列基板的绝缘层3包括平坦层31和钝化层32，当然平坦化层31和钝化层32的层叠顺序可以互换。
示例性地，为了减小第二导线4所在的辅助导电层上与第一导线2所在的金属导电层之间的寄生电容，第二导线4可以设计为镂空结构，该镂空结构的图形可以灵活设置，例如，第二导线4中可以形成有方形或圆形的孔或 切掉部分。
本发明实施例有益效果如下：阵列基板的金属导电层的第一导线通过与之电连接的第二导线延伸至辅助导电层，从而第一导线原本在非显示区的走线可以转移至辅助导电层，这样可以减少第一导线在金属导电层的非显示区内所占用的走线空间，从而减小非显示区的面积或宽度，利于实现窄边框的显示面板；同时，阵列基板应于窄边框的显示面板时，由于不需要对非显示区内的线宽或线间距进行调整，也不需要改进栅极驱动电路，因此容易实现且成本较低。
本发明实施例还提供一种显示面板，包括如上实施例提供的阵列基板。
本发明实施例有益效果如下：阵列基板的金属导电层的第一导线通过与之电连接的第二导线延伸至辅助导电层，从而第一导线原本在非显示区的走线可以转移至辅助导电层，这样可以减少第一导线在金属导电层的非显示区内所占用的走线空间，从而减小非显示区的面积或宽度，利于实现窄边框的显示面板；同时，阵列基板应于窄边框的显示面板时，由于不需要对非显示区内的线宽或线间距进行调整，也不需要改进栅极驱动电路，因此容易实现且成本较低。
本发明实施例提供一种显示装置，包括如上实施例提供的显示面板。
本发明实施例有益效果如下：阵列基板的金属导电层的第一导线通过与之电连接的第二导线延伸至辅助导电层，从而第一导线原本在非显示区的走线可以转移至辅助导电层，这样可以减少第一导线在金属导电层的非显示区内所占用的走线空间，从而减小非显示区的面积或宽度，利于实现窄边框的显示面板；同时，阵列基板应于窄边框的显示面板时，由于不需要对非显示区内的线宽或线间距进行调整，也不需要改进栅极驱动电路，因此容易实现且成本较低。
此外，本发明的实施例还提供一种阵列基板的制造方法，包括：
步骤601、准备衬底基板，其中所述衬底基板包括显示区和非显示区；
步骤602，在所述衬底基板上形成金属导电层，金属导电层包括多条第一导线。
金属导电层可以包括栅极金属层和源漏极金属层中的任一种或组合。当然，如果金属导电层包括栅极金属层和源漏极金属层的组合时，栅极金属层 和源漏极金属层之间应当具有栅极绝缘层。这也意味着第一导线可以仅形成于栅极金属层，或仅形成于源漏极金属层，或形成于栅极金属层和源漏极金属层。
步骤603，在金属导电层上方形成绝缘层，绝缘层中形成有多个连接结构，连接结构的垂直投影位于非显示区内。
步骤604，在绝缘层上方形成辅助导电层，辅助导电层包括多条第二导线，第二导线经连接结构与相对应的第一导线电连接。
需要说明的是，本实施例中的金属导电层上方的绝缘层3和绝缘层3上方的辅助导电层，是指绝缘层3可以形成于金属导电层之上并相互接触，也可以是绝缘层3与金属导电层之间存在其他层，辅助导电层可以形成于绝缘层3之上并相互接触，也可以是辅助导电层与绝缘层3存在其他层。因此，根据阵列基板上TFT的不同结构或者层级结构，在本实施例提供的制造方法的基础上，可以进行一些调整，其仍在本发明实施例的保护范围内，在此不再赘述。
本发明实施例有益效果如下：阵列基板的金属导电层的第一导线通过与之电连接的第二导线延伸至辅助导电层，从而第一导线原本在非显示区的走线转移至辅助导电层，这样可以减少第一导线在金属导电层的非显示区内所占用的走线空间，从而减小非显示区的面积或宽度，利于实现窄边框的显示面板；同时，阵列基板应于窄边框的显示面板时，由于不需要对非显示区内的线宽或线间距进行调整，也不需要改进栅极驱动电路，因此容易实现且成本较低。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。
本申请要求于2015年1月26日递交的中国专利申请第201510038705.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (18)

  1. 一种阵列基板，包括：
    衬底基板，包括显示区和非显示区；以及
    金属导电层、所述金属导电层上方的绝缘层和所述绝缘层上方的辅助导电层，依次形成于所述衬底基板上，
    其中所述金属导电层包括多条第一导线，所述辅助导电层包括多条第二导线，所述多条第一导线中每条对应所述多条第二导线中至少之一，
    所述多个第二导线中每条经所述绝缘层中的连接结构与相对应的所述第一导线电连接，所述连接结构的垂直投影位于所述非显示区内。
  2. 如权利要求1所述的阵列基板，其中所述多条第一导线的每条至少包括位于所述非显示区的部分。
  3. 如权利要求2所述的阵列基板，其中所述多个第二导线中每条电连接到相对应的所述第一导线的位于所述非显示区的部分。
  4. 如权利要求1-3中任一项所述的阵列基板，其中所述多条第一导线包括数据线、栅线、电源信号线、接地线、公共电极线、时钟信号线中的至少一种。
  5. 如权利要求1-3中任一项所述的阵列基板，其中所述金属导电层包括源漏极金属层，所述第一导线包括数据线、电源信号线和接地线中的至少一种。
  6. 如权利要求1-3中任一项所述的阵列基板，其中所述金属导电层包括栅极金属层，所述第一导线包括栅线、公共电极线中的至少一种。
  7. 如权利要求1-3中任一项所述的阵列基板，其中所述金属导电层包括栅极金属层和源漏极金属层，所述第一导线包括数据线、栅线、电源信号线、接地线、公共电极线、时钟信号线中的至少一种。
  8. 如权利要求1-3中任一项所述的阵列基板，其中所述绝缘层为钝化层和平坦化层中的任一种或组合。
  9. 如权利要求8所述的阵列基板，其中所述钝化层为氧化硅膜层和氮化硅膜层中的任一种或复合膜层，所述平坦化层为聚甲基丙烯酸甲酯膜层。
  10. 如权利要求1-3中任一项所述的阵列基板，其中所述连接结构为过 孔，所述第二导线经所述过孔与相对应的所述第一导线电连接。
  11. 如权利要求1-3中任一项所述的阵列基板，其中所述连接结构为切口，所述第二导线在所述切口处覆盖相对应的所述第一导线。
  12. 如权利要求1-3中任一项所述的阵列基板，其中所述第二导线具有镂空结构。
  13. 如权利要求12所述的阵列基板，其中所述第二导线形成为具有方形或圆形的孔。
  14. 如权利要求12所述的阵列基板，其中所述第二导线的材料为透明导电材料。
  15. 一种显示面板，包括：
    如权利要求1至14中任一项所述的阵列基板；以及
    对置基板，与所述阵列基板对盒。
  16. 一种阵列基板的制造方法，包括：
    准备衬底基板，其中所述衬底基板包括显示区和非显示区；
    在所述衬底基板上形成金属导电层，所述金属导电层包括多条第一导线；
    在所述金属导电层上方形成绝缘层，所述绝缘层中形成有多个连接结构，所述连接结构的垂直投影位于所述非显示区内；以及
    在所述绝缘层上方形成辅助导电层，所述辅助导电层包括多条第二导线，所述第二导线经所述连接结构与相对应的所述第一导线电连接。
  17. 如权利要求16所述的阵列基板的制造方法，其中所述多条第一导线的每条至少包括位于所述非显示区的部分。
  18. 如权利要求17所述的阵列基板的制造方法，其中所述多个第二导线中每条电连接到相对应的所述第一导线的位于所述非显示区的部分。
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