WO2016141709A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2016141709A1
WO2016141709A1 PCT/CN2015/090713 CN2015090713W WO2016141709A1 WO 2016141709 A1 WO2016141709 A1 WO 2016141709A1 CN 2015090713 W CN2015090713 W CN 2015090713W WO 2016141709 A1 WO2016141709 A1 WO 2016141709A1
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Prior art keywords
layer
touch electrode
disposed
array substrate
touch
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PCT/CN2015/090713
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English (en)
French (fr)
Inventor
鲁友强
祁小敬
王志东
王静
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP15832870.8A priority Critical patent/EP3267482A4/en
Priority to US14/914,399 priority patent/US10254876B2/en
Publication of WO2016141709A1 publication Critical patent/WO2016141709A1/zh

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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04111—Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate

Definitions

  • At least one embodiment of the present invention is directed to an array substrate, a method of fabricating the same, and a display device.
  • Touch screens have been used in people's lives, especially ADS (Advanced Super Dimensional Field Conversion) type touch screens with wide viewing angles.
  • ADS Advanced Super Dimensional Field Conversion
  • ADS technology is a mainstream wide viewing angle technology of TFT-LCD (Thin Film Transistor-Liquid Crystal Display).
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • ADS type TFT-LCD has the advantages of relatively simple process, wide viewing angle, high aperture ratio, low response time and the like.
  • Capacitive touch screens are widely used in smart mobile terminals such as mobile phones and tablet computers because of their good user experience.
  • At least one embodiment of the present invention provides an array substrate, a method of fabricating the same, and a display device to reduce the number of reticle used in the process of fabricating an array substrate.
  • At least one embodiment of the present invention provides an array substrate including a substrate, a plurality of touch electrodes disposed on the substrate, and signals for respectively extracting the plurality of touch electrodes a plurality of touch electrode leads, and an array structure including a plurality of conductive structures; at least a portion of each of the touch electrode leads is disposed in the same layer and the same material as at least one of the plurality of conductive structures.
  • At least one embodiment of the present invention also provides a display device including the above array substrate.
  • At least one embodiment of the present invention further provides a method of fabricating an array substrate, comprising: forming a plurality of touch electrodes on a substrate; forming a plurality of touch electrodes on the substrate a plurality of touch electrode leads drawn from the signal; and forming an array structure including a plurality of conductive structures on the base substrate such that at least a portion of each of the touch electrode leads is at the same time as at least one of the plurality of conductive structures Formed in the mask process.
  • FIG. 1 is a cross-sectional view showing an ADS type array substrate
  • FIG. 2a is a schematic top view of an array substrate according to an embodiment of the present invention.
  • FIG. 2b is a cross-sectional view of an array substrate according to Embodiment 1 of the present invention.
  • FIG. 2c is a schematic top view of an array substrate according to Embodiment 1 of the present invention.
  • FIG. 3a is a cross-sectional view of an array substrate according to Embodiment 2 of the present invention.
  • 3b is a schematic top plan view of an array substrate according to Embodiment 2 of the present invention.
  • FIG. 4 is a cross-sectional view of an array substrate according to Embodiment 3 of the present invention.
  • FIG. 5 is a cross-sectional view of an array substrate according to Embodiment 4 of the present invention.
  • FIG. 1 is a schematic cross-sectional view of an ADS type array substrate.
  • the ADS type array substrate uses a low temperature polysilicon thin film transistor, and the manufacturing method generally includes the following steps S01 to S14, these steps are described one by one below.
  • Step S01 forming a shielding layer 111 on the base substrate 110 by the first masking process.
  • Step S02 forming a buffer layer 112 covering the occlusion layer 111.
  • Step S03 The active layer 123 is formed on the buffer layer 112 by the second mask process.
  • Step S04 forming a gate insulating layer 124 covering the active layer 123; forming a pattern of the photoresist on the gate insulating layer 124 by a third masking process; and then using the pattern of the photoresist as a mask
  • the source layer 123 is doped such that the active layer 123 forms an active region, a source doped region and a drain doped region, the active region corresponds to the occlusion layer 111, and the source doped region and the drain doped region are respectively located Both sides of the active region; the photoresist is removed after the doping is completed.
  • Step S05 forming a gate electrode 125 and a gate line on the gate insulating layer 124 by a fourth mask process.
  • the gate 125 corresponds to an active region.
  • a common electrode line can also be formed in this mask process.
  • Step S06 forming an intermediate dielectric layer 126 covering the gate electrode 125, and forming a via hole at a position corresponding to the source doping region and the drain doping region, respectively, by a fifth masking process to expose the source. Doped region and drain doped region.
  • Step S07 The source electrode 127 and the drain electrode 128 and the data line are formed on the intermediate dielectric layer 126 through the sixth mask process, and the source electrode 127 is in contact with the source doping region through the via hole formed in step S06.
  • the pole 128 is in contact with the drain doping region through the via formed in step S06.
  • Step S08 forming a first passivation layer 130 covering the thin film transistor 120.
  • Step S09 forming a planarization layer 140 on the first passivation layer 130, and forming a via hole at a position corresponding to the drain electrode 128 through the seventh mask process to expose the drain electrode 128.
  • Step S10 The pixel electrode 150 is formed on the flat layer 140 by the eighth mask process, and the pixel electrode 150 is in contact with the drain electrode 128 through the via hole formed in the step S09.
  • Step S11 forming a second passivation layer 160 covering the pixel electrode 150, and forming a via hole at a position corresponding to the common electrode line (not shown in FIG. 1) through the ninth mask process to expose the common electrode line .
  • Step S12 forming a common electrode layer on the second passivation layer 160 by a tenth mask process, for example, forming a common electrode 171 and a touch electrode 172 in the common electrode layer, and the common electrode 171 is formed through the step S11.
  • the vias are connected to corresponding common electrode lines.
  • Step S13 forming a third passivation layer 180 covering the common electrode 171 and the touch electrode 172, And forming a via hole at a position corresponding to the touch electrode 172 through the eleventh mask process to expose the touch electrode 172.
  • Step S14 The touch electrode lead 190 is formed on the third passivation layer 180 through the twelfth mask process, so that each touch electrode is connected to a touch electrode lead 190 through the via hole formed in step S13.
  • the inventors of the present application noticed that the number of masks used in the process of manufacturing the touch panel using the array substrate shown in FIG. 1 is large, and the manufacturing cost is high; even if the contact is made by using the common electrode layer For the control electrode, the step S13 of forming a via hole in the third passivation layer 180 and the step S14 of forming the touch electrode lead 190 of the touch electrode 172 are required. In this case, only 14 array substrates are required. Step, 12 masks.
  • At least one embodiment of the present invention provides an array substrate, a method of fabricating the same, and a display device by using at least a portion of a touch electrode lead and an original conductive structure on the array substrate (eg, a gate, a source/drain of a thin film transistor)
  • the opaque layer or the like is disposed in the same layer and has the same material, thereby simplifying the structure of the array substrate, reducing the number of reticle used in the manufacturing process, and reducing the cost.
  • At least one embodiment of the present invention provides an array substrate, as shown in FIG. 2a, the array substrate includes a substrate substrate 110, and a plurality of touch electrodes disposed on the substrate substrate 110 (not shown in FIG. 2a). a plurality of touch electrode leads (not shown in FIG. 2a) for extracting signals of the plurality of touch electrodes, and an array structure 10 including a plurality of conductive structures 100; at least each of the touch electrode leads A portion is disposed in the same layer as at least one of the plurality of conductive structures 100 and is the same material, that is, formed in the same mask process.
  • the primary mask process refers to a process of using a mask to expose the photoresist to pattern the film layer, which may include, for example, exposure, development, etching, and the like.
  • the array structure 10 may include a plurality of thin film transistors 120.
  • each of the thin film transistors 120 may include a gate 125, a source 127, and a drain 128, and the gate 125, the source 127, and the drain 128 belong to the plurality of conductive structures 100 described above.
  • the array structure 10 may further include a plurality of occlusion layers (not shown in FIG. 2a) including a plurality of thin film transistors 120, each of the occlusion layers being located on the active layer 123 and the lining of each of the thin film transistors 120.
  • the shielding layer may also belong to the plurality of conductive structures 100 between the base substrates 110.
  • the shielding layer is disposed between the base substrate and the active layer of the thin film transistor, so that the light of the backlight can be prevented from being irradiated onto the active layer of the thin film transistor, thereby reducing the thin film crystal. The leakage current of the tube.
  • the array substrate includes a plurality of gate lines 1251 and a plurality of data lines 1282, and the gate lines 1251 and the data lines 1282 cross each other to define a plurality of sub-pixel units, in which case the array substrate 10 is, for example, An array of sub-pixel units.
  • the embodiments of the present invention include, but are not limited to, as long as they are arranged in an array on the array substrate and include a plurality of conductive structures.
  • array structure 10 can also be an array of thin film transistors 120.
  • the touch electrode lead and the touch electrode are disposed in different layers, that is, the touch electrode lead and the touch electrode are formed by different film layers.
  • the touch electrode lead may be a unitary structure (ie, a complete continuous structure), or may include a plurality of component parts.
  • each of the touch electrode leads may be disposed in the same layer and of the same material as any of the plurality of conductive structures.
  • each touch electrode lead is a one-piece structure, which is, for example, a linear structure, so that each touch electrode lead can be formed by only one mask process.
  • each of the touch electrode leads is disposed in the same layer and the same material as any of the gate, the source, the drain, and the occlusion layer.
  • the substrate substrate 110 of the array substrate is provided with a plurality of gate lines 1251 and a plurality of data lines 1282 intersecting horizontally and vertically.
  • the gate lines 1251 are connected to the gate 125 of the thin film transistor 120, for example, and are hidden at the same time.
  • the data line 1282 is, for example, connected to the source 127 of the thin film transistor 120 and formed in the same mask process. Therefore, when the touch electrode lead is disposed in the same layer and the same material as the gate of the thin film transistor, in order to insulate the touch electrode lead from the gate line, the touch electrode lead may be disposed in a gap of the gate line, such as a touch electrode.
  • the lead wire and the gate line extend in the same direction; similarly, when the touch electrode lead is disposed in the same layer and the same material as the source and the drain of the thin film transistor, the touch electrode lead may be disposed in a gap of the data line, such as a touch electrode
  • the leads extend in the same direction as the data lines.
  • this method leads to a complicated wiring on the layer where the gate line is located or where the data line is located.
  • At least one embodiment of the present invention provides a touch electrode lead by providing each touch electrode lead to include a plurality of component parts. It is insulated from the gate and data lines and is easy to route flexibly.
  • each touch electrode lead may include at least two first linear portions and at least one first bridge portion, the at least two first linear portions are disposed in the same layer as the plurality of gate lines, and the touch electrode leads are mostly Article At least one of the gate lines intersects, and at the intersection of the touch electrode lead and the gate line, the adjacent two first linear portions are connected by a first bridge portion.
  • each of the touch electrode leads may include at least two first linear portions and at least one first bridge portion, the at least two first linear portions are disposed in the same layer as the plurality of data lines, and the touch electrode leads are Intersecting with at least one of the plurality of data lines, and at the intersection of the touch electrode lead and the data line, the adjacent two first linear portions are connected by a first bridge.
  • the component parts may be partially or completely formed by using an original mask process of the array substrate. Therefore, at least one of the first linear portion and the first bridging portion of the touch electrode lead can be formed in the same mask process as the original conductive structure on the array substrate, that is, the same layer is disposed and the materials are the same.
  • the first linear portion, the gate line, and the gate may be disposed in the same layer and have the same material; when at least two first lines are formed When the portion is disposed in the same layer as the plurality of data lines, the first line portion, the data line, the source and the drain may be disposed in the same layer and have the same material.
  • the first bridge portion when the at least two first linear portions are disposed in the same layer as the plurality of gate lines, the first bridge portion is disposed in the same layer as the source and the drain and has the same material; when at least two first linear portions are When a plurality of data lines are disposed in the same layer, the first bridge portion is disposed in the same layer as the gate and has the same material.
  • the first linear portion of the touch electrode lead may be disposed in the same layer as the gate and have the same material, and the first bridge portion is disposed in the same layer and the same material as the source and the drain; or the first of the touch electrode leads
  • the linear portion may be disposed in the same layer as the source and the drain and the same material, and the first bridge portion is disposed in the same layer as the gate and is of the same material.
  • each occlusion layer is located between the active layer of each thin film transistor and the substrate
  • the first bridge portion may be disposed in the same layer as the occlusion layer and The materials are the same, and the first linear portion can be disposed in the same layer as the other conductive structures.
  • the active layer of each thin film transistor includes an active region, a source doped region, and a drain doped region, and the source and the drain respectively contact the source doped region through the first via and a drain doping region;
  • the first bridge portion is connected to each of the first linear portions through a second via hole, and a layer through which at least a portion of the second via hole passes and a layer through which at least a portion of the first via hole passes the same. If the first via and the second via are not completely identical, the degree of etching performed is different when the etching process is performed.
  • the layer through which the first via hole passes and the layer through which the second via hole passes are at least partially identical, so that a mask process for fabricating the original via hole on the array substrate can be used to form the first bridge for connection.
  • the vias and the vias of the first line portion further reduce the number of process flows and masks.
  • the active layer of the thin film transistor is provided with a first insulating layer
  • the first insulating layer is provided with a gate and a first linear portion
  • the second insulating layer covers the gate and the first linear portion
  • the second insulating layer a source, a drain and a first bridge are disposed on the layer, in which case the first via penetrates through the first insulating layer and the second insulating layer (ie, includes a portion located in the first insulating layer and is located at the second a portion of the insulating layer, the second via penetrating through the second insulating layer, so that the first via hole and the second via hole may be formed by a mask process before the source, the drain, and the first bridge portion are formed.
  • the common electrode layer (for example, the layer where the common electrode 171 is located in FIG. 2a) is disposed in the ADS type array substrate, in order to further reduce the number of processes and the number of masks, the above may be
  • the touch electrodes are disposed in the common electrode layer to form the touch electrodes by using the common electrode layers.
  • the common electrode and the touch electrode may be separately disposed in the common electrode layer, and the display function and the touch function may be implemented by time-division driving; or only the touch electrode may be disposed in the common electrode layer without setting the common electrode.
  • the multiplexed manner realizes that the electrodes in the common electrode layer serve as a common electrode in the display phase and as a touch electrode in the touch phase.
  • a common electrode line is generally disposed under the common electrode layer (ie, between the common electrode layer and the base substrate), and the common electrode is connected to the corresponding common electrode line through the via. Therefore, in at least one embodiment, the touch electrode lead may be located between the common electrode layer and the base substrate, such that when the plurality of touch electrodes are disposed in the common electrode layer, the mask may be in the same mask process. A via hole corresponding to the common electrode line and a via hole for connecting the touch electrode and the corresponding touch electrode lead are formed, thereby reducing the number of processes and the number of masks.
  • each of the touch electrode leads may include a second linear portion and a second bridge portion, and the second bridge portion connects the touch electrode corresponding to the touch electrode lead and the second linear portion.
  • the components of the touch electrode lead can be formed by using a mask process for fabricating the original conductive structure on the array substrate, without adding a new mask process, or only a part of the component parts can be used to fabricate the array.
  • a masking process of the original conductive structure on the substrate is formed.
  • the array structure 10 may further include a plurality of first electrodes (eg, the pixel electrodes 150 in FIG. 2a) respectively connected to the plurality of thin film transistors, including the plurality of thin film transistors 120, the first The electrodes belong to the plurality of conductive structures 100 described above.
  • the touch electrode The second bridge of the lead may be disposed in the same layer as the first electrode included in the array substrate and of the same material.
  • the second linear portion of the touch electrode lead can be formed by additionally adding a mask process to the existing mask process of the array substrate.
  • the array substrate provided by the embodiment of the present invention may be an array substrate for liquid crystal display, an organic light emitting diode (OLED) array substrate, or the like.
  • the first electrode is a pixel electrode 150, which is connected, for example, to the drain 128 of the thin film transistor 120, as shown in FIG. 2a; when the array substrate is an OLED array substrate
  • the first electrode is, for example, an anode which is, for example, connected to the drain of the thin film transistor.
  • Embodiments of the invention are not limited thereto.
  • the first electrode is connected to the thin film transistor, for example, through a via hole. Therefore, in at least one embodiment, the second linear portion of the touch electrode lead may be located between the layer where the first electrode is located and the substrate. In this way, since the second bridge portion of the touch electrode lead is disposed in the same layer as the first electrode, a via hole for connecting the first electrode and the drain of the thin film transistor, for example, can be formed in the same mask process for connection.
  • the second bridge portion has a via hole corresponding to the touch electrode, and a via hole for connecting the second bridge portion and the corresponding second line portion, thereby reducing the number of processes and the number of masks.
  • the array substrate may further include a common electrode layer (for example, a layer in which the common electrode 171 is located in FIG. 2a) disposed on the substrate.
  • a common electrode layer for example, a layer in which the common electrode 171 is located in FIG. 2a
  • the touch electrode lead includes the second linear portion and the second bridge portion
  • the plurality of touch electrodes may be disposed in the common electrode layer.
  • the first electrode is a pixel electrode.
  • the pixel electrode may be located in the upper layer and the common electrode is located in the lower layer; or, the pixel electrode is located in the lower layer, and the common electrode is located in the upper layer.
  • the second linear portion of the touch electrode lead may be located between the layer where the pixel electrode is located and the common electrode layer, so that the original via process of the array substrate can be used to form the second bridge portion and A via hole of the corresponding touch electrode and a via hole for connecting the second bridge portion and the corresponding second line portion to save the process flow.
  • a via hole for forming a common electrode and a common electrode line or a via hole for connecting the pixel electrode and the drain may be formed by a mask process for connecting the second bridge portion.
  • a via hole corresponding to the corresponding touch electrode and a via hole for connecting the second bridge portion and the corresponding second line portion may be formed by a mask process for connecting the second bridge portion.
  • the gate, the source, the drain, and the shielding layer of the thin film transistor may be made of a metal material such as aluminum or copper or an alloy thereof, and may be a single layer or a multilayer structure, and the pixel electrode and the common electrode are both It can be made of transparent conductive materials such as indium tin oxide and indium zinc oxide.
  • the insulating structures such as buffer layer, gate insulating layer, intermediate dielectric layer and passivation layer can be made of silicon nitride (SiNx) or silicon oxynitride (SixNiyO). Or a single layer or a plurality of layers of insulating materials such as silicon oxide (SiO 2 ), and the flat layer may be made of an organic insulating material such as a resin.
  • the embodiments of the present invention are not limited.
  • the touch electrode lead is made of a metal material; or when the touch electrode lead includes a line portion and a bridge portion, at least the touch electrode lead
  • the linear portion is made of a metal material, and the bridge portion may be made of a metal material or a transparent conductive material.
  • At least one embodiment of the present invention also provides a display device comprising the array substrate of any of the above embodiments.
  • the display device may further include an opposite substrate (for example, a color filter substrate) disposed opposite to the array substrate, and the opposite substrate and the array substrate are sealed together by a sealant.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a watch, and the like.
  • At least one embodiment of the present invention further provides a method for fabricating an array substrate, comprising: forming a plurality of touch electrodes on a base substrate, and multiple contacts for extracting signals of the plurality of touch electrodes
  • the control electrode lead and the plurality of conductive structure array structures are formed such that at least a portion of each of the touch electrode leads and at least one of the plurality of conductive structures are formed in the same mask process.
  • the array structure may include a plurality of thin film transistors.
  • each of the thin film transistors may include a gate, a source, and a drain, and the gate, the source, and the drain belong to the plurality of conductive structures described above.
  • the array structure may further include a plurality of occlusion layers on the basis of including a plurality of thin film transistors, each occlusion layer being located between the active layer of each thin film transistor and the substrate substrate, and the occlusion layer also belongs to the above A plurality of conductive structures.
  • the shielding layer is disposed between the substrate and the active layer of the thin film transistor, so that the light of the backlight can be prevented from being irradiated onto the active layer of the thin film transistor, so that the leakage current of the thin film transistor can be reduced.
  • the touch electrode lead can be formed in the same masking process as any of the plurality of conductive structures described above.
  • the touch electrode lead and the gate of the thin film transistor are formed by a mask process; or the touch electrode lead is formed by a mask process And a source and a drain of the thin film transistor; or forming a touch electrode lead by a mask process and an occlusion layer included in the array structure, the occlusion layer being located between the base substrate and the active layer of the thin film transistor.
  • each of the touch electrode leads may be disposed and intersected in the same layer as the gate lines, or may be disposed and intersected in the same layer as the data lines.
  • each touch electrode lead is insulated from the plurality of gate lines and the plurality of data lines and intersects at least one of the plurality of gate lines or data lines;
  • each touch electrode lead includes at least two first line portions And at least one first bridge portion; and the at least two first line portions are disposed in the same layer as the plurality of gate lines, the touch electrode leads intersecting at least one of the plurality of gate lines, and the touch electrode leads are At the intersection of the gate lines, the adjacent two first linear portions are connected by a first bridge portion, or the at least two first linear portions are disposed in the same layer as the plurality of data lines, and the touch electrode leads are At least one of the plurality of data lines intersects, and at the intersection of the touch electrode lead and the data line, the adjacent two first linear portions are connected by a first bridge.
  • the at least two first linear portions when the at least two first linear portions are disposed in the same layer as the plurality of gate lines, the at least two first linear portions, the gate lines, and the gates of the thin film transistors may be formed by one mask process; or When the at least two first linear portions are disposed in the same layer as the plurality of data lines, the at least two first linear portions, the data lines, and the source and the drain of the thin film transistor may be formed by one mask process.
  • the first bridge portion and the source and the drain of the thin film transistor are formed by one mask process; or, the at least two When the first linear portion is disposed in the same layer as the plurality of data lines, the first bridge portion and the gate of the thin film transistor are formed by a single mask process.
  • the above array structure further includes a plurality of occlusion layers on the basis of including a plurality of thin film transistors, and each occlusion layer is formed by a mask process when being located between the active layer and the substrate of each of the thin film transistors.
  • a bridge and a occlusion layer are examples of occlusion layers on the basis of including a plurality of thin film transistors, and each occlusion layer is formed by a mask process when being located between the active layer and the substrate of each of the thin film transistors.
  • the masking process for fabricating the first linear portion and the first bridging portion may be selectively combined and used according to actual needs, and details are not described herein.
  • each of the touch electrode leads may include a second linear portion and a second bridge portion, and the second bridge portion connects the touch electrode corresponding to the touch electrode lead and the second linear portion.
  • a second bridge portion may be formed by a mask process with a first electrode on the substrate substrate and connected to the thin film transistor.
  • first electrode For example, a second bridge portion may be formed by a mask process with a first electrode on the substrate substrate and connected to the thin film transistor.
  • first electrode Regarding the setting of the first electrode, reference may be made to the above related description. The repetitions are not repeated here.
  • the array substrate provided in this embodiment includes a substrate substrate 110 and a shielding layer 111, a buffer layer 112, and a thin film transistor 120 disposed on the substrate substrate 110 (only one thin film transistor 120 is shown in FIG. 2b.
  • the thin film transistor functions as a switching element of a sub-pixel.
  • the thin film transistor 120 is a low temperature polysilicon thin film transistor including an active layer 123, a gate insulating layer 124, a gate electrode 125, an intermediate dielectric layer 126, and the same layer disposed on the intermediate dielectric layer.
  • Source 127 and drain 128 on 126 are formed in the same mask process.
  • the touch electrode lead 1900 is made of the same material as the source 127 and the drain 128 and is located in the same layer.
  • FIG. 2C is a schematic top view of an array substrate according to an embodiment of the present invention.
  • the touch electrode lead 1900 is located in a gap between the data lines 1282, and the touch electrode lead 1900 and the data line 1282 are both Extending in the longitudinal direction.
  • the gate line 1251 intersects the touch electrode lead 1900 at the opposite side.
  • the first insulating layer 130, the flat layer 140, the pixel electrode 150, the second insulating layer 160, and the common electrode layer may be sequentially disposed on the base substrate 110 on which the thin film transistor 120 is formed.
  • the common electrode 171 and the touch electrode 1720 may be disposed in the common electrode layer, that is, the touch electrode 1720 and the common electrode 171 are disposed in the same layer and have the same material.
  • the touch electrode 1720 is connected to the touch electrode lead 1900 through the via 1721; the via 1721 may be formed in a via for connecting the common electrode 171 and its corresponding common electrode line (not shown in FIG. 2b). Formed in the mask process.
  • the touch electrode lead 1900 is formed in the same mask process as the source electrode 127 and the drain electrode 128, the touch electrode 1720 and the common electrode 171 are formed in the same mask process, and are used for The contact hole 1721 of the contact control electrode 1720 and the corresponding touch electrode lead 1900 and the via hole for connecting the common electrode 171 and the corresponding common electrode line are formed in the same mask process, and therefore, the embodiment is effectively reduced. Process flow for fabricating array substrates and masks used quantity.
  • This embodiment further provides a method for fabricating an array substrate as shown in FIG. 2b.
  • the method includes the following steps S101 to S112, and the steps are described one by one below.
  • Step S101 forming a shielding layer 111 on the base substrate 110 by a first masking process.
  • Step S102 forming a buffer layer 112 covering the occlusion layer 111.
  • Step S103 The active layer 123 is formed on the buffer layer 112 by a second mask process.
  • Step S104 forming a gate insulating layer 124 covering the active layer 123; forming a pattern of the photoresist on the gate insulating layer 124 by a third masking process; and then using the pattern of the photoresist as a mask,
  • the active layer 123 is doped such that the active layer 123 forms an active region 123a, a source doped region 123b and a drain doped region 123c, the active region 123a corresponds to the occlusion layer 111, the source doped region 123b and the drain
  • the electrode doped regions 123c are respectively located on both sides of the active region 123a; the photoresist is removed after the doping is completed.
  • Step S105 A gate electrode 125, a plurality of gate lines, and a common electrode line are formed on the gate insulating layer 124 by a fourth mask process (the gate lines and the common electrode lines are not shown in FIG. 2b).
  • Step S106 forming an intermediate dielectric layer 126 covering the gate electrode 125, and forming via holes 1271 and 1281 at positions corresponding to the source doping region 123b and the drain doping region 123c, respectively, through a fifth masking process, To expose the source doping region 123b and the drain doping region 123c.
  • Step S107 forming a source 127, a drain 128, a touch electrode lead 1900, and a plurality of data lines (not shown in FIG. 2b) on the intermediate dielectric layer 126 through a sixth mask process, and the source 127 passes
  • the via 1271 is in contact with the source doping region 123b
  • the drain 128 is in contact with the drain doping region 123c through the via 1281.
  • Step S108 forming a first passivation layer 130 covering the thin film transistor 120.
  • Step S109 forming a flat layer 140 on the first passivation layer 130, and through the seventh mask process, a via hole 151 is formed at a position corresponding to the drain electrode 128 to expose the drain electrode 128.
  • Step S110 The pixel electrode 150 is formed on the flat layer 140 by the eighth mask process, and the pixel electrode 150 is in contact with the drain electrode 128 through the via 151.
  • Step S111 forming a second passivation layer 160 covering the pixel electrode 150, and forming a via hole at a position corresponding to the common electrode line (not shown in FIG. 2b) through the ninth mask process to expose the common electrode line, A via hole 1721 is formed at a position corresponding to the touch electrode lead 1900 to expose the touch electrode lead 1900.
  • Step S112 forming a common electrode on the second passivation layer 160 through the tenth mask process 171 and the touch electrode 1720, the common electrode 171 is connected to the corresponding common electrode line through the via hole, and the touch electrode 1720 is connected to the corresponding touch electrode lead 1900 through the via hole 1721.
  • the manufacturing method provided by the embodiment only needs 12 steps and 10 mask processes, which saves 2 steps, 2 A mask that effectively reduces the number of processes and reticle.
  • the via 1721 for connecting the touch electrode 1720 and the touch electrode lead 1900 can also be formed by multiple mask processes.
  • the via 151 can be formed in the flat layer while the corresponding touch electrode is formed.
  • a via hole is formed at the position of the lead 1900, and then the pixel electrode material and the second passivation layer material located in the via hole are etched away in a subsequent step.
  • the embodiment is described by taking the common electrode line and the gate in the same mask process as an example, and the common electrode line may be disposed in other layers according to actual needs.
  • each touch electrode lead 1900 intersects and is insulated from at least one gate line 1251, and each touch electrode lead 1900 includes at least two first a linear portion 1901 (shown as a portion between A and B) and at least one first bridge portion 1902 (shown as a portion between B and C); at a position where the touch electrode lead 1900 intersects the gate line 1251 At O, the first bridge portion 1902 connects the adjacent two first linear portions 1901 through the via 1903.
  • the first linear portion 1901, the gate electrode 125, and the gate line 1251 are made of the same material and are on the same layer; in one example, the first bridge portion 1902, the source The pole 127, the drain 128 and the data lines (not shown) are made of the same material and are on the same layer.
  • the embodiment is not limited thereto.
  • the embodiment provides a method for fabricating the array substrate as shown in FIG. 3a, which is generally the same as the manufacturing method provided in Embodiment 1, and only needs 12 steps and 10 masks to complete. Fabrication of array substrates, but the differences are as follows.
  • a gate electrode 125, a plurality of gate lines 1251, a common electrode line, and a first line portion 1901 of the touch electrode lead 1900 are formed on the gate insulating layer 124 by a fourth mask process. At least one gate line 1251 is disposed in a gap between the adjacent first linear portions 1901;
  • step S106 an intermediate dielectric layer 126 covering the gate electrode 125 is formed through the fifth mask.
  • a source 127, a drain 128, a first bridge portion 1902 of the touch electrode lead 1900, and a plurality of data lines are formed on the intermediate dielectric layer 126 by a sixth mask process (not shown in FIG. 3a).
  • the source 127 and the drain 128 are in contact with the source doping region 123b and the drain doping region 123c through the first vias 1271 and 1281, respectively, and the first bridge portion 1902 is connected adjacent through the second via 1903.
  • each of the touch electrode leads 1900 and the shielding layer 111 of the thin film transistor 120 are formed in the same mask process.
  • the touch electrode lead 1900 and the shielding layer 111 of the thin film transistor 120 are made of the same material and are located in the same layer.
  • the embodiment provides a method for fabricating the array substrate as shown in FIG. 4, which is generally the same as the manufacturing method provided in Embodiment 1, and only needs 12 steps and 10 masks to complete.
  • the Array substrate is fabricated, but the difference is that in step S101, the occlusion layer 111 and the touch electrode lead 1900 are formed on the base substrate 110 by the first mask process, and the touch is not required to be formed in step S107. Electrode lead 1900.
  • the touch electrode lead is disposed in the same layer as the shielding layer of the thin film transistor. Since there is no gate line, data line, etc. in the layer where the shielding layer is located, the touch electrode lead is in the layer.
  • the wiring method can be more flexible as long as the aperture ratio is not significantly affected; and compared with the embodiment 2, the manufacturing process of the touch electrode lead is simple.
  • each touch electrode lead 1900 includes a second linear portion 1905 and a second bridge portion 1904, and the second bridge portion 1904 is connected to the touch electrode. 1720 and a second linear portion 1905 of the touch electrode lead corresponding to the touch electrode.
  • the touch electrode 1720 and the common electrode 171 may be in the same mask process. Formed, in this case, the touch electrode 1720 and the common electrode 171 are made of the same material and are located in the same layer.
  • the second passivation layer 160 is disposed on the touch electrode 1720 and the common electrode 171, and the second linear portion 1905 of the touch electrode lead 1900 may be formed on the second passivation layer 160 by a separate mask process.
  • the third passivation layer 180 covers the second linear portion 1905 of the touch electrode lead 1900.
  • the pixel electrode 150 is formed on the third passivation layer 180, and the pixel electrode 150 is connected to the drain 128 of the thin film transistor 120 through the via 151.
  • the second bridge portion 1904 of the touch electrode lead 1900 is formed in the same mask process as the pixel electrode 150 (the same layer is disposed and the materials are the same), and passes through the via 1906 and the via 1907 and the touch electrode 1720 and the The two linear portions 1905 are connected.
  • the present embodiment provides a method for fabricating an array substrate as shown in FIG. 5. Since the touch electrode lead 1900 is not formed by using the material of the conductive structure of the thin film transistor in this embodiment, the method provided in this embodiment is provided. Steps S201 to S208 are similar to steps S01 to S08 in the method of fabricating the array substrate shown in FIG. The method provided by this embodiment differs from the manufacturing method provided in Embodiment 1 in the following differences.
  • step S209 a planarization layer 140 is formed on the first passivation layer 130, and a via hole is formed at a position corresponding to the common electrode line (not shown in FIG. 5) through the seventh mask process to expose the common electrode. line.
  • step S210 the common electrode 171 and the touch electrode 1720 are formed on the flat layer 140 by the eighth mask process, and the common electrode 171 is connected to the corresponding common electrode line through the via hole formed in step S209.
  • Step S211 forming a second passivation layer 160 covering the common electrode 171 and the touch electrode 1720.
  • Step S212 The second linear portion 1905 of the touch electrode lead 1900 is formed on the second passivation layer 160 by the ninth mask process.
  • Step S213 forming a third passivation layer 180 covering the second linear portion 1905 of the touch electrode lead 1900, and forming a via 151 corresponding to the drain 128 and a via corresponding to the touch electrode 1720 through a tenth mask process. 1906 and a via 1907 corresponding to the second linear portion 1905 of the touch electrode lead 1900.
  • Step S214 forming a pixel electrode 150 connected to the drain electrode 128 through the via 151 through the eleventh mask process, and forming a second bridge portion 1904 of the touch electrode lead 1900, and the second bridge portion 1904 passes through the via hole 1906, respectively. Connecting the touch electrode 1720 and the touch electrode lead 1900 with 1907 The second linear portion 1905.
  • the manufacturing method provided by the embodiment only needs 11 mask processes, which saves one mask.
  • the above embodiment of the present invention has been described by taking a thin film transistor as a low temperature polysilicon thin film transistor as an example, but it may be another type of thin film transistor such as an amorphous silicon type or a metal oxide type.
  • the array substrate can adopt the self-capacitance principle or the mutual capacitance principle, that is, the touch electrode can be a self-capacitance electrode, or can be a touch drive electrode or a touch sensing electrode.
  • the embodiments of the present invention are not limited.
  • At least a part of the touch electrode lead is fabricated by using a mask process for fabricating the original conductive structure in the array substrate, thereby reducing the number of the mask.

Abstract

一种阵列基板及其制作方法、显示装置，该制作方法包括在衬底基板(110)上形成多个触控电极(1720)、用于将所述多个触控电极(1720)的信号引出的多条触控电极引线(1900)和包括多个导电结构(100)的阵列结构(10)，使所述触控电极引线(1900)的至少一部分与所述多个导电结构(100)中的至少一个同层设置且材料相同。该制作方法可以减少制作阵列基板的过程中所使用的掩模板的数量。

Description

阵列基板及其制作方法、显示装置 技术领域
本发明的至少一个实施例涉及一种阵列基板及其制作方法、显示装置。
背景技术
触控屏已遍及人们的生活，尤其是具有广视角的ADS(高级超维场转换)型触控屏更是市场潜力巨大。
目前，ADS技术是TFT-LCD(薄膜晶体管-液晶显示器)的一种主流的宽视角技术，ADS型TFT-LCD具有制程相对简单、宽视角、高开口率、低响应时间等优点。电容式触控屏因具有良好的用户体验，在手机、平板电脑等智能移动终端中被广泛使用。
发明内容
本发明的至少一个实施例提供了一种阵列基板及其制作方法、显示装置，以减少制作阵列基板的过程中使用的掩模板的数量。
本发明的至少一个实施例提供了一种阵列基板，其包括衬底基板，设置于所述衬底基板上的多个触控电极、用于分别将所述多个触控电极的信号引出的多条触控电极引线、以及包括多个导电结构的阵列结构；每条触控电极引线的至少一部分与所述多个导电结构中的至少一个同层设置且材料相同。
本发明的至少一个实施例还提供了一种显示装置，其包括上述阵列基板。
本发明的至少一个实施例还提供了一种阵列基板的制作方法，其包括：在衬底基板上形成多个触控电极；在衬底基板上形成用于将所述多个触控电极的信号引出的多条触控电极引线；以及在衬底基板上形成包括多个导电结构的阵列结构，使得每条触控电极引线的至少一部分与所述多个导电结构中的至少一个在同一次掩膜工艺中形成。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为一种ADS型阵列基板的剖视示意图；
图2a为本发明实施例提供的一种阵列基板的俯视示意图；
图2b为本发明实施例1提供的一种阵列基板的剖视示意图；
图2c为本发明实施例1提供的一种阵列基板的俯视示意图；
图3a为本发明实施例2提供的一种阵列基板的剖视示意图；
图3b为本发明实施例2提供的一种阵列基板的俯视示意图；
图4为本发明实施例3提供的一种阵列基板的剖视示意图；
图5为本发明实施例4提供的一种阵列基板的剖视示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种ADS型阵列基板的剖视示意图，如图1所示，该ADS型阵列基板采用低温多晶硅薄膜晶体管，其制作方法通常包括以下步骤S01至 S14，下面逐一介绍这些步骤。
步骤S01：通过第一次掩膜工艺，在衬底基板110上形成遮挡层111。
步骤S02：形成覆盖遮挡层111的缓冲层112。
步骤S03：通过第二次掩膜工艺，在缓冲层112上形成有源层123。
步骤S04：形成覆盖有源层123的栅极绝缘层124；通过第三次掩膜工艺，在栅极绝缘层124上形成光刻胶的图形；之后以光刻胶的图形为掩膜对有源层123进行掺杂，使有源层123形成有源区、源极掺杂区和漏极掺杂区，有源区对应遮挡层111，源极掺杂区和漏极掺杂区分别位于有源区的两侧；在掺杂结束后去除光刻胶。
步骤S05：通过第四次掩膜工艺，在栅极绝缘层124上形成栅极125和栅线。栅极125对应于有源区。例如，在本次掩膜工艺中还可以形成公共电极线。
步骤S06：形成覆盖栅极125的中间介电层126，通过第五次掩膜工艺，分别在对应上述源极掺杂区和漏极掺杂区的位置处形成过孔，以暴露出源极掺杂区和漏极掺杂区。
步骤S07：通过第六次掩膜工艺，在中间介电层126上形成源极127和漏极128和数据线，源极127通过步骤S06中形成的过孔与源极掺杂区接触，漏极128通过步骤S06中形成的过孔与漏极掺杂区接触。
步骤S08：形成覆盖薄膜晶体管120的第一钝化层130。
步骤S09：在第一钝化层130上形成平坦层140，通过第七次掩膜工艺，在对应漏极128的位置处形成过孔，以暴露出漏极128。
步骤S10：通过第八次掩膜工艺，在平坦层140上形成像素电极150，像素电极150通过步骤S09中形成的过孔与漏极128接触。
步骤S11：形成覆盖像素电极150的第二钝化层160，通过第九次掩膜工艺，在对应公共电极线(图1中未示出)的位置处形成过孔，以暴露出公共电极线。
步骤S12：通过第十次掩膜工艺，在第二钝化层160上形成公共电极层，例如在公共电极层中形成公共电极171和触控电极172，并且公共电极171通过步骤S11中形成的过孔与对应的公共电极线连接。
步骤S13：形成覆盖公共电极171和触控电极172的第三钝化层180， 并通过第十一次掩膜工艺在对应触控电极172的位置处形成过孔，以暴露出触控电极172。
步骤S14：通过第十二次掩膜工艺，在第三钝化层180上形成触控电极引线190，使每个触控电极通过步骤S13中形成的过孔连接一条触控电极引线190。
在研究中，本申请的发明人注意到，采用如图1所示的阵列基板的触控屏的制作过程中使用的掩模板数量较多，制作成本较高；即便是利用公共电极层制作触控电极，仍需增加在第三钝化层180中形成过孔的步骤S13以及制作触控电极172的触控电极引线190的步骤S14，在这种情况下，仅制作阵列基板就需要14个步骤、12张掩模板。
本发明的至少一个实施例提供了一种阵列基板及其制作方法、显示装置，通过使触控电极引线的至少一部分与阵列基板上原有的导电结构(例如薄膜晶体管的栅极、源/漏极、或遮挡层等)同层设置且材料相同，由此可简化阵列基板的结构，减少制作过程中使用的掩模板的数量并降低成本。
本发明的至少一个实施例提供了一种阵列基板，如图2a所示，该阵列基板包括衬底基板110，设置于衬底基板110上的多个触控电极(图2a中未示出)、用于将所述多个触控电极的信号引出的多条触控电极引线(图2a中未示出)，以及包括多个导电结构100的阵列结构10；每条触控电极引线的至少一部分与多个导电结构100中的至少一个同层设置且材料相同，即在同一次掩膜工艺中形成。
在本发明实施例中，一次掩膜工艺是指使用一次掩模板来对光刻胶进行曝光以对薄膜层进行构图的工艺，其例如可以包括曝光、显影、刻蚀等步骤。
在阵列基板中，阵列结构10可以包括多个薄膜晶体管120。例如，每个薄膜晶体管120可以包括栅极125、源极127和漏极128，所述栅极125、源极127和漏极128属于上述多个导电结构100。
或者，例如，阵列结构10在包括多个薄膜晶体管120的基础上还可以包括多个遮挡层(图2a中未示出)，每个遮挡层位于每个薄膜晶体管120的有源层123和衬底基板110之间，所述遮挡层也可以属于上述多个导电结构100。在本发明实施例中，遮挡层设置在衬底基板与薄膜晶体管的有源层之间，可以防止背光源的光照射到薄膜晶体管的有源层上，从而可以减小薄膜晶体 管的漏电流。
在图2a所示的情形中，阵列基板包括多条栅线1251和多条数据线1282，栅线1251与数据线1282彼此交叉以限定多个子像素单元，在这种情况下，阵列基板10例如为子像素单元的阵列。当然，本发明实施例包括、但不限于此，只要是在阵列基板上呈阵列排布且包括多个导电结构的结构都可以作为阵列结构。例如，阵列结构10也可以为薄膜晶体管120的阵列。
例如，在至少一个实施例中，触控电极引线与触控电极异层设置，也就是说，触控电极引线与触控电极通过不同的膜层形成。
在本发明实施例中，触控电极引线可以为一体式结构(即完整连续的结构)，也可以包括多个组成部件。
例如，每条触控电极引线可以与上述多个导电结构中的任意一个同层设置且材料相同。在这种情况下，每条触控电极引线为一体式结构，其例如为线状结构，从而每条触控电极引线仅利用一次掩膜工艺即可形成。例如，每条触控电极引线与栅极、源极、漏极和遮挡层中的任意一个同层设置且材料相同。
如图2a所示，阵列基板的衬底基板110上设置有横纵交叉的多条栅线1251和多条数据线1282，栅线1251例如与薄膜晶体管120的栅极125连接并在同一次掩膜工艺中形成，数据线1282例如与薄膜晶体管120的源极127连接并在同一次掩膜工艺中形成。因此，当触控电极引线与薄膜晶体管的栅极同层设置且材料相同时，为了使触控电极引线与栅线相绝缘，触控电极引线可以设置在栅线的间隙中，例如触控电极引线与栅线同向延伸；同样地，当触控电极引线与薄膜晶体管的源极和漏极同层设置且材料相同时，触控电极引线可以设置在数据线的间隙中，例如触控电极引线与数据线同向延伸。但是，当触控电极引线和栅线或数据线的数量较多时，这种方式导致栅线所在的层或数据线所在的层上布线较复杂。
为了使栅线或数据线所在层上可以更灵活地布线，通过将每条触控电极引线设置为包括多个组成部件，本发明的至少一个实施例提供了一种既可以保证触控电极引线与栅线和数据线相绝缘、又便于灵活布线的方式。
例如，每条触控电极引线可以包括至少两个第一线状部和至少一个第一桥接部，该至少两个第一线状部与多条栅线同层设置，触控电极引线与多条 栅线中的至少一条相交，且在触控电极引线与栅线的交叉处，相邻的两个第一线状部通过一个第一桥接部连接。
或者，例如，每条触控电极引线可以包括至少两个第一线状部和至少一个第一桥接部，该至少两个第一线状部与多条数据线同层设置，触控电极引线与多条数据线中的至少一条相交，且在触控电极引线与数据线的交叉处，相邻的两个第一线状部通过一个第一桥接部连接。
在本发明实施例中，当触控电极引线包括多个组成部件时，这些组成部件可以部分或全部利用阵列基板原有的掩膜工艺形成。因此，触控电极引线的第一线状部和第一桥接部中的至少一个可以与阵列基板上原有的导电结构在同一次掩膜工艺中形成，即同层设置且材料相同。
例如，当所述至少两个第一线状部与多条栅线同层设置时，第一线状部、栅线和栅极可以同层设置且材料相同；当至少两个第一线状部与多条数据线同层设置时，第一线状部、数据线、源极和漏极可以同层设置且材料相同。
例如，当所述至少两个第一线状部与多条栅线同层设置时，第一桥接部与源极和漏极同层设置且材料相同；当至少两个第一线状部与多条数据线同层设置时，第一桥接部与栅极同层设置且材料相同。
例如，触控电极引线的第一线状部可以与栅极同层设置且材料相同，且第一桥接部与源极和漏极同层设置且材料相同；或者，触控电极引线的第一线状部可以与源极和漏极同层设置且材料相同，且第一桥接部与栅极同层设置且材料相同。
例如，当上述阵列结构包括多个薄膜晶体管和多个遮挡层，每个遮挡层位于每个薄膜晶体管的有源层与衬底基板之间时，第一桥接部可以与遮挡层同层设置且材料相同，而第一线状部可以与其他导电结构同层设置。
在至少一个实施例中，每个薄膜晶体管的有源层包括有源区、源极掺杂区和漏极掺杂区，源极和漏极分别通过第一过孔接触源极掺杂区和漏极掺杂区；第一桥接部通过第二过孔与每个第一线状部连接，第二过孔的至少一部分所穿过的层与第一过孔的至少一部分所穿过的层相同。如果第一过孔与第二过孔所穿过的层不完全相同，则在进行刻蚀工艺时，进行的刻蚀程度不同。本发明实施例通过使第一过孔所穿过的层与第二过孔所穿过的层至少部分相同，可以实现利用制作阵列基板上原有过孔的掩膜工艺形成用于连接第一桥 接部和第一线状部的过孔，从而进一步减少工艺流程和掩模板的数量。
例如，薄膜晶体管的有源层上设置有第一绝缘层，第一绝缘层上设置有栅极和第一线状部，第二绝缘层覆盖栅极和第一线状部，并且第二绝缘层上设置有源极、漏极以及第一桥接部，在这种情况下，第一过孔贯穿第一绝缘层和第二绝缘层(即包括位于第一绝缘层中的部分和位于第二绝缘层中的部分)，第二过孔贯穿第二绝缘层，从而可以在形成源极、漏极和第一桥接部之前通过一次掩膜工艺形成第一过孔以及第二过孔。
当阵列基板为ADS型阵列基板时，由于ADS型阵列基板中设置有公共电极层(例如，图2a中公共电极171所在的层)，为进一步减少工艺流程和掩模板的数量，可以将上述多个触控电极设置在公共电极层中，从而利用公共电极层制作触控电极。例如，可以在公共电极层中分别设置公共电极和触控电极，可通过分时驱动实现显示功能和触控功能；也可以在公共电极层中只设置触控电极，而不设置公共电极，通过复用的方式实现公共电极层中的电极在显示阶段作为公共电极、在触控阶段作为触控电极。
在阵列基板中，公共电极线通常设置在公共电极层的下方(即公共电极层与衬底基板之间)，并且公共电极与对应的公共电极线通过过孔连接。因此，在至少一个实施例中，触控电极引线可以位于公共电极层与衬底基板之间，这样，当上述多个触控电极设置在公共电极层中时，可以在同一次掩膜工艺中，形成对应公共电极线的过孔，以及用于连接触控电极与其对应触控电极引线的过孔，从而减少工艺流程以及掩模板的数量。
在本发明实施例中，触控电极与触控电极引线的线状部可以直接通过过孔连接，也可以通过其他连接结构连接，以提高触控电极引线布线的灵活性。例如，每条触控电极引线可以包括第二线状部和第二桥接部，第二桥接部连接触控电极引线对应的触控电极与第二线状部。
在本发明实施例中，触控电极引线的各组成部件可以都利用制作阵列基板上原有导电结构的掩膜工艺形成，而不需要增加新的掩膜工艺，也可以只有一部分组成部件利用制作阵列基板上原有导电结构的掩膜工艺形成。
例如，上述阵列结构10在包括多个薄膜晶体管120的基础上还可以包括分别与所述多个薄膜晶体管连接的多个第一电极(例如，图2a中的像素电极150)，所述第一电极属于上述多个导电结构100。在这种情况下，触控电极 引线的第二桥接部可以与阵列基板包括的第一电极同层设置且材料相同。
例如，触控电极引线的第二线状部可以通过在阵列基板已有掩膜工艺的基础上另外增加一次掩膜工艺形成。
需要说明的是，本发明实施例提供的阵列基板可以为用于液晶显示的阵列基板、有机发光二极管(OLED)阵列基板等。相应地，当阵列基板为用于液晶显示的阵列基板时，第一电极为像素电极150，其例如与薄膜晶体管120的漏极128连接，如图2a所示；当阵列基板为OLED阵列基板时，第一电极例如为阳极，其例如与薄膜晶体管的漏极连接。本发明实施例不限于此。
在阵列基板中，第一电极例如通过过孔与薄膜晶体管连接，因此，在至少一个实施例中，触控电极引线的第二线状部可以位于第一电极所在的层与衬底基板之间，这样由于触控电极引线的第二桥接部与第一电极同层设置，因而可以在同一次掩膜工艺中，形成用于连接第一电极和例如薄膜晶体管的漏极的过孔、用于连接第二桥接部与对应的触控电极的过孔、以及用于连接第二桥接部与对应的第二线状部的过孔，从而减少工艺流程以及掩模板数量。
当阵列基板为用于液晶显示的阵列基板时，阵列基板还可以包括设置于衬底基板上的公共电极层(例如，图2a中公共电极171所在的层)。在至少一个实施例中，当触控电极引线包括第二线状部和第二桥接部时，可以将上述多个触控电极设置在公共电极层中。关于公共电极层的设置，可以参考上述实施例中的相关描述，重复之处不再赘述。
在本发明实施例中，当多个触控电极设置在公共电极层中时，上述第一电极为像素电极。像素电极可以位于上层，且公共电极位于下层；或者，像素电极位于下层，且公共电极位于上层。
在至少一个实施例中，触控电极引线的第二线状部可以位于像素电极所在的层与公共电极层之间，从而可以利用阵列基板原有的过孔工艺形成用于连接第二桥接部与对应的触控电极的过孔以及用于连接第二桥接部与对应的第二线状部的过孔，以节省工艺流程。例如，根据实际情况，可以通过一次掩膜工艺，在形成用于连接公共电极与公共电极线的过孔或用于连接像素电极与漏极的过孔的同时，形成用于连接第二桥接部与对应的触控电极的过孔以及用于连接第二桥接部与对应的第二线状部的过孔。
在本发明实施例中，薄膜晶体管的栅极、源极、漏极和遮挡层都可以采 用铝、铜等金属材料或其合金制作并且可以为单层或多层结构，像素电极和公共电极都可以采用氧化铟锡、氧化铟锌等透明导电材料制作，缓冲层、栅极绝缘层、中间介电层、钝化层等绝缘结构都可以采用氮化硅(SiNx)、氧氮化硅(SixNiyO)或氧化硅(SiO2)等单层或多层绝缘材料制作，平坦层可以采用树脂等有机绝缘材料制作。本发明实施例不做限定。
为尽量减小触控电极引线的电阻，在本发明的上述实施例中，触控电极引线采用金属材料制作；或者，当触控电极引线包括线状部和桥接部时，至少触控电极引线的线状部采用金属材料制作，而桥接部可以采用金属材料制作，也可以采用透明导电材料制作。
本发明的至少一个实施例还提供了一种显示装置，其包括上述任一实施例所述的阵列基板。例如，该显示装置还可以包括与阵列基板相对设置的对置基板(例如彩膜基板)，对置基板与阵列基板通过封框胶密封在一起。例如，该显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、手表等任何具有显示功能的产品或部件。
本发明的至少一个实施例还提供了一种阵列基板的制作方法，其包括：在衬底基板上形成多个触控电极、用于将所述多个触控电极的信号引出的多条触控电极引线、以及包括多个导电结构阵列结构，使得每条触控电极引线的至少一部分与多个导电结构中的至少一个在同一次掩膜工艺中形成。
在阵列基板中，阵列结构可以包括多个薄膜晶体管。例如，每个薄膜晶体管可以包括栅极、源极和漏极，所述栅极、源极和漏极属于上述多个导电结构。
或者，例如，阵列结构在包括多个薄膜晶体管的基础上还可以包括多个遮挡层，每个遮挡层位于每个薄膜晶体管的有源层和衬底基板之间，所述遮挡层也属于上述多个导电结构。在本发明实施例中，遮挡层设置在衬底基板与薄膜晶体管的有源层之间，可以防止背光源的光照射到薄膜晶体管的有源层上，从而可以减小薄膜晶体管的漏电流。
因此，在至少一个实施例中，触控电极引线可以与上述多个导电结构中的任意一个在同一次掩膜工艺中形成。例如，通过一次掩膜工艺形成触控电极引线以及薄膜晶体管的栅极；或者通过一次掩膜工艺形成触控电极引线以 及薄膜晶体管的源极和漏极；或者通过一次掩膜工艺形成触控电极引线以及阵列结构包括的遮挡层，遮挡层位于衬底基板与薄膜晶体管的有源层之间。
在本发明实施例中，每条触控电极引线可以与栅线同层设置且相交，或者与数据线同层设置且相交。例如，每条触控电极引线与多条栅线和多条数据线绝缘，且与多条栅线或数据线中的至少一条相交；每条触控电极引线包括至少两个第一线状部和至少一个第一桥接部；并且所述至少两个第一线状部与多条栅线同层设置，触控电极引线与多条栅线中的至少一条相交，且在触控电极引线与栅线的交叉处，相邻的两个第一线状部通过一个第一桥接部连接，或者，所述至少两个第一线状部与多条数据线同层设置，触控电极引线与多条数据线中的至少一条相交，且在触控电极引线与数据线的交叉处，相邻的两个第一线状部通过一个第一桥接部连接。
例如，所述至少两个第一线状部与多条栅线同层设置时，可以通过一次掩膜工艺形成所述至少两个第一线状部、栅线以及薄膜晶体管的栅极；或者，所述至少两个第一线状部与多条数据线同层设置时，可以通过一次掩膜工艺形成至少两个第一线状部、数据线以及薄膜晶体管的源极和漏极。
例如，所述至少两个第一线状部与多条栅线同层设置时，通过一次掩膜工艺形成第一桥接部、以及薄膜晶体管的源极和漏极；或者，所述至少两个第一线状部与多条数据线同层设置时，通过一次掩膜工艺形成第一桥接部、以及薄膜晶体管的栅极。
例如，上述阵列结构在包括多个薄膜晶体管的基础上还包括多个遮挡层，每个遮挡层位于每个薄膜晶体管的有源层和衬底基板之间时，可以通过一次掩膜工艺形成第一桥接部和遮挡层。
需要说明的是，上述制作第一线状部和第一桥接部的掩膜工艺还可以根据实际需要选择性地组合在一起使用，此处不做赘述。
在本发明实施例中，触控电极与触控电极引线的线状部可以直接通过过孔连接，也可以通过其他连接结构连接，以提高触控电极引线布线的灵活性。例如，每条触控电极引线可以包括第二线状部和第二桥接部，第二桥接部连接触控电极引线对应的触控电极与第二线状部。
例如，可以通过一次掩膜工艺，形成第二桥接部与位于衬底基板上且与薄膜晶体管连接的第一电极。关于第一电极的设置，可以参考上述相关描述， 重复之处不再赘述。
下面结合具体实施例详细介绍本发明实施例提供的阵列基板及其制作方法。
实施例1
如图2b所示，本实施例提供的阵列基板包括衬底基板110和设置于衬底基板110上的遮挡层111、缓冲层112和薄膜晶体管120(图2b仅示出了一个薄膜晶体管120，该薄膜晶体管作为一个子像素的开关元件)。薄膜晶体管120为低温多晶硅薄膜晶体管，其包括依次设置于衬底基板110上的有源层123、栅极绝缘层124、栅极125、中间介电层126、以及同层设置在中间介电层126上的源极127和漏极128。在本实施中，每条触控电极引线1900与薄膜晶体管120的源极127和漏极128在同一次掩膜工艺中形成。从图2b中可以看出，触控电极引线1900与源极127和漏极128采用相同的材料制作且位于同一层中。
图2c为本实施例提供的一种阵列基板的俯视示意图，从图2c中可以看出，触控电极引线1900位于数据线1282之间的间隙中，且触控电极引线1900与数据线1282都沿纵向延伸。在图2c中，栅线1251与触控电极引线1900异面相交。
在本实施例中，在形成有薄膜晶体管120的衬底基板110上还可以依次设置第一绝缘层130、平坦层140、像素电极150、第二绝缘层160以及公共电极层。
在一个示例中，公共电极层中可以设置公共电极171和触控电极1720，即触控电极1720和公共电极171同层设置且材料相同。
在一个示例中，触控电极1720通过过孔1721与触控电极引线1900连接；过孔1721可以在形成用于连接公共电极171与其对应的公共电极线(图2b中未示出)的过孔的掩膜工艺中形成。
在本实施例中，由于触控电极引线1900与源极127和漏极128在同一次掩膜工艺中形成，触控电极1720与公共电极171在同一次掩膜工艺中形成，并且用于连接触控电极1720与其对应的触控电极引线1900的过孔1721与用于连接公共电极171与其对应的公共电极线的过孔在同一次掩膜工艺中形成，因此，本实施例有效地减少了制作阵列基板的工艺流程和使用的掩模板 的数量。
本实施例还提供了一种如图2b所示的阵列基板的制作方法，该方法包括如下步骤S101～S112，下面逐一介绍这些步骤。
步骤S101：通过第一次掩膜工艺，在衬底基板110上形成遮挡层111。
步骤S102：形成覆盖遮挡层111的缓冲层112。
步骤S103：通过第二次掩膜工艺，在缓冲层112上形成有源层123。
步骤S104：形成覆盖有源层123的栅极绝缘层124；通过第三次掩膜工艺，在栅极绝缘层124上形成光刻胶的图形；之后以光刻胶的图形为掩膜，对有源层123进行掺杂，使有源层123形成有源区123a、源极掺杂区123b和漏极掺杂区123c，有源区123a对应遮挡层111，源极掺杂区123b和漏极掺杂区123c分别位于有源区123a的两侧；在掺杂结束后去除光刻胶。
步骤S105：通过第四次掩膜工艺，在栅极绝缘层124上形成栅极125、多条栅线以及公共电极线(栅线和公共电极线在图2b中未示出)。
步骤S106：形成覆盖栅极125的中间介电层126，通过第五次掩膜工艺，分别在对应上述源极掺杂区123b和漏极掺杂区123c的位置处形成过孔1271和1281，以暴露出源极掺杂区123b和漏极掺杂区123c。
步骤S107：通过第六次掩膜工艺，在中间介电层126上形成源极127、漏极128、触控电极引线1900以及多条数据线(图2b中未示出)，源极127通过过孔1271与源极掺杂区123b接触，漏极128通过过孔1281与漏极掺杂区123c接触。
步骤S108：形成覆盖薄膜晶体管120的第一钝化层130。
步骤S109：在第一钝化层130上形成平坦层140，通过第七次掩膜工艺，在对应漏极128的位置处形成过孔151以暴露出漏极128。
步骤S110：通过第八次掩膜工艺，在平坦层140上形成像素电极150，像素电极150通过过孔151与漏极128接触。
步骤S111：形成覆盖像素电极150的第二钝化层160，通过第九次掩膜工艺，在对应公共电极线(图2b中未示出)的位置处形成过孔以暴露出公共电极线，并在对应触控电极引线1900的位置处形成过孔1721以暴露出触控电极引线1900。
步骤S112：通过第十次掩膜工艺，在第二钝化层160上形成公共电极 171和触控电极1720，公共电极171通过过孔与对应的公共电极线连接，触控电极1720通过过孔1721与对应的触控电极引线1900连接。
从以上步骤S101至S112可以看出，与图1所示的阵列基板的制作方法相比，本实施例提供的制作方法只需12个步骤、10次掩膜工艺，节省了2个步骤、2个掩模板，有效地减少了工艺流程和掩模板的数量。
需要说明的是，用于连接触控电极1720与触控电极引线1900的过孔1721还可以通过多次掩膜工艺形成，例如，可以在平坦层中形成过孔151的同时在对应触控电极引线1900的位置处形成过孔，然后在后续的步骤中将位于该过孔中的像素电极材料、第二钝化层材料刻蚀掉。此外，本实施例仅以公共电极线与栅极在同一次掩膜工艺中形成为例进行说明，根据实际需要，公共电极线还可以设置在其他层中。
实施例2
图3a和图3b分别为本实施例提供的一种阵列基板的剖视示意图和俯视示意图。如图3a和图3b所示，本实施例与实施例1的区别在于：每个触控电极引线1900与至少一条栅线1251相交且绝缘，每条触控电极引线1900包括至少两个第一线状部1901(如A、B之间的部分所示)和至少一个第一桥接部1902(如B、C之间的部分所示)；在触控电极引线1900与栅线1251相交的位置O处，第一桥接部1902通过过孔1903连接相邻的两个第一线状部1901。
如图3a和图3b所示，在一个示例中，第一线状部1901、栅极125和栅线1251采用相同的材料制作且位于同一层；在一个示例中，第一桥接部1902、源极127、漏极128和数据线(图中未示出)采用相同的材料制作且位于同一层。当然，本实施例不限于此。
相应地，本实施例提供了一种如图3a所示的阵列基板的制作方法，该方法总体上与实施例1提供的制作方法相同，也只需12个步骤、10张掩模板即可完成阵列基板的制作，但区别如下。
在步骤S105中，通过第四次掩膜工艺，在栅极绝缘层124上形成栅极125、多条栅线1251、公共电极线以及触控电极引线1900的第一线状部1901，使相邻的第一线状部1901之间的间隙中设置有至少一条栅线1251；
在步骤S106中，形成覆盖栅极125的中间介电层126，通过第五次掩膜 工艺，分别在对应上述源极掺杂区123b和漏极掺杂区123c的位置处形成第一过孔1271和1281以暴露出源极掺杂区123b和漏极掺杂区123c，并且在相邻的两个第一线状部的位置B和C处形成第二过孔1903；
在步骤S107中，通过第六次掩膜工艺，在中间介电层126上形成源极127、漏极128、触控电极引线1900的第一桥接部1902以及多条数据线(图3a中未示出)，源极127和漏极128分别通过第一过孔1271和1281与源极掺杂区123b和漏极掺杂区123c接触，第一桥接部1902通过第二过孔1903连接相邻的两个第一线状部1901。
实施例3
如图4所示，本实施例与实施例1的区别在于：每条触控电极引线1900与薄膜晶体管120的遮挡层111在同一次掩膜工艺中形成。从图4中可以看出，触控电极引线1900与薄膜晶体管120的遮挡层111采用相同的材料制作并位于同一层中。
相应地，本实施例提供了一种如图4所示的阵列基板的制作方法，该方法总体上与实施例1提供的制作方法相同，也只需12个步骤、10张掩模板即可完成阵列基板的制作，但区别在于：在步骤S101中，通过第一次掩膜工艺，在衬底基板110上形成遮挡层111以及触控电极引线1900，而在步骤S107中则不需要形成触控电极引线1900。
本实施例提供的阵列基板及其制作方法，触控电极引线与薄膜晶体管的遮挡层同层设置，由于在遮挡层所在的层中无栅线、数据线等，触控电极引线在该层的布线方式可以更加灵活，只要不显著影响开口率即可；并且与实施例2相比，触控电极引线的制作工艺较简单。
实施例4
如图5所示，本实施例提供的阵列基板与实施例1的区别在于：每条触控电极引线1900包括第二线状部1905和第二桥接部1904，第二桥接部1904连接触控电极1720以及该触控电极对应的触控电极引线的第二线状部1905。
上述实施例1至3以公共电极171位于上层且像素电极150位于下层为例进行说明；本实施例以公共电极171位于下层且像素电极150位于上层为例进行说明。
在一个示例中，触控电极1720与公共电极171可以在同一次掩膜工艺中 形成，在这种情况下，触控电极1720和公共电极171采用相同的材料制作且位于同一层。
在一个示例中，第二钝化层160设置在触控电极1720和公共电极171上，触控电极引线1900的第二线状部1905可以通过单独的掩膜工艺形成在第二钝化层160上，第三钝化层180覆盖触控电极引线1900的第二线状部1905，之后像素电极150形成在第三钝化层180上，像素电极150通过过孔151与薄膜晶体管120的漏极128连接，触控电极引线1900的第二桥接部1904与像素电极150在同一次掩膜工艺中形成(同层设置且材料相同)，并分别通过过孔1906和过孔1907与触控电极1720以及第二线状部1905连接。
相应地，本实施例提供了一种如图5所示的阵列基板的制作方法，由于本实施例未利用薄膜晶体管的导电结构的材料形成触控电极引线1900，因而，本实施例提供的方法中，步骤S201至步骤S208与如图1所示的阵列基板的制作方法中的步骤S01至步骤S08类似。该本实施例提供的方法与实施例1提供的制作方法相比，有如下区别。
在步骤S209中，在第一钝化层130上形成平坦层140，通过第七次掩膜工艺，在对应公共电极线(图5中未示出)的位置处形成过孔以暴露出公共电极线。
在步骤S210中：通过第八次掩膜工艺，在平坦层140上形成公共电极171和触控电极1720，公共电极171与对应的公共电极线通过步骤S209中形成的过孔连接。
步骤S211：形成覆盖公共电极171和触控电极1720的第二钝化层160。
步骤S212：通过第九次掩膜工艺，在第二钝化层160上形成触控电极引线1900的第二线状部1905。
步骤S213：形成覆盖触控电极引线1900的第二线状部1905的第三钝化层180，并且通过第十次掩膜工艺形成对应漏极128的过孔151、对应触控电极1720的过孔1906以及对应触控电极引线1900的第二线状部1905的过孔1907。
步骤S214：通过第十一次掩膜工艺，形成通过过孔151连接漏极128的像素电极150，并形成触控电极引线1900的第二桥接部1904，第二桥接部1904分别通过过孔1906和1907连接触控电极1720和触控电极引线1900的 第二线状部1905。
从以上步骤可以看出，与图1所示的阵列基板的制作方法相比，本实施例提供的制作方法只需11次掩膜工艺，节省了1张掩模板。
本发明的上述实施例以薄膜晶体管为低温多晶硅薄膜晶体管为例进行说明，但其还可以为非晶硅型、金属氧化物型等其他类型的薄膜晶体管。阵列基板可以采用自电容原理，也可以采用互电容原理，即触控电极可以为自电容电极，也可以为触控驱动电极或触控感应电极。本发明实施例不做限定。
综上所述，本发明实施例通过利用制作阵列基板中原有的导电结构的掩膜工艺制作触控电极引线的至少一部分，减少了掩模板的数量。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2015年3月06日递交的中国专利申请第201510101319.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板，
    多个触控电极，设置于所述衬底基板上；
    多条触控电极引线，设置于所述衬底基板上且用于分别将所述多个触控电极的信号引出；以及
    阵列结构，包括多个导电结构且设置于所述衬底基板上；其中，
    每条触控电极引线的至少一部分与所述多个导电结构中的至少一个同层设置且材料相同。
  2. 如权利要求1所述的阵列基板，其中，
    所述阵列结构包括多个薄膜晶体管，每个薄膜晶体管包括栅极、源极和漏极，所述栅极、源极和漏极属于所述多个导电结构。
  3. 如权利要求2所述的阵列基板，其中，所述阵列结构还包括多个遮挡层，每个遮挡层位于每个薄膜晶体管的有源层和所述衬底基板之间，所述遮挡层属于所述多个导电结构。
  4. 如权利要求2或3所述的阵列基板，其中，每条触控电极引线与所述多个导电结构中的一个同层设置且材料相同。
  5. 如权利要求2所述的阵列基板，还包括：设置于所述衬底基板上且与所述多条触控电极引线绝缘的多条栅线和多条数据线，其中，
    每条触控电极引线包括至少两个第一线状部和至少一个第一桥接部；并且
    所述至少两个第一线状部与所述多条栅线同层设置，所述触控电极引线与所述多条栅线中的至少一条相交，且在所述触控电极引线与所述栅线的交叉处，相邻的两个第一线状部通过一个第一桥接部连接；或者
    所述至少两个第一线状部与所述多条数据线同层设置，所述触控电极引线与所述多条数据线中的至少一条相交，且在所述触控电极引线与所述数据线的交叉处，相邻的两个第一线状部通过一个第一桥接部连接。
  6. 如权利要求5所述的阵列基板，其中，
    当所述至少两个第一线状部与所述多条栅线同层设置时，所述第一线状 部、所述栅线和所述栅极同层设置且材料相同；
    当所述至少两个第一线状部与所述多条数据线同层设置时，所述第一线状部、所述数据线、所述源极和所述漏极同层设置且材料相同。
  7. 如权利要求5或6所述的阵列基板，其中，
    当所述至少两个第一线状部与所述多条栅线同层设置时，所述第一桥接部与所述源极和所述漏极同层设置且材料相同；
    当所述至少两个第一线状部与所述多条数据线同层设置时，所述第一桥接部与所述栅极同层设置且材料相同。
  8. 如权利要求5或6所述的阵列基板，其中，
    所述阵列结构还包括多个遮挡层，每个遮挡层位于每个薄膜晶体管的有源层与所述衬底基板之间，所述遮挡层属于所述多个导电结构；
    所述第一桥接部与所述遮挡层同层设置且材料相同。
  9. 如权利要求5-7任一项所述的阵列基板，其中，
    每个薄膜晶体管的有源层包括有源区、源极掺杂区和漏极掺杂区，所述源极和所述漏极分别通过第一过孔接触所述源极掺杂区和所述漏极掺杂区；
    所述第一桥接部通过第二过孔与每个第一线状部连接，所述第二过孔的至少一部分所在的层与所述第一过孔的至少一部分所在的层相同。
  10. 如权利要求1-9任一项所述的阵列基板，还包括：设置于所述衬底基板上的公共电极层，其中，所述多个触控电极设置于所述公共电极层中。
  11. 如权利要求10所述的阵列基板，其中，所述多条触控电极引线位于所述公共电极层与所述衬底基板之间。
  12. 如权利要求1所述的阵列基板，其中，每条触控电极引线包括第二线状部和第二桥接部，所述第二桥接部连接所述触控电极引线对应的触控电极与所述第二线状部。
  13. 如权利要求12所述的阵列基板，其中，
    所述阵列结构包括多个薄膜晶体管以及与所述多个薄膜晶体管分别连接的多个第一电极，所述第一电极属于所述多个导电结构；
    所述第二桥接部与所述第一电极同层设置且材料相同。
  14. 如权利要求13所述的阵列基板，其中，所述第二线状部位于所述第一电极所在的层与所述衬底基板之间。
  15. 如权利要求13或14所述的阵列基板，还包括：设置于所述衬底基板上的公共电极层，其中，所述多个触控电极设置于所述公共电极层中。
  16. 如权利要求15所述的阵列基板，其中，所述第二线状部位于所述第一电极所在的层与所述公共电极层之间，所述第一电极为像素电极。
  17. 一种显示装置，包括如权利要求1-16任一项所述的阵列基板。
  18. 一种阵列基板的制作方法，包括：
    在衬底基板上形成多个触控电极；
    在衬底基板上形成用于将所述多个触控电极的信号引出的多条触控电极引线；以及
    在衬底基板上形成包括多个导电结构的阵列结构；其中，
    每条触控电极引线的至少一部分与所述多个导电结构中的至少一个在同一次掩膜工艺中形成。
  19. 如权利要求18所述的制作方法，其中，
    每条多条触控电极引线与多条栅线和多条数据线绝缘，且每条触控电极引线与所述多条栅线或数据线中的至少一条相交；
    每条触控电极引线包括至少两个第一线状部和至少一个第一桥接部；并且
    所述至少两个第一线状部与所述多条栅线同层设置，所述触控电极引线与所述多条栅线中的至少一条相交，且在所述触控电极引线与所述栅线的交叉处，相邻的两个第一线状部通过一个第一桥接部连接；或者
    所述至少两个第一线状部与所述多条数据线同层设置，所述触控电极引线与所述多条数据线中的至少一条相交，且在所述触控电极引线与所述数据线的交叉处，相邻的两个第一线状部通过一个第一桥接部连接。
  20. 如权利要求18所述的制作方法，其中，每条触控电极引线包括第二线状部和第二桥接部，所述第二桥接部连接所述触控电极引线对应的触控电极与所述第二线状部。
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