WO2017124686A1 - Tft阵列基板结构及其制作方法 - Google Patents

Tft阵列基板结构及其制作方法 Download PDF

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Publication number
WO2017124686A1
WO2017124686A1 PCT/CN2016/086129 CN2016086129W WO2017124686A1 WO 2017124686 A1 WO2017124686 A1 WO 2017124686A1 CN 2016086129 W CN2016086129 W CN 2016086129W WO 2017124686 A1 WO2017124686 A1 WO 2017124686A1
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layer
tft
silicon nitride
metal layer
array substrate
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PCT/CN2016/086129
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English (en)
French (fr)
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陈辰
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武汉华星光电技术有限公司
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Priority to US15/115,912 priority Critical patent/US20180069033A1/en
Publication of WO2017124686A1 publication Critical patent/WO2017124686A1/zh

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT array substrate structure and a method of fabricating the same.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • liquid crystal displays which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to fill liquid crystal molecules between a Thin Film Transistor Array Substrate (TFT Array Substrate) and a Color Filter (CF), and apply driving on the two substrates.
  • TFT Array Substrate Thin Film Transistor Array Substrate
  • CF Color Filter
  • the TFT array substrate is a circuit substrate for driving the liquid crystal layer, and includes a plurality of gate lines and data lines, and a plurality of pixel lines and a plurality of data lines perpendicular to each other form a plurality of pixel units, and each of the pixel units A thin film transistor, a pixel electrode, a storage capacitor, and the like are provided.
  • the thin film transistor includes a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode.
  • the thin film transistor When the gate line is driven, the thin film transistor is in an on state, and the corresponding data line is fed with a gray scale voltage signal and loaded to the pixel electrode, so that the pixel electrode generates a corresponding electric field, and the liquid crystal molecules in the liquid crystal layer are The orientation change occurs under the action of the electric field, so that different image display can be realized.
  • the gate electrode of the thin film transistor and the gate line are in the same layer to form a first metal layer, and the source electrode, the drain electrode, and the data line of the thin film transistor are located in the same layer to form a second metal layer.
  • An interlayer dielectric (ILD) layer is required between the metal layer and the second metal layer as an insulating layer for isolating the first metal layer from the second metal layer.
  • the existing ILD layer is generally composed of a silicon oxide (SiOx) layer and a silicon nitride (SiNx) layer, wherein the silicon oxide layer has good thermal insulation and film internal stress, and the silicon nitride layer has high hydrogen content and good
  • the impurity ion is isolated, so the silicon oxide layer is preceded or the silicon nitride layer is applied first in the film formation sequence of the ILD layer in the products of major manufacturers.
  • the silicon nitride layer has a high hydrogen content, a large amount of H + can be generated at a high temperature, which can be used as a hydrogen ion source for the hydrogenation process, and its effect on productivity, as shown in FIG.
  • the manufacturer prefers to form a silicon nitride layer 20 (containing hydrogen) on the substrate 10 and then forming a film formation order of the silicon monoxide layer 30 on the silicon nitride layer.
  • a silicon nitride layer 20 containing hydrogen
  • the structure in which the silicon oxide layer 30 is placed on the silicon nitride layer 20 can ensure the production efficiency and productivity of the hydrogenation process, since the silicon oxide layer 30 has a poor effect on the impurity ion isolation, it is necessary to carry out impurity ion contamination using this structure. risks of.
  • the object of the present invention is to provide a TFT array substrate structure capable of improving the isolation protection capability of the interlayer dielectric layer against impurity ions without affecting the hydrogenation effect, avoiding the risk of impurity ion contamination, shortening the hydrogenation time, and increasing the productivity. .
  • Another object of the present invention is to provide a method for fabricating a TFT array substrate, which can improve the isolation protection capability of the interlayer dielectric layer against impurity ions, avoid the risk of impurity ion contamination, shorten the hydrogenation time, and increase the productivity.
  • the present invention provides a TFT array substrate structure including: a substrate, a first metal layer disposed on the substrate, an interlayer dielectric layer covering the first metal layer, and an interlayer dielectric layer a second metal layer on the interlayer dielectric layer;
  • the interlayer dielectric layer includes a lower silicon nitride layer disposed on the first metal layer, a silicon oxide layer disposed on the lower silicon nitride layer, and an upper portion disposed on the silicon oxide layer Silicon nitride layer;
  • the lower silicon nitride layer contains hydrogen.
  • the TFT array substrate structure further includes: a first insulating layer disposed under the first metal layer, a semiconductor layer disposed under the first insulating layer, a buffer layer disposed under the semiconductor layer, and a buffer layer a light shielding layer under the buffer layer.
  • a planar layer disposed on the second metal layer, a bottom electrode disposed on the planar layer, a protective layer disposed on the underlying electrode, and a top electrode disposed on the protective layer.
  • the first metal layer includes a gate of the TFT and a gate line connected to a gate of the TFT.
  • the second metal layer includes a source of the TFT, a drain of the TFT, and a data line connected to a source of the TFT.
  • the invention also provides a method for fabricating a TFT array substrate, comprising the following steps:
  • Step 1 providing a substrate, depositing and patterning a first metal layer on the substrate;
  • Step 2 forming a lower silicon nitride layer on the first metal layer, the lower silicon nitride layer containing hydrogen;
  • Step 3 forming a silicon oxide layer on the lower silicon nitride layer
  • Step 4 forming a silicon nitride layer on the silicon oxide layer, the lower silicon nitride layer and silicon oxide The layer and the upper silicon nitride layer together form an interlayer dielectric layer;
  • Step 5 Form a second metal layer on the interlayer dielectric layer.
  • the step 2 uses a chemical vapor deposition process to form a silicon nitride layer
  • the step 3 uses a chemical vapor deposition process to form a silicon oxide layer
  • the step 4 uses a chemical vapor deposition process to form a silicon nitride layer.
  • the method further comprises: sequentially forming a light shielding layer, a buffer layer, a semiconductor layer, and a first insulating layer on the substrate from bottom to top.
  • the method further comprises: sequentially forming a flat layer, a bottom electrode, a protective layer, and a top electrode from bottom to top on the second metal layer.
  • the first metal layer includes: a gate of the TFT and a gate line connected to a gate of the TFT; the second metal layer includes: a source of the TFT, a drain of the TFT, and the TFT The source is connected to the data line.
  • the present invention also provides a TFT array substrate structure, including: a substrate, a first metal layer disposed on the substrate, an interlayer dielectric layer covering the first metal layer, and a dielectric layer disposed between the layers a second metal layer on the layer;
  • the interlayer dielectric layer includes a lower silicon nitride layer disposed on the first metal layer, a silicon oxide layer disposed on the lower silicon nitride layer, and an upper portion disposed on the silicon oxide layer a silicon nitride layer; the lower silicon nitride layer contains hydrogen;
  • the first metal layer includes: a gate of the TFT; and a gate line connected to a gate of the TFT;
  • the second metal layer includes a source of the TFT, a drain of the TFT, and a data line connected to a source of the TFT.
  • the TFT array substrate structure and the manufacturing method thereof provided by the present invention adopt an interlayer dielectric layer of a lower silicon nitride layer, a silicon oxide layer, and an upper silicon nitride layer, and a lower nitrogen layer
  • the silicon-containing layer contains hydrogen to provide hydrogen ions for the hydrogenation process
  • the upper silicon nitride layer enhances the isolation protection of the interlayer dielectric layer from impurity ions, and includes only a silicon oxide layer and a silicon nitride layer compared to the prior art.
  • the double-layered intermediate dielectric layer can improve the isolation protection of the interlayer dielectric layer against impurity ions without affecting the hydrogenation effect, avoid the risk of impurity ion contamination, shorten the hydrogenation time, and increase the productivity.
  • 1 is a schematic structural view of a conventional interlayer dielectric layer
  • FIG. 2 is a schematic view showing the structure of a TFT array substrate of the present invention.
  • FIG. 3 is a flow chart showing a method of fabricating a TFT array substrate of the present invention.
  • the present invention firstly provides a TFT array substrate structure, including: a substrate 1 , a first metal layer 2 disposed on the substrate 1 , and an interlayer dielectric layer 3 covering the first metal layer 2 . And a second metal layer 4 disposed on the interlayer dielectric layer 3.
  • the interlayer dielectric layer 3 includes a lower silicon nitride layer 31 disposed on the first metal layer 2, a silicon oxide layer 32 disposed on the lower silicon nitride layer 31, and the oxide layer
  • the upper silicon nitride layer 33 on the silicon layer 32; the lower silicon nitride layer 31 contains hydrogen.
  • the present invention employs an interlayer dielectric layer 3 of a three-layer structure of a lower silicon nitride layer 31, a silicon oxide layer 32, and an upper silicon nitride layer 33.
  • the lower silicon nitride layer 31 contains hydrogen as a hydrogen ion during hydrogenation.
  • the source compared with the two-layer interlayer dielectric layer structure in which a silicon nitride layer is disposed on the silicon oxide layer in the prior art, the hydrogenation time is shorter, and the productivity can be improved.
  • the layer 33 has stronger impurity ion isolation protection than the silicon oxide layer 32, compared to the two-layer interlayer dielectric layer structure in which the silicon oxide layer is disposed on a silicon nitride layer in the prior art. Effectively avoid the risk of impurity ion contamination.
  • the first metal layer 2 of the array substrate further includes: a first insulating layer disposed under the first metal layer 2, and a semiconductor layer disposed under the first insulating layer, a buffer layer under the semiconductor layer and a light shielding layer disposed under the buffer layer; and a flat layer provided on the second metal layer 4, a bottom electrode provided on the flat layer, and the bottom layer
  • the protective layer on the electrode and the top electrode disposed on the protective layer are the same as the existing TFT array substrate structure, and will not be further described here.
  • the substrate 1 is a glass substrate, and the materials of the first metal layer 2 and the second metal layer 4 are one of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • the material of the top electrode and the bottom electrode is Indium Tin Oxide (ITO).
  • the first metal layer 2 includes: a gate of the TFT and a gate line connected to a gate of the TFT;
  • the second metal layer 4 includes: a source of the TFT, a drain of the TFT, And a data line connected to the source of the TFT.
  • the semiconductor layer includes a channel region located in the intermediate region, and a contact region located at both ends of the channel region.
  • the source and the drain of the TFT pass through the interlayer dielectric layer 3 and the first
  • the via of the insulating layer is in contact with a contact region at both ends of the semiconductor layer;
  • the top electrode is in contact with the drain of the TFT through a via penetrating through the protective layer, the underlying electrode, and the flat layer.
  • the present invention further provides a method for fabricating an array substrate, comprising the following steps:
  • Step 1 Providing a substrate 1 on which the first metal layer 2 is deposited and patterned.
  • a light shielding layer, a buffer layer, a semiconductor layer, and a first insulating layer are sequentially formed on the substrate 1 in this order from bottom to top.
  • the substrate 1 is a glass substrate; the material of the first metal layer 2 is a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the semiconductor layer includes a channel region at an intermediate region and a contact region at both ends of the channel region.
  • the first metal layer 2 includes a gate of the TFT and a gate line connected to the gate of the TFT.
  • Step 2 Form a lower silicon nitride layer 31 on the first metal layer 2 by a chemical vapor deposition process (CVD), and the lower silicon nitride layer 31 contains hydrogen.
  • CVD chemical vapor deposition process
  • Step 3 Forming a silicon oxide layer 32 on the lower silicon nitride layer 31 by a chemical vapor deposition process.
  • Step 4 forming a silicon nitride layer 33 on the silicon oxide layer 32 by a chemical vapor deposition process, and the lower silicon nitride layer 31, the silicon oxide layer 32, and the upper silicon nitride layer 33 together form an interlayer Dielectric layer 3.
  • Step 5 Depositing and patterning the second metal layer 4 on the interlayer dielectric layer 3.
  • the second metal layer 4 includes a source of the TFT, a drain of the TFT, and a data line connected to a source of the TFT.
  • a flat layer, a bottom electrode, a protective layer, and a top electrode are sequentially formed on the second metal layer 4 from bottom to top.
  • a source and a drain of the TFT are respectively in contact with a contact region of the semiconductor layer through a via hole penetrating the interlayer dielectric layer 3 and the first insulating layer; the top electrode passes through the protective layer, the bottom electrode, and the flat The via of the layer is in contact with the drain of the TFT.
  • the method for fabricating the TFT array substrate of the present invention comprises: continuously forming a silicon nitride layer 31, a silicon oxide layer 32, and an upper silicon nitride layer 33 by a chemical vapor deposition process to obtain the lower silicon nitride layer 31,
  • the silicon oxide layer 32 and the upper silicon nitride layer 33 have a three-layer interlayer dielectric layer 3.
  • the lower silicon nitride layer 31 contains hydrogen as a source of hydrogen ions during hydrogenation, compared to the prior art.
  • the impurity ion isolation protection capability can effectively avoid the risk of impurity ion contamination compared to the two-layer interlayer dielectric layer structure in which the silicon oxide layer is disposed on a silicon nitride layer in
  • the TFT array substrate structure and the manufacturing method thereof of the present invention adopt an interlayer dielectric layer of a lower silicon nitride layer, a silicon oxide layer, and an upper silicon nitride layer, and a lower silicon nitride layer Hydrogen provides hydrogen ions for the hydrogenation process, and the upper silicon nitride layer enhances the isolation protection of the interlayer dielectric layer from impurity ions, compared to the prior art comprising a double layer structure of a silicon oxide layer and a silicon nitride layer.
  • the intermediate dielectric layer can improve the isolation protection ability of the interlayer dielectric layer against impurity ions without affecting the hydrogenation effect, avoid the risk of impurity ion contamination, shorten the hydrogenation time, and increase the production capacity.

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  • Thin Film Transistor (AREA)

Abstract

一种TFT阵列基板结构及其制作方法，采用下氮化硅层（31）、氧化硅层（32）和上氮化硅层（33）三层结构的层间介电层（3），下氮化硅层（31）含氢，为氢化工艺提供氢离子，上氮化硅层（33）提升层间介电层（3）对杂质离子的隔绝防护能力，相比于仅包括一氧化硅层与一氮化硅层的双层结构的层间介电层，能够在不影响氢化效果的前提下，提升层间介电层对杂质离子的隔绝防护能力，避免杂质离子污染的风险，缩短氢化时间，提升产能。

Description

TFT阵列基板结构及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板结构及其制作方法。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片基板(Color Filter，CF)之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
TFT阵列基板是对液晶层进行驱动的电路基板，包括多条栅极线和数据线，相互垂直的多条栅极线和多条数据线形成了多个像素单元，且每个像素单元内均设置有薄膜晶体管、像素电极及存储电容等。薄膜晶体管包括一栅电极连接至栅极线，源电极连接至数据线，漏电极连接至像素电极。当栅极线被驱动时，薄膜晶体管处于导通状态，对应的数据线送入灰阶电压信号并将其加载至像素电极，从而使得像素电极产生相应的电场，液晶层中的液晶分子则在电场的作用下发生取向变化，因此可以实现不同的图像显示。
在TFT阵列基板中薄膜晶体管的栅电极与栅极线位于同一层，共同构成第一金属层，薄膜晶体管的源电极、漏电极、和数据线位于同一层，共同构成第二金属层，在第一金属层和第二金属层之间需要设置层间介电(Interlayer Dielectric，ILD)层作为隔离第一金属层与第二金属层的绝缘层。现有的ILD层一般由一氧化硅(SiOx)层和一氮化硅(SiNx)层组成，其中，氧化硅层拥有良好的保温性及膜内应力，氮化硅层拥有高氢含量及良好的杂质离子隔绝作用，因此在各大厂商的产品中ILD层的成膜顺序上氧化硅层在先或者氮化硅层在先都有所应用。进一步地，考虑到氮化硅层 拥有高氢含量，在高温中可以产生大量的H+，可以被用作氢化工艺的氢离子来源，及其对产能的影响，如图1所示，各大厂商更青睐先在基板10上成膜一氮化硅层20(含氢)、然后在氮化硅层上成膜一氧化硅层30的这种成膜顺序。氧化硅层30置于氮化硅层20之上的结构虽然可以保证氢化工艺的生产效率和产能，但由于氧化硅层30对杂质离子隔绝效果较差，使用这种结构就需要承担杂质离子污染的风险。
发明内容
本发明的目的在于提供一种TFT阵列基板结构，能够在不影响氢化效果的前提下，提升层间介电层对杂质离子的隔绝防护能力，避免杂质离子污染的风险，缩短氢化时间，提升产能。
本发明的目的还在于提供一种TFT阵列基板的制作方法，能够提升层间介电层对杂质离子的隔绝防护能力，避免杂质离子污染的风险，缩短氢化时间，提升产能。
为实现上述目的，本发明提供了一种TFT阵列基板结构，包括：基板、设于所述基板上的第一金属层、覆盖所述第一金属层的层间介电层、及设于所述层间介电层上第二金属层；
所述层间介电层包括设于所述第一金属层上的下氮化硅层、设于所述下氮化硅层上的氧化硅层、及设于所述氧化硅层上的上氮化硅层；
所述下氮化硅层含氢。
所述TFT阵列基板结构还包括：设于所述第一金属层下方的第一绝缘层、设于所述第一绝缘层下方的半导体层、设于所述半导体层下方的缓冲层、以及设于所述缓冲层下方的遮光层。
以及设于所述第二金属层上的平坦层、设于所述平坦层上的底层电极、设于所述底层电极上的保护层、以及设于所述保护层上的顶层电极。
所述第一金属层包括：TFT的栅极、及与所述TFT的栅极连接的栅极线。
所述第二金属层包括：TFT的源极、TFT的漏极、及与所述TFT的源极连接的数据线。
本发明还提供一种TFT阵列基板的制作方法，包括如下步骤：
步骤1、提供一基板，在所述基板上沉积并图案化第一金属层；
步骤2、在所述第一金属层上成膜下氮化硅层，所述下氮化硅层含氢；
步骤3、在所述下氮化硅层上成膜氧化硅层；
步骤4、在所述氧化硅层上成膜上氮化硅层，所述下氮化硅层、氧化硅 层、及上氮化硅层共同构成层间介电层；
步骤5、在所述层间介电层上制作第二金属层。
所述步骤2采用化学气相沉积工艺成膜下氮化硅层，所述步骤3采用化学气相沉积工艺成膜氧化硅层，所述步骤4采用化学气相沉积工艺成膜上氮化硅层。
所述步骤1之前还包括：在所述基板上自下而上依次制作遮光层、缓冲层、半导体层、和第一绝缘层。
所述步骤5之后还包括：在所述第二金属层上自下而上依次制作平坦层、底层电极、保护层、和顶层电极。
所述第一金属层包括：TFT的栅极、及与所述TFT的栅极连接的栅极线；所述第二金属层包括：TFT的源极、TFT的漏极、及与所述TFT的源极连接的数据线。
本发明还提供一种TFT阵列基板结构，包括：基板、设于所述基板上的第一金属层、覆盖所述第一金属层的层间介电层、及设于所述层间介电层上第二金属层；
所述层间介电层包括设于所述第一金属层上的下氮化硅层、设于所述下氮化硅层上的氧化硅层、及设于所述氧化硅层上的上氮化硅层；所述下氮化硅层含氢；
其中，所述第一金属层包括：TFT的栅极、及与所述TFT的栅极连接的栅极线；
其中，所述第二金属层包括：TFT的源极、TFT的漏极、及与所述TFT的源极连接的数据线。
本发明的有益效果：本发明提供的一种TFT阵列基板结构及其制作方法，采用下氮化硅层、氧化硅层、和上氮化硅层三层结构的层间介电层，下氮化硅层含氢为氢化工艺提供氢离子，上氮化硅层提升层间介电层对杂质离子的隔绝防护能力，相比于现有技术中仅包括一氧化硅层与一氮化硅层的双层结构的中间介电层，能够在不影响氢化效果的前提下，提升层间介电层对杂质离子的隔绝防护能力，避免杂质离子污染的风险，缩短氢化时间，提升产能。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的层间介电层的结构示意图；
图2为本发明的TFT阵列基板结构的示意图；
图3为本发明的TFT阵列基板的制作方法的流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明首先提供一种TFT阵列基板结构，包括：基板1、设于所述基板1上的第一金属层2、覆盖所述第一金属层2的层间介电层3、及设于所述层间介电层3上第二金属层4。所述层间介电层3包括设于所述第一金属层2上的下氮化硅层31、设于所述下氮化硅层31上的氧化硅层32、及设于所述氧化硅层32上的上氮化硅层33；所述下氮化硅层31含氢。
本发明采用下氮化硅层31、氧化硅层32、和上氮化硅层33三层结构的层间介电层3，下氮化硅层31含氢能够在进行氢化时作为氢离子的来源，相比于现有技术中将一氮化硅层设于一氧化硅层之上的双层的层间介电层结构，氢化的时间更短，可以提升产能，所述上氮化硅层33具有比氧化硅层32更强的杂质离子隔离防护能力，相比于现有技术中将一氧化硅层设于一氮化硅层之上的双层的层间介电层结构，能够有效避免杂质离子污染的风险。
具体地，所述阵列基板的第一金属层2下方还包括：设于所述第一金属层2下方的第一绝缘层、设于所述第一绝缘层下方的半导体层、设于所述半导体层下方的缓冲层、和设于所述缓冲层下方的遮光层；以及设于所述第二金属层4上的平坦层、设于所述平坦层上的底层电极、设于所述底层电极上的保护层、和设于所述保护层上的顶层电极，这与现有的TFT阵列基板结构无异，此处不再展开进行详细描述。优选的，所述基板1为玻璃基板，所述第一金属层2和第二金属层4的材料为钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合，所述顶层电极和底层电极的材料为氧化铟锡(Indium Tin Oxide，ITO)。
具体地，所述第一金属层2包括：TFT的栅极、及与所述TFT的栅极连接的栅极线；所述第二金属层4包括：TFT的源极、TFT的漏极、及与所述TFT的源极连接的数据线。
进一步地，所述半导体层包括位于中间区域的沟道区、和位于沟道区两端的接触区。所述TFT的源极、漏极分别通过贯穿层间介电层3和第一 绝缘层的过孔与半导体层两端的接触区相接触；所述顶层电极通过贯穿保护层、底层电极、和平坦层的过孔与TFT的漏极相接触。
请参阅图3并结合图2，本发明还提供一种阵列基板的制作方法，包括如下步骤：
步骤1、提供一基板1，在所述基板1上沉积并图案化第一金属层2。
具体地，所述基板1上预先自下而上依次制作有遮光层、缓冲层、半导体层、和第一绝缘层。
所述基板1为玻璃基板；所述第一金属层2的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
所述半导体层包括位于中间区域的沟道区、和位于沟道区两端的接触区。所述第一金属层2包括：TFT的栅极、及与所述TFT的栅极连接的栅极线。
步骤2、采用化学气相沉积工艺(Chemical Vapor Deposition，CVD)在所述第一金属层2上成膜下氮化硅层31，所述下氮化硅层31含氢。
步骤3、采用化学气相沉积工艺在所述下氮化硅层31上成膜氧化硅层32。
步骤4、采用化学气相沉积工艺在所述氧化硅层32上成膜上氮化硅层33，所述下氮化硅层31、氧化硅层32、及上氮化硅层33共同构成层间介电层3。
步骤5、在所述层间介电层3上沉积并图案化第二金属层4。
具体地，所述第二金属层4包括：TFT的源极、TFT的漏极、及与所述TFT的源极连接的数据线。
随后在所述第二金属层4上自下而上依次制作平坦层、底层电极、保护层、顶层电极。所述TFT的源极、漏极分别通过贯穿层间介电层3和第一绝缘层的过孔与半导体层两端的接触区相接触；所述顶层电极通过贯穿保护层、底层电极、和平坦层的过孔与TFT的漏极相接触。
本发明的TFT阵列基板的制作方法，连续通过化学气相沉积工艺成膜下氮化硅层31、氧化硅层32、及上氮化硅层33，制得包括所述下氮化硅层31、氧化硅层32、及上氮化硅层33三层结构的层间介电层3，下氮化硅层31含氢能够在进行氢化时作为氢离子的来源，相比于现有技术中将一氮化硅层设于一氧化硅层之上的双层的层间介电层结构，氢化的时间更短，可以提升产能，所述上氮化硅层33具有比氧化硅层32更强的杂质离子隔离防护能力，相比于现有技术中将一氧化硅层设于一氮化硅层之上的双层的层间介电层结构，能够有效避免杂质离子污染的风险。
综上所述，本发明的TFT阵列基板结构及其制作方法，采用下氮化硅层、氧化硅层、和上氮化硅层三层结构的层间介电层，下氮化硅层含氢为氢化工艺提供氢离子，上氮化硅层提升层间介电层对杂质离子的隔绝防护能力，相比于现有技术中仅包括一氧化硅层与一氮化硅层的双层结构的中间介电层，能够在不影响氢化效果的前提下，提升层间介电层对杂质离子的隔绝防护能力，避免杂质离子污染的风险，缩短氢化时间，提升产能。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (13)

  1. 一种TFT阵列基板结构，包括：基板、设于所述基板上的第一金属层、覆盖所述第一金属层的层间介电层、及设于所述层间介电层上第二金属层；
    所述层间介电层包括设于所述第一金属层上的下氮化硅层、设于所述下氮化硅层上的氧化硅层、及设于所述氧化硅层上的上氮化硅层；所述下氮化硅层含氢。
  2. 如权利要求1所述的TFT阵列基板结构，还包括：设于所述第一金属层下方的第一绝缘层、设于所述第一绝缘层下方的半导体层、设于所述半导体层下方的缓冲层、以及设于所述缓冲层下方的遮光层。
  3. 如权利要求2所述的TFT阵列基板结构，还包括设于所述第二金属层上的平坦层、设于所述平坦层上的底层电极、设于所述底层电极上的保护层、以及设于所述保护层上的顶层电极。
  4. 如权利要求1所述的TFT阵列基板结构，其中，所述第一金属层包括：TFT的栅极、及与所述TFT的栅极连接的栅极线。
  5. 如权利要求1所述的TFT阵列基板结构，其中，所述第二金属层包括：TFT的源极、TFT的漏极、及与所述TFT的源极连接的数据线。
  6. 一种TFT阵列基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在所述基板上沉积并图案化第一金属层；
    步骤2、在所述第一金属层上成膜下氮化硅层，所述下氮化硅层含氢；
    步骤3、在所述下氮化硅层上成膜氧化硅层；
    步骤4、在所述氧化硅层上成膜上氮化硅层，所述下氮化硅层、氧化硅层、及上氮化硅层共同构成层间介电层；
    步骤5、在所述层间介电层上沉积并图案化第二金属层。
  7. 如权利要求6所述的TFT阵列基板的制作方法，其中，所述步骤2采用化学气相沉积工艺成膜下氮化硅层，所述步骤3采用化学气相沉积工艺成膜氧化硅层，所述步骤4采用化学气相沉积工艺成膜上氮化硅层。
  8. 如权利要求6所述的TFT阵列基板的制作方法，其中，所述步骤1之前还包括：在所述基板上自下而上依次制作遮光层、缓冲层、半导体层、和第一绝缘层。
  9. 如权利要求8所述的TFT阵列基板的制作方法，其中，所述步骤5之后还包括：在所述第二金属层上自下而上依次制作平坦层、底层电极、 保护层、和顶层电极。
  10. 如权利要求6所述的TFT阵列基板的制作方法，其中，所述第一金属层包括：TFT的栅极、及与所述TFT的栅极连接的栅极线；所述第二金属层包括：TFT的源极、TFT的漏极、及与所述TFT的源极连接的数据线。
  11. 一种TFT阵列基板结构，包括：基板、设于所述基板上的第一金属层、覆盖所述第一金属层的层间介电层、及设于所述层间介电层上第二金属层；
    所述层间介电层包括设于所述第一金属层上的下氮化硅层、设于所述下氮化硅层上的氧化硅层、及设于所述氧化硅层上的上氮化硅层；所述下氮化硅层含氢；
    其中，所述第一金属层包括：TFT的栅极、及与所述TFT的栅极连接的栅极线；
    其中，所述第二金属层包括：TFT的源极、TFT的漏极、及与所述TFT的源极连接的数据线。
  12. 如权利要求11所述的TFT阵列基板结构，还包括：设于所述第一金属层下方的第一绝缘层、设于所述第一绝缘层下方的半导体层、设于所述半导体层下方的缓冲层、以及设于所述缓冲层下方的遮光层。
  13. 如权利要求12所述的TFT阵列基板结构，还包括设于所述第二金属层上的平坦层、设于所述平坦层上的底层电极、设于所述底层电极上的保护层、以及设于所述保护层上的顶层电极。
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CN106707639B (zh) * 2016-12-20 2021-01-22 厦门天马微电子有限公司 阵列基板、显示面板、阵列基板制作方法
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